WO2021197429A1

WO2021197429A1 - Liquid crystal panel driving method and display device

Info

Publication number: WO2021197429A1
Application number: PCT/CN2021/084954
Authority: WO
Inventors: 张晓乐; 陈宥烨; 赵玉财
Original assignee: 咸阳彩虹光电科技有限公司
Priority date: 2020-04-03
Filing date: 2021-04-01
Publication date: 2021-10-07
Also published as: CN113496684A

Abstract

A liquid crystal panel driving method and a display device (10). The liquid crystal panel driving method comprises: presetting a skip scan mode of a GOA circuit of a liquid crystal panel (S1); achieving driving display of the liquid crystal panel by combining the skip scan mode with polarity conversion of data lines (DLs) within the time of each image frame (S2), wherein the skip scan mode indicates that the scanning of scan lines (GLs) is performed non-continuously and sequentially in a GOA timing cycle period, the polarity conversion frequency of the DLs is reduced by at least 0.5 times. The use of the liquid crystal panel driving method in the display device (10) can reduce the polarity conversion frequency of the DLs within the time of each image frame, thereby effectively reducing power consumption and preventing excessive temperature.

Description

Liquid crystal panel driving method and display device

Technical field

This application belongs to the technical field of liquid crystal display, and specifically relates to a method for driving a liquid crystal panel and a display device.

Background technique

With the development of display technology, liquid crystal display devices (Liquid Crystal Display, referred to as LCD) have gradually replaced cathode ray tube (Cathode Ray Tube, referred to as CRT) display devices due to their advantages of lightness, thinness, and low radiation. Liquid crystal display devices are widely used in information terminals such as televisions, computers, smart phones, mobile phones, car machines, and e-books, and have become the most common display devices.

A general liquid crystal display device mainly includes a source drive circuit and a gate drive circuit arranged on a liquid crystal panel (Panel), a horizontal direction circuit board (X-board, referred to as XB), and a system level arranged on a system board or a main board (MB board) Chip (System On Chip, SOC for short) and Timing Control (TCON for short) are usually connected to the circuit board and the horizontally oriented circuit board through a flexible flat cable (Flexible Flat Cable, for short FFC). Signal transmission, where the system-level chip receives the image data signal to be transmitted, and outputs the image data signal to be transmitted, and then the row expansion module and the column expansion module process the input signal, and transmit the processed data to the timing control The timing controller transmits the received data to the source driving circuit and the gate driving circuit through the horizontal direction circuit board, thereby driving the panel for display.

With the development of liquid crystal display technology, GOA (Gate-On Array, gate drive circuit integrated on the array substrate) technology is widely used in high-end products. The timing signals of the GOA on the drive panel are all in the sequence of forward scan or reverse scan, and a certain single direction is fixed to drive and control the scan lines of the panel. When the panel size is large, the scan control of a single forward scan or reverse scan sequence, combined with the Data (data line) drive, will cause excessive drive power consumption and excessive temperature when the screen is overloaded.

In the panel, Scan or GL (scan line) and Data or DL (data line) jointly control and drive the polarity of the pixel. When the gate is sequentially scanned by the scan line within one frame, Date The timing cycle polarity change will increase the power consumption/temperature of the COF (Chip-On-Flex) source driver end; within one frame of picture time, the faster the polarity change cycle, the higher the polarity change frequency , The greater the increase in power consumption and temperature. In view of the problem of the temperature rise of the Driver (drive area), the current solution is to stick a heat sink (Driver heat sink) in the drive area, see Figure 1, but this method will obviously increase the development cost of the product. Conducive to cost control of display panel production.

Therefore, how can the problem of the temperature rise of the Driver (driving area) caused by the high polarity change frequency be solved without increasing the cost?

Application content

In order to solve the above-mentioned problems in the prior art, the present application provides a liquid crystal panel driving method and display device, which can solve the driver (driving area) temperature caused by the high polarity change frequency without increasing the cost. The problem of rising.

An embodiment of the present application provides a method for driving a liquid crystal panel, including:

Step 1. Preset the skip scan mode of the GOA circuit in the LCD panel;

Step 2: Combining the skip scan mode with the polarity conversion of the data line within each frame of picture time to realize the driving display of the liquid crystal panel;

Wherein, the skip scan mode is that in a GOA timing cycle, the scan sequence of scan lines or gates is performed in a non-continuous sequence;

The polarity conversion frequency of the data line is reduced by at least 0.5 times.

In an embodiment of the present application, the skip scan mode includes: a first preset skip scan mode and a second preset skip scan mode; wherein, the first preset skip scan mode is performed by turning on a timing signal It is realized by sequential control, and the second preset skip scan method is by changing the wiring of the GOA circuit and the timing signal line, or changing the wiring of the GOA circuit and the timing signal line and changing the GOA in combination. The circuit is realized by cascading multiple GOA units.

In an embodiment of the present application, the first preset skip scan mode includes:

Keeping the wiring sequence of the GOA unit and the timing signal line unchanged;

The turn-on sequence of the timing signal is controlled by the timing control circuit.

In an embodiment of the present application, the sequence of turning on the timing signals is: first timing signal (CLK1)→third timing signal (CLK3)→second timing signal (CLK2)→fourth timing signal (CLK4)→first timing signal (CLK4) Five timing signal (CLK5) → seventh timing signal (CLK7) → sixth timing signal (CLK6) → eighth timing signal (CLK8), used to control the corresponding scan line or gate output signal; the liquid crystal panel The pixels of is M*N, that is, when the number of pixels in a row is N, the polarity change frequency of the data line is N/2 times.

In an embodiment of the present application, the sequence of turning on the timing signal (CLK signal) is the first timing signal (CLK1) → the third timing signal (CLK3) → the fifth timing signal (CLK5) → the seventh timing signal ( CLK7) → second timing signal (CLK2) → fourth timing signal (CLK4) → sixth timing signal (CLK6) → eighth timing signal (CLK8); the pixels of the liquid crystal panel are M*N, that is, the number of rows of pixels is When N, the polarity change frequency of the data line is N/4 times.

In an embodiment of the present application, the second preset skip scan mode includes:

Keep the timing signal (external timing CLK signal) turned on in sequence, adjust the sequence of the GOA circuit accessing the timing signal, or adjust the sequence of the GOA circuit accessing the timing signal, and adjust the multiple A cascade connection between GOA units to realize the skip sweep of the scan line (Gate) by the GOA circuit.

In an embodiment of the present application, the sequence of the skip scan is the first scan line (Gate1)→the third scan line (Gate3)→the second scan line (Gate2)→the fourth scan line (Gate4)→the fifth scan line (Gate4). Scan line (Gate5)→seventh scan line (Gate7)→sixth scan line (Gate6)→eighth scan line (Gate8); the pixels of the liquid crystal panel are M*N, that is, when the number of row pixels is N, the The polarity change frequency of the data line is N/2 times.

In an embodiment of the present application, the sequence of the skip scan is the first scan line (Gate1)→the third scan line (Gate3)→the fifth scan line (Gate5)→the seventh scan line (Gate7)→the second scan line (Gate7). Scan line (Gate2)→fourth scan line (Gate4)→sixth scan line (Gate6)→eighth scan line (Gate8); the pixels of the liquid crystal panel are M*N, that is, when the number of row pixels is N, the The polarity change frequency of the data line is N/4 times.

Another embodiment of the present application also provides a display device, which adopts any one of the aforementioned liquid crystal panel driving methods.

Compared with the prior art, this application has the following beneficial effects:

In this application, when the GOA circuit and the CLK signal connection remain unchanged, and the cascade relationship between the GOA units remains unchanged, the external circuit controls the turn-on sequence of the CLK signal to achieve the skip sweep function of the GOA circuit; or through the turn-on of the CLK signal The sequence remains the same, and the cascade between the GOA units remains unchanged, only the wiring sequence of the GOA unit and the CLK signal is changed, such as Gate1→Gate3→Gate2→Gate4→Gate5→Gate7→Gate6→Gate8 jump scan, and the Gate circuit The pre-charging time remains the same; you can also change the wiring sequence of the GOA unit and the CLK signal and change the cascading relationship between the GOA units by changing the turn-on sequence of the CLK signal, such as Gate1→Gate3→Gate5→Gate7→ Gate2→Gate4→Gate6→Gate8 skips the sweep, and the precharging time of the Gate circuit remains unchanged; to reduce the polarity conversion frequency of the data line within one frame of picture time, which can effectively reduce power consumption and avoid excessive temperature.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the following will briefly introduce the drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative work, other drawings can be obtained from these drawings.

FIG. 1 is a schematic view showing the structure of a driver attached to a heat sink of a liquid crystal display device in the prior art.

FIG. 2 is a schematic structural diagram of a liquid crystal display device provided by an embodiment of the application.

FIG. 3 is a timing principle diagram of a liquid crystal display device provided by an embodiment of the application.

FIG. 4 is a schematic diagram of a Column Inversion+Flip-Pixel liquid crystal panel with a heavy-duty monochrome R screen provided by an embodiment of the application.

5 is a schematic circuit diagram of a liquid crystal display device provided by an embodiment of the application when CLK1 to CLK8 are sequentially turned on.

FIG. 6 is a schematic diagram of waveforms when CLK1 to CLK8 of a liquid crystal display device according to an embodiment of the application are sequentially turned on.

FIG. 7 is a schematic diagram of the corresponding Gate/Data1 waveforms when CLK1 to CLK8 of a liquid crystal display device according to an embodiment of the application are sequentially turned on.

FIG. 8 is a schematic diagram of a method for driving a liquid crystal panel provided by an embodiment of the application.

FIG. 9a is a schematic diagram of a waveform diagram when the CLK signal is turned on according to an embodiment of the application.

FIG. 9b is a schematic diagram of the Gate/Data1 waveform corresponding to a CLK signal turn-on sequence provided by an embodiment of the application.

FIG. 10 is a schematic diagram of another waveform diagram of turning on the CLK signal provided by an embodiment of the application.

FIG. 11 is a schematic diagram of the Gate/Data1 waveform corresponding to another CLK signal turn-on sequence provided by an embodiment of the application.

FIG. 12 is a schematic diagram of a circuit for realizing a jump scan sequence by changing the wiring sequence of the GOA unit and the CLK signal line according to an embodiment of the application.

FIG. 13 is a schematic diagram of a connection between a GOA unit and a CLK signal line provided by an embodiment of the application.

FIG. 14 is a schematic diagram of waveforms corresponding to the wiring of a GOA unit and a CLK signal line provided by an embodiment of the application.

FIG. 15 is a schematic diagram of the Gate/Data1 waveform corresponding to the connection between the GOA unit and the CLK signal line provided by an embodiment of the application.

FIG. 16 is a schematic diagram of another circuit corresponding to a jump scan sequence by changing the wiring sequence of the GOA unit and the CLK signal line provided by an embodiment of the application.

FIG. 17 is a schematic diagram of another connection between a GOA unit and a CLK signal line provided by an embodiment of the application.

FIG. 18 is a schematic diagram of waveforms corresponding to the wiring of another GOA unit and the CLK signal line provided by an embodiment of the application.

FIG. 19 is a schematic diagram of the Gate/Data1 waveform corresponding to another GOA unit and the CLK signal line connection provided by an embodiment of the application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

Example one

Please refer to FIG. 2, which is a schematic structural diagram of a liquid crystal display device provided by an embodiment of the application; for example, an active matrix display device 10 provided by this embodiment includes: a display panel 111 having a gate driver thereon Circuit, source drive circuit; XB board 113, on which there are drive circuit board assembly 1130, system board 13, and connector CL1. The active matrix display device 10 of this embodiment is, for example, a TCONLESS LCD TV. The system-level chip on the system board integrates at least part of the functions of the traditional TCON chip, and the XB board integrates at least part of the functions of the traditional TCON chip. However, the embodiments of the present application are not limited to this.

The display panel 111 includes a display area 1111 and a gate drive circuit and a source drive circuit electrically connected to the display area 1111. A plurality of data lines DL, a plurality of gate lines GL, and a plurality of pixels P electrically connecting each data line DL and each gate line GL are provided in the display area 1111; each pixel P is located on the corresponding gate line GL The intersection with the data line DL. The gate drive circuit includes, for example, two GOA (Gate-On Array, gate drive circuits integrated on an array substrate) circuits 1113, and the two GOA circuits 1113 are located in the peripheral area of the display area 1111 and are separately arranged at two opposite sides of the display area 1111. On the other hand, that is, the gate drive circuit of the display panel 111 is a double-sided GOA circuit. Each GOA circuit 1113 is electrically connected to the gate line GL in the display area 1111, and is used to provide a gate driving signal to each gate line GL in the display area 1111. The source driving circuit includes, for example, a plurality of COF-type source drivers 1115, such as the twelve COF (Chip-On-Flex, chip-on-film) source drivers 1115 shown in FIG. 1; each COF-type source driver 1115 is electrically connected The data lines DL in the display area 1111 are used for each data line DL to provide image data signals. More specifically, a single COF-type source driver 1115 includes, for example, a flexible circuit board and a source driver IC (source driver IC) provided on the flexible circuit board.

Please refer to FIG. 3. FIG. 3 is a timing principle diagram of a liquid crystal display device provided by an embodiment of the application. For example, on the basis of the above-mentioned liquid crystal display device, each scan line corresponds to one row of the pixel matrix, and each data line corresponds to one column of the pixel matrix. In the prior art, when a frame of image is input, scan line 1 controls the TFT gate to turn on in the first clock cycle, scan lines 2 to 4 controls the TFT gate to turn off, and the data line synchronizes the transmission of row 1 pixel Data signal. In the second clock cycle, the scan line 2 controls the gate of the TFT to turn on, the scan lines 1, 3, and 4 control the gate of the TFT to turn off, and the data line synchronously transmits the data signal of the row 2 pixel. In the third clock cycle, the scan line 3 controls the gate of the TFT to turn on, the

scan lines

1, 2, and 4 control the gate of the TFT to turn off, and the data line synchronously transmits the data signals of the row 3 pixels. In the fourth clock cycle, the scan line 4 controls the gate of the TFT to turn on, and the scan lines 1 to 3 control the gate of the TFT to turn off, and the data line synchronously transmits the data signal of row 4 pixels to complete the scan of the current frame of image. When the next frame of image data is input, it scans cyclically according to the aforementioned principle, that is, the existing display device is designed such that the pixels use scan lines as gates and data lines provide data, and the scan order of each frame is 1, 2, 3, 4... scanning.

Please refer to FIG. 4 to FIG. 7. FIG. 4 is a schematic diagram of a Column Inversion+Flip-Pixel liquid crystal panel provided by an embodiment of the application with a reloaded monochrome R screen. Take the Column Inversion+Flip-Pixel (column flip+interlace control pixel) design of the 4K screen, for example, when the monochrome R screen is reloaded, the CLK1～CLK8 signals are turned on in turn, the gate line is scanned, the corresponding Gate waveform and the waveform of Data1 are as follows As shown in FIGS. 6 and 7, FIG. 6 is a schematic diagram of waveforms when CLK1 to CLK8 of a liquid crystal display device provided by an embodiment of the application are sequentially turned on, and FIG. 7 is a schematic diagram of CLK1 of a liquid crystal display device provided by an embodiment of the application. The corresponding Gate/Data1 waveform diagram when CLK8 is turned on in sequence. FIG. 5 is a schematic diagram of a circuit when CLK1 to CLK8 of a liquid crystal display device are turned on sequentially according to an embodiment of the application. In this circuit, the GOA cascade relationship is 1 push 5, 5 pull 1, and precharge three stages, so the Gate is turned on The time is 4*Tp (the fourth Tp is the effective charging time of the output signal of the scan line controlled by the GOA of the current stage), and so on. Obviously, when the panel size is large, the scanning control of the single forward scan or reverse scan sequence described above, combined with the Data (data line) drive, will cause excessive drive power consumption and excessive temperature when the screen is overloaded. In one frame of picture time, the faster the cycle of the polarity change, that is, the higher the frequency of the polarity change, the greater the increase in power consumption and temperature.

Please refer to FIG. 8. FIG. 8 is a schematic diagram of a method for driving a liquid crystal panel according to an embodiment of the application; this embodiment provides a method for driving a liquid crystal panel, including:

Step one (S1), preset the skip scan mode of the GOA circuit in the liquid crystal panel;

Step two (S2), combining the skip scan method with the polarity conversion of the data line within each frame time to realize the drive display of the liquid crystal panel, that is, the low power consumption drive display at the COF end;

Wherein, the skip scan mode is that in a GOA timing cycle, the scan sequence of the scan line or gate is performed in a non-continuous sequence; the polarity conversion frequency of the data line is reduced by at least 0.5 times.

Further, in this embodiment, the skip sweep mode includes: a first preset skip sweep mode and a second preset skip sweep mode; wherein, the first preset skip sweep mode is performed by using the timing signal (GOA timing ) Realized by controlling the opening sequence.

Further, the first preset skip scan mode includes: keeping the wiring sequence of the GOA unit and the timing signal line unchanged, and controlling the turn-on sequence of the timing signal through a timing control circuit. Wherein, the GOA circuit includes a plurality of the GOA units cascaded.

Further, the turn-on sequence of the timing signal is: first timing signal (CLK1)→third timing signal (CLK3)→second timing signal (CLK2)→fourth timing signal (CLK4)→fifth timing signal (CLK5) )→seventh timing signal (CLK7)→sixth timing signal (CLK6)→eighth timing signal (CLK8), used to control the corresponding scan line or gate output signal; the pixels of the liquid crystal panel are M*N, That is, when the number of row pixels is N, the polarity change frequency of the data line is N/2 times.

Specifically, when the turn-on sequence of the CLK signal (timing signal) is adjusted and controlled to CLK1→CLK3→CLK2→CLK4→CLK5→CLK7→CLK6→CLK8 through the external circuit, then the corresponding gate output signal changes, and the corresponding waveform is shown in the figure As shown in 9a and 9b, FIG. 9a is a schematic diagram of a waveform diagram of a CLK signal turning on provided by an embodiment of this application, and FIG. 9b is a schematic diagram of a Gate/Data1 waveform corresponding to a CLK signal turning on sequence provided by an embodiment of this application; Column Inversion+Flip Pixel with 4K screen is used. When the monochrome R screen is reloaded, the waveforms of the CLK signal turn-on sequence are compared. The above-mentioned control method reduces the switching times of Data1 from 2160 to 1080, and the pre-turn on time is 3. *Tp.

It should be noted that the turn-on sequence of the CLK signal includes the above sequence, but the technical effect is not limited to the above-described turn-on sequence.

Example two

This embodiment introduces the driving method proposed in this application in detail on the basis of the active matrix display device 10 of the above embodiment.

Further, in this embodiment, the skip sweep mode includes: a first preset skip sweep mode and a second preset skip sweep mode; wherein, the first preset skip sweep mode is performed by comparing a timing signal (GOA Time sequence) is realized by controlling the opening sequence.

Further, the first preset skip scan mode includes: keeping the wiring sequence of the GOA unit and the timing signal line unchanged, and controlling the turn-on sequence of the timing signal through the timing control circuit. Wherein, the GOA circuit includes: a plurality of the GOA units cascaded.

Further, the turn-on sequence of the CLK signal is the first timing signal (CLK1)→the third timing signal (CLK3)→the fifth timing signal (CLK5)→the seventh timing signal (CLK7)→the second timing signal (CLK2) → The fourth timing signal (CLK4) → The sixth timing signal (CLK6) → The eighth timing signal (CLK8); the pixels of the liquid crystal panel are M*N, that is, when the number of rows of pixels is N, the polarity of the data line The conversion frequency is N/4 times.

Specifically, when the external circuit is used to adjust the turn-on sequence of the control CLK signal as CLK1→CLK3→CLK5→CLK7→CLK2→CLK4→CLK6→CLK8, the corresponding waveforms are shown in Fig. 10 and Fig. 11, and Fig. 10 is an embodiment of the application. Provides another schematic diagram of the waveform diagram for turning on the CLK signal. FIG. 11 is a schematic diagram of the Gate/Data1 waveform corresponding to another CLK signal turning on sequence provided in an embodiment of the application; for example, a 4K screen Column Inversion+Flip-Pixel is used. When the monochrome R screen is loaded, compared with the waveforms of the CLK signal sequentially turning on, the above control method can reduce the number of switching of Data1 from 2160 to 540, but there is also a shortcoming, that is, the gate precharge time of this method It is 1*Tp.

It should be noted that the turn-on sequence of the CLK signal includes the above sequence, but the technical effect is not limited to the turn-on sequence.

The connection between the GOA circuit and the CLK signal in the first or second embodiment is unchanged, that is, when the connection between the control GOA unit and the CLK signal line is unchanged, and the cascade relationship between the GOA units is unchanged, the external timing control circuit Control the turn-on sequence of the CLK signal to realize the skip sweep function of GOA; only realize CLK1→CLK3→CLK5→CLK7→CLK2→CLK4→CLK6→CLK8, the gate precharge time is 1*Tp; but they can be reduced by one to varying degrees. The polarity conversion frequency of the data line within the frame time can effectively reduce power consumption and avoid excessive temperature.

Example three

In this embodiment, on the basis of the active matrix display device 10 of the first embodiment, the driving method proposed in this application is further described in detail.

Further, in this embodiment, the skip scan mode includes: a first preset skip scan mode and a second preset skip scan mode; wherein, the second preset skip scan mode is achieved by changing the GOA circuit and timing The wiring of the signal (CLK) line or the combination of changing the cascade connection between multiple GOA units in the GOA circuit is realized.

Further, the second preset skip scan method includes: the external timing CLK signal is turned on in sequence, that is, the timing signal is kept turned on in sequence, and the sequence of the GOA circuit access timing signal (CLK signal) is adjusted or the GOA unit is adjusted in combination. The cascade between the GOA circuit to achieve the jump sweep of the Gate.

Further, the sequence of the skip scan is the first scan line (Gate1)→the third scan line (Gate3)→the second scan line (Gate2)→the fourth scan line (Gate4)→the fifth scan line (Gate5)→ Seventh scan line (Gate7) → sixth scan line (Gate6) → eighth scan line (Gate8); the pixels of the liquid crystal panel are M*N, that is, when the number of rows of pixels is N, the polarity of the data line changes The frequency is N/2 times.

Specifically, by changing the wiring sequence of the GOA circuit and the CLK signal, that is, changing the wiring sequence of the GOA unit and the CLK signal line, the jump sweep sequence is Gate1→Gate3→Gate2→Gate4→Gate5→Gate7→Gate6→Gate8, corresponding to the circuit diagram As shown in FIG. 12, FIG. 12 is a schematic diagram of a circuit for realizing a jump scan sequence by changing the wiring sequence of the GOA unit and the CLK signal line according to an embodiment of the application. The connection between each GOA unit and the CLK signal line and the corresponding waveform diagrams are shown in Figure 13, Figure 14, Figure 15. Figure 13 is a schematic diagram of the connection between the GOA unit and the CLK signal line according to an embodiment of the application, and Figure 14 A schematic diagram of waveforms corresponding to the wiring of a GOA unit and a CLK signal line provided in an embodiment of this application. FIG. 15 is a schematic diagram of the Gate/Data1 waveforms corresponding to a wiring of a GOA unit and the CLK signal line provided in an embodiment of this application. For example, using a Column Inversion+Flip-Pixel 4K LCD screen as shown in Figure 4, when the monochrome R screen is reloaded, the control method of this embodiment also reduces the switching times of Data1 from 2160 to 1080, and the The turn-on time is 3*Tp.

It should be noted that the skip sweep sequence includes the above sequence, but achieving the technical effect is not limited to the skip sweep sequence.

In this embodiment, the turn-on sequence of the CLK signal remains unchanged, and the cascade connection between the GOA units remains unchanged. Only by changing the wiring sequence of the GOA unit and the CLK signal line, it can be implemented Gate1→Gate3→Gate2→Gate4→Gate5→Gate7→ Gate6→Gate8 skips scanning, and the precharge time of the Gate circuit remains unchanged, which can reduce the polarity conversion frequency of the data line within one frame of picture time, which can effectively reduce power consumption and avoid excessive temperature.

Example four

This embodiment introduces the driving method proposed in this application in detail on the basis of the active matrix display device 10 of the first embodiment.

Further, in this embodiment, the skip sweep mode includes: a first preset skip sweep mode and a second preset skip sweep mode; wherein, the second preset skip sweep mode is achieved by changing the GOA circuit and timing The wiring of the signal (CLK) line or collocation changes the cascade connection between multiple GOA units in the GOA circuit.

Further, the second preset skip scan mode includes: the external timing CLK signal is turned on in sequence, that is, the timing signal is kept turned on in sequence, and the sequence of the GOA circuit access timing signal (CLK signal) is adjusted or coordinated adjustment The cascade between the GOA units realizes the jump sweep of the Gate by the GOA circuit.

Further, the sequence of the skip scan is the first scan line (Gate1)→the third scan line (Gate3)→the fifth scan line (Gate5)→the seventh scan line (Gate7)→the second scan line (Gate2)→ The fourth scan line (Gate4) → the sixth scan line (Gate6) → the eighth scan line (Gate8); the pixels of the liquid crystal panel are M*N, that is, when the number of row pixels is N, the polarity of the data line changes The frequency is N/4 times.

Specifically, by changing the wiring sequence of the GOA circuit and the CLK signal, that is, changing the wiring sequence of the GOA unit and the CLK signal line, the jump scan of Gate1→Gate3→Gate5→Gate7→Gate2→Gate4→Gate6→Gate8 is realized. The corresponding circuit diagram is shown in the figure As described in 16, FIG. 16 is another schematic diagram of a circuit corresponding to a jump scan sequence by changing the wiring sequence of the GOA unit and the CLK signal line provided by the embodiment of the application; the wiring of the GOA unit and the CLK signal line and the corresponding waveform diagram As shown in FIG. 17, FIG. 18, and FIG. 19, FIG. 17 is a schematic diagram of the connection between another GOA unit and a CLK signal line provided by an embodiment of the application, and FIG. 18 is another GOA unit and a CLK signal line provided by an embodiment of the application. The waveform diagram corresponding to the wiring of the signal line. FIG. 19 is a waveform diagram of Gate/Data1 corresponding to the wiring of another GOA unit and the CLK signal line provided by an embodiment of the application. For example, using the Column Inversion+Flip-Pixel 4K LCD screen as shown in Figure 4, when the monochrome R screen is reloaded, the control method of this embodiment also reduces the number of data1 switching times from 2160 to 540, and it is pre-opened The time is 3*Tp.

In this embodiment, the sequence of turning on the CLK signal remains unchanged. By changing the wiring sequence of the GOA unit and the CLK signal line, and changing the cascade relationship between the GOA units, Gate1→Gate3→Gate5→Gate7→Gate2→Gate4→Gate6→ Gate8 skips scanning, and the Gate precharge time remains unchanged, which can also reduce the polarity conversion frequency of the data line within one frame of picture time, which can effectively reduce power consumption and avoid excessive temperature.

Example five

This embodiment provides a display device, which adopts the liquid crystal panel driving method described in any of the foregoing embodiments.

Specifically, please refer to FIG. 2, which is a schematic structural diagram of a liquid crystal display device provided by an embodiment of the application; for example, an active matrix display device 10 provided by this embodiment includes: a display panel 111 on which It has a gate drive circuit and a source drive circuit; an XB board 113 with a drive circuit board assembly 1130, a system board 13 and a connector CL1. The active matrix display device 10 of this embodiment is, for example, a TCONLESS LCD TV. The system-level chip on the system board integrates at least part of the functions of the traditional TCON chip, and the XB board integrates at least part of the functions of the traditional TCON chip. However, the embodiments of the present application are not limited to this.

The display panel 111 includes a display area 1111 and a gate drive circuit and a source drive circuit electrically connected to the display area 1111. A plurality of data lines DL, a plurality of gate lines GL, and a plurality of pixels P electrically connecting each data line DL and each gate line GL are provided in the display area 1111; each pixel P is located on the corresponding gate line GL The intersection with the data line DL. The gate drive circuit includes, for example, two GOA (Gate-On Array, gate drive circuits integrated on an array substrate) circuits 1113. The two GOA circuits 1113 are located in the peripheral area of the display area 1111 and are separately provided on two opposite sides of the display area 1111. On the other hand, that is, the gate drive circuit of the display panel 111 is a double-sided GOA circuit. Each GOA circuit 1113 is electrically connected to the gate line GL in the display area 1111, and is used to provide a gate driving signal to each gate line GL in the display area 1111. The source driving circuit includes, for example, a plurality of COF-type source drivers 1115, such as the twelve COF (Chip-On-Flex, chip-on-film) source drivers 1115 shown in FIG. 1; each COF-type source driver 1115 is electrically connected The data lines DL in the display area 1111 are used for each data line DL to provide image data signals. More specifically, a single COF-type source driver 1115 includes, for example, a flexible circuit board and a source driver IC (source driver IC) provided on the flexible circuit board.

Please refer to FIGS. 3 and 5 again. FIG. 3 is a timing principle diagram of a liquid crystal display device provided by an embodiment of the application. For example, on the basis of the above liquid crystal display device, each scan line corresponds to a row of the pixel matrix, The data line corresponds to a column of the pixel matrix; FIG. 5 is a schematic circuit diagram of a liquid crystal display device provided by an embodiment of the application when CLK1 to CLK8 are sequentially turned on. In this circuit, the GOA cascade relationship is 1 push 5, 5 pull 1. There are three stages of pre-charging, so the gate turn-on time is 4*Tp (Tp is the effective charging time of the output signal of the scan line controlled by the GOA of the current stage), and so on. Obviously, when the panel size is large, the scanning control of the single forward scan or reverse scan sequence described above, combined with the Data (data line) drive, will cause excessive drive power consumption and excessive temperature when the screen is overloaded. In one frame of picture time, the faster the cycle of the polarity change, that is, the higher the frequency of the polarity change, the greater the increase in power consumption and temperature. At this time, the driving method of the liquid crystal panel of the first embodiment, the second embodiment, the third embodiment or the fourth embodiment can be adopted, by:

Further, the skip sweep mode includes: a first preset skip sweep mode and a second preset skip sweep mode; wherein, the first preset skip sweep mode is performed by turning on a timing signal (GOA timing). It is realized by control, and the second preset skip scan mode is realized by changing the wiring of the GOA circuit and the timing signal (CLK) line or by changing the cascade connection between multiple GOA units in the GOA circuit.

Specifically, when the connection between the GOA unit and the CLK signal remains unchanged, and the cascade relationship between the GOA units remains unchanged, the external circuit is used to control the turn-on sequence of the CLK signal to realize the skip sweep function of the GOA circuit; or through the CLK signal The turn-on sequence of the GOA unit remains unchanged, and the cascade connection between the GOA units remains unchanged. Only the wiring sequence of the GOA unit and the CLK signal line is changed to achieve Gate1→Gate3→Gate2→Gate4→Gate5→Gate7→Gate6→Gate8 jump scan, and The pre-charging time of the Gate circuit remains unchanged; it is also possible to change the wiring sequence of the GOA unit and the CLK signal line and change the cascade relationship between the GOA units by changing the turn-on sequence of the CLK signal to achieve Gate1→Gate3→Gate5→ Gate7→Gate2→Gate4→Gate6→Gate8 skips the sweep, and the precharge time of the Gate circuit remains unchanged; to reduce the polarity conversion frequency of the data line within one frame of time, and effectively reduce the power consumption of the display device described in this implementation. , To avoid too high temperature.

The above content is a further detailed description of a liquid crystal panel driving method and display device provided by this application in combination with specific preferred embodiments. It cannot be considered that the specific embodiments of this application are limited to these descriptions, nor should the application be undisclosed. The drive, architecture, circuit, and related technologies of the liquid crystal display panel that are well-known or easily understood in the art are considered to be insufficiently disclosed. For those of ordinary skill in the technical field to which this application belongs, a number of simple deductions or substitutions can be made without departing from the concept of this application, which should be regarded as the scope of protection of this application.

Claims

A method for driving a liquid crystal panel, which includes:

Preset the skip scan mode of the GOA circuit in the LCD panel;

Combining the skip scan mode with the polarity conversion of the data line within each frame of time to realize the driving display of the liquid crystal panel;

Wherein, the skip scan mode is that in a GOA timing cycle, the scan order of the scan lines is non-continuously performed sequentially;

The polarity conversion frequency of the data line is reduced by at least 0.5 times.
The method for driving a liquid crystal panel according to claim 1, wherein:

The skip sweep mode includes: a first preset skip sweep mode and a second preset skip sweep mode;

in,

The first preset skip scan mode is realized by controlling the turn-on sequence of the timing signal;

The second preset skip scan method is to change the wiring of the GOA circuit and the timing signal line, or change the wiring of the GOA circuit and the timing signal line and change the combination of multiple GOA units in the GOA circuit. Cascade between.
The method of driving a liquid crystal panel according to claim 2, wherein:

The first preset skip scan mode includes:

Keeping the wiring sequence of the GOA unit and the timing signal line unchanged;

The turn-on sequence of the timing signal is controlled by the timing control circuit.
The method for driving a liquid crystal panel according to claim 3, wherein:

The turn-on sequence of the timing signal is: a first timing signal, a third timing signal, a second timing signal, a fourth timing signal, a fifth timing signal, a seventh timing signal, a sixth timing signal, and an eighth timing signal. For controlling the output signal of the corresponding scan line;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/2 times.
The method for driving a liquid crystal panel according to claim 3, wherein:

The turn-on sequence of the timing signal is: a first timing signal, a third timing signal, a fifth timing signal, a seventh timing signal, a second timing signal, a fourth timing signal, a sixth timing signal, and an eighth timing signal;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/4 times.
The method of driving a liquid crystal panel according to claim 2, wherein:

The second preset skip scan mode includes:

Keeping the timing signals turned on in sequence;

Adjust the sequence in which the GOA circuit connects to the timing signal, or adjust the sequence in which the GOA circuit connects to the timing signal, and adjust the cascade connection between the multiple GOA units to realize the GOA circuit pair Jump scan of the scan line.
The method of driving a liquid crystal panel according to claim 6, wherein:

The sequence of the skip scan is: the first scan line, the third scan line, the second scan line, the fourth scan line, the fifth scan line, the seventh scan line, the sixth scan line, and the eighth scan line;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/2 times.
The method of driving a liquid crystal panel according to claim 6, wherein:

The sequence of the skip scan is: the first scan line, the third scan line, the fifth scan line, the seventh scan line, the second scan line, the fourth scan line, the sixth scan line, and the eighth scan line;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/4 times.
A display device, wherein the liquid crystal panel driving method according to claim 1 is adopted.
The display device according to claim 9, wherein:

The skip sweep mode includes: a first preset skip sweep mode and a second preset skip sweep mode;

in,

The first preset skip scan mode is realized by controlling the turn-on sequence of the timing signal;

The second preset skip scan method is to change the wiring of the GOA circuit and the timing signal line, or change the wiring of the GOA circuit and the timing signal line and change the combination of multiple GOA units in the GOA circuit. Cascade between.
The display device according to claim 10, wherein:

The first preset skip scan mode includes:

Keeping the wiring sequence of the GOA unit and the timing signal line unchanged;

The turn-on sequence of the timing signal is controlled by the timing control circuit.
The display device according to claim 11, wherein:

The turn-on sequence of the timing signal is: a first timing signal, a third timing signal, a second timing signal, a fourth timing signal, a fifth timing signal, a seventh timing signal, a sixth timing signal, and an eighth timing signal. For controlling the output signal of the corresponding scan line;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/2 times.
The display device according to claim 11, wherein:

The turn-on sequence of the timing signal is: a first timing signal, a third timing signal, a fifth timing signal, a seventh timing signal, a second timing signal, a fourth timing signal, a sixth timing signal, and an eighth timing signal;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/4 times.
The display device according to claim 10, wherein:

The second preset skip scan mode includes:

Keeping the timing signals turned on in sequence;

Adjust the sequence in which the GOA circuit connects to the timing signal, or adjust the sequence in which the GOA circuit connects to the timing signal, and adjust the cascade connection between the multiple GOA units to realize the GOA circuit pair Jump scan of the scan line.
The display device according to claim 14, wherein:

The sequence of the skip scan is: the first scan line, the third scan line, the second scan line, the fourth scan line, the fifth scan line, the seventh scan line, the sixth scan line, and the eighth scan line;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/2 times.
The display device according to claim 14, wherein:

The sequence of the skip scan is: the first scan line, the third scan line, the fifth scan line, the seventh scan line, the second scan line, the fourth scan line, the sixth scan line, and the eighth scan line;

When the number of row pixels of the liquid crystal panel is N, the polarity change frequency of the data line is N/4 times.