WO2021197234A1 - 路由信息的处理方法、装置、设备及存储介质 - Google Patents

路由信息的处理方法、装置、设备及存储介质 Download PDF

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Publication number
WO2021197234A1
WO2021197234A1 PCT/CN2021/083384 CN2021083384W WO2021197234A1 WO 2021197234 A1 WO2021197234 A1 WO 2021197234A1 CN 2021083384 W CN2021083384 W CN 2021083384W WO 2021197234 A1 WO2021197234 A1 WO 2021197234A1
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Prior art keywords
link
chip
routing information
destination
valid signal
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PCT/CN2021/083384
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English (en)
French (fr)
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韩叶兵
汪为汉
汪振国
张士峰
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中兴通讯股份有限公司
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Publication of WO2021197234A1 publication Critical patent/WO2021197234A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/54—Organization of routing tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • This application relates to the technical field of routing data exchange, for example, to a method, device, device, and storage medium for processing routing information.
  • the routing system is a key component of the packet switching system, which includes the update of routing information, the sending of routing information, and the routing lookup.
  • the sending process of routing information is mainly to complete the generation and sending of routing protocol cells by operating the routing sending table.
  • Each row of the routing table shows the link connection relationship between the source chip and the destination chip. Calculate these on-off link relationships to obtain the destination reachable (DR) information of the link, and fill in the DR information
  • the upstream routing table is updated to realize the self-routing process of the switching system.
  • the routing information transmission is to read the routing table through the destination chip's identification code (Identifier, ID) number DST_ID as the row address, generally starting from the smallest destination chip ID number to obtain the link connection relationship, and connect according to the link
  • the relationship with the effective signal of the current link completes the calculation of the DR information.
  • the routing protocol cell sending interval counter reaches the preset sending interval, according to the version number of the sent cell, the calculated DR information, the destination chip ID number, the source chip level, the source chip ID number, and the link ID number, etc.
  • the information is sequentially assembled into cells conforming to the defined routing protocol and sent out from the current link.
  • the system cannot respond to the abnormality of the effective signal drop caused by the abnormal operation of the board or the abnormal system hardware environment, which will cause a large number of packet loss in the switching system, and the entire routing needs to be executed.
  • the generation and sending operations of routing protocol cells in the sending table consume a lot of time.
  • the present application provides a routing information processing method, device, equipment, and storage medium, which can reduce the packet loss rate of the switching system and improve the efficiency of routing information processing.
  • a method for processing routing information including:
  • Obtain a valid destination chip ID sequentially obtain the link connection relationship between the source chip and the destination chip from the routing table according to the destination chip ID, and process the link connection relationship under the destination chip ID according to the link connection relationship Routing information; when it is detected that the link has a valid signal down hop, obtain the target chip ID of the link where the valid signal down hop occurs; jump processing the target chip ID under the target chip ID of the link where the valid signal down hop occurs Routing information.
  • a device for processing routing information including:
  • the effective destination chip ID obtaining module is configured to obtain a valid destination chip ID;
  • the first routing information processing module is configured to sequentially obtain the link connection between the source chip and the destination chip from the routing table according to the destination chip ID And process the routing information under the destination chip ID according to the link connection relationship;
  • the effective signal drop detection module is set to obtain the link where the effective signal drop occurs when the effective signal drop is detected in the link The ID of the destination chip where the path is located;
  • the second routing information processing module is configured to jump and process the routing information under the ID of the destination chip where the link where the valid signal is dropped is located.
  • a communication device which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the foregoing routing information processing method when the program is executed.
  • a storage medium is also provided, the storage medium stores a computer program, and when the computer program is executed by a processor, the foregoing routing information processing method is implemented.
  • FIG. 1 is a flowchart of a method for processing routing information according to an embodiment of the application
  • FIG. 2 is a schematic diagram of a routing table provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a single-stage switching system provided by an embodiment of this application.
  • FIG. 4 is a schematic diagram of another routing table provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a routing information processing apparatus provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a device provided by an embodiment of the application.
  • FIG. 1 is a flowchart of a method for processing routing information according to an embodiment of the application, and this embodiment is suitable for processing routing information.
  • This embodiment can be implemented by switching equipment.
  • the method provided in this embodiment includes S110-S140.
  • S120 Acquire the link connection relationship between the source chip and the destination chip from the routing table according to the destination chip ID in turn, and process the routing information under the destination chip ID according to the link connection relationship.
  • An effective target chip can be understood as a chip used in this application scenario, and the target chip can be a switch access (SA) chip.
  • the destination chip ID can be written as DST_ID.
  • the method for obtaining the valid destination chip ID may be: determining the invalid destination chip according to the physical connection information of the route; and masking the invalid destination chip ID by configuring a mask.
  • the invalid destination chip may be a destination chip that is not physically connected. After shielding the invalid destination chip ID, there is no need to process the routing information under the invalid destination chip ID, thereby improving the efficiency of route convergence.
  • the routing sending table may be preset or established by way of route update.
  • FIG. 2 is a schematic diagram of a routing sending table provided in an embodiment of the application. As shown in FIG. 2, each routing sending table A link connection relationship corresponding to the destination chip ID, and each column is link information.
  • the routing table after obtaining the valid target chip ID, read the routing table using the valid target chip ID as the row address according to the ID number from small to large or from large to small to obtain the current effective target chip ID. And then process the routing information under the currently valid destination chip according to the link connection relationship.
  • the process of processing the routing information under the destination chip ID according to the link connection relationship may be: traversing the link contained in the destination chip ID; when traversing to the current link, generating the routing protocol cell of the current link ; Send the routing protocol cell through the current link and continue to traverse the next link.
  • the DR information when traversing to the current link LINK_ID, is calculated according to the current link traffic information and the link connection relationship, and the DR information is calculated according to the version number of the sent cell, the calculated DR information, and the target chip ID number.
  • Source chip level, source chip ID number and link ID number and other information are sequentially assembled into routing protocol cells conforming to the definition, and the routing protocol cells are sent out through the current link. Continue to traverse the next link LINK_ID+1 until the link under the current target chip ID is traversed, and the routing information processing under the current target chip ID is completed.
  • the down jump of the valid signal may be caused by abnormal board pulling operation or abnormal hardware environment.
  • the target chip ID of the link where the valid signal jump occurs is obtained. If the routing information under the current target chip ID has not been processed, the routing information under the current target chip ID will continue to be processed until The routing information processing under the current destination chip ID is completed.
  • the jump process is under the destination chip ID where the link where the valid signal jump occurs Routing information.
  • the route information under the destination chip ID of the link where the valid signal is dropped is further included is included: After the information processing is completed, continue to process the routing information under the next valid destination chip ID of the destination chip where the link where the valid signal jumps occurs.
  • a buffer with a set depth is created; the destination chip ID of the link where the unprocessed valid signal drop is located is stored in the buffer .
  • Multiple links with valid signal down-hops may be detected at the same time or not at the same time. For example, it can be that another valid signal is detected when the route information under the target chip ID of the link where the valid signal is dropped is processed.
  • the set depth can be determined by the number of links.
  • the destination chip ID of the link where the unprocessed valid signal jumps down is stored in the cache, and the jumps are processed in the order of the destination chip ID from small to large to process the routes under the destination chip ID in the cache. information.
  • the one with the smallest DST_ID corresponding to the next hop link is processed first, and the others are also processed one by one in the order of the DST_ID address size.
  • the jump processing further includes the following steps: if the routing information under the current destination chip ID has not been processed, continue processing The routing information under the current destination chip ID will not be processed until the routing information under the current destination chip ID has been processed.
  • the method further includes the following step: judging whether the destination chip where the link where the valid signal drop occurs is the first time a valid signal is generated in the current cycle Jump; If the target chip where the link where the valid signal jumps is located is not the first time the valid signal jumps in the current cycle, then the current valid signal jump is ignored. After the routing information processing under the current target chip ID is completed, continue to process the routing information under the next valid destination chip ID of the current target chip. This is to ensure that the same target chip ID can only be interrupted once in a cycle.
  • FIG. 3 is a schematic structural diagram of a single-stage switching system provided by an embodiment of the application. As shown in FIG. 3, it includes 4 effective destination chips, and their DST_IDs are 0, 1, 1021, and 1023, respectively.
  • the routing sending table established by switching unit 0# is shown in Figure 4.
  • the routing sending table row in the black box represents the relationship between switching unit 0# and the SA chip with DST_ID 0, 1, 1021, and 1023.
  • a valid link path, and the other rows with all 0s indicate that there is no valid link path between the exchange unit 0# and the destination chip of the corresponding address.
  • the switching unit 0# uses a mask to mask the DST_ID that is not used in the actual application scenario.
  • the effective signal jumps down, it uses the interrupt DST_ID address jump to respond to the processing.
  • the processing process is as follows deal with:
  • Step 4 When the link down hop is detected in step 3, it is detected that other links have valid signal down hops, and a buffer with a depth of 192 is set according to the maximum value of the link number to store the unprocessed DST_ID, and The same DST_ID can only be processed once by interrupt, and then processed one by one in the order of DST_ID address size.
  • the link valid (Link Valid, LV) signal is down hop, the one with the smallest DST_ID corresponding to the next hop link is processed first, and the others are processed one by one in the order of the DST_ID address size .
  • FIG. 5 is a schematic structural diagram of a routing information processing apparatus provided by an embodiment of the application.
  • the device includes: a valid destination chip ID acquisition module 210, a first routing information processing module 220, a valid signal drop detection module 230, and a second routing information processing module 240.
  • the effective destination chip ID obtaining module 210 is configured to obtain a valid destination chip ID; the first routing information processing module 220 is configured to sequentially obtain the link between the source chip and the destination chip from the routing table according to the destination chip ID. And process the routing information under the target chip ID according to the link connection relationship; the effective signal drop detection module 230 is set to obtain the effective signal drop when detecting that the link has a valid signal drop The ID of the destination chip where the jumped link is located; the second routing information processing module 240 is configured to jump and process routing information under the ID of the destination chip where the link where the effective signal jumps down occurs.
  • the effective target chip ID acquisition module 210 is also set to:
  • the invalid destination chip is determined according to the physical connection information of the route; the invalid destination chip is shielded by a configuration mask.
  • it further includes:
  • the effective signal drop detection module 230 is further configured as:
  • a buffer with a set depth is created; and the unprocessed target chip ID of the link where the valid signal down-hops is stored is stored in the cache.
  • the second routing information processing module 240 is further configured to:
  • the jump processes the routing information under the destination chip in the cache in the descending order of the destination chip ID.
  • the method further includes:
  • the method further includes:
  • the first routing information processing module 220 is further configured to:
  • FIG. 6 is a schematic structural diagram of a device provided by an embodiment of the application.
  • the device provided by the present application includes: a processor 310 and a memory 320.
  • the number of processors 310 in the device may be one or more.
  • one processor 310 is taken as an example.
  • the number of memories 320 in the device may be one or more, and one memory 320 is taken as an example in FIG. 6.
  • the processor 310 and the memory 320 of the device may be connected through a bus or in other ways. In FIG. 6, the connection through a bus is taken as an example.
  • the device is the receiving end.
  • the receiving end may be one of a scheduling node, a base station, or a user equipment (User Equipment, UE).
  • UE User Equipment
  • the memory 320 can be configured to store software programs, computer-executable programs, and modules, such as the program instructions/modules corresponding to the equipment of any embodiment of the present application (for example, the effective routing information processing device).
  • the memory 320 may include a program storage area and a data storage area.
  • the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created according to the use of the device, and the like.
  • the memory 320 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.
  • the memory 320 may include a memory remotely provided with respect to the processor 310, and these remote memories may be connected to the device through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the device provided above can be configured to execute the processing method applied to routing information provided by any of the above embodiments, and has corresponding functions and effects.
  • the program stored in the corresponding memory 320 may be program instructions/modules corresponding to the processing method applied to routing information provided in the embodiments of the present application.
  • the processor 310 executes the computer by running the software programs, instructions, and modules stored in the memory 320
  • One or more functional applications and data processing of the device is to implement the processing method applied to routing information in the foregoing method embodiments.
  • the device may be one of a base station or a UE.
  • An embodiment of the present application also provides a storage medium containing computer-executable instructions.
  • the computer-executable instructions are used to execute a routing information processing method when executed by a computer processor, and the method includes: obtaining a valid target chip ID; In turn, obtain the link connection relationship between the source chip and the destination chip from the routing table according to the destination chip ID, and process the routing information under the destination chip ID according to the link connection relationship; when a link is detected When a valid signal jump occurs on the path, the target chip ID of the link where the valid signal jump occurs is obtained, and the routing information under the current target chip ID is processed; after the routing information under the current target chip ID is processed, the jump is processed The routing information under the destination chip ID where the link where the valid signal jumps occurs.
  • user equipment covers any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers, or vehicular mobile stations.
  • the various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the present application is not limited thereto.
  • Computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or written in any combination of one or more programming languages Source code or object code.
  • ISA Instruction Set Architecture
  • the block diagram of any logic flow in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions.
  • the computer program can be stored on the memory.
  • the memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), optical Memory devices and systems (Digital Video Disc (DVD) or Compact Disk (CD)), etc.
  • Computer-readable media may include non-transitory storage media.
  • the data processor can be any type suitable for the local technical environment, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (Digital Signal Processing, DSP), application specific integrated circuits (ASICs) ), programmable logic devices (Field-Programmable Gate Array, FPGA), and processors based on multi-core processor architecture.
  • DSP Digital Signal Processing
  • ASICs application specific integrated circuits
  • FPGA Field-Programmable Gate Array
  • FPGA Field-Programmable Gate Array

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Abstract

本文公开一种路由信息的处理方法、装置、设备及存储介质。路由信息的处理方法包括：获取有效的目的芯片ID；依次根据所述目的芯片ID从路由发送表中获取源芯片与所述目的芯片间的链路连接关系，并根据所述链路连接关系处理所述目的芯片ID下的路由信息；当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID；跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息。

Description

路由信息的处理方法、装置、设备及存储介质 技术领域
本申请涉及路由数据交换技术领域，例如涉及一种路由信息的处理方法、装置、设备及存储介质。
背景技术
路由系统是分组交换系统中的关键组成部分，它包括了路由信息的更新、路由信息的发送和路由查找等部分。路由信息的发送过程主要是通过操作路由发送表完成路由协议信元的生成和发送功能。路由发送表的每行内容显示的是源芯片与目的芯片之间通路的链路连接关系，计算这些通断链路关系得到链路的目标可抵达(Destination Reachable，DR)信息，将DR信息填充到路由协议信元中并发送到上游，更新上游路由表，实现交换系统的自路由过程。
路由信息发送是通过目的芯片的识别码(Identifier，ID)号DST_ID作为行地址读取路由发送表，一般是从最小的目的芯片ID号开始读取，得到链路连接关系，根据该链路连接关系与当前链路的有效信号完成DR信息的计算。等到路由协议信元发送间隔计数器计时达到预设的发送间隔时，根据发送信元的版本号、计算出的DR信息、目的芯片ID号、源芯片级别、源芯片ID号及链路ID号等信息依次组装成符合定义的路由协议信元从当前链路发送出去。针对该目的芯片地址，从最小链路号LINK_ID＝0开始完成当前链路的路由协议信元发送操作后，跳转到下一条链路即LINK_ID＝LINK_ID+1号链路继续完成路由发送过程。当该目的芯片地址完成一轮LINK_ID的遍历后，再以DST_ID+1为行地址读取路由发送表，同样完成一轮LINK_ID的路由发送过程，如此循环完成整张路由发送表的路由协议信元产生和发送。
上述路由信息的发送方式，对于拔板操作异常或系统硬件环境异常等带来的有效信号下跳情形，系统不能及时响应该异常，会导致交换系统的大量的丢包，而且需要执行整张路由发送表的路由协议信元产生和发送操作，耗费大量的时间。
发明内容
本申请提供一种路由信息的处理方法、装置、设备及存储介质，可以降低交换系统的丢包率，并且提高路由信息处理的效率。
提供一种路由信息的处理方法，包括：
获取有效的目的芯片ID；依次根据所述目的芯片ID从路由发送表中获取源芯片与所述目的芯片间的链路连接关系，并根据所述链路连接关系处理所述目的芯片ID下的路由信息；当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID；跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
还提供一种路由信息的处理装置，包括：
有效目的芯片ID获取模块，设置为获取有效的目的芯片ID；第一路由信息处理模块，设置为依次根据所述目的芯片ID从路由发送表中获取源芯片与所述目的芯片间的链路连接关系，并根据所述链路连接关系处理所述目的芯片ID下的路由信息；有效信号下跳检测模块，设置为当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID；第二路由信息处理模块，设置为跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
还提供一种通信设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现上述的路由信息的处理方法。
还提供了一种存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时实现上述的路由信息的处理方法。
附图说明
图1为本申请实施例提供的一种路由信息的处理方法的流程图；
图2为本申请实施例提供的一种路由发送表的示意图；
图3为本申请实施例提供的一种单级交换系统的结构示意图；
图4为本申请实施例提供的另一种路由发送表的示意图；
图5为本申请实施例提供的一种路由信息的处理装置的结构示意图；
图6为本申请实施例提供的一种设备的结构示意图。
具体实施方式
下文中将结合附图对本申请的实施例进行说明。
在一个实施例中，图1为本申请实施例提供的一种路由信息的处理方法的流程图，本实施例适用于对路由信息进行处理的情况。本实施例可通过交换设备来实现。如图1所示，本实施例提供的方法包括S110-S140。
S110，获取有效的目的芯片ID。
S120，依次根据目的芯片ID从路由发送表中获取源芯片与目的芯片间的链路连接关系，并根据链路连接关系处理目的芯片ID下的路由信息。
S130，当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID。
S140，跳转处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
有效的目的芯片可以理解为在本应用场景下使用的芯片，目的芯片可以是交换接入(Switch Access，SA)芯片。本实施例中，目的芯片ID可以写为DST_ID。
在一个实施例中，获取有效的目的芯片ID的方式可以是：根据路由的物理连接信息确定无效的目的芯片；采用配置掩码的方式屏蔽无效的目的芯片ID。
无效的目的芯片可以是没有进行物理连接的目的芯片。将无效的目的芯片ID屏蔽掉后，就无需处理无效的目的芯片ID下的路由信息，从而提高路由收敛的效率。
在一个实施例中，路由发送表可以是预先设置或通过路由更新的方式建立的，图2为本申请实施例提供的一种路由发送表的示意图，如图2所示，路由发送表中每一行为目的芯片ID对应的链路连接关系，每一列为链路信息。
在一个实施例中，在获得有效的目的芯片ID后，按照ID号从小到大或从大到小的顺序依次将有效的目的芯片ID作为行地址读取路由表，获得当前有效的目的芯片ID下的链路连接关系，然后根据链路连接关系处理当前有效的目的芯片下的路由信息。
在一个实施例中，根据链路连接关系处理目的芯片ID下的路由信息的过程可以是：遍历目的芯片ID包含的链路；当遍历至当前链路时，生成当前链路的路由协议信元；将路由协议信元通过当前链路发送出去，并继续遍历下一个链路。
在一个实施例中，当遍历至当前链路LINK_ID时，根据当前链路的流量信息及链路连接关系计算获得DR信息，根据发送信元的版本号、计算出的DR信息、目的芯片ID号、源芯片级别、源芯片ID号及链路ID号等信息依次组装成符合定义的路由协议信元，并将路由协议信元通过当前链路发送出去。继续遍历下一个链路LINK_ID+1，直到遍历完当前目的芯片ID下的链路，当前目的芯片ID下的路由信息处理完成。
在一个实施例中，有效信号下跳可以是由拔板操作异常或者硬件环境异常带来的。当检测到有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID，若当前目的芯片ID下的路由信息未处理完，则继续处理当前目的芯片ID下的路由信息，直到当前目的芯片ID下的路由信息处理完成。
在一个实施例中，若检测到发生有效信号下跳的链路有一个，则当前目的芯片ID下的路由信息处理完成后，跳转处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
在一个实施例中，在跳转处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息之后，还包括如下步骤：发生有效信号下跳的链路所在的目的芯片ID下的路由信息处理完成后，继续处理发生有效信号下跳的链路所在的目的芯片的下一个有效的目的芯片ID下的路由信息。
在一个实施例中，若检测到发生有效信号下跳的链路有多个，则创建设定深度的缓存；将未处理的发生有效信号下跳的链路所在的目的芯片ID存储至缓存中。
多个发生有效信号下跳的链路可以是同时检测到，也可以不是同时检测到的。例如：可以是在处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息时，检测到另一个有效信号下跳。设定深度可以由链路数量确定。
在一个实施例中，将未处理的发生有效信号下跳的链路所在的目的芯片ID存储至缓存中，跳转按照目的芯片ID从小到大的顺序依次处理缓存中的目的芯片ID下的路由信息。本实施例中，先处理下跳链路对应的DST_ID最小的那一个，其它的亦按照DST_ID地址大小的顺序逐个处理。
在一个实施例中，在跳转处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息之前，还包括如下步骤：若当前目的芯片ID下的路由信息未处理完，则继续处理当前目的芯片ID下的路由信息，直到当前目的芯片ID下的路由信息处理完成后。
在一个实施例中，在获取发生有效信号下跳的链路所在的目的芯片ID之后，还包括如下步骤：判断发生有效信号下跳的链路所在的目的芯片在当前周期是否为首次发生有效信号下跳；若发生有效信号下跳的链路所在的目的芯片在当前周期不为首次发生有效信号下跳，则忽略此次有效信号下跳。在当前目的芯片ID下的路由信息处理完成后，继续处理当前目的芯片的下一个有效的目的芯片ID下的路由信息。这样是为了保证在一个周期内，同一个目的芯片ID只能被中断处理一次。
在一个实施例中，缓存中的所有目的芯片ID下的路由信息处理完成后，继续处理缓存中最后一个目的芯片的下一个有效的目的芯片ID下的路由信息。
示例性的，图3为本申请实施例提供的一种单级交换系统的结构示意图，如图3所示，包括4个有效目的芯片，其DST_ID分别为0、1、1021和1023，两个交换单元，交换单元0#和交换单元12#。交换系统中交换单元0#和交换单 元12#各自有一条链路与4个目的芯片连接。在系统路由信息更新后，交换单元0#建立的路由发送表如图4所示，黑色框内的路由发送表行表示交换单元0#与DST_ID为0、1、1021、1023的SA芯片之间有效的链接通路，其他为全0的行则表示交换单元0#与对应地址的目的芯片无有效链接通路。交换单元0#在路由信息处理过程中，用掩码掩去实际应用场景中不使用的DST_ID，当有效信号下跳时采用中断DST_ID地址跳转的方式去响应处理，其处理过程按如下步骤进行处理：
步骤1：以DST_ID＝0为行地址读取路由发送表，得到去往该DST_ID的链路连接关系。从LINK_ID＝0开始完成路由协议信元的产生和发送操作。该链路完成后跳转到LINK_ID＝LINK_ID+1号链路继续完成路由协议信元的产生和发送过程。当完成LINK_ID＝191号链路的处理过程后即完成了DST_ID＝0地址的所有链路路由协议信元的发送。
步骤2：以DST_ID＝1为行地址读取路由发送表完成该DST_ID下的路由信元发送过程。然后再分别以DST_ID＝1021、DST_ID＝1023为行地址重复上述过程。
步骤3：在步骤1中，若检测到DST_ID＝1021发生有效信号下跳，在完成步骤1后立即跳转到DST_ID＝1021进行处理。在DST_ID＝1021下所有链路路由协议信元完毕后，接着以DST_ID＝1023为行地址读取路由发送表完成路由协议信元的产生和发送，而不进行地址回跳到DST_ID＝1进行处理。
步骤4：在步骤3中检测到链路下跳时又检测到有其它链路发生有效信号下跳，根据链路号的最大的值设置一深度为192的缓存来存放没有处理的DST_ID，且同一个DST_ID只能被中断处理一次，然后按照DST_ID地址大小的顺序逐个处理。对于同时检测到有多条链路的链路有效(Link Valid，LV)信号下跳的情形，先处理下跳链路对应的DST_ID最小的那一个，其它的亦按照DST_ID地址大小的顺序逐个处理。
在一个实施例中，图5为本申请实施例提供的一种路由信息的处理装置的结构示意图。如图5所示，该装置包括：有效目的芯片ID获取模块210，第一路由信息处理模块220，有效信号下跳检测模块230和第二路由信息处理模块240。
有效目的芯片ID获取模块210，设置为获取有效的目的芯片ID；第一路由信息处理模块220，设置为依次根据所述目的芯片ID从路由发送表中获取源芯片与所述目的芯片间的链路连接关系，并根据所述链路连接关系处理所述目的芯片ID下的路由信息；有效信号下跳检测模块230，设置为当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID；第二路由 信息处理模块240，设置为跳转处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
在一个实施例中，有效的目的芯片ID获取模块210，还设置为：
根据路由的物理连接信息确定无效的目的芯片；采用配置掩码的方式屏蔽所述无效的目的芯片。
在一个实施例中，还包括：
若检测到发生有效信号下跳的链路有一个且当前目的芯片ID下的路由信息未处理完，则继续处理当前目的芯片ID下的路由信息，直到当前目的芯片ID下的路由信息处理完成后。
在一个实施例中，有效信号下跳检测模块230，还设置为：
若检测到发生有效信号下跳的链路有多个，则创建设定深度的缓存；将未处理的发生有效信号下跳的链路所在的目的芯片ID存储至所述缓存中。
在一个实施例中，第二路由信息处理模块240，还设置为：
跳转按照目的芯片ID从小到大的顺序依次处理所述缓存中的目的芯片下的路由信息。
在一个实施例中，在获取发生有效信号下跳的链路所在的目的芯片ID之后，还包括：
判断发生有效信号下跳的链路所在的目的芯片在当前周期是否为首次发生有效信号下跳；若发生有效信号下跳的链路所在的目的芯片在当前周期不为首次发生有效信号下跳，则忽略此次有效信号下跳。
在一个实施例中，在跳转处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息之后，还包括：
发生有效信号下跳的链路所在的目的芯片ID下的路由信息处理完成后，继续处理发生有效信号下跳的链路所在的目的芯片的下一个有效的目的芯片ID下的路由信息。
在一个实施例中，第一路由信息处理模块220，还设置为：
遍历所述目的芯片ID包含的链路；当遍历至当前链路时，生成所述当前链路的路由协议信元；将所述路由协议信元通过所述当前链路发送出去，并继续遍历下一个链路。
图6为本申请实施例提供的一种设备的结构示意图。如图6所示，本申请提供的设备，包括：处理器310以及存储器320。该设备中处理器310的数量可 以是一个或者多个，图6中以一个处理器310为例。该设备中存储器320的数量可以是一个或者多个，图6中以一个存储器320为例。该设备的处理器310以及存储器320可以通过总线或者其他方式连接，图6中以通过总线连接为例。实施例中，该设备为接收端。其中，接收端可以为调度节点、基站或用户设备(User Equipment，UE)中的其中一个。
存储器320作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请任意实施例的设备对应的程序指令/模块(例如，路由信息的处理装置中的有效目的芯片ID获取模块210、第一路由信息处理模块220、有效信号下跳检测模块230和第二路由信息处理模块240)。存储器320可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据设备的使用所创建的数据等。此外，存储器320可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实例中，存储器320可包括相对于处理器310远程设置的存储器，这些远程存储器可以通过网络连接至设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
上述提供的设备可设置为执行上述任意实施例提供的应用于路由信息的处理方法，具备相应的功能和效果。
对应存储器320中存储的程序可以是本申请实施例所提供应用于路由信息的处理方法对应的程序指令/模块，处理器310通过运行存储在存储器320中的软件程序、指令以及模块，从而执行计算机设备的一种或多种功能应用以及数据处理，即实现上述方法实施例中应用于路由信息的处理法。上述设备为接收端时，可执行本申请任意实施例所提供的应用于路由信息的处理方法，且具备相应的功能和效果。其中，设备可以为基站或UE中的其中一个。
本申请实施例还提供一种包含计算机可执行指令的存储介质，计算机可执行指令在由计算机处理器执行时用于执行一种路由信息的处理方法，该方法包括：获取有效的目的芯片ID；依次根据所述目的芯片ID从路由发送表中获取源芯片与所述目的芯片间的链路连接关系，并根据所述链路连接关系处理所述目的芯片ID下的路由信息；当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID，并继续处理当前目的芯片ID下的路由信息；当前目的芯片ID下的路由信息处理完成后，跳转处理发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
术语用户设备涵盖任何适合类型的无线用户设备，例如移动电话、便携数据处理装置、便携网络浏览器或车载移动台。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构(Instruction Set Architecture，ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(Read-Only Memory，ROM)、随机访问存储器(Random Access Memory，RAM)、光存储器装置和系统(数码多功能光碟(Digital Video Disc，DVD)或光盘(Compact Disk，CD))等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号处理器(Digital Signal Processing，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑器件(Field-Programmable Gate Array，FPGA)以及基于多核处理器架构的处理器。

Claims (11)

  1. 一种路由信息的处理方法，包括：
    获取有效的目的芯片识别码ID；
    依次根据所述目的芯片ID从路由发送表中获取源芯片与所述目的芯片间的链路连接关系，并根据所述链路连接关系处理所述目的芯片ID下的路由信息；
    当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID；
    跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
  2. 根据权利要求1所述的方法，其中，获取有效的目的芯片ID，包括：
    根据路由的物理连接信息确定无效的目的芯片；
    采用配置掩码的方式屏蔽所述无效的目的芯片ID以获取所述有效的目的芯片ID。
  3. 根据权利要求1所述的方法，在所述跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息之前，还包括：
    在当前目的芯片ID下的路由信息未处理完的情况下，继续处理所述当前目的芯片ID下的路由信息，直到所述当前目的芯片ID下的路由信息处理完成。
  4. 根据权利要求1所述的方法，其中，所述当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID，包括：
    在检测到发生有效信号下跳的链路有多个的情况下，创建设定深度的缓存；
    将未处理的发生有效信号下跳的链路所在的目的芯片ID存储至所述缓存中。
  5. 根据权利要求4所述的方法，其中，所述跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息，包括：
    跳转按照目的芯片ID从小到大的顺序依次处理所述缓存中的目的芯片ID下的路由信息。
  6. 根据权利要求1所述的方法，在所述获取发生有效信号下跳的链路所在的目的芯片ID之后，还包括：
    判断所述发生有效信号下跳的链路所在的目的芯片在当前周期是否为首次发生有效信号下跳；响应于所述发生有效信号下跳的链路所在的目的芯片在当前周期不为首次发生有效信号下跳，忽略所述有效信号下跳。
  7. 根据权利要求1所述的方法，在所述跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息之后，还包括：
    在所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息处理完成后，继续处理所述发生有效信号下跳的链路所在的目的芯片ID的下一个有效的目的芯片ID下的路由信息。
  8. 根据权利要求1-7任一项所述的方法，其中，所述根据所述链路连接关系处理所述目的芯片ID下的路由信息，包括：
    遍历所述目的芯片ID包含的链路；
    在遍历至当前链路的情况下，生成所述当前链路的路由协议信元；
    将所述路由协议信元通过所述当前链路发送出去，并继续遍历所述当前链路的下一个链路。
  9. 一种路由信息的处理装置，包括：
    有效目的芯片识别码ID获取模块，设置为获取有效的目的芯片ID；
    第一路由信息处理模块，设置为依次根据所述目的芯片ID从路由发送表中获取源芯片与所述目的芯片间的链路连接关系，并根据所述链路连接关系处理所述目的芯片ID下的路由信息；
    有效信号下跳检测模块，设置为当检测到链路发生有效信号下跳时，获取发生有效信号下跳的链路所在的目的芯片ID；
    第二路由信息处理模块，设置为跳转处理所述发生有效信号下跳的链路所在的目的芯片ID下的路由信息。
  10. 一种通信设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，其中，所述处理器执行所述程序时实现如权利要求1-8中任一项所述的路由信息的处理方法。
  11. 一种计算机可读存储介质，存储有计算机程序，其中，所述程序被处理器执行时实现如权利要求1-8中任一项所述的路由信息的处理方法。
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