WO2021196342A1 - 一种 goa 电路及显示装置 - Google Patents

一种 goa 电路及显示装置 Download PDF

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Publication number
WO2021196342A1
WO2021196342A1 PCT/CN2020/089126 CN2020089126W WO2021196342A1 WO 2021196342 A1 WO2021196342 A1 WO 2021196342A1 CN 2020089126 W CN2020089126 W CN 2020089126W WO 2021196342 A1 WO2021196342 A1 WO 2021196342A1
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Prior art keywords
goa
numbered
odd
rows
trigger signal
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Ceased
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PCT/CN2020/089126
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English (en)
French (fr)
Inventor
石龙强
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/969,248 priority Critical patent/US20230144279A1/en
Publication of WO2021196342A1 publication Critical patent/WO2021196342A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time

Definitions

  • This application relates to the field of display technology, and in particular to a GOA circuit and a display device.
  • AMOLED In the AMOLED display device, the light-emitting performance of the OLED will change due to the long-term influence of the electrical stress on the thin film transistor. Therefore, AMOLED needs to be compensated.
  • One of the compensation methods is to add an external compensation circuit for external compensation during shutdown.
  • the technology for achieving a narrow frame is mainly GOA technology.
  • GOA Global System for Mobile Communications
  • the current existing technology uses multiple clock signals to control GOA to increase the charging time, but there is overlap between the waveforms of adjacent G(n) signals, and the G(n) signal waveform is required when shutting down for external compensation. There must be no overlap, otherwise the correct signal cannot be read. Therefore, it is necessary to improve this defect.
  • This application provides a GOA circuit, which is used to solve the technical problem that the GOA circuit in the prior art cannot be compatible with multiple clock signals in controlling the GOA drive and external compensation.
  • the embodiment of the present application provides a GOA circuit for providing a line scan driving signal and a driving signal of a compensation circuit to a display panel, and includes a cascaded multi-row GOA unit, at least four clock signal lines, and a first start trigger signal line.
  • each row of GOA units in the plurality of rows of GOA units is respectively connected to one of the at least four clock signal lines.
  • the multiple rows of GOA units are divided into odd-numbered rows of GOA units and even-numbered rows of GOA units, and the first GOA unit of the odd-numbered rows of GOA units is connected to the first start trigger signal line.
  • the GOA unit of the odd row starts to work, and the GOA unit of the even row is reset; when When the waveform of the first initial trigger signal corresponds to an even-numbered frame, the GOA units in the even-numbered rows start to work, and the GOA units in the odd-numbered rows are reset.
  • the clock signal line corresponding to the GOA unit of the odd row provides a pulse signal in the odd frame
  • the GOA unit of the even row corresponds to the
  • the clock signal line provides a low-level signal in the odd-numbered frame
  • the clock signal line corresponding to the GOA unit in the odd-numbered row provides a low-level signal in the even-numbered frame
  • the clock signal corresponding to the GOA unit in the even-numbered row The line provides pulse signals in even-numbered frames.
  • the cascading manner of the multiple rows of GOA units is: GOA units in odd rows and GOA units in odd rows are cascaded; GOA units in even rows and GOA units in even rows cascade.
  • a GOA circuit provided by an embodiment of the present application, it further includes a second initial trigger signal line, wherein the second GOA unit in the even-numbered rows of GOA units is connected to the second initial trigger signal line.
  • the second initial trigger signal provided by the second initial trigger signal line corresponds to an even-numbered frame
  • the first initial trigger signal corresponds to an odd-numbered frame
  • An embodiment of the present application provides a display device, including a display panel and a GOA circuit disposed on the display panel.
  • the GOA circuit is used to provide the display panel with a line scan driving signal and a compensation circuit driving signal.
  • the GOA circuit includes multiple rows of cascaded GOA units, at least four clock signal lines, and a first start trigger signal line. Wherein, each row of GOA units in the plurality of rows of GOA units is respectively connected to one of the at least four clock signal lines.
  • the multiple rows of GOA units are divided into odd-numbered rows of GOA units and even-numbered rows of GOA units, and the first GOA unit of the odd-numbered rows of GOA units is connected to the first start trigger signal line.
  • the GOA unit of the odd row starts to work, and the GOA unit of the even row is reset; when When the waveform of the first initial trigger signal corresponds to an even-numbered frame, the GOA units in the even-numbered rows start to work, and the GOA units in the odd-numbered rows are reset.
  • the clock signal line corresponding to the GOA unit of the odd-numbered row provides a pulse signal in the odd-numbered frame
  • the GOA unit of the even-numbered row corresponds to the
  • the clock signal line provides a low-level signal in the odd-numbered frame
  • the clock signal line corresponding to the GOA unit in the odd-numbered row provides a low-level signal in the even-numbered frame
  • the clock signal corresponding to the GOA unit in the even-numbered row The line provides pulse signals in even-numbered frames.
  • the cascading manner of the multiple rows of GOA units is: GOA units in odd rows and GOA units in odd rows are cascaded; GOA units in even rows and GOA units in even rows cascade.
  • the GOA circuit further includes a second start trigger signal line, wherein the second GOA unit in the even-numbered row of GOA units and the second start trigger The signal line is connected.
  • the second initial trigger signal provided by the second initial trigger signal line corresponds to an even-numbered frame
  • the first initial trigger signal corresponds to an odd-numbered frame
  • the GOA units in the odd rows are controlled to start working, and the GOA units in the even rows are reset ;
  • the waveform of the first initial trigger signal corresponds to an even-numbered frame
  • the GOA unit in the even-numbered row is controlled to start working, and the GOA unit in the odd-numbered row is reset, so that the G(n) waveform output by the GOA does not overlap and can solve multiple clock signals
  • FIG. 1 is a schematic diagram of the driving structure of the GOA circuit provided in the first embodiment of the application
  • FIG. 2 is a timing waveform diagram of the clock signal corresponding to the compensation phase provided in the first embodiment of the application;
  • 3 is a timing waveform diagram of the driving signal G(n) provided in the first embodiment of the application corresponding to the compensation stage;
  • FIG. 4 is a schematic diagram of the driving architecture of the GOA circuit provided in the second embodiment of the application.
  • FIG. 6 is a timing waveform diagram of the driving signal G(n) provided in the second embodiment of the application corresponding to the compensation stage.
  • the embodiment of the present application provides a GOA circuit for providing a row scan driving signal G(n) and a driving signal G(n) of a compensation circuit to a display panel.
  • the GOA circuit includes multiple rows of cascaded GOA units, at least four clock signal lines, And the first start trigger signal line.
  • the first start trigger signal provided by the first start trigger signal line controls the multi-row GOA unit to turn on, and the clock signals provided by the at least four clock signal lines control the output of the multi-row GOA unit.
  • each row of GOA units in the plurality of rows of GOA units is respectively connected to one of the at least four clock signal lines.
  • the multiple rows of GOA units are divided into odd-numbered rows of GOA units and even-numbered rows of GOA units, and the first GOA unit of the odd-numbered rows of GOA units is connected to the first start trigger signal line.
  • the GOA unit of the odd row starts to work, and the GOA unit of the even row is reset; when When the waveform of the first initial trigger signal corresponds to an even-numbered frame, the GOA units in the even-numbered rows start to work, and the GOA units in the odd-numbered rows are reset.
  • the GOA circuit includes four rows of cascaded GOA units, four clock signal lines, and a first start trigger signal line. Wherein, each row of GOA units in the four rows of GOA units is respectively connected to one of the four clock signal lines.
  • the four rows of GOA units are divided into odd rows of GOA units and even rows of GOA units, and the first GOA unit 101 of the odd rows of GOA units is connected to the first start trigger signal line.
  • this embodiment takes four rows of GOA units and four clock signal lines as an example. In other embodiments, there may be more than four rows of GOA units and four or more clock signal lines.
  • the first start trigger signal STV1 provided by the first start trigger signal line controls the first GOA unit 101 in the odd-numbered rows of GOA units to be turned on, and the clock signal CK1 provided by the four clock signal lines CK2, CK3 and CK4 respectively control the output of the four rows of GOA units.
  • the cascading mode of the four rows of GOA units is series, that is, any row of GOA units is triggered by the output signal of the GOA unit of the previous row, and the first GOA unit 101 is started by the first GOA unit.
  • the trigger signal STV1 triggers.
  • the GOA unit of the odd row starts to work, and the GOA of the even row The unit is reset; when the waveform of the first start trigger signal STV1 corresponds to an even-numbered frame, the GOA unit of the even-numbered row starts to work, and the GOA unit of the odd-numbered row is reset.
  • the clock signal provided in the first embodiment of the present application corresponds to the timing waveform diagram of the compensation phase.
  • the clock signal lines CK1 and CK3 corresponding to the odd-numbered rows of GOA units are A pulse signal is provided during a frame, and the clock signal lines CK2 and CK4 corresponding to the GOA unit in the even-numbered row provide a low-level signal in an odd-numbered frame; the clock signal lines CK1, CK3 corresponding to the GOA unit in the odd-numbered row A low-level signal is provided in an even-numbered frame, and the clock signal lines CK2 and CK4 corresponding to the GOA unit of the even-numbered row provide a pulse signal in an even-numbered frame.
  • this embodiment takes two refresh frequencies as an example, that is, two frames.
  • the driving signal G(n) provided in the first embodiment of the present application corresponds to the timing waveform diagram of the compensation phase.
  • the driving signals G1 and G3 output by the GOA units of the odd rows are The odd-numbered frame is a pulse signal (start to work), and the driving signals G2 and G4 output by the GOA unit of the even-numbered row are low-level signals (reset) in the odd-numbered frame; the driving signal output by the GOA unit of the odd-numbered row G1 and G3 are low-level signals (reset) in even-numbered frames, and the driving signals G2 and G4 output by the GOA units of the even-numbered rows are pulse signals (starting to work) in even-numbered frames.
  • the compensation method of the GOA circuit provided in the first embodiment of the present application adopts a method of sequential compensation of odd and even lines, that is, the method of "compensating odd lines for odd frames and compensating even lines for even frames" alternately in turn. Since the G(n) waveforms of the odd-numbered rows and the even-numbered rows are not overlapped, external compensation can be performed effectively, that is, the problem of incompatibility between multiple clock signal drives and external compensation is solved.
  • the GOA circuit It includes four rows of cascaded GOA units, four clock signal lines, a first start trigger signal line, and a second start trigger signal line. Wherein, each row of GOA units in the four rows of GOA units is respectively connected to one of the four clock signal lines.
  • the four rows of GOA units are divided into odd rows of GOA units and even rows of GOA units.
  • the first GOA unit 401 of the odd rows of GOA units is connected to the first start trigger signal line, and the even rows of GOA units
  • the second GOA unit 402 in the GOA unit is connected to the second start trigger signal line.
  • this embodiment takes four rows of GOA units and four clock signal lines as an example. In other embodiments, there may be more than four rows of GOA units and four or more clock signal lines.
  • the first start trigger signal STV1 provided by the first start trigger signal line controls the first GOA unit 401 in the odd-numbered rows of GOA units to turn on
  • the second start trigger signal line provides The second start trigger signal STV2 controls the second GOA unit 402 in the even rows of GOA units to turn on
  • the clock signals CK1, CK2, CK3, CK4 provided by the four clock signal lines control the four rows of GOA respectively The output of the unit.
  • the cascading manner of the four-row GOA units is that the GOA units of the odd rows are cascaded with the GOA units of the odd rows; the GOA units of the even rows are cascaded with the GOA units of the even rows. That is: GOA units in any row are triggered by the output signals of GOA units spaced one row above it.
  • the first GOA unit 401 is triggered by the first start trigger signal STV1; the second GOA unit 402 is triggered by the second start trigger signal STV2.
  • the GOA unit of the odd row starts to work, and the GOA of the even row The unit is reset; when the waveform of the first start trigger signal STV1 corresponds to an even-numbered frame, the GOA unit of the even-numbered row starts to work, and the GOA unit of the odd-numbered row is reset.
  • the clock signal provided in the second embodiment of the present application corresponds to the timing waveform diagram of the compensation phase.
  • the waveform of the clock signal is consistent with the waveform of the normal working phase, and both provide pulse signals.
  • the first start trigger signal STV1 provided by the first start trigger signal line corresponds to an odd frame
  • the second start trigger signal STV2 provided by the second start trigger signal line corresponds to an even frame.
  • the driving signal G(n) provided in the second embodiment of the present application corresponds to the timing waveform diagram of the compensation phase.
  • the driving signals G1 and G3 output by the GOA units of the odd rows are The odd-numbered frame is a pulse signal (start to work), and the driving signals G2 and G4 output by the GOA unit of the even-numbered row are low-level signals (reset) in the odd-numbered frame; the driving signal output by the GOA unit of the odd-numbered row G1 and G3 are low-level signals (reset) in even-numbered frames, and the driving signals G2 and G4 output by the GOA units of the even-numbered rows are pulse signals (starting to work) in even-numbered frames.
  • the compensation method of the GOA circuit provided in the second embodiment of the present application is to use two start trigger signals STV1 and STV2 to control the opening of the GOA units of the odd and even rows, respectively.
  • the first start trigger signal STV1 is connected to the first GOA unit
  • the second start trigger signal STV2 is connected to the second GOA unit, so that STV1 can control odd rows (CK1, CK3) and STV2 can control even rows (CK2, CK4).
  • An embodiment of the present application provides a display device, including a display panel and a GOA circuit disposed on the display panel.
  • the GOA circuit is used to provide the display panel with a line scan driving signal and a compensation circuit driving signal.
  • the GOA circuit includes multiple rows of cascaded GOA units, at least four clock signal lines, and a first start trigger signal line. Wherein, each row of GOA units in the plurality of rows of GOA units is respectively connected to one of the at least four clock signal lines.
  • the multiple rows of GOA units are divided into odd-numbered rows of GOA units and even-numbered rows of GOA units, and the first GOA unit of the odd-numbered rows of GOA units is connected to the first start trigger signal line.
  • the GOA unit of the odd row starts to work, and the GOA unit of the even row is reset; when When the waveform of the first initial trigger signal corresponds to an even-numbered frame, the GOA units in the even-numbered rows start to work, and the GOA units in the odd-numbered rows are reset.
  • the specific working mode is consistent with the above-mentioned Embodiment 1 and Embodiment 2, and will not be repeated here.
  • the display device provided by the embodiment of the present application may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital camera, a navigator, and the like.
  • the GOA unit in the odd row is controlled to start working.
  • the GOA unit of the even-numbered row is reset; when the waveform of the first initial trigger signal corresponds to the even-numbered frame, the GOA unit of the even-numbered row is controlled to start working, and the GOA unit of the odd-numbered row is reset, so that the G(n) waveform output by the GOA does not overlap

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  • Physics & Mathematics (AREA)
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Abstract

一种GOA电路，包括级联的多行GOA单元、至少四条时钟信号线(CK1,CK2,CK3,CK4)、以及第一起始触发信号线。多行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，第一GOA单元(101,401)与第一起始触发信号线相连。

Description

一种GOA电路及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种GOA电路及显示装置。
 背景技术
在AMOLED显示装置中，由于薄膜晶体管长期受到电学应力的影响，OLED的发光性能会发生改变。所以，AMOLED需要进行补偿。其中一种补偿方式就是增加一个外部补偿电路以便在关机时进行外部补偿。
目前实现窄边框的技术主要为GOA技术，在大尺寸高刷新频率下，GOA输出的G(n)波形受到影响，不能正常驱动栅极，从而影响显示。目前的现有技术采用多个时钟信号控制GOA的方案增加充电时间，但相邻的G(n)信号的波形之间有重叠，而在关机进行外部补偿时，要求G(n)信号的波形不能有重叠，否则无法读取到正确信号。故，有必要改善这一缺陷。
 技术问题
本申请提供了一种GOA电路，用于解决现有技术的GOA电路，多个时钟信号在控制GOA驱动与外部补偿两者不能兼容的技术问题。
 技术解决方案
本申请实施例提供一种GOA电路，用于给显示面板提供行扫描驱动信号以及补偿电路的驱动信号，包括级联的多行GOA单元、至少四条时钟信号线、以及第一起始触发信号线。其中，所述多行GOA单元中的每一行GOA单元均分别与所述至少四条时钟信号线中的一条时钟信号线相连。所述多行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元与所述第一起始触发信号线相连。其中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。
在本申请实施例提供的一种GOA电路中，在补偿阶段，所述奇数行的GOA单元对应的所述时钟信号线在奇数帧时提供脉冲信号，所述偶数行的GOA单元对应的所述时钟信号线在奇数帧时提供低电平信号；所述奇数行的GOA单元对应的所述时钟信号线在偶数帧时提供低电平信号，所述偶数行的GOA单元对应的所述时钟信号线在偶数帧时提供脉冲信号。
在本申请实施例提供的一种GOA电路中，所述多行GOA单元的级联方式为：奇数行的GOA单元与奇数行的GOA单元级联；偶数行的GOA单元与偶数行的GOA单元级联。
在本申请实施例提供的一种GOA电路中，还包括第二起始触发信号线，其中，所述偶数行的GOA单元中的第二GOA单元与所述第二起始触发信号线相连。
在本申请实施例提供的一种GOA电路中，在补偿阶段，所述第二起始触发信号线提供的第二起始触发信号对应偶数帧，所述第一起始触发信号对应奇数帧。
本申请实施例提供一种显示装置，包括显示面板以及设置于所述显示面板上的GOA电路，所述GOA电路用于给所述显示面板提供行扫描驱动信号以及补偿电路的驱动信号，所述GOA电路包括级联的多行GOA单元、至少四条时钟信号线、以及第一起始触发信号线。其中，所述多行GOA单元中的每一行GOA单元均分别与所述至少四条时钟信号线中的一条时钟信号线相连。所述多行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元与所述第一起始触发信号线相连。其中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。
在本申请实施例提供的一种显示装置中，在补偿阶段，所述奇数行的GOA单元对应的所述时钟信号线在奇数帧时提供脉冲信号，所述偶数行的GOA单元对应的所述时钟信号线在奇数帧时提供低电平信号；所述奇数行的GOA单元对应的所述时钟信号线在偶数帧时提供低电平信号，所述偶数行的GOA单元对应的所述时钟信号线在偶数帧时提供脉冲信号。
在本申请实施例提供的一种显示装置中，所述多行GOA单元的级联方式为：奇数行的GOA单元与奇数行的GOA单元级联；偶数行的GOA单元与偶数行的GOA单元级联。
在本申请实施例提供的一种显示装置中，所述GOA电路还包括第二起始触发信号线，其中，所述偶数行的GOA单元中的第二GOA单元与所述第二起始触发信号线相连。
在本申请实施例提供的一种显示装置中，在补偿阶段，所述第二起始触发信号线提供的第二起始触发信号对应偶数帧，所述第一起始触发信号对应奇数帧。
 有益效果
本申请提供的一种GOA电路，在补偿阶段，当第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，控制奇数行的GOA单元开始工作，偶数行的GOA单元进行复位；当第一起始触发信号的波形对应偶数帧时，控制偶数行的GOA单元开始工作，奇数行的GOA单元进行复位，可使得GOA输出的G(n)波形无重叠，可解决多个时钟信号在控制GOA驱动与外部补偿两者不能兼容的技术问题。
 附图说明
图1为本申请实施例一提供的GOA电路的驱动架构示意图；
图2为本申请实施例一提供的时钟信号对应于补偿阶段的时序波形图；
图3为本申请实施例一提供的驱动信号G(n)对应于补偿阶段的时序波形图；
图4为本申请实施例二提供的GOA电路的驱动架构示意图；
图5为本申请实施例二提供的时钟信号对应于补偿阶段的时序波形图；
图6为本申请实施例二提供的驱动信号G(n)对应于补偿阶段的时序波形图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例提供一种GOA电路，用于给显示面板提供行扫描驱动信号G(n)以及补偿电路的驱动信号G(n)，包括级联的多行GOA单元、至少四条时钟信号线、以及第一起始触发信号线。所述第一起始触发信号线提供的第一起始触发信号是控制所述多行GOA单元开启，所述至少四条时钟信号线提供的时钟信号是控制所述多行GOA单元的输出。
其中，所述多行GOA单元中的每一行GOA单元均分别与所述至少四条时钟信号线中的一条时钟信号线相连。所述多行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元与所述第一起始触发信号线相连。
其中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。此工作方式可避免G(n)波形重叠，导致外部补偿读取信号错误，导致的显示不良问题。
如图1所示，本申请实施例一提供的GOA电路的驱动架构示意图，从图中可以很直观地看到本电路的各组成部分，以及各组成部分之间的连接关系，所述GOA电路包括级联的四行GOA单元、四条时钟信号线、以及第一起始触发信号线。其中，所述四行GOA单元中的每一行GOA单元均分别与所述四条时钟信号线中的一条时钟信号线相连。所述四行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元101与所述第一起始触发信号线相连。
需要说明的是，本实施例是以四行GOA单元、四条时钟信号线为例，在其他实施例中，也可以是四行以上的GOA单元、四条以上的时钟信号线。
需要说明的是，所述第一起始触发信号线提供的第一起始触发信号STV1是控制所述奇数行的GOA单元中的第一GOA单元101开启，所述四条时钟信号线提供的时钟信号CK1、CK2、CK3、CK4是分别控制所述四行GOA单元的输出。
需要说明的是，所述四行GOA单元的级联方式是串联，即任一行GOA单元均是由其上一行的GOA单元的输出信号触发，而第一GOA单元101是由所述第一起始触发信号STV1触发。
在本实施例中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号STV1的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号STV1的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。
具体地，如图2所示，本申请实施例一提供的时钟信号对应于补偿阶段的时序波形图，在补偿阶段，所述奇数行的GOA单元对应的所述时钟信号线CK1、CK3在奇数帧时提供脉冲信号，所述偶数行的GOA单元对应的所述时钟信号线CK2、CK4在奇数帧时提供低电平信号；所述奇数行的GOA单元对应的所述时钟信号线CK1、CK3在偶数帧时提供低电平信号，所述偶数行的GOA单元对应的所述时钟信号线CK2、CK4在偶数帧时提供脉冲信号。需要说明的是，本实施例是以两个刷新频率为例，即两帧。
具体地，如图3所示，本申请实施例一提供的驱动信号G(n)对应于补偿阶段的时序波形图，在补偿阶段，所述奇数行的GOA单元输出的驱动信号G1、G3在奇数帧时为脉冲信号（开始工作），所述偶数行的GOA单元输出的驱动信号G2、G4在奇数帧时为低电平信号（进行复位）；所述奇数行的GOA单元输出的驱动信号G1、G3在偶数帧时为低电平信号（进行复位），所述偶数行的GOA单元输出的驱动信号G2、G4在偶数帧时为脉冲信号（开始工作）。
需要说明的是，由于像素关机补偿的驱动时间量级（毫秒量级）大于正常工作的驱动时间量级（微秒量级），所以关机补偿时的充电速度较快，充电时间足够，所以不需要G(n)波形交叠设计。
需要说明的是，本申请实施例一提供的GOA电路的补偿方式是采用奇偶行依次补偿的方法，即“奇数帧补偿奇数行、偶数帧补偿偶数行”的方式依次交替进行。由于奇数行和偶数行的G(n)波形没有交叠，外部补偿可以有效进行，即解决了多个时钟信号驱动与外部补偿不能兼容的问题。
如图4所示，本申请实施例二提供的GOA电路的驱动架构示意图，从图中可以很直观地看到本电路的各组成部分，以及各组成部分之间的连接关系，所述GOA电路包括级联的四行GOA单元、四条时钟信号线、第一起始触发信号线、以及第二起始触发信号线。其中，所述四行GOA单元中的每一行GOA单元均分别与所述四条时钟信号线中的一条时钟信号线相连。所述四行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元401与所述第一起始触发信号线相连，所述偶数行的GOA单元中的第二GOA单元402与所述第二起始触发信号线相连。
需要说明的是，本实施例是以四行GOA单元、四条时钟信号线为例，在其他实施例中，也可以是四行以上的GOA单元、四条以上的时钟信号线。
需要说明的是，所述第一起始触发信号线提供的第一起始触发信号STV1是控制所述奇数行的GOA单元中的第一GOA单元401开启，所述第二起始触发信号线提供的第二起始触发信号STV2是控制所述偶数行的GOA单元中的第二GOA单元402开启，所述四条时钟信号线提供的时钟信号CK1、CK2、CK3、CK4是分别控制所述四行GOA单元的输出。
需要说明的是，所述四行GOA单元的级联方式是奇数行的GOA单元与奇数行的GOA单元级联；偶数行的GOA单元与偶数行的GOA单元级联。即：任一行GOA单元均是由其上间隔一行的GOA单元的输出信号触发。而第一GOA单元401是由所述第一起始触发信号STV1触发；第二GOA单元402是由所述第二起始触发信号STV2触发。
在本实施例中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号STV1的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号STV1的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。
具体地，如图5所示，本申请实施例二提供的时钟信号对应于补偿阶段的时序波形图，在补偿阶段，所述时钟信号的波形与正常工作阶段的波形一致，均是提供脉冲信号，所述第一起始触发信号线提供的第一起始触发信号STV1对应奇数帧，所述第二起始触发信号线提供的第二起始触发信号STV2对应偶数帧。
具体地，请继续参阅图6，本申请实施例二提供的驱动信号G(n)对应于补偿阶段的时序波形图，在补偿阶段，所述奇数行的GOA单元输出的驱动信号G1、G3在奇数帧时为脉冲信号（开始工作），所述偶数行的GOA单元输出的驱动信号G2、G4在奇数帧时为低电平信号（进行复位）；所述奇数行的GOA单元输出的驱动信号G1、G3在偶数帧时为低电平信号（进行复位），所述偶数行的GOA单元输出的驱动信号G2、G4在偶数帧时为脉冲信号（开始工作）。
需要说明的是，本申请实施例二提供的GOA电路的补偿方式是采用两个起始触发信号STV1、STV2分别控制奇数行和偶数行的GOA单元的开启。第一起始触发信号STV1连接第一GOA单元，第二起始触发信号STV2连接第二GOA单元，这样可以实现STV1控制奇数行(CK1、CK3)，STV2控制偶数行(CK2、CK4)。
需要说明的是，当关机补偿时，奇数帧STV1打开，偶数帧STV2打开，其它信号不变，这样可以实现奇数帧奇数行的GOA单元开启，偶数帧偶数行的GOA单元开启。由于奇数行和偶数行的G(n)波形没有交叠，外部补偿可以有效进行，即解决了多个时钟信号驱动与外部补偿不能兼容的问题。
本申请实施例提供一种显示装置，包括显示面板以及设置于所述显示面板上的GOA电路，所述GOA电路用于给所述显示面板提供行扫描驱动信号以及补偿电路的驱动信号，所述GOA电路包括级联的多行GOA单元、至少四条时钟信号线、以及第一起始触发信号线。其中，所述多行GOA单元中的每一行GOA单元均分别与所述至少四条时钟信号线中的一条时钟信号线相连。所述多行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元与所述第一起始触发信号线相连。其中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。具体工作方式与上述实施例一和实施例二一致，在此不再赘述。
本申请实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相机、导航仪等任何具有显示功能的产品或部件。
综上所述，本申请实施例提供的一种GOA电路，在补偿阶段，当第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，控制奇数行的GOA单元开始工作，偶数行的GOA单元进行复位；当第一起始触发信号的波形对应偶数帧时，控制偶数行的GOA单元开始工作，奇数行的GOA单元进行复位，可使得GOA输出的G(n)波形无重叠，解决了现有技术的GOA电路，多个时钟信号控制GOA驱动与外部补偿不能兼容的技术问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (10)

  1. 一种GOA电路，用于给显示面板提供行扫描驱动信号以及补偿电路的驱动信号，其包括级联的多行GOA单元、至少四条时钟信号线、以及第一起始触发信号线；
    其中，所述多行GOA单元中的每一行GOA单元均分别与所述至少四条时钟信号线中的一条时钟信号线相连；
    所述多行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元与所述第一起始触发信号线相连；
    其中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。
  2. 如权利要求1所述的GOA电路，其中，在补偿阶段，所述奇数行的GOA单元对应的所述时钟信号线在奇数帧时提供脉冲信号，所述偶数行的GOA单元对应的所述时钟信号线在奇数帧时提供低电平信号；所述奇数行的GOA单元对应的所述时钟信号线在偶数帧时提供低电平信号，所述偶数行的GOA单元对应的所述时钟信号线在偶数帧时提供脉冲信号。
  3. 如权利要求1所述的GOA电路，其中，所述多行GOA单元的级联方式为：奇数行的GOA单元与奇数行的GOA单元级联；偶数行的GOA单元与偶数行的GOA单元级联。
  4. 如权利要求3所述的GOA电路，其中，还包括第二起始触发信号线，其中，所述偶数行的GOA单元中的第二GOA单元与所述第二起始触发信号线相连。
  5. 如权利要求4所述的GOA电路，其中，在补偿阶段，所述第二起始触发信号线提供的第二起始触发信号对应偶数帧，所述第一起始触发信号对应奇数帧。
  6. 一种显示装置，其包括显示面板以及设置于所述显示面板上的GOA电路，所述GOA电路用于给所述显示面板提供行扫描驱动信号以及补偿电路的驱动信号，所述GOA电路包括级联的多行GOA单元、至少四条时钟信号线、以及第一起始触发信号线；
    其中，所述多行GOA单元中的每一行GOA单元均分别与所述至少四条时钟信号线中的一条时钟信号线相连；
    所述多行GOA单元分为奇数行的GOA单元和偶数行的GOA单元，所述奇数行的GOA单元中的第一GOA单元与所述第一起始触发信号线相连；
    其中，在补偿阶段，当所述第一起始触发信号线提供的第一起始触发信号的波形对应奇数帧时，所述奇数行的GOA单元开始工作，所述偶数行的GOA单元进行复位；当所述第一起始触发信号的波形对应偶数帧时，所述偶数行的GOA单元开始工作，所述奇数行的GOA单元进行复位。
  7. 如权利要求6所述的显示装置，其中，在补偿阶段，所述奇数行的GOA单元对应的所述时钟信号线在奇数帧时提供脉冲信号，所述偶数行的GOA单元对应的所述时钟信号线在奇数帧时提供低电平信号；所述奇数行的GOA单元对应的所述时钟信号线在偶数帧时提供低电平信号，所述偶数行的GOA单元对应的所述时钟信号线在偶数帧时提供脉冲信号。
  8. 如权利要求6所述的显示装置，其中，所述多行GOA单元的级联方式为：奇数行的GOA单元与奇数行的GOA单元级联；偶数行的GOA单元与偶数行的GOA单元级联。
  9. 如权利要求8所述的显示装置，其中，所述GOA电路还包括第二起始触发信号线，其中，所述偶数行的GOA单元中的第二GOA单元与所述第二起始触发信号线相连。
  10. 如权利要求9所述的显示装置，其中，在补偿阶段，所述第二起始触发信号线提供的第二起始触发信号对应偶数帧，所述第一起始触发信号对应奇数帧。
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