WO2021185107A1 - 硬件电路故障注入测试方法、装置、设备、介质和系统 - Google Patents

硬件电路故障注入测试方法、装置、设备、介质和系统 Download PDF

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Publication number
WO2021185107A1
WO2021185107A1 PCT/CN2021/079539 CN2021079539W WO2021185107A1 WO 2021185107 A1 WO2021185107 A1 WO 2021185107A1 CN 2021079539 W CN2021079539 W CN 2021079539W WO 2021185107 A1 WO2021185107 A1 WO 2021185107A1
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fault
hardware circuit
tested
target
hardware
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PCT/CN2021/079539
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English (en)
French (fr)
Inventor
杨莉
李海波
王宗罡
隋建鹏
雷奥
王强
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中国第一汽车股份有限公司
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Publication of WO2021185107A1 publication Critical patent/WO2021185107A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

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  • This application relates to the technical field of automated testing, for example, to a hardware circuit fault injection testing method, device, equipment, medium, and system.
  • This application provides a hardware circuit fault injection test method, device, equipment, storage medium, and system, so as to realize the fault injection test of the hardware circuit and realize efficient hardware functional safety verification.
  • a hardware circuit fault injection test method including:
  • a hardware circuit fault injection test device which includes:
  • the fault instruction module is set to generate a fault generation instruction according to the preset fault information table
  • a fault generation module configured to control the relay card to generate a target fault in the hardware circuit to be tested according to the fault generation instruction
  • the information acquisition module is configured to acquire the fault information of the hardware circuit to be tested after the target fault is generated.
  • a device including:
  • One or more processors are One or more processors;
  • Memory set to store one or more programs
  • the one or more processors When the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned hardware fault injection test method.
  • a computer-readable storage medium is also provided, on which a computer program is stored, wherein the program is executed by a processor to implement the above-mentioned hardware fault injection test method.
  • a hardware fault injection test system which includes a hardware circuit to be tested, at least one relay card, and terminal equipment;
  • the hardware circuit to be tested is connected to the at least one relay card through a relay card interface
  • Each relay card is connected to the terminal device through a communication serial port, and is set to generate a hardware fault in the hardware circuit to be tested;
  • the terminal device is connected to the hardware circuit to be tested through a universal interface, and is configured to obtain fault information of the hardware circuit to be tested;
  • the terminal equipment includes the above hardware circuit fault injection test device.
  • FIG. 1 is a flowchart of the steps of a hardware circuit fault injection test method provided in Embodiment 1 of the present application;
  • FIG. 2 is a flow chart of the steps of a hardware circuit fault injection test method provided by the second embodiment of the present application.
  • Fig. 3 is a working example diagram of a fault generating element provided in the second embodiment of the present application.
  • FIG. 4 is an example diagram of a circuit for obtaining fault information provided by the second embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a hardware circuit fault injection test device provided in the third embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a device provided in Embodiment 4 of the present application.
  • FIG. 7 is a schematic structural diagram of a hardware circuit fault injection test system provided by Embodiment 6 of the present application.
  • FIG. 8 is an example diagram of a terminal device provided by Embodiment 6 of the present application.
  • Fig. 9 is a structural example diagram of a relay card provided in the sixth embodiment of the present application.
  • FIG. 1 is a flow chart of the steps of a hardware circuit fault injection test method provided in Embodiment 1 of the present application. This embodiment can be applied to the case of automated hardware circuit testing.
  • the method can be executed by a hardware circuit fault injection test device, which can be implemented in hardware and/or software, see Figure 1, which is provided in the embodiment of this application.
  • the method includes the following steps:
  • Step 101 Generate a fault generation instruction according to a preset fault information table.
  • the preset failure information table may be a storage table storing at least one type of hardware circuit failure.
  • the preset fault information table can store information such as the identification number, name, and fault description of the hardware circuit fault.
  • the preset fault information table can be stored in an Excel table.
  • the preset fault information table may also store fault generation instructions, and the identification numbers of hardware circuit faults may correspond to the fault generation instructions one-to-one.
  • the fault generation command corresponding to the fault can be found in the preset fault information table according to the circuit structure and circuit type of the hardware circuit to be tested, and one fault command or multiple fault commands can be determined in the preset fault information table.
  • the preset fault information table can be stored in the upper computer in the form of Excel, and the general symbol instruction code macro language (Visual beginnerer's All-purpose Symbolic Instruction Code for Applications, VBA) code can be used to find the preset The fault information table obtains the fault generation instruction.
  • Step 102 Control the relay card to generate a target fault in the hardware circuit to be tested according to the fault generation instruction.
  • the relay card can be a relay switch array, which can control the circuit in the hardware circuit to be tested to generate corresponding circuit faults, such as short circuit and open circuit, according to the fault generation instruction.
  • the hardware circuit to be tested can be a hardware circuit that needs to be tested, and can be a vehicle control circuit.
  • the target fault may be a fault that needs to be tested in the hardware circuit to be tested, the target fault may correspond to the circuit structure of the hardware circuit to be tested, and the corresponding target faults in different hardware circuits to be tested may be different.
  • the fault generation instruction can be sent to the relay card, and the control relay card can generate the corresponding target fault in the circuit to be tested.
  • the control relay card can generate the corresponding target fault in the circuit to be tested.
  • Step 103 Obtain fault information of the hardware circuit to be tested after the target fault is generated.
  • the fault information may be the information output by the hardware circuit under test after the target fault occurs, and may include power supply error information, processor error information, sensor error information, actuator error information, and so on.
  • It can be connected to the hardware circuit to be tested through the universal serial port to obtain the fault information of the hardware circuit to be tested that generates the target fault.
  • the technical solution of the embodiment of the present application generates a fault generation instruction according to a preset fault information table, controls the relay card to generate a target fault in the hardware circuit to be tested through the fault generation command, and obtains the feedback of the hardware circuit to be tested after the target fault is generated.
  • the fault information realizes the fault injection test of the hardware circuit, ensures the comprehensive coverage of the test process, and enhances the reliability of the hardware test, thereby improving the safety of the hardware circuit.
  • FIG. 2 is a flowchart of steps of a hardware circuit fault injection test method provided in the second embodiment of the present application.
  • the embodiment of the present application is described based on the foregoing embodiment. Referring to FIG. 2, the method of the embodiment of the present application includes the following steps:
  • Step 201 Generate a fault generation instruction according to a preset fault information table.
  • Step 202 Determine the target relay card corresponding to the fault generation instruction, and send the fault generation instruction to the target relay card.
  • the target relay card may be a relay card controlled by a fault generation instruction.
  • a fault generation instruction table can correspond to one target relay card or multiple relay cards.
  • the target address of the fault generation instruction can be obtained, the relay card corresponding to the target address can be used as the target relay card, and the fault generation instruction can be transmitted to the corresponding relay card according to the target address.
  • Step 203 Control the target relay card to generate a short-circuit and/or open-circuit target fault in the hardware circuit to be tested according to the fault generation instruction.
  • the fault generating element may be a hardware device that generates a circuit fault in the hardware circuit to be tested.
  • the fault generating element may be mounted in the hardware circuit to be tested, and a fault may be generated in the hardware circuit to be tested by opening and closing.
  • FIG. 3 is a working example diagram of a fault generating element provided in the second embodiment of the present application. Taking the fault generating component as the pin as an example, see Figure 3.
  • the hardware circuit to be tested can include sensors, resistors, main control chips, capacitors, and actuators. Multiple pins can be set in the hardware circuit to be tested. Perform failure control for the hardware circuit to be tested by inserting, so that a corresponding failure occurs in the hardware circuit to be tested.
  • the fault generating element can be controlled by the target relay card, so that the fault generating element generates a short circuit and/or open circuit in the hardware circuit to be tested, and causes the corresponding component element in the hardware circuit to be tested to malfunction.
  • the fault generating element includes at least one of a pin, a short-circuit jumper, and a relay card.
  • the pin and/or short-circuit jumper can be used to perform part of the manual test verification in the early stage of the automatic test, and the relay card is set to the automatic test.
  • Step 204 Obtain fault information of the hardware circuit to be tested after the target fault is generated.
  • FIG. 4 is an example diagram of a circuit for obtaining fault information provided in the second embodiment of the present application.
  • the circuit for obtaining fault information can be composed of a single-chip microcomputer, a controller area network (Controller Area Network, CAN) interface filter circuit, and a serial port level conversion chip. Standard 232, RS232)
  • the serial port sends commands to the hardware circuit under test to obtain the feedback fault information.
  • Step 205 Count the fault information to determine the test result of the hardware circuit to be tested.
  • the fault information can be counted, and the test results can be generated by classifying and counting according to different fault types.
  • different result scores can be determined according to the severity of the fault, and the test result can be determined by synthesizing the fault information of the hardware circuit to be tested.
  • the fault generation instruction is determined by a preset fault information table, the target relay card corresponding to each fault generation instruction is determined, and the fault generation instruction is sent to the target relay card, and each target relay card is controlled according to the fault.
  • Generate instructions to realize short-circuit or open circuit in the hardware circuit under test to generate the target fault obtain the fault information of the hardware circuit under test after the target fault is generated, and calculate the fault information to determine the test result of the hardware circuit under test, thereby realizing the hardware circuit Injection testing improves the comprehensiveness of hardware testing and improves the safety of hardware circuits.
  • FIG. 5 is a schematic structural diagram of a hardware circuit fault injection test device provided in the third embodiment of the application, which can execute the hardware circuit fault injection test method provided by any embodiment of the embodiment of the present application, and has the corresponding functional modules and effects of the execution method .
  • the device can be implemented by software and/or hardware, and includes: a fault instruction module 301, a fault generation module 302, and an information acquisition module 303.
  • the fault instruction module 301 is configured to generate a fault generation instruction according to a preset fault information table.
  • the fault generation module 302 is configured to control the relay card to generate a target fault in the hardware circuit to be tested according to the fault generation instruction.
  • the information acquisition module 303 is configured to acquire the fault information of the hardware circuit to be tested after the target fault is generated.
  • the fault instruction module presets the fault information table to generate the corresponding fault generation instruction
  • the fault generation module controls the relay card to generate the target fault in the hardware circuit to be tested according to the fault generation instruction
  • the information acquisition module acquires the generation target The fault information of the hardware circuit to be tested after the fault realizes the injection test of the hardware circuit, realizes the full fault coverage test, and improves the safety of the hardware circuit.
  • the fault generation module 302 includes:
  • the instruction sending unit is configured to determine the target relay card corresponding to the fault generation instruction, and send the fault generation instruction to the target relay card.
  • the fault generating unit is configured to control the target relay card to generate a short-circuit and/or open-circuit target fault in the hardware circuit to be tested according to the fault generation instruction.
  • the fault generating element in the fault generating module 302 includes at least one of a pin, a short-circuit jumper, and a relay card.
  • it further includes a result statistics module, which is configured to count the fault information to determine the test result of the hardware circuit to be tested.
  • FIG. 6 is a schematic structural diagram of a device provided in Embodiment 4 of the present application.
  • the device includes a processor 40, a memory 41, an input device 42 and an output device 43.
  • the number of processors 40 in the device may be one or more.
  • One processor 40 is taken as an example in FIG. 4.
  • the device processor 40, the memory 41, the input device 42, and the output device 43 may be connected by a bus or other methods. In FIG. 6, the connection by a bus is taken as an example.
  • the memory 41 can be configured to store software programs, computer-executable programs, and modules, such as the modules corresponding to the hardware circuit fault injection test in the embodiment of the present application (fault instruction module 301, fault generation module 302). And information acquisition module 303).
  • the processor 40 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 41, that is, realizes the above-mentioned hardware circuit fault injection test method.
  • the memory 41 may mainly include a program storage area and a data storage area.
  • the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created according to the use of the terminal, and the like.
  • the memory 41 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.
  • the memory 41 may include a memory remotely provided with respect to the processor 40, and these remote memories may be connected to the device through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the input device 42 may be configured to receive input numeric or character information, and to generate key signal input related to user settings and function control of the device.
  • the output device 43 may include a display device such as a display screen.
  • the fifth embodiment of the present application also provides a storage medium containing computer-executable instructions, which are used to execute a hardware circuit fault injection test method when the computer-executable instructions are executed by a computer processor, and the method includes:
  • An embodiment of the application provides a storage medium containing computer-executable instructions.
  • the computer-executable instructions are not limited to the method operations described above, and can also execute the hardware circuit fault injection test method provided by any embodiment of the application. Related operations.
  • this application can be implemented by software and necessary general-purpose hardware, or can be implemented by hardware.
  • the technical solution of this application can essentially be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access Memory (Random Access Memory, RAM), flash memory (FLASH), hard disk or optical disk, etc., including multiple instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the embodiments described in this application Methods.
  • ROM read-only memory
  • RAM random access Memory
  • FLASH flash memory
  • hard disk or optical disk etc.
  • FIG. 7 is a schematic structural diagram of a hardware circuit fault injection test system provided by Embodiment 6 of the present application. This embodiment can be applied to the case of automated hardware circuit testing.
  • the system of the embodiment of the present application includes: a hardware circuit 61 to be tested, a relay card 62 and a terminal device 63.
  • the hardware circuit under test 61 is connected to at least one relay card 62 through a relay card interface, and the relay card 62 is connected to the terminal device 63 through a communication serial port, wherein the relay card 62 is set to be in the hardware under test A hardware fault occurs in the circuit 61; the terminal device 63 is also connected to the hardware circuit under test 61 through a universal interface to obtain the fault information of the hardware circuit under test 61; wherein, the terminal device 63 includes the implementation of this application The hardware circuit fault injection test device described in any of the examples.
  • the hardware circuit under test 61 may be an enlarged hardware circuit, and may have the same hardware circuit as the device under test, and can realize the product function of the device under test.
  • the hardware circuit 61 to be tested may include a fault generating element, for example, it may include at least one pin holder and a short-circuit jumper.
  • the hardware circuit to be tested can produce different faults according to the control situation of the relay card to realize fault injection.
  • the relay card 62 may be a control circuit or a control device that controls the hardware circuit 61 to be tested to produce a fault.
  • the circuit 61 generates different failure modes, for example, controller failure or capacitor failure.
  • the terminal device 63 may be a device having any hardware fault injection test device provided in the embodiment of the present application, and may be, for example, an upper computer.
  • the terminal device 63 can store a preset fault information table, and can send commands through the serial port to generate a fault in the hardware circuit 61 to be tested, and obtain fault information.
  • FIG. 8 is an exemplary diagram of a terminal device provided in Embodiment 6 of the present application. Referring to Figure 8, the terminal device 63 can have a test result statistics function, and can realize fault generation commands through the Microsoft Communications Control (MScomm) control in Excel and VBA code, and realize the information interaction with the hardware circuit under test through the interface .
  • MScomm Microsoft Communications Control
  • the relay card 62 includes a serial port level conversion chip, a single-chip microcomputer, a relay group and pins; the serial port level conversion chip is connected through a transistor-transistor logic circuit (Transistor-Transistor Logic, TTL) serial port To the single-chip microcomputer, it is set to convert the obtained RS232 level standard signal into the TTL level standard signal corresponding to the single-chip microcomputer; the single-chip microcomputer is connected to the relay group and the pins in turn through the universal input and output ports, and is set as the control plug The needle has a fault in the hardware circuit to be tested.
  • TTL Transistor-Transistor Logic
  • the relay card 62 can essentially be a relay switch array, and the relay card 62 can have a single-chip microcomputer, which can receive control commands issued by the terminal device 63, so that the corresponding relays in the relay group can generate on and/or off actions, as an example, as shown in Figure 9.
  • the relay card 62 may be composed of a level conversion chip, a single-chip microcomputer, an input/output interface, and pins connected in sequence.
  • the relay group includes at least one of a horizontal relay group and a vertical relay group.
  • the arrangement of the relay groups in the relay card 62 may include horizontal relays and vertical relays.
  • the multiple units and modules included are only divided according to the functional logic, but are not limited to the above division, as long as the corresponding function can be realized; in addition, each function
  • the names of the units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

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Abstract

一种硬件电路故障注入测试方法、装置、设备、介质和系统。该硬件电路故障注入测试方法包括：根据预设故障信息表产生故障生成指令(101)；根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障(102)；获取生成所述目标故障后的所述待测硬件电路的故障信息(103)。

Description

硬件电路故障注入测试方法、装置、设备、介质和系统
本申请要求在2020年03月17日提交中国专利局、申请号为202010188315.9的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及自动化测试技术领域，例如涉及一种硬件电路故障注入测试方法、装置、设备、介质和系统。
背景技术
随着汽车领域中功能安全标准的推行，对汽车领域中硬件电路的功能安全提出了更高要求，例如，功能安全标准中对汽车安全完整性等级(Automotive Safety Integration Level，ASIL)D等级的汽车控制器明确提出了硬件电路故障注入测试的要求。然而，相关技术中还未对硬件故障注入测试进行说明和阐述，如何高效并且高执行度的对硬件电路进行故障注入测试，成为汽车领域内的研究重点。
发明内容
本申请提供一种硬件电路故障注入测试方法、装置、设备、存储介质和系统，以实现硬件电路的故障注入测试，实现高效的硬件功能安全验证。
提供了一种硬件电路故障注入测试方法，包括：
根据预设故障信息表产生故障生成指令；
根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障；
获取生成所述目标故障后的所述待测硬件电路的故障信息。
还提供了一种硬件电路故障注入测试装置，包括：
故障指令模块，设置为根据预设故障信息表产生故障生成指令；
故障生成模块，设置为根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障；
信息获取模块，设置为获取生成所述目标故障后的所述待测硬件电路的故障信息。
还提供了一种设备，包括：
一个或多个处理器；
存储器，设置为存储一个或多个程序；
当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现上述的硬件故障注入测试方法。
还提供了一种计算机可读存储介质，其上存储有计算机程序，其中，该程序被处理器执行时实现上述的硬件故障注入测试方法。
还提供了一种硬件故障注入测试系统，该系统包括待测硬件电路、至少一个继电器卡和终端设备；
所述待测硬件电路通过继电器卡接口与所述至少一个继电器卡连接；
每个继电器卡通过通信串口连接至所述终端设备，设置为在所述待测硬件电路中产生硬件故障；
所述终端设备通过通用接口连接至所述待测硬件电路，设置为获取所述待测硬件电路的故障信息；
其中，所述终端设备包括上述的硬件电路故障注入测试装置。
附图说明
图1是本申请实施例一提供的一种硬件电路故障注入测试方法的步骤流程图；
图2是本申请实施例二提供的一种硬件电路故障注入测试方法的步骤流程图；
图3是本申请实施例二提供的一种故障产生元件的工作示例图；
图4是本申请实施例二提供的一种获取故障信息的电路示例图；
图5是本申请实施例三提供的一种硬件电路故障注入测试装置的结构示意图；
图6是本申请实施例四提供的一种设备的结构示意图；
图7是本申请实施例六提供的一种硬件电路故障注入测试系统的结构示意图；
图8是本申请实施例六提供的一种终端设备的示例图；
图9是本申请实施例六提供的一种继电器卡的结构示例图。
具体实施方式
下面结合附图和实施例对本申请进行说明。
实施例一
图1是本申请实施例一提供的一种硬件电路故障注入测试方法的步骤流程图。本实施例可适用于硬件电路自动化测试的情况，该方法可以由硬件电路故障注入测试装置来执行，该装置可以采用硬件和/或软件的方式来实现，参加见图1，本申请实施例提供的方法包括如下步骤：
步骤101、根据预设故障信息表产生故障生成指令。
预设故障信息表可以是存储有至少一种硬件电路故障的存储表。预设故障信息表中可以存储硬件电路故障的标识号、名称和故障描述等信息。预设故障信息表可以通过Excel表格存储。预设故障信息表中还可以存储有故障生成指令，硬件电路故障的标识号可以与故障生成指令一一对应。
可以根据待测硬件电路的电路结构和电路类型在预设故障信息表中查找对应故障的故障生成指令，可以在预设故障信息表中确定一个故障指令或者多个故障指令。示例性的，可以将预设故障信息表以Excel形式存储在上位机中，可以利用图形界面初学者通用符号指令代码宏语言(Visual Beginner's All-purpose symbolic instruction Code for Applications，VBA)代码查找预设故障信息表获取到故障生成指令。
步骤102、根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障。
继电器卡可以是继电器开关阵列，可以根据故障生成指令控制待测硬件电路中电路生成相应的电路故障，例如，短路和断路等。待测硬件电路可以是需要测试的硬件电路，可以是车辆控制电路等。目标故障可以是需要在待测硬件电路中进行测试的故障，目标故障可以与待测硬件电路的电路结构对应，不同的待测硬件电路中对应的目标故障可以不同。
可以将故障生成指令发送给继电器卡，控制继电器卡在待测电路中产生相应的目标故障。当故障生成指令为多个时，可以根据不同的故障生成指令对应不同的继电器卡，可以在待测硬件电路中产生相应的目标故障。
步骤103、获取生成目标故障后的所述待测硬件电路的故障信息。
故障信息可以是待测硬件电路在产生目标故障后输出的信息，可以包括电源错误信息、处理器错误信息、传感器错误信息、执行器错误信息等。
可以通过通用串口连接到待测硬件电路，获取产生目标故障的待测硬件电路的故障信息。
本申请实施例的技术方案，通过根据预设故障信息表产生故障生成指令，通过故障生成指令控制继电器卡在待测硬件电路中产生目标故障，并获取产生目标故障后的待测硬件电路反馈的故障信息，实现了硬件电路的故障注入测试，保证了测试过程的覆盖全面，增强了硬件测试的可靠性，从而提高了硬件电路的安全性。
实施例二
图2是本申请实施例二提供的一种硬件电路故障注入测试方法的步骤流程图。本申请实施例是以上述实施例为基础进行说明，参见图2，本申请实施例的方法包括如下步骤：
步骤201、根据预设故障信息表产生故障生成指令。
步骤202、确定所述故障生成指令对应的目标继电器卡，并将所述故障生成指令发送到所述目标继电器卡。
目标继电器卡可以是故障生成指令控制的继电器卡。一个故障生成指令表可以对应一个目标继电器卡，也可以对应多个继电器卡。
可以获取故障生成指令的目标地址，可以将目标地址对应的继电器卡作为目标继电器卡，可以根据目标地址将故障生成指令传输到对应的继电器卡中。
步骤203、控制所述目标继电器卡根据所述故障生成指令，在所述待测硬件电路中产生短路和/或断路的目标故障。
故障产生元件可以是在待测硬件电路中产生电路故障的硬件器件，故障产生元件可以搭载在待测硬件电路中，可以通过开启和闭合的方式在待测硬件电路中产生故障。示例性的，图3是本申请实施例二提供的一种故障产生元件的工作示例图。以故障产生元件为插针为例，参见图3，待测硬件电路中可以包括传感器、电阻、主控芯片、电容和执行器等元件，可以通过在待测硬件电路中设置多个插针，通过插针对待测硬件电路进行失效控制，以使得待测硬件电路中产生相应的故障。
可以通过目标继电器卡对故障产生元件进行控制，使得故障产生元件在待测硬件电路中产生短路和/或断路等故障，使得待测硬件电路中相应的组成元件产生故障。
在上述申请实施例的基础上，所述故障产生元件包括插针、短路跳帽和继电器卡中的至少一种。其中，插针和/或短路跳帽可以用来在自动测试前期进行部分手动测试验证，继电器卡设置为自动测试。
步骤204、获取生成目标故障后的所述待测硬件电路的故障信息。
执行本申请实施例方法的设备可以通过通用接口卡连接到待测硬件电路，可以通过串口发送命令，接收待测硬件电路反馈的故障信息。示例性的，图4是本申请实施例二提供的一种获取故障信息的电路示例图。参见图4，获取故障信息的电路可以由单片机、控制器局域网络(Controller Area Network，CAN)接口滤波电路和串口电平转换芯片组成，执行本申请实施例方法的设备可以通过推荐标准232(Recommeded Standard 232，RS232)串口向待测硬件电路发送命令以获取到反馈的故障信息。
步骤205、统计所述故障信息以确定所述待测硬件电路的测试结果。
在本申请实施例中，可以对故障信息进行统计，可以根据不同的故障类型进行分类统计生成测试结果。示例性的，可以根据故障的严重程度确定不同的结果评分，可以综合待测硬件电路的故障信息确定出测试结果。
本申请实施例的技术方案，通过预设故障信息表确定故障生成指令，确定出每个故障生成指令对应的目标继电器卡并将故障生成指令发送到目标继电器卡，控制每个目标继电器卡根据故障生成指令在待测硬件电路中实现短路或者断路，以产生目标故障，获取产生目标故障后的待测硬件电路的故障信息，统计故障信息以确定待测硬件电路的测试结果，实现了硬件电路的注入测试，提高了硬件测试的全面性，提高了硬件电路的安全性。
实施例三
图5是本申请实施例三提供的一种硬件电路故障注入测试装置的结构示意图，可执行本申请实施例任意实施例体提供的硬件电路故障注入测试方法，具有执行方法相应的功能模块和效果。该装置可以由软件和/或硬件实现，包括：故障指令模块301、故障生成模块302和信息获取模块303。
故障指令模块301，设置为根据预设故障信息表产生故障生成指令。
故障生成模块302，设置为根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障。
信息获取模块303，设置为获取生成目标故障后的所述待测硬件电路的故障信息。
本申请实施例的技术方案，通过故障指令模块预设故障信息表生成对应的故障生成指令，故障生成模块根据故障生成指令控制继电器卡在待测硬件电路中生成目标故障，信息获取模块获取生成目标故障后的待测硬件电路的故障信息，实现了硬件电路的注入测试，实现了全故障覆盖测试，提高了硬件电路的安全性。
在上述申请实施例的基础上，故障生成模块302包括：
指令发送单元，设置为确定所述故障生成指令对应的目标继电器卡，并将所述故障生成指令发送到所述目标继电器卡。
故障产生单元，设置为控制所述目标继电器卡根据所述故障生成指令，在所述待测硬件电路中的产生短路和/或断路的目标故障。
在上述申请实施例的基础上，故障生成模块302中的故障产生元件包括插针、短路跳帽和继电器卡中至少一种。
在上述申请实施例的基础上，还包括结果统计模块，设置为统计所述故障信息以确定所述待测硬件电路的测试结果。
实施例四
图6是本申请实施例四提供的一种设备的结构示意图。参见图6，该设备包括处理器40、存储器41、输入装置42和输出装置43。设备中处理器40的数量可以是一个或多个，图4中以一个处理器40为例。设备处理器40、存储器41、输入装置42和输出装置43可以通过总线或其他方式连接，图6中以通过总线连接为例。
存储器41作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请实施例中的硬件电路故障注入测试对应的模块(故障指令模块301、故障生成模块302和信息获取模块303)。处理器40通过运行存储在存储器41中的软件程序、指令以及模块，从而执行设备的多种功能应用以及数据处理，即实现上述的硬件电路故障注入测试方法。
存储器41可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端的使用所创建的数据等。此外，存储器41可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实例中，存储器41可包括相对于处理器40远程设置的存储器，这些远程存储器可以通过网络连接至设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
输入装置42可设置为接收输入的数字或字符信息，以及产生与设备的用户设置以及功能控制有关的键信号输入。输出装置43可包括显示屏等显示设备。
实施例五
本申请实施例五还提供一种包含计算机可执行指令的存储介质，所述计算机可执行指令在由计算机处理器执行时用于执行一种硬件电路故障注入测试方法，该方法包括：
根据预设故障信息表产生故障生成指令；根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障；获取生成目标故障后的所述待测硬件电路的故障信息。
本申请实施例所提供的一种包含计算机可执行指令的存储介质，其计算机可执行指令不限于如上所述的方法操作，还可以执行本申请任意实施例所提供的硬件电路故障注入测试方法中的相关操作。
通过以上关于实施方式的描述，本申请可借助软件及必需的通用硬件来实现，也可以通过硬件实现。本申请的技术方案本质上可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如计算机的软盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、闪存(FLASH)、硬盘或光盘等，包括多个指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请实施例所述的方法。
实施例六
图7是本申请实施例六提供的一种硬件电路故障注入测试系统的结构示意图。本实施例可以适用于硬件电路自动化测试的情况，参见图7，本申请实施例的系统包括：待测硬件电路61、继电器卡62和终端设备63。
所述待测硬件电路61通过继电器卡接口与至少一个继电器卡62连接，所述继电器卡62通过通信串口连接至所述终端设备63，其中，所述继电器卡62设置为在所述待测硬件电路61中产生硬件故障；所述终端设备63还通过通用接口连接至所述待测硬件电路61以获取所述待测硬件电路61的故障信息；其中，所述终端设备63包括如本申请实施例中任意所述的硬件电路故障注入测试装置。
待测硬件电路61可以是扩大化的硬件电路，可以具有与待测设备相同的硬件电路，可以实现待测设备的产品功能。待测硬件电路61中可以包括故障产生元件，例如可以包括至少一个插针座和短路跳帽。待测硬件电路可以根据继电器卡的控制情况产生不同的故障，实现故障注入。
在本申请实施例中，继电器卡62可以是控制待测硬件电路61产生故障的控制电路或者控制器件，可以通过开启和闭合在待测硬件电路61中产生断路或短路等电路故障使得待测硬件电路61产生不同的失效模式，例如，控制器失效或者电容失效等。终端设备63可以是具有本申请实施例任意提供的硬件故障注入测试装置的设备，例如可以是上位机。终端设备63中可以存储有预设故障信息表，可以通过串口发送命令，在待测硬件电路61中产生故障，并获取故障信 息。示例性的，图8是本申请实施例六提供的一种终端设备的示例图。参见图8，终端设备63可以具有测试结果统计功能，可以通过Excel中的微软通信控制(Microsoft Communications Control，MScomm)控件结合VBA代码实现故障生成命令，并通过接口实现与待测硬件电路的信息交互。
在上述申请实施例的基础上，继电器卡62包括串口电平转换芯片、单片机、继电器组和插针；所述串口电平转换芯片通过晶体管-晶体管逻辑电路(Transistor-Transistor Logic，TTL)串口连接至所述单片机，设置为将获取到的RS232电平标准信号转化为所述单片机对应的TTL电平标准信号；所述单片机通过通用输入输出口依次连接到继电器组和插针，设置为控制插针在所述待测硬件电路产生故障。
继电器卡62本质上可以是继电器开关阵列，继电器卡62上可以具有单片机，可以接收终端设备63发出的控制指令，使得继电器组中相应的继电器产生开和/或关动作，示例性的，图9是本申请实施例六提供的一种继电器卡的结构示例图。参见图9，继电器卡62可以由电平转换芯片、单片机、输入输出接口和插针依次连接组成。
在上述申请实施例的基础上，所述继电器组包括横排继电器组和竖排继电器组中至少一种。在本申请实施例中继电器卡62中的继电器组的排列方式可以包括横排继电器和竖排继电器。
上述硬件电路注入测试装置的实施例中，所包括的多个单元和模块只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，每个功能单元的名称也只是为了便于相互区分，并不用于限制本申请的保护范围。

Claims (10)

  1. 一种硬件电路故障注入测试方法，包括：
    根据预设故障信息表产生故障生成指令；
    根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障；
    获取生成所述目标故障后的所述待测硬件电路的故障信息。
  2. 根据权利要求1所述的方法，其中，所述根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障，包括：
    确定所述故障生成指令对应的目标继电器卡，并将所述故障生成指令发送到所述目标继电器卡；
    控制所述目标继电器卡根据所述故障生成指令，在所述待测硬件电路中产生以下目标故障中的至少之一：短路、断路。
  3. 根据权利要求2所述的方法，其中，在所述待测硬件电路中产生所述目标故障的元件包括插针、短路跳帽和继电器中的至少一种。
  4. 根据权利要求1所述的方法，还包括：
    统计所述故障信息以确定所述待测硬件电路的测试结果。
  5. 一种硬件电路故障注入测试装置，包括：
    故障指令模块，设置为根据预设故障信息表产生故障生成指令；
    故障生成模块，设置为根据所述故障生成指令控制继电器卡在待测硬件电路中生成目标故障；
    信息获取模块，设置为获取生成所述目标故障后的所述待测硬件电路的故障信息。
  6. 一种设备，包括：
    至少一个处理器；
    存储器，设置为存储至少一个程序；
    当所述至少一个程序被所述至少一个处理器执行，使得所述至少一个处理器实现如权利要求1-4中任一项所述的硬件故障注入测试方法。
  7. 一种计算机可读存储介质，存储有计算机程序，其中，所述程序被处理器执行时实现如权利要求1-4中任一项所述的硬件故障注入测试方法。
  8. 一种硬件故障注入测试系统，包括：待测硬件电路、至少一个继电器卡和终端设备；
    所述待测硬件电路通过继电器卡接口与所述至少一个继电器卡连接；
    每个继电器卡通过通信串口连接至所述终端设备，设置为在所述待测硬件电路中产生硬件故障；
    所述终端设备通过通用接口连接至所述待测硬件电路，设置为获取所述待测硬件电路的故障信息；
    其中，所述终端设备包括如权利要求5所述的硬件电路故障注入测试装置。
  9. 根据权利要求8所述系统，其中，所述继电器卡包括串口电平转换芯片、单片机、继电器组和插针；
    所述串口电平转换芯片通过晶体管-晶体管逻辑电路TTL串口连接至所述单片机，设置为将获取到的推荐标准RS232电平标准信号转化为所述单片机对应的TTL电平标准信号；
    所述单片机通过通用输入输出口连接继电器组和插针，设置为通过所述继电器组控制所述插针在所述待测硬件电路中产生故障。
  10. 根据权利要求9所述的系统，其中，所述的继电器组包括横排继电器组和竖排继电器组中的至少一种。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113886158A (zh) * 2021-09-28 2022-01-04 北京时代民芯科技有限公司 一种自动化的fpga故障注入测试系统以及方法
CN114415637A (zh) * 2022-01-21 2022-04-29 苏州挚途科技有限公司 Can通信的一致性测试方法、装置及系统
CN115134280A (zh) * 2022-06-23 2022-09-30 安徽江淮汽车集团股份有限公司 一种车载以太网的故障测试系统及方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111459735A (zh) * 2020-03-17 2020-07-28 中国第一汽车股份有限公司 硬件电路故障注入测试方法、装置、设备、介质和系统
CN112631846B (zh) * 2020-12-25 2024-10-01 广州品唯软件有限公司 一种故障演练方法、装置、计算机设备及存储介质
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070288822A1 (en) * 2006-04-27 2007-12-13 Xijiang Lin Timing-aware test generation and fault simulation
CN103529820A (zh) * 2013-09-26 2014-01-22 北京航天自动控制研究所 一种适用于嵌入式设备的故障注入测试系统及测试方法
CN108333987A (zh) * 2018-02-05 2018-07-27 北京龙坤盛达科技有限公司 一种多类型多通道的可控故障注入装置
CN110632495A (zh) * 2018-06-25 2019-12-31 联合汽车电子有限公司 电路故障模拟系统和方法
CN111459735A (zh) * 2020-03-17 2020-07-28 中国第一汽车股份有限公司 硬件电路故障注入测试方法、装置、设备、介质和系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070288822A1 (en) * 2006-04-27 2007-12-13 Xijiang Lin Timing-aware test generation and fault simulation
CN103529820A (zh) * 2013-09-26 2014-01-22 北京航天自动控制研究所 一种适用于嵌入式设备的故障注入测试系统及测试方法
CN108333987A (zh) * 2018-02-05 2018-07-27 北京龙坤盛达科技有限公司 一种多类型多通道的可控故障注入装置
CN110632495A (zh) * 2018-06-25 2019-12-31 联合汽车电子有限公司 电路故障模拟系统和方法
CN111459735A (zh) * 2020-03-17 2020-07-28 中国第一汽车股份有限公司 硬件电路故障注入测试方法、装置、设备、介质和系统

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113886158A (zh) * 2021-09-28 2022-01-04 北京时代民芯科技有限公司 一种自动化的fpga故障注入测试系统以及方法
CN113886158B (zh) * 2021-09-28 2024-04-02 北京时代民芯科技有限公司 一种自动化的fpga故障注入测试系统以及方法
CN114415637A (zh) * 2022-01-21 2022-04-29 苏州挚途科技有限公司 Can通信的一致性测试方法、装置及系统
CN114415637B (zh) * 2022-01-21 2023-09-22 苏州挚途科技有限公司 Can通信的一致性测试方法、装置及系统
CN115134280A (zh) * 2022-06-23 2022-09-30 安徽江淮汽车集团股份有限公司 一种车载以太网的故障测试系统及方法
CN115134280B (zh) * 2022-06-23 2023-11-24 安徽江淮汽车集团股份有限公司 一种车载以太网的故障测试系统及方法

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