WO2021184741A1 - 一种提高pcie控制ddr通信速率的装置及方法 - Google Patents

一种提高pcie控制ddr通信速率的装置及方法 Download PDF

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WO2021184741A1
WO2021184741A1 PCT/CN2020/120842 CN2020120842W WO2021184741A1 WO 2021184741 A1 WO2021184741 A1 WO 2021184741A1 CN 2020120842 W CN2020120842 W CN 2020120842W WO 2021184741 A1 WO2021184741 A1 WO 2021184741A1
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ddr
pcie
unit
central processing
read
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程绪
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上海御渡半导体科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the invention relates to the field of PCIE transmission rate, in particular to a device and method for improving PCIE to control DDR communication rate.
  • PCIE Peripheral Component Interconnect Express
  • CPU central processing unit
  • DDRs Data Direction Registers
  • FPGA Field Programmable Gate Array
  • the central processing unit issues a read instruction to the PCIE unit in the FPGA through the PCIE bus;
  • the FPGA includes a PCIE unit and multiple DDR units, and the PCIE unit is used to connect to the PCIE bus, and each DDR unit is connected to a corresponding DDR.
  • PCIE After PCIE receives the read instruction, it transmits the read instruction to the DDR unit through the intercommunication interface;
  • the DDR unit After receiving the read instruction, the DDR unit reads the data to be DDR according to the read instruction;
  • the DDR unit transmits the read DDR data to the PCIE unit through the intercommunication interface;
  • the PCIE unit parses the DDR data and transmits it to the central processing unit through the PCIE bus.
  • the central processing unit needs to read the DDR memory data of each VP motherboard.
  • Each VP has 32Gb DDR memory data.
  • a single business board has 8 VPs.
  • the number of boards in the entire system is Dozens of blocks, according to the traditional PCIE mode of controlling the DDR mounted under multiple FPGAs, it takes nearly 1 minute to read each VP (32Gb) data. If you read all the memory data of the entire system, it will be completed. It takes several hours, which is very slow for the processing and analysis of the upper-level software, so it is imminent to improve the speed of PCIE to read DDR data.
  • the purpose of the present invention is to provide a device and method for improving the PCIE control DDR communication rate, which pre-read the DDR data to be read, saves the time for communication between the PCIE unit and the DDR unit in the FPGA, and greatly improves The time taken by the central processing unit to read DDR data through the PCIE bus.
  • the present invention adopts the following technical solution: a method for increasing the PCIE control DDR communication rate, including the following steps:
  • the central processing unit issues control instructions to the FPGA
  • the FPGA After receiving the control instruction, the FPGA buffers the DDR data to be read into the FPGA;
  • the central processing unit issues a read instruction to the FPGA
  • the FPGA After receiving the read instruction, the FPGA transmits the cached DDR data to the central processing unit through the PCIE bus.
  • control instruction in the step S01 includes a chip select register, a length register, an initial address register, and a start signal register.
  • the FPGA includes a PCIE unit and M DDR units, and each DDR unit is connected to a DDR through a DDR bus; M is an integer greater than 0; the step S01 specifically includes:
  • the central processing unit issues a chip select register to the PCIE unit;
  • S012 The central processing unit where it is located sequentially sends the length register, the initial address register and the start signal register to the corresponding DDR unit.
  • step S02 specifically includes:
  • the DDR unit After receiving the start signal register, the DDR unit reads the DDR data to be read, and performs buffering;
  • S022 The DDR data to be read buffered by the DDR unit is transmitted to the PCIE unit for buffering through the intercommunication interface.
  • the central processing unit issues a read instruction to the PCIE unit.
  • the PCIE unit transmits the cached DDR data to be read to the central processing unit through the PCIE bus.
  • a device for improving the communication rate of PCIE to control DDR including a central processing unit, FPGA and M DDRs, wherein the FPGA includes a PCIE unit and M DDR units, and each DDR unit is connected to a DDR through a DDR bus;
  • the PCIE unit is connected to the central processing unit through the PCIE bus, and the DDR unit is respectively connected to the corresponding DDR through the DDR bus;
  • M is an integer greater than 0;
  • the central processing unit issues a control instruction to the FPGA, the DDR unit caches the DDR data to be read into the FPGA according to the issued instruction; the central processing unit issues a read instruction, the The DDR data cached in the FPGA is transmitted to the central processing unit through the PCIE bus.
  • control instruction includes a chip select register, a length register, an initial address register, and a start signal register; the central processing unit issues a chip select register to the PCIE unit, and the central processing unit sequentially issues a length register, The initial address register and the start signal register to the corresponding DDR unit.
  • the DDR unit reads the to-be-read DDR data after receiving the start signal register and performs buffering; the to-be-read DDR data buffered by the DDR unit is transmitted to the PCIE unit for buffering through an intercommunication interface.
  • the central processing unit issues a read instruction
  • the DDR data to be read buffered by the PCIE unit is transmitted to the central processing unit through the PCIE bus.
  • the present invention has the following beneficial effects: the present invention pre-reads the DDR data to be read through control instructions and caches it in the PCIE unit of the FPGA, and the PCIE unit is directly connected to the central processing unit through the PCIE bus.
  • the control method in the prior art needs to send read instructions to the FPGA multiple times, and each DDR data needs to be transmitted from the DDR unit to the PCIE unit within the FPGA.
  • the central processing The present invention is different from the prior art in that all DDR data can be cached to the PCIE unit at one time through the control command.
  • Fig. 1 is a schematic diagram of a device for improving PCIE to control DDR communication rate according to the present invention.
  • a method for improving PCIE to control DDR communication rate includes the following steps:
  • the central processing unit issues control instructions to the FPGA.
  • the FPGA includes a PCIE unit and M DDR units. Each DDR unit is connected to a DDR through the DDR bus; M is an integer greater than 0; the PCIE unit is connected to the central processing unit through the PCIE bus.
  • the DDR units are respectively connected to each DDR through the DDR bus.
  • multiple DDRs can be externally connected to the FPGA, and each DDR is connected to the corresponding DDR unit through the DDR bus.
  • the control instruction in the present invention includes a chip select register, a length register, an initial address register, and a start signal register.
  • the chip select register is used to control which DDR unit the FPGA communicates with, and each DDR unit corresponds to a DDR external to the FPGA.
  • the length register is used to determine the total length of data to be read in this read cycle.
  • the initial address register is used to determine the starting address of the DDR data to be read in this read cycle.
  • the start signal register is used to control the corresponding DDR unit to read data.
  • the chip selection register, the length register, the initial address register and the start signal register are all control signals.
  • This step specifically includes:
  • the central processing unit issues the chip select register to the PCIE unit;
  • the central processing unit sequentially sends the length register, the initial address register and the start signal register to the corresponding DDR unit.
  • the DDR unit receives the length register, the initial address register, and the start signal register in sequence. After the DDR unit receives the start signal register, that is, all the registers have been received. At this time, according to the specific control instructions in the length register and the initial address register , Read the DDR data to be read, and cache it;
  • the DDR data to be read buffered by the DDR unit is transmitted to the PCIE unit for buffering through the intercommunication interface.
  • the PCIE unit receives the chip select register earliest. After receiving the chip select register, it automatically establishes a data communication relationship with the corresponding DDR unit. When the corresponding DDR unit has buffered the DDR data to be read, it will be transferred to the PCIE unit. Cache.
  • the intercommunication interface inside FPGA includes but not limited to SerDes (Serializer-Deserializer) interface.
  • the central processing unit issues a read instruction to the PCIE unit in the FPGA;
  • the PCIE unit After receiving the read instruction, the PCIE unit transmits the cached DDR data to be read to the central processing unit through the PCIE bus. Since all the DDR data to be read has been cached in the PCIE unit, at this time, the PCIE unit can directly transmit the cached DDR data to be read to the central processing unit.
  • the single transmission capacity of the PCIE bus is limited.
  • the DDR data read by the central processing unit exceeds the word transmission range of the PCIE bus
  • a part of the DDR data to be read passes through the corresponding DDR
  • the unit is transferred to the PCIE unit, and the PCIE unit transfers this part of the DDR data to the central processing unit; then the remaining part of the DDR data to be read is transferred to the PCIE unit through the corresponding DDR unit, and the PCIE unit transfers this part of the DDR data to the PCIE unit.
  • the central processing unit; and the transmission of DDR data between the DDR unit and the PCIE unit is very slow, especially when there are many DDR data to be read, it is necessary to perform DDR data transmission within the FPGA multiple times, which makes the central The processor wasted most of the waiting time.
  • the DDR data to be read is cached from the corresponding DDR unit to the PCIE unit at one time through a control instruction. Even if the PCIE bus transmission capacity is limited, it only needs to transfer the DDR data cached in the PCIE unit to the center in multiple times. The processor is sufficient, saving a lot of time for transmission inside the FPGA.
  • the invention provides a device for improving the communication rate of PCIE to control DDR, which includes a central processing unit, an FPGA, and M DDRs, where the FPGA includes a PCIE unit and M DDR units, and each DDR unit is connected to a DDR through a DDR bus;
  • the PCIE unit is connected to the central processing unit through the PCIE bus, and the DDR unit is respectively connected to M DDRs through the DDR bus; M is an integer greater than 0;
  • the central processing unit sends control instructions to the FPGA, and the DDR unit reads the DDR data according to the issued instructions Cached in the FPGA; the central processing unit issues a read instruction, and the DDR data buffered in the FPGA is transmitted to the central processing unit through the PCIE bus.
  • Control instructions include chip select registers, length registers, initial address registers, and start signal registers; the central processing unit issues chip select registers to the PCIE unit, and the central processing unit sequentially issues length registers, initial address registers, and start signal registers to the corresponding DDR unit.
  • the DDR unit reads the DDR data to be read after receiving the start signal register, and performs buffering; the DDR data to be read buffered by the DDR unit is transferred to the PCIE unit for buffering through the intercommunication interface.
  • the central processing unit issues a read instruction, the DDR data to be read buffered by the PCIE unit is transmitted to the central processing unit through the PCIE bus.

Abstract

本发明公开了一种提高PCIE控制DDR通信速率的方法，包括如下步骤：S01：中央处理器下发控制指令至FPGA；S02：所述FPGA接收到控制指令之后，将待读出DDR数据缓存至所述FPGA中；S03：中央处理器下发读取指令至FPGA；S04：所述FPGA接收到读取指令之后，将缓存的DDR数据通过PCIE总线传输至中央处理器。本发明提供的一种提高PCIE控制DDR通信速率的装置及方法，将待读出DDR数据进行了预读取，省去了FPGA中PCIE单元和DDR单元之间通信的时间，大大提高了中央处理器通过PCIE总线读取DDR数据的时间。

Description

一种提高PCIE控制DDR通信速率的装置及方法
交叉引用
本申请要求2020年3月19日提交的申请号为CN202010196287.5的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及PCIE传输速率领域，具体涉及一种提高PCIE控制DDR通信速率的装置及方法。
技术背景
PCIE(Peripheral Component Interconnect Express)总线由于其开放性和通用性，在通讯领域得到了极为广泛的应用。当中央处理器(CPU)通过PCIE总线控制FPGA(Field Programmable Gate Array)下挂载的多个DDR(Data Direction Register)时，通常采用如下方式进行控制：
S01：中央处理器通过PCIE总线向FPGA中PCIE单元下发读取指令；其中FPGA包括PCIE单元和多个DDR单元，且PCIE单元用于连接PCIE总线，每个DDR单元连接一个对应的DDR。
S02：PCIE接收到读取指令之后，通过互通接口将读取指令传输给DDR单元；
S03：DDR单元接收到读取指令之后，根据读取指令读取待DDR数据；
S04：DDR单元将读取的DDR数据通过互通接口传输至PCIE单元；
S05：PCIE单元解析DDR数据，并将其通过PCIE总线传输至中央处理器。
在完整的产品框架内，中央处理器需要读取每一片VP主板的DDR内 存数据，每片VP有32Gb大小的DDR内存数据，单块业务板有8片VP，整个系统内的单板数量有几十块，按照传统的PCIE控制多片FPGA下挂载的DDR的模式，读取每一片VP(32Gb)数据需要的时间将近1分钟的时间，如果对整个系统所有的内存数据进行读取完成则需要几个小时的时间，这对于上层软件的处理分析是非常缓慢的，所以提升PCIE读取DDR数据的速度迫在眉睫。
发明概要
本发明的目的是提供的一种提高PCIE控制DDR通信速率的装置及方法，将待读出DDR数据进行了预读取，省去了FPGA中PCIE单元和DDR单元之间通信的时间，大大提高了中央处理器通过PCIE总线读取DDR数据的时间。
为了实现上述目的，本发明采用如下技术方案：一种提高PCIE控制DDR通信速率的方法，包括如下步骤：
S01：中央处理器下发控制指令至FPGA；
S02：所述FPGA接收到控制指令之后，将待读出DDR数据缓存至所述FPGA中；
S03：中央处理器下发读取指令至FPGA；
S04：所述FPGA接收到读取指令之后，将缓存的DDR数据通过PCIE总线传输至中央处理器。
进一步地，所述步骤S01中控制指令包括片选寄存器、长度寄存器、初始地址寄存器和开始信号寄存器。
进一步地，所述FPGA包括PCIE单元和M个DDR单元，且每个DDR 单元通过DDR总线连接一个DDR；M为大于0的整数；所述步骤S01具体包括：
S011：所述中央处理器下发片选寄存器至所述PCIE单元；
S012：所处中央处理器依次下发长度寄存器、初始地址寄存器和开始信号寄存器至对应的DDR单元。
进一步地，所述步骤S02具体包括：
S021：所述DDR单元接收到开始信号寄存器之后，读取待读出DDR数据，并进行缓存；
S022：所述DDR单元缓存的待读出DDR数据通过互通接口传输至所述PCIE单元进行缓存。
进一步地，所述步骤S03中所述中央处理器下发读取指令至所述PCIE单元。
进一步地，所述步骤S04中所述PCIE单元接收到读取指令之后，将缓存的待读出DDR数据通过PCIE总线传输至中央处理器。
一种提高PCIE控制DDR通信速率的装置，包括中央处理器、FPGA和M个DDR，其中，所述FPGA包括PCIE单元和M个DDR单元，且每个DDR单元通过DDR总线连接一个DDR；所述PCIE单元通过PCIE总线连接所述中央处理器，所述DDR单元通过DDR总线分别连接对应的DDR；M为大于0的整数；
所述中央处理器下发控制指令至所述FPGA，所述DDR单元根据所述下发指令将待读出DDR数据缓存至所述FPGA中；所述中央处理器下发读取指令，所述FPGA中缓存的DDR数据通过PCIE总线传输至中央处理器。
进一步地，所述控制指令包括片选寄存器、长度寄存器、初始地址寄存器和开始信号寄存器；所述中央处理器下发片选寄存器至所述PCIE单元，所述中央处理器依次下发长度寄存器、初始地址寄存器和开始信号寄存器至对应的DDR单元。
进一步地，所述DDR单元接收到所述开始信号寄存器之后读取待读出DDR数据，并进行缓存；所述DDR单元缓存的待读出DDR数据通过互通接口传输至所述PCIE单元进行缓存。
进一步地，所述中央处理单元下发读取指令之后，所述PCIE单元缓存的待读出DDR数据通过PCIE总线传输至所述中央处理器。
本发明具有如下有益效果：本发明通过控制指令，将待读出DDR数据进行了预读取，并缓存在FPGA的PCIE单元中，而PCIE单元直接通过PCIE总线连接中央处理器。鉴于PCIE总线每次传输的有限性，现有技术中控制方式需要多次向FPGA发送读取指令，且每一次DDR数据均需要在FPGA内部从DDR单元传输至PCIE单元，在这期间，中央处理器处于等待时间；本发明不同于现有技术的地方在于通过控制指令，一次就可以将所有的DDR数据缓存至PCIE单元，当中央处理器下发读取指令时，只需要直接在PCIE单元中进行读取即可，省去了FPGA中PCIE单元和DDR单元之间通信的时间，大大提高了中央处理器通过PCIE总线读取DDR数据的时间。
附图说明
附图1为本发明一种提高PCIE控制DDR通信速率的装置示意图。
发明内容
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明 的具体实施方式做进一步的详细说明。
请参阅附图1，本发明提供的一种提高PCIE控制DDR通信速率的方法，包括如下步骤：
S01：中央处理器下发控制指令至FPGA，FPGA包括PCIE单元和M个DDR单元，每个DDR单元通过DDR总线连接一个DDR；M为大于0的整数；PCIE单元通过PCIE总线连接中央处理器，DDR单元通过DDR总线分别连接各个DDR。本发明中FPGA下可以外挂多个DDR，每一个DDR通过DDR总线连接至对应的DDR单元。
具体的，本发明中控制指令包括片选寄存器、长度寄存器、初始地址寄存器和开始信号寄存器。其中，片选寄存器用于控制FPGA和哪一个DDR单元进行数据通信，每一个DDR单元对应FPGA外挂的一个DDR。长度寄存器用于确定本次读周期需要读取的数据总长度。初始地址寄存器用于确定本次读周期中待读出DDR数据的开始地址。开始信号寄存器用于控制对应的DDR单元进行数据读取。本发明中片选寄存器、长度寄存器、初始地址寄存器和开始信号寄存器均为控制信号。
本步骤具体包括：
S011：中央处理器下发片选寄存器至PCIE单元；
S012：中央处理器依次下发长度寄存器、初始地址寄存器和开始信号寄存器至对应的DDR单元。
S02：FPGA接收到控制指令之后，将待读出DDR数据缓存至FPGA中。本步骤主要分为以下两步：
S021：DDR单元依次接收到长度寄存器、初始地址寄存器和开始信号 寄存器，当DDR单元接收到开始信号寄存器之后，即所有的寄存器均接收完毕，此时，根据长度寄存器和初始地址寄存器中具体控制指令，读取待读出DDR数据，并进行缓存；
S022：DDR单元缓存的待读出DDR数据通过互通接口传输至PCIE单元进行缓存。PCIE单元最早接收到片选寄存器，当接收到片选寄存器之后，自动与对应的DDR单元建立数据通信关系，当对应的DDR单元缓存好待读出DDR数据之后，便将其传输至PCIE单元中进行缓存。其中，FPGA内部的互通接口包括但不限于SerDes(Serializer-Deserializer)接口。
S03：中央处理器下发读取指令至FPGA中PCIE单元；
S04：PCIE单元接收到读取指令之后，将缓存的待读出DDR数据通过PCIE总线传输至中央处理器。由于待读出DDR数据已经全部缓存在PCIE单元中了，此时，PCIE单元可以将缓存的待读出DDR数据直接传输至中央处理器。
值得说明的是，PCIE总线的单次传输能力有限，在现有技术中，当中央处理器读出的DDR数据超出PCIE总线的单词传输范围时，待读出DDR数据中的一部分通过对应的DDR单元传输至PCIE单元，PCIE单元再将这部分DDR数据传输至中央处理器；之后待读出DDR数据中的其余部分通过对应的DDR单元传输至PCIE单元，PCIE单元再将这部分DDR数据传输至中央处理器；而DDR数据在DDR单元和PCIE单元之间的传输是非常缓慢的，尤其针对待读出DDR数据较多的情况下，需要多次在FPGA内部进行DDR数据传输，这就使中央处理器浪费了大部分的等待时间。本发明中通过控制指令，一次性将待读出DDR数据从对应的DDR单元缓存至PCIE 单元，即使PCIE总线传输能力有限，其只需要分多次将PCIE单元中缓存的DDR数据传输至中中央处理器即可，节省了大量的在FPGA内部传输的时间。
本发明提供的一种提高PCIE控制DDR通信速率的装置，包括中央处理器、FPGA和M个DDR，其中，FPGA包括PCIE单元和M个DDR单元，且每个DDR单元通过DDR总线连接一个DDR；PCIE单元通过PCIE总线连接中央处理器，DDR单元通过DDR总线分别连接M个DDR；M为大于0的整数；中央处理器下发控制指令至FPGA，DDR单元根据下发指令将待读出DDR数据缓存至FPGA中；中央处理器下发读取指令，FPGA中缓存的DDR数据通过PCIE总线传输至中央处理器。
控制指令包括片选寄存器、长度寄存器、初始地址寄存器和开始信号寄存器；中央处理器下发片选寄存器至PCIE单元，中央处理器依次下发长度寄存器、初始地址寄存器和开始信号寄存器至对应的DDR单元。DDR单元接收到开始信号寄存器之后读取待读出DDR数据，并进行缓存；DDR单元缓存的待读出DDR数据通过互通接口传输至PCIE单元进行缓存。中央处理单元下发读取指令之后，所述PCIE单元缓存的待读出DDR数据通过PCIE总线传输至所述中央处理器。
以上所述仅为本发明的优选实施例，所述实施例并非用于限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明所附权利要求的保护范围内。

Claims (10)

  1. 一种提高PCIE控制DDR通信速率的方法，其特征在于，包括如下步骤：
    S01：中央处理器下发控制指令至FPGA；
    S02：所述FPGA接收到控制指令之后，将待读出DDR数据缓存至所述FPGA中；
    S03：中央处理器下发读取指令至FPGA；
    S04：所述FPGA接收到读取指令之后，将缓存的DDR数据通过PCIE总线传输至中央处理器。
  2. 根据权利要求1所述的一种提高PCIE控制DDR通信速率的方法，其特征在于，所述步骤S01中控制指令包括片选寄存器、长度寄存器、初始地址寄存器和开始信号寄存器。
  3. 根据权利要求2所述的一种提高PCIE控制DDR通信速率的方法，其特征在于，所述FPGA包括PCIE单元和M个DDR单元，且每个DDR单元通过DDR总线连接一个DDR；M为大于0的整数；所述步骤S01具体包括：
    S011：所述中央处理器下发片选寄存器至所述PCIE单元；
    S012：所处中央处理器依次下发长度寄存器、初始地址寄存器和开始信号寄存器至对应的DDR单元。
  4. 根据权利要求3所述的一种提高PCIE控制DDR通信速率的方法，其特征在于，所述步骤S02具体包括：
    S021：所述DDR单元接收到开始信号寄存器之后，读取待读出DDR 数据，并进行缓存；
    S022：所述DDR单元缓存的待读出DDR数据通过互通接口传输至所述PCIE单元进行缓存。
  5. 根据权利要求4所述的一种提高PCIE控制DDR通信速率的方法，其特征在于，所述步骤S03中所述中央处理器下发读取指令至所述PCIE单元。
  6. 根据权利要求5所述的一种提高PCIE控制DDR通信速率的方法，其特征在于，所述步骤S04中所述PCIE单元接收到读取指令之后，将缓存的待读出DDR数据通过PCIE总线传输至中央处理器。
  7. 一种提高PCIE控制DDR通信速率的装置，其特征在于，包括中央处理器、FPGA和M个DDR，其中，所述FPGA包括PCIE单元和M个DDR单元，且每个DDR单元通过DDR总线连接一个DDR；所述PCIE单元通过PCIE总线连接所述中央处理器，所述DDR单元通过DDR总线分别连接对应的DDR；M为大于0的整数；
    所述中央处理器下发控制指令至所述FPGA，所述DDR单元根据所述下发指令将待读出DDR数据缓存至所述FPGA中；所述中央处理器下发读取指令，所述FPGA中缓存的DDR数据通过PCIE总线传输至中央处理器。
  8. 根据权利要求7所述的一种提高PCIE控制DDR通信速率的装置，其特征在于，所述控制指令包括片选寄存器、长度寄存器、初始地址寄存器和开始信号寄存器；所述中央处理器下发片选寄存器至所述PCIE单元，所述中央处理器依次下发长度寄存器、初始地址寄存器和开始信号寄存器至对应的DDR单元。
  9. 根据权利要求8所述的一种提高PCIE控制DDR通信速率的装置，其 特征在于，所述DDR单元接收到所述开始信号寄存器之后读取待读出DDR数据，并进行缓存；所述DDR单元缓存的待读出DDR数据通过互通接口传输至所述PCIE单元进行缓存。
  10. 根据权利要求9所述的一种提高PCIE控制DDR通信速率的装置，其特征在于，所述中央处理单元下发读取指令之后，所述PCIE单元缓存的待读出DDR数据通过PCIE总线传输至所述中央处理器。
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