WO2021182222A1 - Dispositif de calcul et procédé de calcul - Google Patents

Dispositif de calcul et procédé de calcul Download PDF

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Publication number
WO2021182222A1
WO2021182222A1 PCT/JP2021/008131 JP2021008131W WO2021182222A1 WO 2021182222 A1 WO2021182222 A1 WO 2021182222A1 JP 2021008131 W JP2021008131 W JP 2021008131W WO 2021182222 A1 WO2021182222 A1 WO 2021182222A1
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WO
WIPO (PCT)
Prior art keywords
instruction
unit
executing
functional
pipeline
Prior art date
Application number
PCT/JP2021/008131
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English (en)
Japanese (ja)
Inventor
成司 西村
Original Assignee
株式会社エヌエスアイテクス
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社エヌエスアイテクス, 株式会社デンソー filed Critical 株式会社エヌエスアイテクス
Priority to JP2022505966A priority Critical patent/JP7393519B2/ja
Publication of WO2021182222A1 publication Critical patent/WO2021182222A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Definitions

  • This disclosure relates to an arithmetic unit and an arithmetic method.
  • an arithmetic unit having a plurality of functional units that are arithmetic units that process instructions, and performing pipeline processing (hereinafter, also referred to as "multi-stage arithmetic pipeline") with a plurality of functional units for a series of input instructions. Is used.
  • the computing device of one aspect of the present disclosure is a computing device that includes a pipeline including a plurality of functional units having the same function and performs calculations by chaining, and determines the presence or absence of the functional unit that is not executing an instruction.
  • the determination unit and any of the functional units are executing an instruction
  • the functional unit that is not executing the instruction can be executed in parallel with the execution of the instruction by any of the functional units.
  • a control unit for executing the command is provided.
  • a vector arithmetic unit composed of four stages of a pipeline (hereinafter referred to as "the number of stages of a pipeline") and five functional units (LD, ST, ADD, MUL, DIV). 20 is assumed.
  • the hardware state of the vector arithmetic unit 20 having four pipeline stages is referred to as a default mode.
  • the mask register 30 is provided corresponding to the vector register length, and "0" is rewritten to "1" according to the progress of the operation.
  • all the mask registers 30 are set to "1".
  • the overhead time required for the start-up and down-down of the pipeline is achieved. Can be reduced and the efficiency of calculation can be improved.
  • the control unit 24 causes the functional unit 12 that is not executing the instruction to execute an executable instruction.
  • the control unit 24 of the present embodiment when any of the functional units 12 is executing an instruction, for the functional unit 12 that is not executing the instruction, in parallel with executing the instruction by any of the functional units 12. Execute an executable instruction.
  • the arithmetic unit 10 controls according to the number of stages of the pipeline, in other words, according to the mode. For example, in a four-stage pipeline (default mode), the Out-of-Order function is not executed, and in a two-stage or one-stage pipeline (mode 1 or mode 2), the Out-of-Order function is executed. In other words, the Out-of-Order function is performed on a pipeline having a plurality of functional units 12 having the same function.
  • the mode is appropriately selected according to a series of operations to be executed by the vector arithmetic unit 20.
  • the Out-of-Order function may be executed even in the default mode. That is, not only the functional units 12 having the same function but also the functional units 12 having no dependency in all the different functional units 12 (LD, ST, MUL, ADD, DIV) may be able to be executed at the same time.
  • the Out-of-Order function can be performed by checking the mode register before executing the chaining operation process. It is determined whether or not the mode is executable. If the mode is not such that the Out-of-Order function can be executed, the normal chaining operation processing that does not execute the Out-of-Order function is executed. Alternatively, the Out-of-Order function is reconfigured into a feasible mode.
  • step S102 if there is a functional unit 12 that is not executing the instruction, the process proceeds to step S106, while if there is no functional unit 12 that does not execute the instruction, the process proceeds to step S104.
  • step S106 the control unit 24 assigns an instruction to the functional unit 12 that is not executing the instruction.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Advance Control (AREA)

Abstract

Dispositif de calcul (10) pourvu d'un pipeline qui comprend une pluralité d'unités fonctionnelles (12) ayant la même fonction et qui effectue un calcul par chaînage. Ce dispositif de calcul (10) est pourvu : d'une partie d'évaluation d'exécution (22) destinée à évaluer s'il existe une unité fonctionnelle (12) qui n'est pas en train d'exécuter des instructions ; et d'une partie de commande (24) qui amène, lorsqu'une des unités fonctionnelles (12) est en train d'exécuter des instructions, une unité fonctionnelle (12) qui n'est pas en train d'exécuter des instructions à exécuter les instructions pouvant être exécutées en parallèle de l'exécution d'instructions par l'une des unités fonctionnelles (12).
PCT/JP2021/008131 2020-03-11 2021-03-03 Dispositif de calcul et procédé de calcul WO2021182222A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022505966A JP7393519B2 (ja) 2020-03-11 2021-03-03 演算装置及び演算方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020042169 2020-03-11
JP2020-042169 2020-03-11

Publications (1)

Publication Number Publication Date
WO2021182222A1 true WO2021182222A1 (fr) 2021-09-16

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PCT/JP2021/008131 WO2021182222A1 (fr) 2020-03-11 2021-03-03 Dispositif de calcul et procédé de calcul

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JP (1) JP7393519B2 (fr)
WO (1) WO2021182222A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11259290A (ja) * 1998-03-12 1999-09-24 Fujitsu Ltd マイクロプロセッサ、演算処理実行方法及び記憶媒体
JP2006040254A (ja) * 2004-06-21 2006-02-09 Sanyo Electric Co Ltd リコンフィギュラブル回路および処理装置
JP2007166535A (ja) * 2005-12-16 2007-06-28 Matsushita Electric Ind Co Ltd デジタルフィルタ
JP2016103240A (ja) * 2014-11-28 2016-06-02 キヤノン株式会社 データ処理装置とデータ処理方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11259290A (ja) * 1998-03-12 1999-09-24 Fujitsu Ltd マイクロプロセッサ、演算処理実行方法及び記憶媒体
JP2006040254A (ja) * 2004-06-21 2006-02-09 Sanyo Electric Co Ltd リコンフィギュラブル回路および処理装置
JP2007166535A (ja) * 2005-12-16 2007-06-28 Matsushita Electric Ind Co Ltd デジタルフィルタ
JP2016103240A (ja) * 2014-11-28 2016-06-02 キヤノン株式会社 データ処理装置とデータ処理方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YOSHIMA MASATO ET AL.: "FPGA-based stochastic biochemical simulator", TRANSACTIONS OF INFORMATION PROCESSING SOCIETY OF JAPAN, vol. 4 8, no. SIG3, 15 February 2007 (2007-02-15), pages 45 - 58, ISSN: 0387-5806 *

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JPWO2021182222A1 (fr) 2021-09-16
JP7393519B2 (ja) 2023-12-06

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