WO2021181795A1 - Power supply circuit - Google Patents

Power supply circuit Download PDF

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Publication number
WO2021181795A1
WO2021181795A1 PCT/JP2020/047033 JP2020047033W WO2021181795A1 WO 2021181795 A1 WO2021181795 A1 WO 2021181795A1 JP 2020047033 W JP2020047033 W JP 2020047033W WO 2021181795 A1 WO2021181795 A1 WO 2021181795A1
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WIPO (PCT)
Prior art keywords
power supply
transistor
supply circuit
thermistor
capacitor
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PCT/JP2020/047033
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French (fr)
Japanese (ja)
Inventor
智紀 渡邉
光平 谷野
昌明 長野
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オムロン株式会社
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Publication of WO2021181795A1 publication Critical patent/WO2021181795A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present disclosure relates to a power supply circuit, particularly to a step-down chopper circuit.
  • Patent Document 1 discloses a lighting device capable of preventing an overcurrent to a light source.
  • the lighting device includes an input filter circuit, a rectifier circuit, a step-down chopper circuit, a switch control unit, an inrush current prevention circuit, and a drive circuit.
  • the inrush current prevention circuit is composed of a thermistor and a thyristor.
  • a drive circuit using a pulse transformer to drive a high-side switch (usually MOSFET) of a step-down chopper circuit is known. Since the drive circuit can reduce the number of parts as compared with the case where the high-side switch is driven by using an insulated gate driver or the like, the cost of the power supply device can be reduced.
  • the pulse transformer is driven by the controller.
  • the MOSFET turns on when the on signal is output from the drive terminal of the controller. On the other hand, when an off signal is output from the drive terminal of the controller (when the voltage of the drive terminal is 0V), the MOSFET is turned off.
  • the pulse transformer drive circuit does not continue to extract the charge between the gate and source of the MOSFET during the entire period when the drive terminal of the controller is 0V. If the charge is charged between the gate and source of the MOSFET via parasitic capacitance such as MOSFET during the period when the charge between the gate and source of the MOSFET cannot be extracted during the off period, the MOSFET is turned on. Become. In such a case, the output voltage of the power supply circuit tends to increase. If the output voltage of the power supply circuit rises significantly, parts of the power supply circuit may be damaged.
  • Japanese Unexamined Patent Publication No. 2014-137864 discloses a circuit for preventing an overcurrent of a light source.
  • Japanese Patent Application Laid-Open No. 2014-137864 does not disclose problems that may occur in the operation of the power supply device at a low temperature.
  • An object of the present disclosure is to provide a power supply circuit capable of suppressing an increase in output voltage at low temperatures.
  • the power supply circuit includes a drain connected to an input voltage from a DC power supply, a transistor having a gate and a source, a cathode connected to the source of the transistor, and an anode connected to a common voltage node.
  • a choke coil having a diode having a transistor, a first end connected to the source of the transistor and the cathode of the diode, and a second end connected to the output node, and connected between the output node and the common voltage node.
  • a transformer having a first capacitor, a primary winding, and a secondary winding connected to the gate of the transistor, and a drive signal for turning the transistor on and off based on the output voltage, which is the voltage at the output node.
  • a control circuit applied to the primary winding of the transformer and a thermistor provided in the current path of the DC power supply are provided.
  • the DC power supply has a first end and a second end that supply an input voltage to the drain of the transistor, and the power supply circuit has the first end connected to the drain of the transistor and the anode of the diode.
  • a second capacitor with a second end connected to is further provided, and the thermistor is connected between the second end of the second capacitor and the second end of the DC power supply.
  • the DC power supply has a first end and a second end for supplying an input voltage to the drain of the transistor, and the power supply circuit has the first end connected to the drain of the transistor and the DC power supply. Further comprising a second capacitor with a second end connected to the second end, the thermistor is connected between the anode of the diode and the second end of the second capacitor.
  • the thermistor is an NTC thermistor. According to this disclosure, it is possible to suppress an increase in the input voltage input to the power supply circuit at a low temperature.
  • FIG. 5 is a waveform diagram illustrating the effect of the power supply circuit 10 according to the embodiment of the present invention. It is a circuit diagram which showed another structural example of the power supply circuit according to embodiment of this invention.
  • FIG. 1 is a circuit diagram showing a basic configuration of a power supply circuit according to the present embodiment.
  • the power supply circuit 10 is a step-down chopper circuit.
  • the power supply circuit 10 includes choke coils 3 and 6, capacitors C1 and C2, a transistor 4, a drive circuit 5, and a diode D1.
  • Transistor 4 is an N-channel MOSFET.
  • the transistor 4 has a drain, a gate, and a source.
  • the drain of the transistor 4 is connected to the input voltage Vin.
  • the input voltage Vin is generated by the DC power supply 1.
  • the DC power supply 1 includes an AC power supply E1 that generates an AC voltage and a rectifier circuit 2 that rectifies the AC voltage from the AC power supply E1.
  • the choke coil 3 and the capacitor C2 smooth the voltage from the DC power supply 1.
  • the first end of the choke coil 3 is connected to the first end of the DC power supply.
  • the second end of the choke coil 3 is connected to the first end of the capacitor C2 and the drain of the transistor 4. Therefore, the drain of the transistor 4 is electrically connected to the first end of the DC power supply.
  • the second end of the capacitor C2 is connected to a common voltage node (ie, terminal T2).
  • the diode D1 has a cathode connected to the source of the transistor 4 and an anode connected to a common voltage node.
  • the terminal T2 shown in FIG. 1 corresponds to a common voltage node.
  • the common voltage is the ground voltage.
  • the choke coil 6 has a first end connected to the source of the transistor 4 and the cathode of the diode D1 and a second end connected to the output node.
  • the capacitor C1 is connected between the output node and the common voltage node.
  • the terminal T1 shown in FIG. 1 corresponds to an output node.
  • the output node (terminal T1) is a node for outputting the output voltage Vdc from the power supply circuit 10. As shown in FIG. 1, the output voltage Vdc is a voltage between the terminal T1 and the terminal T2.
  • the drive circuit 5 drives the transistor 4 based on the output voltage Vdc.
  • FIG. 2 is a circuit diagram showing a schematic configuration of a drive circuit. As shown in FIG. 2, the drive circuit 5 has a control IC 51, a pulse transformer 52, and a resistor 53.
  • the pulse transformer 52 has a primary winding 52p and a secondary winding 52s.
  • the primary winding 52p is connected to the control IC 51.
  • the secondary winding 52s is connected to the gate of the transistor 4.
  • the resistor 53 is connected between the gate of the transistor 4 and the source of the transistor 4.
  • the control IC 51 is a control circuit that gives a drive signal for turning on / off the transistor 4 to the primary winding 52p of the pulse transformer 52 based on the output voltage Vdc of the power supply circuit 10.
  • FIG. 3 is a waveform diagram illustrating problems that may occur when driving a transistor of a step-down chopper by a pulse transformer.
  • the control IC 51 outputs a control signal for turning on and off the transistor 4 from the drive terminal.
  • the control signal from the control IC 51 is applied to the primary winding 52p of the pulse transformer 52.
  • a voltage is induced in the secondary winding 52s of the pulse transformer 52.
  • the gate of the transistor 4 is connected to the secondary winding 52s of the pulse transformer 52.
  • the gate voltage (gate voltage Vgs) of the transistor 4 changes following the control signal output from the control IC 51.
  • the electric charge is discharged from the gate-source capacitance of the transistor 4 by the current flowing through the secondary winding 52s of the pulse transformer 52.
  • the control signal from the control IC 51 is off for a long period of time, a period in which no current flows through the secondary winding 52s of the pulse transformer 52 occurs. Therefore, when an electric charge is accumulated in the gate-source capacitance of the transistor 4 via a parasitic capacitance or the like during this period, the gate voltage Vgs may increase even though the control signal is off.
  • the capacitor C1 smoothes the output voltage Vdc, it is possible to prevent the output voltage Vdc from greatly exceeding the set voltage.
  • the capacitance of the capacitor C1 decreases.
  • the ESR (equivalent series resistance) of the capacitor C1 becomes large. In such a case, since the smoothing of the output voltage by the capacitor C1 is not sufficient, the output voltage Vdc may increase significantly as shown in FIG.
  • FIG. 4 is a circuit diagram showing one configuration example of a power supply circuit according to an embodiment of the present invention.
  • the power supply circuit 10 includes a thermistor 7 in addition to the configuration shown in FIG.
  • the thermistor 7 is provided in the current path of the DC power supply 1. Specifically, the thermistor 7 is connected between the second end of the capacitor C2 and the second end of the DC power supply.
  • the resistance value of the thermistor 7 changes according to the temperature.
  • the input voltage Vin input to the drain of the transistor 4 can be changed according to the ambient temperature of the power supply circuit 10.
  • the thermistor 7 is an NTC thermistor.
  • the resistance value of the NTC thermistor increases as the temperature decreases.
  • the resistance value of the thermistor 7 increases as the ambient temperature of the power supply circuit 10 decreases. Thereby, the voltage Vin can be lowered. Therefore, it is possible to suppress an increase in the voltage between both ends of the capacitor C1 (that is, the output voltage Vdc).
  • the capacitor C2 is charged, so that a large current tends to flow to the input side of the power supply circuit 10.
  • the circuit shown in FIG. 4 can suppress the inrush current by including the thermistor 7.
  • a breaker is installed on the input side of the power supply circuit 10, a low-capacity breaker can be adopted for the breaker.
  • FIG. 5 is a waveform diagram illustrating the effect of the power supply circuit 10 according to the embodiment of the present invention.
  • FIG. 5 shows a waveform showing an increase in the output voltage Vdc.
  • the increase in the output voltage Vdc is large.
  • the resistance of the thermistor 7 is 20 ⁇ , the increase in the output voltage Vdc is small. From FIG. 5, it is understood that the increase in the output voltage Vdc becomes smaller as the resistance value of the thermistor 7 increases.
  • the capacity of the capacitor C1 decreases.
  • the ESR (equivalent series resistance) of the capacitor C1 becomes large.
  • the resistance value of the thermistor 7 it is possible to suppress an increase in the output voltage Vdc. Therefore, it is possible to prevent damage to the components (for example, capacitors) constituting the power supply circuit 10.
  • FIG. 6 is a circuit diagram showing another configuration example of the power supply circuit according to the embodiment of the present invention. As shown in FIG. 6, the thermistor 7 is connected between the anode of the diode D1 and the second end of the capacitor C2. Even in the configuration shown in FIG. 6, the thermistor 7 is provided in the current path of the DC power supply.
  • the thermistor 7 is preferably an NTC thermistor. According to the configuration shown in FIG. 6, the resistance value of the thermistor 7 increases as the ambient temperature of the power supply circuit 10 decreases. Thereby, the voltage Vin can be lowered. Therefore, it is possible to suppress an increase in the voltage of the capacitor C1 (that is, the output voltage Vdc). Further, the inrush current can be suppressed at the time of starting the power supply circuit 10.
  • a transistor (4) having a drain, a gate, and a source connected to an input voltage (Vin) from a DC power supply (1), and a transistor (4).
  • a diode (D1) having a cathode connected to the source of the transistor (4) and an anode connected to a common voltage node (T2).
  • a choke coil (6) having a first end connected to the source of the transistor (4) and the cathode of the diode (D1) and a second end connected to the output node (T1).
  • Vdc the output voltage
  • the DC power supply (1) has a first end and a second end for supplying the input voltage (Vin) to the drain of the transistor.
  • the power supply circuit (10) Further comprising a second capacitor (C2) having a first end connected to the drain of the transistor (4) and a second end connected to the anode of the diode (D1).
  • the DC power supply (1) has a first end and a second end for supplying the input voltage (Vin) to the drain of the transistor (4).
  • the power supply circuit (10) A second capacitor (C2) having a first end connected to the drain of the transistor (4) and a second end connected to the second end of the DC power supply (1) is further provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)

Abstract

A power supply circuit (10) is provided with: a transistor (4) having a drain connected to an input voltage (Vin) from a DC power supply (1), a gate, and a source; a diode (D1) connected to the source of the transistor (4) and a common voltage node (T2); a choke coil (6) having a first end connected to the source of the transistor (4) and the cathode of the diode (D1) and a second end connected to an output node (T1); a capacitor (C1) connected between the output node (T1) and the common voltage node (T2); a drive circuit (5); and a thermistor (7) provided in the current path of the DC power supply (1).

Description

電源回路Power circuit
　本開示は、電源回路に関し、特に降圧チョッパ回路に関する。 The present disclosure relates to a power supply circuit, particularly to a step-down chopper circuit.
　特開２０１４－１３７８６４号公報（特許文献１）は、光源への過電流を防止することができる点灯装置を開示する。点灯装置は、入力フィルタ回路と、整流回路と、降圧チョッパ回路と、スイッチ制御部と、突入電流防止回路と、駆動回路とを備える。突入電流防止回路は、サーミスタおよびサイリスタによって構成される。 Japanese Unexamined Patent Publication No. 2014-137864 (Patent Document 1) discloses a lighting device capable of preventing an overcurrent to a light source. The lighting device includes an input filter circuit, a rectifier circuit, a step-down chopper circuit, a switch control unit, an inrush current prevention circuit, and a drive circuit. The inrush current prevention circuit is composed of a thermistor and a thyristor.
特開２０１４－１３７８６４号公報Japanese Unexamined Patent Publication No. 2014-137864
　降圧チョッパ回路のハイサイドスイッチ（通常はＭＯＳＦＥＴ）を駆動するためにパルストランスを利用した駆動回路が知られている。上記駆動回路は、絶縁ゲートドライバなどを使用してハイサイドスイッチを駆動するケースに比べて、部品点数を少なくすることができるので、電源装置の低コスト化が可能である。パルストランスはコントローラにより駆動される。コントローラのドライブ端子からオン信号を出力するときにＭＯＳＦＥＴはオンする。一方、コントローラのドライブ端子からオフ信号を出力するとき（ドライブ端子の電圧が０Ｖのとき）にはＭＯＳＦＥＴはオフする。 A drive circuit using a pulse transformer to drive a high-side switch (usually MOSFET) of a step-down chopper circuit is known. Since the drive circuit can reduce the number of parts as compared with the case where the high-side switch is driven by using an insulated gate driver or the like, the cost of the power supply device can be reduced. The pulse transformer is driven by the controller. The MOSFET turns on when the on signal is output from the drive terminal of the controller. On the other hand, when an off signal is output from the drive terminal of the controller (when the voltage of the drive terminal is 0V), the MOSFET is turned off.
　しかし、パルストランス駆動回路は、コントローラのドライブ端子が０Ｖになっているすべての期間でＭＯＳＦＥＴのゲート―ソース間の電荷を引き抜き続けているわけではない。オフ期間でＭＯＳＦＥＴのゲート―ソース間の電荷を引き抜くことができていない期間に、ＭＯＳＦＥＴなどの寄生容量を介してＭＯＳＦＥＴのゲート―ソース間に電荷が充電された場合には、ＭＯＳＦＥＴはオン状態となる。このような場合には、電源回路の出力電圧が上昇しやすい。電源回路の出力電圧が大きく上昇すると、電源回路の部品が損傷する可能性がある。 However, the pulse transformer drive circuit does not continue to extract the charge between the gate and source of the MOSFET during the entire period when the drive terminal of the controller is 0V. If the charge is charged between the gate and source of the MOSFET via parasitic capacitance such as MOSFET during the period when the charge between the gate and source of the MOSFET cannot be extracted during the off period, the MOSFET is turned on. Become. In such a case, the output voltage of the power supply circuit tends to increase. If the output voltage of the power supply circuit rises significantly, parts of the power supply circuit may be damaged.
　特開２０１４－１３７８６４号公報は、光源の過電流を防ぐための回路を開示する。しかし、特開２０１４－１３７８６４号公報は、低温での電源装置の動作において生じうる課題について開示していない。 Japanese Unexamined Patent Publication No. 2014-137864 discloses a circuit for preventing an overcurrent of a light source. However, Japanese Patent Application Laid-Open No. 2014-137864 does not disclose problems that may occur in the operation of the power supply device at a low temperature.
　本開示の目的は、低温時における出力電圧の上昇を抑制できる電源回路を提供することである。 An object of the present disclosure is to provide a power supply circuit capable of suppressing an increase in output voltage at low temperatures.
　本開示に係る電源回路は、直流電源からの入力電圧に接続されたドレインと、ゲートと、ソースとを有するトランジスタと、トランジスタのソースに接続されたカソードと、共通電圧ノードに接続されたアノードとを有するダイオードと、トランジスタのソースおよびダイオードのカソードに接続された第１端と、出力ノードに接続された第２端とを有するチョークコイルと、出力ノードと、共通電圧ノードとの間に接続された第１のコンデンサと、一次巻線と、トランジスタのゲートに接続された二次巻線とを有するトランスと、出力ノードにおける電圧である出力電圧に基づいて、トランジスタをオンオフさせるための駆動信号を、トランスの一次巻線に与える制御回路と、直流電源の電流経路に設けられるサーミスタとを備える。 The power supply circuit according to the present disclosure includes a drain connected to an input voltage from a DC power supply, a transistor having a gate and a source, a cathode connected to the source of the transistor, and an anode connected to a common voltage node. A choke coil having a diode having a transistor, a first end connected to the source of the transistor and the cathode of the diode, and a second end connected to the output node, and connected between the output node and the common voltage node. A transformer having a first capacitor, a primary winding, and a secondary winding connected to the gate of the transistor, and a drive signal for turning the transistor on and off based on the output voltage, which is the voltage at the output node. , A control circuit applied to the primary winding of the transformer and a thermistor provided in the current path of the DC power supply are provided.
　この開示によれば、低温時において電源回路の出力電圧の急峻な上昇を抑制できる。
　上述の開示において、直流電源は、入力電圧をトランジスタのドレインに供給する第１端と、第２端とを有し、電源回路は、トランジスタのドレインに接続された第１端と、ダイオードのアノードに接続された第２端とを有する第２のコンデンサをさらに備え、サーミスタは、第２のコンデンサの第２端と、直流電源の第２端との間に接続される。 According to this disclosure, it is possible to suppress a steep rise in the output voltage of the power supply circuit at a low temperature.
In the above disclosure, the DC power supply has a first end and a second end that supply an input voltage to the drain of the transistor, and the power supply circuit has the first end connected to the drain of the transistor and the anode of the diode. A second capacitor with a second end connected to is further provided, and the thermistor is connected between the second end of the second capacitor and the second end of the DC power supply.
　この開示によれば、簡易な構成によって、電源回路の出力電圧が低温で急峻に上昇することを抑制できる。 According to this disclosure, it is possible to suppress a sharp rise in the output voltage of the power supply circuit at a low temperature by a simple configuration.
　上述の開示において、直流電源は、入力電圧をトランジスタのドレインに供給する第１端と、第２端とを有し、電源回路は、トランジスタのドレインに接続された第１端と、直流電源の第２端に接続された第２端とを有する第２のコンデンサをさらに備え、サーミスタは、ダイオードのアノードと第２のコンデンサの第２端との間に接続される。 In the above disclosure, the DC power supply has a first end and a second end for supplying an input voltage to the drain of the transistor, and the power supply circuit has the first end connected to the drain of the transistor and the DC power supply. Further comprising a second capacitor with a second end connected to the second end, the thermistor is connected between the anode of the diode and the second end of the second capacitor.
　この開示によれば、簡易な構成によって、電源回路の出力電圧が低温で急峻に上昇することを抑制できる。 According to this disclosure, it is possible to suppress a sharp rise in the output voltage of the power supply circuit at a low temperature by a simple configuration.
　上述の開示においてサーミスタは、ＮＴＣサーミスタである。
　この開示によれば、低温において、電源回路に入力される入力電圧が上昇することを抑制できる。 In the above disclosure, the thermistor is an NTC thermistor.
According to this disclosure, it is possible to suppress an increase in the input voltage input to the power supply circuit at a low temperature.
　本開示によれば、低温時における出力電圧の上昇を抑制できる電源回路を提供することができる。 According to the present disclosure, it is possible to provide a power supply circuit capable of suppressing an increase in output voltage at a low temperature.
本実施の形態に従う電源回路の基本構成を示した回路図である。It is a circuit diagram which showed the basic structure of the power supply circuit according to this embodiment. 駆動回路の概略的な構成を示した回路図である。It is a circuit diagram which showed the schematic structure of the drive circuit. パルストランスによって、降圧チョッパのトランジスタを駆動する場合に起こりうる課題を説明する波形図である。It is a waveform diagram explaining the problem which may occur when the transistor of a step-down chopper is driven by a pulse transformer. 本発明の実施の形態に従う電源回路の１つの構成例を示した回路図である。It is a circuit diagram which showed one structural example of the power supply circuit according to embodiment of this invention. 本発明の実施の形態に従う電源回路１０による効果を説明する波形図である。FIG. 5 is a waveform diagram illustrating the effect of the power supply circuit 10 according to the embodiment of the present invention. 本発明の実施の形態に従う電源回路の別の構成例を示した回路図である。It is a circuit diagram which showed another structural example of the power supply circuit according to embodiment of this invention.
　以下、実施の形態について、図面を参照しながら詳細に説明する。なお、図中の同一または相当部分については、同一符号を付してその説明は繰返さない。 Hereinafter, the embodiment will be described in detail with reference to the drawings. The same or corresponding parts in the drawings are designated by the same reference numerals and the description thereof will not be repeated.
　＜適用例＞
　図１は、本実施の形態に従う電源回路の基本構成を示した回路図である。図１に示すように、この実施形態では、電源回路１０は、降圧チョッパ回路である。電源回路１０は、チョークコイル３，６と、コンデンサＣ１，Ｃ２と、トランジスタ４と、駆動回路５と、ダイオードＤ１とを備える。 <Application example>
FIG. 1 is a circuit diagram showing a basic configuration of a power supply circuit according to the present embodiment. As shown in FIG. 1, in this embodiment, the power supply circuit 10 is a step-down chopper circuit. The power supply circuit 10 includes choke coils 3 and 6, capacitors C1 and C2, a transistor 4, a drive circuit 5, and a diode D1.
　トランジスタ４は、ＮチャネルＭＯＳＦＥＴである。トランジスタ４は、ドレインと、ゲートと、ソースとを有する。トランジスタ４のドレインは、入力電圧Ｖｉｎに接続される。入力電圧Ｖｉｎは、直流電源１によって生成される。 Transistor 4 is an N-channel MOSFET. The transistor 4 has a drain, a gate, and a source. The drain of the transistor 4 is connected to the input voltage Vin. The input voltage Vin is generated by the DC power supply 1.
　この実施の形態では、直流電源１は、交流電圧を発生させる交流電源Ｅ１と、交流電源Ｅ１からの交流電圧を整流する整流回路２とを含む。チョークコイル３およびコンデンサＣ２は、直流電源１からの電圧を平滑化する。チョークコイル３の第１端は、直流電源の第１端に接続される。チョークコイル３の第２端は、コンデンサＣ２の第１端およびトランジスタ４のドレインに接続される。したがって、トランジスタ４のドレインは、直流電源の第１端に電気的に接続される。コンデンサＣ２の第２端は、共通電圧ノード（すなわち端子Ｔ２）に接続される。 In this embodiment, the DC power supply 1 includes an AC power supply E1 that generates an AC voltage and a rectifier circuit 2 that rectifies the AC voltage from the AC power supply E1. The choke coil 3 and the capacitor C2 smooth the voltage from the DC power supply 1. The first end of the choke coil 3 is connected to the first end of the DC power supply. The second end of the choke coil 3 is connected to the first end of the capacitor C2 and the drain of the transistor 4. Therefore, the drain of the transistor 4 is electrically connected to the first end of the DC power supply. The second end of the capacitor C2 is connected to a common voltage node (ie, terminal T2).
　ダイオードＤ１は、トランジスタ４のソースに接続されたカソードと、共通電圧ノードに接続されたアノードとを有する。図１に示す端子Ｔ２は、共通電圧ノードに相当する。本実施形態において、共通電圧とは接地電圧である。 The diode D1 has a cathode connected to the source of the transistor 4 and an anode connected to a common voltage node. The terminal T2 shown in FIG. 1 corresponds to a common voltage node. In this embodiment, the common voltage is the ground voltage.
　チョークコイル６は、トランジスタ４のソースおよびダイオードＤ１のカソードに接続された第１端と、出力ノードに接続された第２端とを有する。 The choke coil 6 has a first end connected to the source of the transistor 4 and the cathode of the diode D1 and a second end connected to the output node.
　コンデンサＣ１は、出力ノードと、共通電圧ノードとの間に接続される。図１に示す端子Ｔ１は、出力ノードに相当する。出力ノード（端子Ｔ１）は電源回路１０から出力電圧Ｖｄｃを出力するためのノードである。なお、図１に示すように出力電圧Ｖｄｃは、端子Ｔ１と端子Ｔ２との間の電圧である。駆動回路５は、出力電圧Ｖｄｃに基づいてトランジスタ４を駆動する。 The capacitor C1 is connected between the output node and the common voltage node. The terminal T1 shown in FIG. 1 corresponds to an output node. The output node (terminal T1) is a node for outputting the output voltage Vdc from the power supply circuit 10. As shown in FIG. 1, the output voltage Vdc is a voltage between the terminal T1 and the terminal T2. The drive circuit 5 drives the transistor 4 based on the output voltage Vdc.
　図２は、駆動回路の概略的な構成を示した回路図である。図２に示すように、駆動回路５は、制御ＩＣ５１と、パルストランス５２と、抵抗５３とを有する。 FIG. 2 is a circuit diagram showing a schematic configuration of a drive circuit. As shown in FIG. 2, the drive circuit 5 has a control IC 51, a pulse transformer 52, and a resistor 53.
　パルストランス５２は、一次巻線５２ｐと、二次巻線５２ｓとを有する。一次巻線５２ｐは制御ＩＣ５１に接続される。二次巻線５２ｓは、トランジスタ４のゲートに接続される。抵抗５３は、トランジスタ４のゲートとトランジスタ４のソースとの間に接続される。 The pulse transformer 52 has a primary winding 52p and a secondary winding 52s. The primary winding 52p is connected to the control IC 51. The secondary winding 52s is connected to the gate of the transistor 4. The resistor 53 is connected between the gate of the transistor 4 and the source of the transistor 4.
　制御ＩＣ５１は、電源回路１０の出力電圧Ｖｄｃに基づいて、トランジスタ４をオンオフさせるための駆動信号を、パルストランス５２の一次巻線５２ｐに与える制御回路である。 The control IC 51 is a control circuit that gives a drive signal for turning on / off the transistor 4 to the primary winding 52p of the pulse transformer 52 based on the output voltage Vdc of the power supply circuit 10.
　図３は、パルストランスによって、降圧チョッパのトランジスタを駆動する場合に起こりうる課題を説明する波形図である。図２および図３に示すように、制御ＩＣ５１は、トランジスタ４をオンおよびオフさせる制御信号をドライブ端子から出力する。制御ＩＣ５１からの制御信号はパルストランス５２の一次巻線５２ｐに印加される。これによりパルストランス５２の二次巻線５２ｓに電圧が誘起される。 FIG. 3 is a waveform diagram illustrating problems that may occur when driving a transistor of a step-down chopper by a pulse transformer. As shown in FIGS. 2 and 3, the control IC 51 outputs a control signal for turning on and off the transistor 4 from the drive terminal. The control signal from the control IC 51 is applied to the primary winding 52p of the pulse transformer 52. As a result, a voltage is induced in the secondary winding 52s of the pulse transformer 52.
　トランジスタ４のゲートはパルストランス５２の二次巻線５２ｓに接続される。基本的には、トランジスタ４のゲートの電圧（ゲート電圧Ｖｇｓ）は、制御ＩＣ５１から出力される制御信号に追随して変化する。制御ＩＣ５１からの制御信号がオフ状態になっている期間では、パルストランス５２の二次巻線５２ｓに電流が流れることにより、トランジスタ４のゲート―ソース間容量から電荷が放出される。 The gate of the transistor 4 is connected to the secondary winding 52s of the pulse transformer 52. Basically, the gate voltage (gate voltage Vgs) of the transistor 4 changes following the control signal output from the control IC 51. During the period when the control signal from the control IC 51 is off, the electric charge is discharged from the gate-source capacitance of the transistor 4 by the current flowing through the secondary winding 52s of the pulse transformer 52.
　しかし、制御ＩＣ５１からの制御信号がオフである期間が長い場合、パルストランス５２の二次巻線５２ｓには電流が流れなくなる期間が発生する。このため、この期間に寄生容量などを介しトランジスタ４のゲート―ソース間容量に電荷が蓄積された場合、制御信号がオフ状態であるにもかかわらず、ゲート電圧Ｖｇｓが上昇することが起こりえる。 However, if the control signal from the control IC 51 is off for a long period of time, a period in which no current flows through the secondary winding 52s of the pulse transformer 52 occurs. Therefore, when an electric charge is accumulated in the gate-source capacitance of the transistor 4 via a parasitic capacitance or the like during this period, the gate voltage Vgs may increase even though the control signal is off.
　通常では、コンデンサＣ１が出力電圧Ｖｄｃを平滑化するので、出力電圧Ｖｄｃが設定電圧を大きく上回ることが防がれる。しかし、電源回路１０の周囲温度が低い場合には、コンデンサＣ１の容量が低下する。あるいは電源回路１０の周囲温度が低い場合には、コンデンサＣ１のＥＳＲ（等価直列抵抗）が大きくなる。このような場合には、コンデンサＣ１による出力電圧の平滑化が十分でないために、図３に示すように、出力電圧Ｖｄｃが大きく上昇する可能性がある。 Normally, since the capacitor C1 smoothes the output voltage Vdc, it is possible to prevent the output voltage Vdc from greatly exceeding the set voltage. However, when the ambient temperature of the power supply circuit 10 is low, the capacitance of the capacitor C1 decreases. Alternatively, when the ambient temperature of the power supply circuit 10 is low, the ESR (equivalent series resistance) of the capacitor C1 becomes large. In such a case, since the smoothing of the output voltage by the capacitor C1 is not sufficient, the output voltage Vdc may increase significantly as shown in FIG.
　図４は、本発明の実施の形態に従う電源回路の１つの構成例を示した回路図である。電源回路１０は、図１に示した構成に加えてサーミスタ７を備える。サーミスタ７は、直流電源１の電流経路に設けられる。詳細には、サーミスタ７は、コンデンサＣ２の第２端と、直流電源の第２端との間に接続される。 FIG. 4 is a circuit diagram showing one configuration example of a power supply circuit according to an embodiment of the present invention. The power supply circuit 10 includes a thermistor 7 in addition to the configuration shown in FIG. The thermistor 7 is provided in the current path of the DC power supply 1. Specifically, the thermistor 7 is connected between the second end of the capacitor C2 and the second end of the DC power supply.
　サーミスタ７の抵抗値は、温度に応じて変化する。これにより、電源回路１０の周囲温度に応じてトランジスタ４のドレインに入力される入力電圧Ｖｉｎを変化させることができる。 The resistance value of the thermistor 7 changes according to the temperature. As a result, the input voltage Vin input to the drain of the transistor 4 can be changed according to the ambient temperature of the power supply circuit 10.
　好ましくは、サーミスタ７は、ＮＴＣサーミスタである。温度が低下するにつれてＮＴＣサーミスタの抵抗値が増大する。電源回路１０の周囲温度が低下するにつれてサーミスタ７の抵抗値が増大する。これにより電圧Ｖｉｎを低下させることができる。したがってコンデンサＣ１の両端間の電圧（すなわち出力電圧Ｖｄｃ）の上昇を抑制することができる。 Preferably, the thermistor 7 is an NTC thermistor. The resistance value of the NTC thermistor increases as the temperature decreases. The resistance value of the thermistor 7 increases as the ambient temperature of the power supply circuit 10 decreases. Thereby, the voltage Vin can be lowered. Therefore, it is possible to suppress an increase in the voltage between both ends of the capacitor C1 (that is, the output voltage Vdc).
　さらに、電源回路１０の起動時には、コンデンサＣ２が充電されるために、電源回路１０の入力側に大きな電流が流れやすい。図４に示す回路は、サーミスタ７を備えることによって、突入電流を抑制できる。たとえば電源回路１０の入力側にブレーカを設置する場合において、そのブレーカに低容量のブレーカを採用することができる。 Further, when the power supply circuit 10 is started, the capacitor C2 is charged, so that a large current tends to flow to the input side of the power supply circuit 10. The circuit shown in FIG. 4 can suppress the inrush current by including the thermistor 7. For example, when a breaker is installed on the input side of the power supply circuit 10, a low-capacity breaker can be adopted for the breaker.
　図５は、本発明の実施の形態に従う電源回路１０による効果を説明する波形図である。図５には、出力電圧Ｖｄｃの上昇を示す波形が示される。サーミスタ７の抵抗が０．１Ωのときに出力電圧Ｖｄｃの上昇は大きい。一方、サーミスタ７の抵抗が２０Ωのときには出力電圧Ｖｄｃの上昇は小さい。図５から、サーミスタ７の抵抗値が増大するほど、出力電圧Ｖｄｃの上昇が小さくなることが理解される。 FIG. 5 is a waveform diagram illustrating the effect of the power supply circuit 10 according to the embodiment of the present invention. FIG. 5 shows a waveform showing an increase in the output voltage Vdc. When the resistance of the thermistor 7 is 0.1Ω, the increase in the output voltage Vdc is large. On the other hand, when the resistance of the thermistor 7 is 20Ω, the increase in the output voltage Vdc is small. From FIG. 5, it is understood that the increase in the output voltage Vdc becomes smaller as the resistance value of the thermistor 7 increases.
　電源回路１０の周囲温度が低い場合、コンデンサＣ１の容量が低下する。あるいはコンデンサＣ１のＥＳＲ（等価直列抵抗）が大きくなる。しかし、サーミスタ７の抵抗値が増大することで、出力電圧Ｖｄｃの電圧上昇を抑制できる。したがって、電源回路１０を構成する部品（たとえばコンデンサ）の破損を防止することができる。 When the ambient temperature of the power supply circuit 10 is low, the capacity of the capacitor C1 decreases. Alternatively, the ESR (equivalent series resistance) of the capacitor C1 becomes large. However, by increasing the resistance value of the thermistor 7, it is possible to suppress an increase in the output voltage Vdc. Therefore, it is possible to prevent damage to the components (for example, capacitors) constituting the power supply circuit 10.
　図６は、本発明の実施の形態に従う電源回路の別の構成例を示した回路図である。図６に示すように、サーミスタ７は、ダイオードＤ１のアノードとコンデンサＣ２の第２端との間に接続される。図６に示された構成においても、サーミスタ７は直流電源の電流経路に設けられている。 FIG. 6 is a circuit diagram showing another configuration example of the power supply circuit according to the embodiment of the present invention. As shown in FIG. 6, the thermistor 7 is connected between the anode of the diode D1 and the second end of the capacitor C2. Even in the configuration shown in FIG. 6, the thermistor 7 is provided in the current path of the DC power supply.
　サーミスタ７は、ＮＴＣサーミスタであることが好ましい。図６に示す構成によれば、電源回路１０の周囲温度が低下するにつれてサーミスタ７の抵抗値が増大する。これにより電圧Ｖｉｎを低下させることができる。したがってコンデンサＣ１の電圧（すなわち出力電圧Ｖｄｃ）の上昇を抑制することができる。さらに、電源回路１０の起動時において、突入電流を抑制することができる。 The thermistor 7 is preferably an NTC thermistor. According to the configuration shown in FIG. 6, the resistance value of the thermistor 7 increases as the ambient temperature of the power supply circuit 10 decreases. Thereby, the voltage Vin can be lowered. Therefore, it is possible to suppress an increase in the voltage of the capacitor C1 (that is, the output voltage Vdc). Further, the inrush current can be suppressed at the time of starting the power supply circuit 10.
　＜付記＞
　上述したような実施の形態は、以下のような技術思想を含む。 <Additional notes>
The above-described embodiments include the following technical ideas.
　（構成１）
　直流電源（１）からの入力電圧（Ｖｉｎ）に接続されたドレインと、ゲートと、ソースとを有するトランジスタ（４）と、
　前記トランジスタ（４）の前記ソースに接続されたカソードと、共通電圧ノード（Ｔ２）に接続されたアノードとを有するダイオード（Ｄ１）と、
　前記トランジスタ（４）の前記ソースおよび前記ダイオード（Ｄ１）の前記カソードに接続された第１端と、出力ノード（Ｔ１）に接続された第２端とを有するチョークコイル（６）と、
　前記出力ノード（Ｔ１）と、前記共通電圧ノード（Ｔ２）との間に接続された第１のコンデンサ（Ｃ１）と、
　一次巻線（５２ｐ）と、前記トランジスタ（４）の前記ゲートに接続された二次巻線（５２ｓ）とを有するトランス（５２）と、
　前記出力ノード（Ｔ１）における電圧である出力電圧（Ｖｄｃ）に基づいて、前記トランジスタ（４）をオンオフさせるための駆動信号を、前記トランス（５２）の前記一次巻線（５２ｐ）に与える制御回路（５１）と、
　前記直流電源（１）の電流経路に設けられるサーミスタ（７）とを備える、電源回路（１０）。 (Structure 1)
A transistor (4) having a drain, a gate, and a source connected to an input voltage (Vin) from a DC power supply (1), and a transistor (4).
A diode (D1) having a cathode connected to the source of the transistor (4) and an anode connected to a common voltage node (T2).
A choke coil (6) having a first end connected to the source of the transistor (4) and the cathode of the diode (D1) and a second end connected to the output node (T1).
A first capacitor (C1) connected between the output node (T1) and the common voltage node (T2), and
A transformer (52) having a primary winding (52p) and a secondary winding (52s) connected to the gate of the transistor (4).
A control circuit that gives a drive signal for turning on / off the transistor (4) to the primary winding (52p) of the transformer (52) based on the output voltage (Vdc) which is the voltage at the output node (T1). (51) and
A power supply circuit (10) including a thermistor (7) provided in the current path of the DC power supply (1).
　（構成２）
　前記直流電源（１）は、前記入力電圧（Ｖｉｎ）を前記トランジスタの前記ドレインに供給する第１端と、第２端とを有し、
　前記電源回路（１０）は、
　前記トランジスタ（４）の前記ドレインに接続された第１端と、前記ダイオード（Ｄ１）の前記アノードに接続された第２端とを有する第２のコンデンサ（Ｃ２）をさらに備え、
　前記サーミスタ（７）は、前記第２のコンデンサ（Ｃ２）の前記第２端と、前記直流電源（１）の前記第２端との間に接続される、構成１に記載の電源回路。 (Structure 2)
The DC power supply (1) has a first end and a second end for supplying the input voltage (Vin) to the drain of the transistor.
The power supply circuit (10)
Further comprising a second capacitor (C2) having a first end connected to the drain of the transistor (4) and a second end connected to the anode of the diode (D1).
The power supply circuit according to configuration 1, wherein the thermistor (7) is connected between the second end of the second capacitor (C2) and the second end of the DC power supply (1).
　（構成３）
　前記直流電源（１）は、前記入力電圧（Ｖｉｎ）を前記トランジスタ（４）の前記ドレインに供給する第１端と、第２端とを有し、
　前記電源回路（１０）は、
　前記トランジスタ（４）の前記ドレインに接続された第１端と、前記直流電源（１）の前記第２端に接続された第２端とを有する第２のコンデンサ（Ｃ２）をさらに備え、
　前記サーミスタ（７）は、前記ダイオード（Ｄ１）の前記アノードと前記第２のコンデンサ（Ｃ２）の前記第２端との間に接続される、構成１に記載の電源回路。 (Structure 3)
The DC power supply (1) has a first end and a second end for supplying the input voltage (Vin) to the drain of the transistor (4).
The power supply circuit (10)
A second capacitor (C2) having a first end connected to the drain of the transistor (4) and a second end connected to the second end of the DC power supply (1) is further provided.
The power supply circuit according to configuration 1, wherein the thermistor (7) is connected between the anode of the diode (D1) and the second end of the second capacitor (C2).
　（構成４）
　前記サーミスタは、ＮＴＣサーミスタである、構成１～構成３のいずれか１つに記載の電源回路。 (Structure 4)
The power supply circuit according to any one of configurations 1 to 3, wherein the thermistor is an NTC thermistor.
　今回開示された実施の形態はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した実施の形態ではなく請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiment disclosed this time is an example in all respects and is not restrictive. The scope of the present invention is shown by the scope of claims rather than the embodiment described above, and is intended to include meaning equivalent to the scope of claims and all modifications within the scope.
　１　直流電源、２　整流回路、３，６　チョークコイル、４　トランジスタ、５　駆動回路、７　サーミスタ、１０　電源回路、５１　制御ＩＣ、５２　パルストランス、５２ｐ　一次巻線、５２ｓ　二次巻線、５３　抵抗、Ｃ１，Ｃ２　コンデンサ、Ｄ１　ダイオード、Ｅ１　交流電源、Ｔ１，Ｔ２　端子、Ｖｄｃ　出力電圧、Ｖｇｓ　ゲート電圧、Ｖｇｓｔｈ　閾値電圧。 1 DC power supply, 2 rectifier circuit, 3, 6 choke coil, 4 transistor, 5 drive circuit, 7 thermistor, 10 power supply circuit, 51 control IC, 52 pulse transformer, 52p primary winding, 52s secondary winding, 53 resistance, C1, C2 capacitor, D1 diode, E1 AC power supply, T1, T2 terminal, Vdc output voltage, Vgs gate voltage, Vgsth threshold voltage.

Claims (4)

  1. 　直流電源からの入力電圧に接続されたドレインと、ゲートと、ソースとを有するトランジスタと、
    　前記トランジスタの前記ソースに接続されたカソードと、共通電圧ノードに接続されたアノードとを有するダイオードと、
    　前記トランジスタの前記ソースおよび前記ダイオードの前記カソードに接続された第１端と、出力ノードに接続された第２端とを有するチョークコイルと、
    　前記出力ノードと、前記共通電圧ノードとの間に接続された第１のコンデンサと、
    　一次巻線と、前記トランジスタの前記ゲートに接続された二次巻線とを有するトランスと、
    　前記出力ノードにおける電圧である出力電圧に基づいて、前記トランジスタをオンオフさせるための駆動信号を、前記トランスの前記一次巻線に与える制御回路と、
    　前記直流電源の電流経路に設けられるサーミスタとを備える、電源回路。     A transistor having a drain, a gate, and a source connected to an input voltage from a DC power supply,
    A diode having a cathode connected to the source of the transistor and an anode connected to a common voltage node.
    A choke coil having a first end connected to the source of the transistor and the cathode of the diode and a second end connected to the output node.
    A first capacitor connected between the output node and the common voltage node,
    A transformer having a primary winding and a secondary winding connected to the gate of the transistor,
    A control circuit that supplies a drive signal for turning on / off the transistor to the primary winding of the transformer based on an output voltage which is a voltage at the output node.
    A power supply circuit including a thermistor provided in the current path of the DC power supply.
  2. 　前記直流電源は、前記入力電圧を前記トランジスタの前記ドレインに供給する第１端と、第２端とを有し、
    　前記電源回路は、
    　前記トランジスタの前記ドレインに接続された第１端と、前記ダイオードの前記アノードに接続された第２端とを有する第２のコンデンサをさらに備え、
    　前記サーミスタは、前記第２のコンデンサの前記第２端と、前記直流電源の前記第２端との間に接続される、請求項１に記載の電源回路。     The DC power supply has a first end and a second end that supply the input voltage to the drain of the transistor.
    The power supply circuit
    Further comprising a second capacitor having a first end connected to the drain of the transistor and a second end connected to the anode of the diode.
    The power supply circuit according to claim 1, wherein the thermistor is connected between the second end of the second capacitor and the second end of the DC power supply.
  3. 　前記直流電源は、前記入力電圧を前記トランジスタの前記ドレインに供給する第１端と、第２端とを有し、
    　前記電源回路は、
    　前記トランジスタの前記ドレインに接続された第１端と、前記直流電源の前記第２端に接続された第２端とを有する第２のコンデンサをさらに備え、
    　前記サーミスタは、前記ダイオードの前記アノードと前記第２のコンデンサの前記第２端との間に接続される、請求項１に記載の電源回路。     The DC power supply has a first end and a second end that supply the input voltage to the drain of the transistor.
    The power supply circuit
    Further comprising a second capacitor having a first end connected to the drain of the transistor and a second end connected to the second end of the DC power supply.
    The power supply circuit according to claim 1, wherein the thermistor is connected between the anode of the diode and the second end of the second capacitor.
  4. 　前記サーミスタは、ＮＴＣサーミスタである、請求項１～請求項３のいずれか１項に記載の電源回路。 The power supply circuit according to any one of claims 1 to 3, wherein the thermistor is an NTC thermistor.
PCT/JP2020/047033 2020-03-11 2020-12-16 Power supply circuit WO2021181795A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010130786A (en) * 2008-11-27 2010-06-10 Denso Corp Drive circuit of power switching element
JP2011130543A (en) * 2009-12-16 2011-06-30 Mitsubishi Electric Corp Power circuit and lighting system
JP2018007345A (en) * 2016-06-28 2018-01-11 パナソニックＩｐマネジメント株式会社 Drive device for insulated gate type semiconductor element
WO2019239453A1 (en) * 2018-06-11 2019-12-19 三菱電機株式会社 Light source lighting device and illumination apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010130786A (en) * 2008-11-27 2010-06-10 Denso Corp Drive circuit of power switching element
JP2011130543A (en) * 2009-12-16 2011-06-30 Mitsubishi Electric Corp Power circuit and lighting system
JP2018007345A (en) * 2016-06-28 2018-01-11 パナソニックＩｐマネジメント株式会社 Drive device for insulated gate type semiconductor element
WO2019239453A1 (en) * 2018-06-11 2019-12-19 三菱電機株式会社 Light source lighting device and illumination apparatus

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