WO2021175172A1 - 显示器及其驱动方法 - Google Patents

显示器及其驱动方法 Download PDF

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Publication number
WO2021175172A1
WO2021175172A1 PCT/CN2021/078385 CN2021078385W WO2021175172A1 WO 2021175172 A1 WO2021175172 A1 WO 2021175172A1 CN 2021078385 W CN2021078385 W CN 2021078385W WO 2021175172 A1 WO2021175172 A1 WO 2021175172A1
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WIPO (PCT)
Prior art keywords
signal
driving
display
pixel
row
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PCT/CN2021/078385
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English (en)
French (fr)
Inventor
姚远
叶帅
孙光远
郗文远
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2021175172A1 publication Critical patent/WO2021175172A1/zh
Priority to US17/684,247 priority Critical patent/US11636803B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • This application relates to display technology, in particular to a display and a driving method thereof.
  • the high refresh rate display has the advantages of fast response speed and smooth dynamic picture display.
  • the display usually uses a low refresh rate when displaying a static picture, and uses a high refresh rate when displaying a dynamic picture.
  • the present application provides a display driving method for driving the display.
  • the display includes n rows of pixel units and n pixel scanning circuits, and each of the pixel scanning circuits corresponds to one row of the pixel units.
  • the display driving method includes:
  • n is an integer greater than or equal to 2.
  • a display including: a display panel, a plurality of data signal driving circuits, n pixel scanning circuits, and a controller;
  • the display panel includes n rows of pixel units and is used for supplying power to n pixel units
  • Each of the data signal drive circuits is electrically connected to the pixel drive circuit of a corresponding column of pixel units;
  • each of the pixel scanning circuits is electrically connected to the pixel drive circuit of a corresponding row of pixel units;
  • the controller It is electrically connected to a plurality of data signal driving circuits and the n pixel scanning circuits, and is used for controlling the data signal driving circuit and the pixel scanning circuit, and executing the above-mentioned display driving method.
  • the above display driving method includes driving the pixel scanning circuit with a first driving signal corresponding to a first refresh frequency, and after obtaining the switching signal, driving the pixel scanning circuit with a second driving signal corresponding to the second refresh frequency.
  • the next frame of image at the first refresh frequency has n line cycles
  • the next frame of image at the second refresh frequency has n line cycles
  • the first refresh frequency is less than the second refresh frequency
  • the line cycle of the first drive signal is greater than the second The line period of the drive signal.
  • Figure 1 is a timing diagram of a drive signal of a display.
  • FIG. 2 is a schematic diagram of the structure of a display in an embodiment of the application.
  • FIG. 3 is a schematic diagram of the circuit connection of the display in an embodiment of the application.
  • FIG. 4 is a timing diagram of driving signals of the display in an embodiment of the application.
  • FIG. 5 is a timing diagram of driving signals of a display in another embodiment of the application.
  • FIG. 6 is a timing diagram of driving signals of a display in another embodiment of the application.
  • a display can have multiple refresh rates, such as a 60Hz refresh rate and a 90Hz refresh rate.
  • a 60Hz refresh rate when the monitor displays static images such as pictures or texts, a low refresh rate of 60Hz can be used to save the power consumption of the monitor; when the monitor displays dynamic images, a high refresh rate of 90Hz can be adopted to improve the screen flow of the monitor.
  • the 60Hz refresh rate means that the monitor displays 60 frames of images per second
  • the 90Hz refresh rate means that the monitor displays 90 frames of images per second.
  • H represents the line period, that is, the scanning time of each row of light-emitting pixels of each frame of image during the working process of the display; among them, the low power of the square wave signal in the clock signals CLK1 and CLK2
  • the duration of the flat signals C1 and C2 corresponds to the charging time of the capacitor in the pixel driving circuit, that is, the charging time of the energy storage capacitor of the pixel driving circuit in one line period.
  • the time occupied by one line cycle includes the charging time and the discharging time of the energy storage capacitor.
  • the voltage difference of the driving signal between discharging and charging is about 7V.
  • the line period of the display at a refresh rate of 60Hz is the same as the line period at a refresh rate of 90Hz; the time allocated for capacitor charging at a refresh rate of 60Hz is the same as that of capacitor charging at a refresh rate of 90Hz.
  • the allocated time is also the same. Since the scanning time of each row of pixel units in each frame of image is shorter at a refresh frequency of 90Hz, and the time occupied by the line cycle and capacitor charging is also shorter, in order to make all the line cycles in the scanning duration of a frame of image evenly distributed, A period of blank time must be filled between two adjacent line cycles at a refresh frequency of 60 Hz.
  • the present application provides a display 10 and a driving method thereof.
  • the display 10 of the present application includes a display panel 110, a plurality of data signal driving circuits 120, n pixel scanning circuits 130 and a controller 140.
  • the display panel 110 is used to display images.
  • the display panel 110 may include n rows of pixel units 112 and a plurality of pixel driving circuits 114 (not shown in FIG. 2) for supplying power to the n rows of pixel units 112.
  • the pixel unit 112 includes an anode, a cathode, and a light-emitting pixel arranged between the anode and the cathode.
  • the pixel driving circuit 114 may include at least two thin film transistors and at least one capacitor. As shown in FIG. 3, in one embodiment, the pixel driving circuit 114 includes a first thin film transistor T1 and a second thin film transistor T2, an energy storage capacitor Cs.
  • Each pixel unit 112 is correspondingly provided with a pixel driving circuit 114 for driving the pixel unit 112.
  • the data signal driving circuit 120 and the pixel scanning circuit 130 are electrically connected to the pixel driving circuit 114 respectively.
  • the gate of the first thin film transistor T1 is electrically connected to the drain of the second thin film transistor T2; the energy storage capacitor Cs is connected to the first thin film transistor Between the gate and the source of T1; each data signal driving circuit 120 is electrically connected to the source of the second thin film transistor T2 in each pixel driving circuit 114 of a corresponding column of pixel units 112; The pixel scanning circuit 130 is electrically connected to the gate of the second thin film transistor T2 in each pixel driving circuit 114 of the corresponding row of pixel units 112.
  • Each pixel scanning circuit 130 is electrically connected to the pixel driving circuit 114 of the corresponding row of pixel units, and is used to output a level signal to the switching thin film transistor in the pixel driving circuit 114 of the row of pixel units, that is, the gate of the second thin film transistor T2
  • the pixel scanning circuit 130 can be used to control the on and off of the second thin film transistor T2.
  • Each data signal driving circuit 120 is electrically connected to the pixel driving circuit 114 of a corresponding column of pixel units 112, and is used to output a level signal to the source of the switching thin film transistor in the pixel driving circuit 114, that is, the second thin film transistor T2, thereby
  • the pixel driving circuit 114 provides a digital signal data to charge the energy storage capacitor.
  • the data signal driving circuit 120 can control and drive the first thin film transistor T1 to be turned on through the second thin film transistor T2, and to the storage device. It can be charged in the capacitor Cs.
  • the controller 140 is used for generating a control signal according to the image to be displayed, and controlling the data signal driving circuit 120 and the pixel scanning circuit 130 through the control signal, thereby controlling the power on and off of the pixel driving circuit 114.
  • the controller 140 may be an integrated circuit (Integrated Circuit, IC chip).
  • the display panel 110 includes a plurality of pixel units 112 arranged in an array.
  • Each pixel unit 112 is driven by a pixel driving circuit 114, and each pixel driving circuit 114 is respectively connected to a data signal driving circuit 120 and a pixel scanning circuit 130, and the data signal driving circuit 120 and the pixel scanning circuit 130 jointly control each pixel
  • the drive circuit is energized or de-energized.
  • the display 10 may have n pixel scanning circuits 130, and the number of pixel scanning circuits 130 is the same as the number of rows of pixel units 112, so that each pixel scanning circuit 130 corresponds to one row of pixel units 112.
  • the letter n represents the number of rows of pixel units 112.
  • the display 10 has n rows of pixel units 112 and n pixel scanning circuits 130, and each pixel scanning circuit 130 is used to output a scanning signal to one row of pixel units 112.
  • the pixel driving circuit 114 on the display panel 110 is turned on row by row, that is, all the pixel units 112 emit light row by row.
  • the scanning time of each row of pixel units is called the line period.
  • the controller 140 can control the pixel scanning circuit by executing the display driving method as described below, so as to improve the display quality of the display 10.
  • the driving sequence of the display driving method of the present application is shown in FIG. 4, and the display driving method includes:
  • the controller 140 drives the pixel scanning circuit 130 one by one with the first driving signal, thereby driving the pixel driving circuit 114 row by row.
  • the first driving signal means that when the controller 140 drives the pixel scanning circuit 130 with the first driving signal, the refresh frequency of the display panel 110 is the first refresh frequency. In other words, when the display 10 uses the first driving signal to drive the pixel scanning circuit 130, the display panel 110 is refreshed at the first refresh frequency.
  • the line period of the first driving signal refers to the scanning duration of one line of pixel units 112 of each frame of image at the first refresh frequency.
  • the pixel units 112 on the display panel 110 are turned on row by row, that is, all the pixel units emit light row by row.
  • n is the number of rows of the pixel unit 112 of the display panel 110.
  • the first driving signal has n line periods corresponding to one frame of image at the first refresh frequency.
  • n may be an integer greater than or equal to 2, that is, the display 10 includes at least two rows of pixel units 112 and at least two pixel scanning circuits 130, and each pixel scanning circuit 130 corresponds to each row of pixel units 112 one-to-one.
  • the controller 140 may obtain the first refresh frequency according to the type of the picture to be displayed, or may obtain the first refresh frequency according to other devices built in the display 10, which is not limited here.
  • the controller 140 drives the pixel scanning circuit through the first driving signal, thereby completing the scanning of the pixel driving circuit 114.
  • the controller 140 obtains the switching signal.
  • the switching signal here refers to a switching signal of the refresh frequency when the display 10 displays an image.
  • the controller 140 can switch to obtain the switching signal according to the type of the picture to be displayed, and can also obtain the switching signal according to other devices built in the display 10, which is not limited here.
  • the pixel scanning circuit 130 is driven one by one with the second driving signal.
  • the second driving signal here means that when the controller 140 drives the pixel scanning circuit 130 with the second driving signal, the refresh frequency of the display panel 110 is the second refresh frequency. In other words, under the driving of the second driving signal, the display panel 110 is refreshed at the second refresh frequency.
  • the line period of the second driving signal refers to the scanning process time of one line of light-emitting pixels of each frame of image at the second refresh frequency. Therefore, when the display panel 110 has n rows of light-emitting pixels, the second driving signal has n row periods corresponding to one frame of image at the second refresh frequency.
  • n is greater than or equal to 2, so I won’t repeat it here.
  • the first refresh frequency is less than the second refresh frequency, and the line period of the first driving signal is greater than the line period of the second driving signal.
  • the first refresh frequency may be 60 Hz, that is, at the first refresh frequency, the display panel 110 displays 60 frames of images per second. At this time, assuming that the display panel 110 has n rows of light-emitting pixels, the occupation time of the row period of the first driving signal should be equal to or less than 1/60n second.
  • the second refresh frequency may be 90 Hz, that is, at the second refresh frequency, the display panel 110 displays 90 frames of images per second. At this time, the occupation time of the line period of the second driving signal may be 1/90n second. Then the line period of the first driving signal is equal to or less than 1/60n second and greater than 1/90n second.
  • the first refresh frequency is less than the second refresh frequency
  • the line period of the first driving signal is greater than the line period of the second driving signal. Therefore, when the display is refreshed at the first refresh rate, compared with the related art, the blank time between the line periods of two adjacent first driving signals is shortened, thereby improving the display effect of the display 10 at a low refresh rate.
  • the inventor’s test shows that when switching from a lower first refresh frequency to a higher second refresh frequency, because two different drive timings of the first drive signal and the second drive signal are used, the control can be avoided.
  • the output waveform of the detector 140 is abnormal, thereby avoiding the flickering phenomenon of the display 10 and improving the display quality.
  • the inventive idea of the display driving method of the present application is to use two different driving timings under different conditions of the first refresh frequency and the second refresh frequency, so that the display 10 avoids the phenomenon of flickering when the refresh frequency is switched. Therefore, although the above embodiments only limit the switching from the first refresh frequency to the second refresh frequency, those skilled in the art can also unambiguously conclude that when switching from the second refresh frequency to the first refresh frequency, The technical solution for avoiding the flickering phenomenon of the display 10 by using two different driving timings should also be understood as falling within the protection scope of the present application.
  • the time occupied by a single line period of the first driving signal is the reciprocal of the product of the first refresh frequency and the number of line periods of the first driving signal in a frame of image, that is, the ratio of the first refresh frequency and the number of rows of light-emitting pixels n
  • the inverse of the product may be 60 Hz
  • the display panel 110 has n rows of light-emitting pixels
  • the time taken by a single row period of the first driving signal is 1/60n second.
  • the time occupied by a single line cycle of the second drive signal is the reciprocal of the product of the second refresh frequency and the number of line cycles of the second drive signal in a frame of image, that is, the reciprocal of the product of the second refresh frequency and the number of rows of light-emitting pixels n .
  • the second refresh frequency may be 90 Hz
  • the display panel 110 has n rows of light-emitting pixels
  • the time occupied by a single row period of the second driving signal is 1/90n second.
  • step S100 that is, when the pixel scanning circuit 114 is driven by the first driving signal corresponding to the first refresh rate, there is no blank time between two adjacent line periods, thereby improving the display effect of the display 10 at a low refresh rate. , And avoid the abnormal output waveform of the controller 140, thereby avoiding the flickering phenomenon of the display 10, and improving the display quality.
  • each line period of the first driving signal includes a first charging time for charging the energy storage capacitor
  • each line period of the second driving signal includes a charge time for charging the energy storage capacitor.
  • the second charging time, the first charging time is longer than the second charging time, so that each row of pixel units has a longer charging time under the low refresh frequency of the display, and the blank time filled between two adjacent row cycles is reduced, thereby improving the display Display effect at low refresh rate.
  • the first charging time corresponding to the i-th row of pixel units is located at the i-th row period of the first driving signal, and the second charging time corresponding to the i-th row of pixel units is located at the time of the second driving signal.
  • the i-th row period where i is greater than or equal to 1, and less than or equal to n.
  • the controller 140 drives the pixel scanning circuit 130 with the first driving signal, it needs to start scanning from the first row of pixel units of a frame of image, and the first row of pixel units corresponds to the first row of the first driving signal.
  • the first charging time corresponding to the first row of pixel units is within the first row period of the first driving signal.
  • the controller 140 drives the pixel scanning circuit 130 with the second driving signal, it corresponds to each row of pixels
  • the second charging time of the cell is within the corresponding row period of the second driving signal for driving the row of pixel cells.
  • each first charging time has the same starting time point and the same ending time point in the row period of the corresponding first driving signal, and each second charging time is at the corresponding first charging time.
  • the line periods of the two driving signals have the same starting time point and the same ending time point. As shown in FIG.
  • the start time point and the end time point of the first charging time It is consistent with the start time point and the end time point of the first charging time in the n-1th row period of the first driving signal; the start time of the second charging time in the first row period of the second driving signal.
  • the point and the end time point are consistent with the start time point and the end time point of the second charging time in the second line period of the second driving signal, so that the display of each row of pixel units when displaying a frame of image at the same refresh frequency The effect tends to be consistent, which effectively reduces display mura problems, thereby improving the overall display effect of the display panel 110.
  • the first driving signal includes two clock signals, which are a first clock signal CLK1 and a second clock signal CLK2, respectively.
  • the first clock signal CLK1 of the first driving signal and the second clock signal CLK2 of the first driving signal include n first effective level signals C1 corresponding to n first charging times.
  • the second drive signal still includes two clock signals, which are the third clock signal CLK3 and the fourth clock signal CLK4, respectively.
  • the third clock signal CLK3 and the fourth clock signal CLK4 include corresponding n second clock signals. N second effective level signals C2 for charging time.
  • the first effective level signal C1 corresponding to the first charging time in the n-1th row period of the first driving signal is located in the n-1th row period H(n -1) In the first clock signal CLK1 of the corresponding first driving signal; the first effective level signal C1 corresponding to the first charging time in the nth row period of the first driving signal is located in the same position as the first driving signal In the second clock signal CLK2 of the first driving signal corresponding to the nth row period H(n); the second effective level signal corresponding to the second charging time in the first row period of the second driving signal C2 is located in the third clock signal CLK3 of the second driving signal corresponding to the first row period H(1) of the second driving signal; corresponds to the second charging time in the second row period of the second driving signal
  • the second effective level signal C2 of is located at the fourth clock signal CLK4 of the second driving signal corresponding to the second row period H(2) of the second driving signal.
  • the first effective level signal C1 corresponding to the first charging time in the n-1th row period of the first driving signal is located at the same level as the first driving signal.
  • the second clock signal CLK2 of the first driving signal corresponding to the n-1th line period H(n-1) of the signal the first charging time corresponding to the first charging time in the nth line period of the first driving signal
  • An effective level signal C1 is located at the first clock signal CLK1 of the first driving signal corresponding to the nth line period H(n) of the first driving signal;
  • the second effective level signal C2 corresponding to the charging time is located at the fourth clock signal CLK4 of the second driving signal corresponding to the first line period H(1) of the second driving signal, and the second signal C2 of the second driving signal
  • the second effective level signal C2 corresponding to the second charging time of the row period is located in the third clock signal CLK3 of the second driving signal corresponding to the second row period H(2) of the second driving signal.
  • each first effective level signal C1 includes a first falling edge and a first rising edge, and the first effective level of the i-th row period of the first drive signal
  • the first falling edge of the level signal C1 is within the first charging time of the i-th row period of the first driving signal, and the first effective level signal C1 of the i-th row period of the first driving signal falls first
  • the start time of the edge is the same as the start time of the first charging time of the i-th line period of the first driving signal, and the first rising edge of the first effective level signal C1 of the i-th line period of the first driving signal It is within the first non-charging time of the (i+1)th row period of the first driving signal.
  • each second effective level signal C2 includes a second falling edge and a second rising edge, and the second falling edge of the second effective level signal C2 of the i-th line period of the second driving signal is at the first falling edge of the second driving signal.
  • the second charging time of the i line period, and the start time of the second falling edge of the second effective level signal C2 of the i-th line period of the second driving signal and the i-th line period of the second driving signal The start time point of the second charging time is the same, the second rising edge of the second effective level signal C2 of the i-th line period of the second driving signal is at the second of the i+1-th line period of the second driving signal During non-charging time.
  • i is equal to n
  • the second rising edge of the second effective level signal C2 of the i-th line period of the second driving signal is in the second non-charging of the first line period of the second driving signal of the next frame of image in time.
  • the display 10 drives and displays with the first driving signal and the second driving signal as shown in FIG. 6, not only can the display effect at a low refresh frequency be ensured, but it can also avoid switching from the first refresh frequency to the second refresh frequency.
  • the signal waveform is abnormal, the pixel scanning circuit works abnormally, and then causes the phenomenon of flickering screen.
  • the first clock signal CLK1 and the third clock signal CLK3 are clock signals corresponding to the display 10 at different refresh frequencies, and they pass through the same signal line at different display times. Output, the same second clock signal CLK2 and fourth clock signal CLK4 are also output through the same signal line at different display times.
  • the duration of the first rising edge of each of the first effective levels in the first drive signal is the same, and each of the first effective levels in the first drive signal has the same duration.
  • the duration of the first falling edge of the level is the same, and the duration of the second rising edge of each of the second effective levels in the second drive signal is the same; in the second drive signal
  • the duration of the second falling edge of each of the second effective levels is the same, which can avoid the phenomenon of flickering when the display 10 switches the refresh frequency.
  • Each line period of the first driving signal has the same first charging time, and each line period of the second driving signal has the same second charging time, thereby improving the display effect of the display 10.
  • the duration of the first effective level signal is greater than the duration of the second effective level signal.
  • the duration of the first effective level signal in the corresponding first charging time in the i-th row period of the first driving signal is greater than that of the second driving signal
  • the second effective level signal in the i-th row period of the signal is within its corresponding second charging time; the first effective level signal in the i-th row period of the first drive signal
  • the duration in the corresponding first charging time is greater than the duration in the i+1th line period of the first driving signal that the first valid level signal is in the corresponding first charging time ;
  • the second effective level signal in the i-th row period of the second drive signal is in its corresponding second charging time for a duration greater than in the i+1-th row period of the second drive signal
  • the second effective level signal is in its corresponding duration of the second charging time.
  • the first refresh frequency may be one of 60 Hz, 30 Hz, 10 Hz, 5 Hz, 4 Hz, 2 Hz, and 1 Hz
  • the second refresh frequency may be one of 90 Hz, 120 Hz, and 240 Hz. It should be understood that one of the technical problems to be solved by this application is generated when the display 10 is switched from a low refresh rate to a high refresh rate. Therefore, the size of the first refresh rate and the second refresh rate only needs to satisfy that the first refresh rate is less than The second refresh frequency should be understood to be within the protection scope of this application.
  • the pixel scanning circuit 130 is driven by a first driving signal corresponding to a first refresh frequency, and after obtaining the switching signal, the pixel scanning circuit 130 is driven by a second driving signal corresponding to the second refresh frequency.
  • the first driving signal corresponds to a frame of image at the first refresh frequency and has n line periods
  • the second driving signal corresponds to a frame of image at the second refresh frequency and has n line periods
  • the first refresh frequency is less than the second refresh.
  • the line period of the first drive signal is greater than the line period of the second drive signal.
  • the first driving signal and the second driving signal use two driving signals, the first driving signal and the second driving signal, respectively.
  • Different driving timings can avoid abnormal output waveforms of the controller 140, thereby avoiding the flickering phenomenon of the display 10 and improving the display quality.
  • the line period of the first driving signal is greater than the line period of the second driving signal, which can also prevent the display effect from being affected by the excessively long blank time between the line periods when the refresh frequency is low, and the display quality under the low refresh frequency can be improved.
  • a display 10 includes a display panel 110, a plurality of data signal driving circuits 120, n pixel scanning circuits 130, and a controller; the display panel 110 includes n rows of pixel units 112 and a controller for N rows of pixel drive circuits 114 powered by the row of pixel units 112; each data signal drive circuit 120 is electrically connected to the pixel drive circuit 114 of a corresponding column of pixel units 112; each of the pixel scanning circuits 130 is connected to a corresponding row of pixel units 112 The pixel driving circuit 114 is electrically connected; and the controller 140 is electrically connected to a plurality of data signal driving circuits 120 and n of the pixel scanning circuits 130 for controlling the data signal driving circuit 120 and the pixel scanning circuits 130. And the display 10 is driven by the display driving method described above.

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Abstract

本申请涉及一种显示器及显示驱动方法。该显示驱动方法包括以对应第一刷新频率的第一驱动信号驱动像素扫描电路，以及获取切换信号后，以对应第二刷新频率的第二驱动信号驱动像素扫描电路。其中，第一刷新频率下一帧图像具有n个第一驱动信号的行周期，第二刷新频率下一帧图像具有n个第二驱动信号的行周期，第一刷新频率小于第二刷新频率，第一驱动信号的行周期大于第二驱动信号的行周期。

Description

显示器及其驱动方法
相关申请的交叉引用
本申请要求于2020年3月3日提交中国专利局，申请号为202010140727.5的中国专利申请的优先权,在此将其全文引入作为参考。
技术领域
本申请涉及显示技术，特别是涉及一种显示器及其驱动方法。
背景技术
高刷新频率的显示器具有响应速度快，动态画面显示流畅的优点。
相关技术中，在显示静态画面时，显示器通常采用低刷新频率，显示动态画面时采用高刷新频率。
申请人在实现相关技术的过程中发现：传统的显示器，在低刷新频率到高刷新频率的切换过程中，容易出现屏闪现象。
发明内容
基于此，有必要针对传统的显示器在切换刷新频率时容易出现闪屏现象的问题，提供一种显示器及其驱动方法。
本申请一方面提供了一种显示器驱动方法，用于驱动所述显示器，所述显示器包括n行像素单元和n个像素扫描电路，每个所述像素扫描电路对应一行所述像素单元，其特征在于，所述显示器驱动方法包括：
以对应第一刷新频率的第一驱动信号驱动n个所述像素扫描电路，其中，所述第一驱动信号对应所述第一刷新频率下的一帧图像具有n个行周期；
获取切换信号，根据所述切换信号以对应第二刷新频率的第二驱动信号驱动n个所述像素扫描电路，其中，所述第二驱动信号对应所述第二刷新频率下的一帧图像具有n个行周期，所述第一刷新频率小于所述第二刷新频率，所述第一驱动信号的所述行周期大于所述第二驱动信号的所述行周期；
其中，n为大于等于2的整数。
本申请另一方面提供了一种显示器，包括：显示面板、多个数据信号驱动电路、n个像素扫描电路和控制器；所述显示面板包括n行像素单元和用于向n个像素单元供电的n 个像素驱动电路；每一数据信号驱动电路与对应的一列像素单元的像素驱动电路电连接；每个所述像素扫描电路与对应的一行像素单元的像素驱动电路电连接；所述控制器与多个数据信号驱动电路和n个所述像素扫描电路电连接，用于控制数据信号驱动电路和所述像素扫描电路，并执行上述的显示器驱动方法。
上述显示器驱动方法，包括以对应第一刷新频率的第一驱动信号驱动像素扫描电路，以及获取切换信号后，以对应第二刷新频率的第二驱动信号驱动像素扫描电路。其中，第一刷新频率下一帧图像具有n个行周期，第二刷新频率下一帧图像具有n个行周期，第一刷新频率小于第二刷新频率，第一驱动信号的行周期大于第二驱动信号的行周期。以此，在从较低的第一刷新频率切换至较高的第二刷新频率时，由于使用了第一驱动信号和第二驱动信号两个不同的驱动时序，可以避免控制器输出波形异常，从而避免显示器出现闪屏现象，提升显示品质。
附图说明
图1为一种显示器的驱动信号时序图。
图2为本申请一个实施例中显示器的结构示意图。
图3为本申请一个实施例中显示器的电路连接示意图。
图4为本申请一个实施例中显示器的驱动信号时序图。
图5为本申请另一个实施例中显示器的驱动信号时序图。
图6为本申请又一个实施例中显示器的驱动信号时序图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
一个显示器可以具有多种刷新频率，如具有60Hz刷新频率和90Hz刷新频率。其中，当显示器显示图片或文字等静态图像时可以采用60Hz的低刷新频率，从而节约显示器功耗；而当显示器显示动态画面时，则可以采用90Hz的高刷新频率，从而提升显示器的画面流程度。其中，60Hz刷新频率是指显示器每秒显示60帧图像，90Hz刷新频率是指显示器每秒显示90帧图像。
一种显示器的扫描信号时序如图1所示，H表示行周期，即显示器工作过程中，每帧图像的每行发光像素的扫描时长；其中，时钟信号CLK1和CLK2中方波信号的低电平信号C1和C2持续时间对应像素驱动电路中的电容的充电时间，即在一个行周期内，像素驱动电路的储能电容的充电时间。一个行周期所占用的时间包括储能电容充电时间和放电时间，放电和充电之间的驱动信号的电压差约为7V。由图1可以看出，该显示器在60Hz刷新频率时的行周期与90Hz刷新频率时的行周期分配的时间相同；显示器在60Hz刷新频率时的电容充电分配的时间与90Hz刷新频率时的电容充电分配的时间也相同。由于90Hz刷新频率时每帧图像中每行像素单元的扫描占用的时间较短，行周期和电容充电占用的时间也较短，为了使一帧图像的扫描持续时间中的所有行周期均匀分布，60Hz刷新频率下相邻两个行周期之间须填充一段空白时间。
在上述实现过程中，在低刷新频率的情况下，相邻两个行周期之间存在较长的空白时间，致使低刷新频率下显示器的显示效果较差，且在从低刷新频率切换到高刷新频率的过程中会出现闪屏现象。
针对上述技术问题，本申请提供一种显示器10及其驱动方法。如图2所示，本申请的显示器10包括显示面板110、多个数据信号驱动电路120、n个像素扫描电路130和控制器140。
具体的，显示面板110用于显示图像。显示面板110可以包括n行像素单元112和用于向n行像素单元112供电的多个像素驱动电路114(图2未示出)。所述像素单元112包括阳极、阴极以及设于阳极和阴极之间的发光像素。所述像素驱动电路114可以包括至少两个薄膜晶体管以及至少一个电容。如图3所示，在一个实施例中，所述像素驱动电路114包括第一薄膜晶体管T1和第二薄膜晶体管T2、储能电容Cs。每个所述像素单元112对应设置有一个用于驱动所述像素单元112的像素驱动电路114。所述数据信号驱动电路120和所述像素扫描电路130分别与所述像素驱动电路114电连接。
在一实施例中，如图3所示，所述第一薄膜晶体管T1的栅极与所述第二薄膜晶体管T2的漏极电连接；所述储能电容Cs连接于所述第一薄膜晶体管T1的栅极与源极之间；每个数据信号驱动电路120与对应的一列像素单元112的每一所述像素驱动电路114中的第二薄膜晶体管T2的源极电连接；每个所述像素扫描电路130与对应的一行像素单元112的每一所述像素驱动电路114中的第二薄膜晶体管T2的栅极电连接。
每个像素扫描电路130与其对应的一行像素单元的像素驱动电路114电连接，用于向该行像素单元的像素驱动电路114中的开关薄膜晶体管即第二薄膜晶体管T2的栅极输出 电平信号，从而控制第二薄膜晶体管T2的通断，如图3所示的实施例中，像素扫描电路130可用于控制第二薄膜晶体管T2的通断。
每个数据信号驱动电路120与对应的一列像素单元112的像素驱动电路114电连接，用于向像素驱动电路114中的开关薄膜晶体管即第二薄膜晶体管T2的源极输出电平信号，从而向像素驱动电路114提供数字信号data，以向储能电容充电。如图3所示的实施例中，当像素扫描电路130控制第二薄膜晶体管T2导通时，数据信号驱动电路120可通过第二薄膜晶体管T2控制驱动第一薄膜晶体管T1导通，并向储能电容Cs内充电。
控制器140用于根据待显示的图像生成控制信号，并通过该控制信号控制数据信号驱动电路120和像素扫描电路130，从而控制像素驱动电路114的通电与断电。所述控制器140可以是集成电路(Integrated Circuit，IC芯片)。
通常，显示面板110包括多个呈阵列分布的像素单元112。每个像素单元112由一个像素驱动电路114驱动，每个像素驱动电路114分别与数据信号驱动电路120和像素扫描电路130连接，数据信号驱动电路120和像素扫描电路130共同控制所述每个像素驱动电路通电或断电。在一些实施例中，显示器10可以具有n个像素扫描电路130，且像素扫描电路130的个数与像素单元112的行数相同，从而使每个像素扫描电路130对应一行像素单元112。字母n表示像素单元112的行的数量，所述显示器10具有n行像素单元112和n个像素扫描电路130，每个像素扫描电路130用于向一行像素单元112输出扫描信号。在此情况下，当显示面板110显示一帧图像时，显示面板110上的像素驱动电路114逐行导通，即所有的像素单元112逐行发光。一帧图像中，每行像素单元的扫描时长称为行周期。
在一实施例中，控制器140可以通过执行如下述的显示器驱动方法，以控制像素扫描电路，从而提升显示器10的显示品质。
在一个实施例中，本申请的显示器驱动方法的驱动时序如图4所示，所述显示器驱动方法包括：
S100，以对应第一刷新频率的第一驱动信号驱动n个像素扫描电路130，其中，第一驱动信号对应第一刷新频率下的一帧图像具有n个行周期。
控制器140以第一驱动信号逐个驱动像素扫描电路130，从而逐行驱动像素驱动电路114。所述第一驱动信号是指：当控制器140以第一驱动信号驱动像素扫描电路130时，显示面板110的刷新频率为第一刷新频率。换句话说，当显示器10采用第一驱动信号驱动像素扫描电路130时，显示面板110以第一刷新频率进行刷新。
第一驱动信号的行周期是指在第一刷新频率下，每帧图像的一行像素单元112的扫描时长。一般的，显示面板110显示一帧图像时，显示面板110上的像素单元112逐行导通，即所有的像素单元逐行发光。在本申请中，n为显示面板110像素单元112的行数。在步骤S100中，第一驱动信号对应第一刷新频率下的一帧图像具有n个行周期。n可以是大于等于2的整数，即该显示器10包括至少两行像素单元112，以及至少两个像素扫描电路130，且每个像素扫描电路130和每行像素单元112一一对应。
一般的，控制器140可以根据待显示画面的类型得到第一刷新频率，也可以根据显示器10内置的其它器件得到第一刷新频率，在此不做限制。当显示器10需要以第一刷新频率显示图像时，控制器140通过第一驱动信号驱动像素扫描电路，从而完成对像素驱动电路114的扫描。
S200，获取切换信号，根据切换信号以对应第二刷新频率的第二驱动信号驱动n个像素扫描电路，其中，第二驱动信号对应第二刷新频率下的一帧图像具有n个行周期，第一刷新频率小于第二刷新频率，第一驱动信号的行周期大于第二驱动信号的行周期。
控制器140获取切换信号。这里的切换信号指显示器10显示图像时的刷新频率的切换信号。控制器140可以根据待显示画面的类型切换得到切换信号，也可以根据显示器10内置的其它器件得到切换信号，在此不做限制。控制器140获取切换信号后，以第二驱动信号逐个驱动像素扫描电路130。这里的第二驱动信号是指：当控制器140以第二驱动信号驱动像素扫描电路130时，显示面板110的刷新频率为第二刷新频率。换句话说，在第二驱动信号的驱动下，显示面板110以第二刷新频率进行刷新。
第二驱动信号的行周期是指第二刷新频率下，每帧图像的一行发光像素的扫描过程时间。因此，在显示面板110具有n行发光像素时，第二驱动信号对应第二刷新频率下的一帧图像具有n个行周期。这里的n大于等于2，不再赘述。
在一实施例中，第一刷新频率小于第二刷新频率，第一驱动信号的行周期大于第二驱动信号的行周期。例如，第一刷新频率可以是60Hz，即在第一刷新频率下，显示面板110每秒钟显示60帧图像。此时，假设显示面板110具有n行发光像素，则第一驱动信号的行周期的占用时长应等于或小于1/60n秒。第二刷新频率可以是90Hz，即在第二刷新频率下，显示面板110每秒钟显示90帧图像。此时，第二驱动信号的行周期的占用时长可以是1/90n秒。则第一驱动信号的行周期等于或小于1/60n秒，且大于1/90n秒。
在该实施例中，第一刷新频率小于第二刷新频率，第一驱动信号的行周期大于第二驱动信号的行周期。由此，在显示器以第一刷新频率刷新的情况下，相较于相关技术，相邻 两个第一驱动信号的行周期之间的空白时间缩短，从而提升低刷新频率下显示器10的显示效果。同时，经发明人测试表明，在从较低的第一刷新频率切换至较高的第二刷新频率时，由于使用了第一驱动信号和第二驱动信号两种不同的驱动时序，可以避免控制器140输出波形异常，从而避免显示器10出现闪屏现象，提升显示品质。
本申请的显示器驱动方法的发明思路为：在第一刷新频率和第二刷新频率的不同情况下使用两种不同的驱动时序，使显示器10在刷新频率切换时避免出现闪屏现象。因此，虽然上述实施例仅限定了从第一刷新频率切换至第二刷新频率的情况，本领域技术人员也可以毫无疑义的得出，在从第二刷新频率切换至第一刷新频率时，通过使用两种不同的驱动时序以避免显示器10出现闪屏现象的技术方案也应理解为在本申请的保护范围之内。
进一步的，第一驱动信号的单个行周期所占用时间为第一刷新频率与一帧图像里第一驱动信号的行周期个数乘积的倒数，即第一刷新频率与发光像素的行数n的乘积的倒数。例如，第一刷新频率可以是60Hz，显示面板110具有n行发光像素，则第一驱动信号的单个行周期所占用时间为1/60n秒。第二驱动信号的单个行周期所占用时间为第二刷新频率与一帧图像里第二驱动信号的行周期个数乘积的倒数，即第二刷新频率与发光像素的行数n的乘积的倒数。例如，第二刷新频率可以是90Hz，显示面板110具有n行发光像素，则第二驱动信号的单个行周期所占用的时间为1/90n秒。此时，执行步骤S100时，即以对应第一刷新频率的第一驱动信号驱动像素扫描电路114时，相邻两个行周期之间没有空白时间，从而提升低刷新频率下显示器10的显示效果，并避免控制器140输出波形异常，从而避免显示器10出现闪屏现象，提升显示品质。
在本申请的另一个实施例中，每个第一驱动信号的行周期包括对储能电容进行充电的第一充电时间，每个第二驱动信号的行周期内包括对储能电容进行充电的第二充电时间，第一充电时间大于第二充电时间，使得在显示器低刷新频率下每一行像素单元具有较长的充电时间，相邻两个行周期间填充的空白时间减少，从而能够提高显示器在低刷新频率下的显示效果。
在本申请的另一个实施例中，对应第i行像素单元的第一充电时间位于第一驱动信号的第i个行周期，对应第i行像素单元的第二充电时间位于第二驱动信号的第i个行周期，其中i大于等于1，小于等于n。
具体地，控制器140以第一驱动信号驱动像素扫描电路130时，需要从一帧图像的第1行像素单元起开始扫描，此时第1行像素单元对应第一驱动信号的第1个行周期，对应第1行像素单元的第一充电时间则位于第一驱动信号的第1个行周期内；同理，当控制器 140以第二驱动信号驱动像素扫描电路130时，对应每一行像素单元的第二充电时间位于驱动该行像素单元的第二驱动信号的对应行周期内。
在本申请另一个实施例中，每个第一充电时间在对应的第一驱动信号的行周期内有相同的起始时间点和相同的结束时间点,每个第二充电时间在对应的第二驱动信号的行周期内有相同的起始时间点和相同的结束时间点。如图4所示，以第一驱动信号和第二驱动信号对应的两个行周期为例，第一驱动信号的第n个行周期内，第一充电时间的起始时间点和结束时间点与第一驱动信号的第n-1个行周期内的第一充电时间的起始时间点和结束时间点一致；第二驱动信号的第1个行周期内，第二充电时间的起始时间点和结束时间点与第二驱动信号的第2个行周期内的第二充电时间的起始时间点和结束时间点一致，使得在同一刷新频率下显示一帧图像时每一行像素单元的显示效果趋于一致，有效减少显示的mura问题，从而提高显示面板110的整体显示效果。
进一步地，如图4至图6所示，第一驱动信号包括两个时钟信号，分别为第一时钟信号CLK1和第二时钟信号CLK2。第一驱动信号的第一时钟信号CLK1和第一驱动信号的第二时钟信号CLK2包括对应n个第一充电时间的n个第一有效电平信号C1。同样地，刷新频率改变后，第二驱动信号仍包括两个时钟信号，分别为第三时钟信号CLK3和第四时钟信号CLK4，第三时钟信号CLK3和第四时钟信号CLK4包括对应n个第二充电时间的n个第二有效电平信号C2。如图4所示，第一驱动信号的第n-1个行周期内的第一充电时间对应的第一有效电平信号C1位于与第一驱动信号的第n-1个行周期H(n-1)所对应的第一驱动信号的第一时钟信号CLK1中；与第一驱动信号的第n个行周期内的第一充电时间对应的第一有效电平信号C1位于与第一驱动信号的第n个行周期H(n)所对应的第一驱动信号的第二时钟信号CLK2中；与第二驱动信号的第1个行周期内的第二充电时间对应的第二有效电平信号C2位于与第二驱动信号的第1个行周期H(1)所对应的第二驱动信号的第三时钟信号CLK3中；与第二驱动信号的第2个行周期内的第二充电时间对应的第二有效电平信号C2位于与第二驱动信号的第2个行周期H(2)所对应的第二驱动信号的第四时钟信号CLK4。
在本申请的另一个实施例中，如附图5所示，与第一驱动信号的第n-1个行周期内的第一充电时间对应的第一有效电平信号C1位于与第一驱动信号的第n-1个行周期H(n-1)所对应的第一驱动信号的第二时钟信号CLK2中，与第一驱动信号的第n个行周期内的第一充电时间对应的第一有效电平信号C1位于与第一驱动信号的第n个行周期H(n)所对应的第一驱动信号的第一时钟信号CLK1；与第二驱动信号的第1个行周期的第二充电时间 对应的第二有效电平信号C2位于与第二驱动信号的第1个行周期H(1)所对应的第二驱动信号的第四时钟信号CLK4，与第二驱动信号的第2个行周期的第二充电时间对应的第二有效电平信号C2位于与第二驱动信号的第2个行周期H(2)所对应的第二驱动信号的第三时钟信号CLK3中。
在本申请的另一个实施例中，如图6所示，每个第一有效电平信号C1包括第一下降沿和第一上升沿，第一驱动信号的第i个行周期的第一有效电平信号C1的第一下降沿处于第一驱动信号的第i个行周期的第一充电时间内，且第一驱动信号的第i个行周期的第一有效电平信号C1的第一下降沿的开始时间与第一驱动信号的第i个行周期的第一充电时间的起始时间点相同，第一驱动信号的第i个行周期的第一有效电平信号C1的第一上升沿处于第一驱动信号的第i+1个行周期的第一非充电时间内。当i等于n时，第一驱动信号的第i个行周期的第一有效电平信号C1的第一上升沿处于下一帧图像的第一驱动信号的第1个行周期的第一充非电时间内。每个第二有效电平信号C2包括第二下降沿和第二上升沿，第二驱动信号的第i个行周期的第二有效电平信号C2的第二下降沿处于第二驱动信号的第i个行周期的第二充电时间内，且第二驱动信号的第i个行周期的第二有效电平信号C2的第二下降沿的开始时间与第二驱动信号的第i个行周期的第二充电时间的起始时间点相同，第二驱动信号的第i个行周期的第二有效电平信号C2的第二上升沿处于第二驱动信号的第i+1个行周期的第二非充电时间内。当i等于n时，第二驱动信号的第i个行周期的第二有效电平信号C2的第二上升沿处于下一帧图像的第二驱动信号的第1个行周期的第二非充电时间内。当显示器10以如图6所示的第一驱动信号和第二驱动信号进行驱动显示时，不仅能够保证在低刷新频率下的显示效果，也能够避免在第一刷新频率切换为第二刷新频率时信号波形的异常，导致像素扫描电路工作异常，进而引起闪屏的现象。
需要说明的是，在驱动像素扫描电路130时，第一时钟信号CLK1和第三时钟信号CLK3是显示器10在不同刷新频率下所对应的时钟信号，两者在不同的显示时间通过同一条信号线输出，同样的第二时钟信号CLK2和第四时钟信号CLK4也在不同的显示时间通过同一条信号线输出。
更进一步地，所述第一驱动信号中的每个所述第一有效电平的所述第一上升沿的持续时间长度相同，所述第一驱动信号中的每个所述第一有效电平的所述第一下降沿的持续时间长度相同，所述第二驱动信号中的每个所述第二有效电平所述第二上升沿的持续时间长度相同；所述第二驱动信号中的每个所述第二有效电平的所述第二下降沿的持续时间长度 相同，即可避免在显示器10切换刷新频率时出现闪屏现象。在第一驱动信号的各个行周期内具有相同的第一充电时间，第二驱动信号的各个行周期内具有相同的第二充电时间，从而提升显示器10的显示效果。
在其中一个实施例中，所述第一有效电平信号的持续时间大于所述第二有效电平信号的持续时间。
在其中一个实施例中，所述第一驱动信号的第i个行周期中的所述第一有效电平信号处于其对应的所述第一充电时间内的持续时间大于所述第二驱动信号的第i个行周期中的所述第二有效电平信号处于其对应的所述第二充电时间内持续的时间；所述第一驱动信号的第i个行周期中第一有效电平信号处于其对应的所述第一充电时间内的持续时间大于所述第一驱动信号的第i+1个行周期中第一有效电平信号处于其对应的所述第一充电时间内的持续时间；所述第二驱动信号的第i个行周期中第二有效电平信号处于其对应的所述第二充电时间内的持续时间大于所述第二驱动信号的第i+1个行周期中第二有效电平信号处于其对应的所述第二充电时间内的持续时间。
在一个实施例中，第一刷新频率可以是60Hz、30Hz、10Hz、5Hz、4Hz、2Hz和1Hz中的一个，第二刷新频率可以是90Hz、120Hz和240Hz中的一个。需要理解的是，本申请所要解决的技术问题之一是在显示器10从低刷新频率切换至高刷新频率时产生的，因此，第一刷新频率和第二刷新频率的大小只要满足第一刷新频率小于第二刷新频率，即应理解为在本申请的保护范围之内。
本申请的显示器驱动方法，以对应第一刷新频率的第一驱动信号驱动像素扫描电路130，获取切换信号后，以对应第二刷新频率的第二驱动信号驱动像素扫描电路130。其中，第一驱动信号对应第一刷新频率下的一帧图像具有n个行周期，第二驱动信号对应第二刷新频率下的一帧图像具有n个行周期，第一刷新频率小于第二刷新频率，第一驱动信号的行周期大于第二驱动信号的行周期。在这种情况下，在从较低的第一刷新频率切换至较高的第二刷新频率时，由于第一刷新频率和第二刷新频率分别使用了第一驱动信号和第二驱动信号两个不同的驱动时序，可以避免控制器140输出波形异常，从而避免显示器10出现闪屏现象，提升显示品质。同时，第一驱动信号的行周期大于第二驱动信号的行周期，还可以避免低刷新频率时，因行周期之间的空白时间过长影响显示效果，提升低刷新频率下的显示质量。
在一个实施例中，一种显示器10，包括显示面板110、多个数据信号驱动电路120、n 个像素扫描电路130和控制器；所述显示面板110包括n行像素单元112和用于向n行像素单元112供电的n行像素驱动电路114；每一数据信号驱动电路120与对应的一列像素单元112的像素驱动电路114电连接；每个所述像素扫描电路130与对应的一行像素单元112的像素驱动电路114电连接；以及所述控制器140与多个数据信号驱动电路120和n个所述像素扫描电路130电连接，用于控制所述数据信号驱动电路120和所述像素扫描电路130。且所述显示器10由上述显示器驱动方法驱动。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种显示器驱动方法，用于驱动所述显示器，所述显示器包括n行像素单元和n个像素扫描电路，每个所述像素扫描电路对应一行所述像素单元，其中，所述显示器驱动方法包括：
    以对应第一刷新频率的第一驱动信号驱动n个所述像素扫描电路，其中，所述第一驱动信号对应所述第一刷新频率下的一帧图像具有n个行周期；
    获取切换信号，根据所述切换信号以对应第二刷新频率的第二驱动信号驱动n个所述像素扫描电路，其中，所述第二驱动信号对应所述第二刷新频率下的一帧图像具有n个行周期，所述第一刷新频率小于所述第二刷新频率，所述第一驱动信号的所述行周期大于所述第二驱动信号的所述行周期；
    其中，n为大于或等于2的整数。
  2. 根据权利要求1所述的显示器驱动方法，其中，所述第一驱动信号的每个所述行周期包括第一充电时间，所述第二驱动信号的每个所述行周期包括第二充电时间，所述第一充电时间大于所述第二充电时间。
  3. 根据权利要求2所述的显示器驱动方法，其中，对应第i行所述像素单元的所述第一充电时间位于所述第一驱动信号的第i个行周期内；
    对应第i行所述像素单元的所述第二充电时间位于所述第二驱动信号的第i个行周期内；
    其中，i大于等于1，小于等于n。
  4. 根据权利要求3所述的显示器驱动方法，其中，每个所述第一充电时间在所述第一驱动信号的每个所述行周期内具有相同的起始时间点和相同的结束时间；
    每个所述第二充电时间在所述第二驱动信号的每个所述行周期内具有相同的起始时间点和相同的结束时间点。
  5. 根据权利要求2所述的显示器驱动方法，其中，所述第一驱动信号包括两个时钟信号，所述两个时钟信号包括对应n个所述第一充电时间的n个第一有效电平信号；每个所述第一有效电平信号包括第一下降沿和第一上升沿；所述第一驱动信号的第i个行周期中的所述第一有效电平信号的所述第一下降沿处于第i个行周期中的所述第一充电时间内，且所述第一驱动信号的第i个行周期中所述第一有效电平信号的所述第一下降沿的开始时间与所述第一驱动信号的第i个行周期中的所述第一充电时间的起始时间点相同；所 述第一驱动信号的第i个行周期中所述第一有效电平信号的所述第一上升沿处于所述第一驱动信号的第i+1个行周期的非所述第一充电时间内；
    所述第二驱动信号包括两个时钟信号，所述两个时钟信号包括对应n个所述第二充电时间的n个第二有效电平信号；每个所述第二有效电平信号包括第二下降沿和第二上升沿；所述第二驱动信号的第i个行周期中的所述第二有效电平信号的所述第二下降沿处于所述第二驱动信号的第i个行周期中的所述第二充电时间内，且所述第二驱动信号的第i个行周期中的所述第二有效电平信号的所述第二下降沿的开始时间与所述第二驱动信号的第i个行周期中的所述第二充电时间的起始时间点相同；所述第二驱动信号的第i个行周期中的所述第二有效电平信号的所述第二上升沿处于所述第二驱动信号的第i+1个行周期中的非所述第二充电时间内。
  6. 根据权利要求5所述的显示器驱动方法，其中，所述第一驱动信号中的每个所述第一有效电平的所述第一上升沿的持续时间长度相同；所述第一驱动信号中的每个所述第一有效电平的所述第一下降沿的持续时间长度相同；
    所述第二驱动信号中的每个所述第二有效电平的所述第二上升沿的持续时间长度相同；所述第二驱动信号中的每个所述第二有效电平的所述第二下降沿的持续时间长度相同。
  7. 根据权利要求5所述的显示器驱动方法，其中，所述第一有效电平信号的持续时间大于所述第二有效电平信号的持续时间。
  8. 根据权利要求7所述的显示器驱动方法，其中，所述第一驱动信号的第i个行周期中的所述第一有效电平信号处于其对应的所述第一充电时间内的持续时间大于所述第二驱动信号的第i个行周期中的所述第二有效电平信号处于其对应的所述第二充电时间内持续的时间；
    所述第一驱动信号的第i个行周期中的第一有效电平信号处于其对应的所述第一充电时间内的持续时间大于所述第一驱动信号的第i+1个行周期中第一有效电平信号处于其对应的所述第一充电时间内的持续时间；
    所述第二驱动信号的第i个行周期中的第二有效电平信号处于其对应的所述第二充电时间内的持续时间大于所述第二驱动信号的第i+1个行周期中第二有效电平信号处于其对应的所述第二充电时间内的持续时间。
  9. 根据权利要求1所述的显示器驱动方法，其中，所述第一刷新频率为60Hz、30Hz、 10Hz、5Hz、4Hz、2Hz和1Hz中的一个；
    所述第二刷新频率为90Hz、120Hz和240Hz中的一个。
  10. 根据权利要求1所述的显示器驱动方法，其中，所述行周期为一行所述像素单元的扫描时长。
  11. 一种显示器，包括：显示面板、多个数据信号驱动电路、n个像素扫描电路和控制器；
    所述显示面板包括n行像素单元和用于向n行像素单元供电的n行像素驱动电路；
    每一数据信号驱动电路与对应的一列像素单元的像素驱动电路电连接；
    每个所述像素扫描电路与对应的一行像素单元的像素驱动电路电连接；以及
    所述控制器与多个数据信号驱动电路和n个所述像素扫描电路电连接，用于控制所述数据信号驱动电路和所述像素扫描电路，并执行如权利要求1至9任意一项所述的显示器驱动方法。
  12. 根据权利要求11所述的显示器，其中，每一所述像素单元包括阳极、阴极以及设于阳极和阴极之间的发光像素。
  13. 根据权利要求11所述的显示器，其中，每一所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管和储能电容；
    所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的漏极电连接；
    所述储能电容连接于所述第一薄膜晶体管的栅极与源极之间；
    每一数据信号驱动电路与对应的一列像素单元的每一所述像素驱动电路中的第二薄膜晶体管的源极电连接；
    每一所述像素扫描电路与对应的一行像素单元的每一所述像素驱动电路中的第二薄膜晶体管的栅极电连接。
  14. 根据权利要求13所述的显示器，其中，每一所述像素扫描电路控制对应的一行像素单元的每一所述像素驱动电路的所述第二薄膜晶体管的通断。
  15. 根据权利要求11所述的显示器，其中，所述控制器是集成电路芯片。
  16. 根据权利要求11所述的显示器，其中，所述控制器根据待显示画面的类型得到所述第一刷新频率。
  17. 根据权利要求11所述的显示器，其中，所述控制器根据待显示画面的类型切换 得到所述切换信号，所述切换信号为所述显示器显示图像时的刷新频率的切换信号。
PCT/CN2021/078385 2020-03-03 2021-03-01 显示器及其驱动方法 WO2021175172A1 (zh)

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