WO2021164268A1

WO2021164268A1 - Layer distribution method considering bus and non-bus networks

Info

Publication number: WO2021164268A1
Application number: PCT/CN2020/119324
Authority: WO
Inventors: 刘耿耿; 朱伟大; 郭文忠; 陈国龙
Original assignee: 福州大学
Priority date: 2020-02-17
Filing date: 2020-09-30
Publication date: 2021-08-26
Also published as: CN111291525B; CN111291525A

Abstract

The present invention relates to construction of a layer distributor of a super-large-scale integrated circuit in the technical field of integrated circuit computer aided designs. Due to continuous development of the manufacturing industry and appearance of a system-on-chip design concept, the number of buses between modules on a chip is rapidly increased and becomes a decisive factor of performance and power consumption. Therefore, the important influence of the bus on the chip design is fully considered, and the layer distributor considering the bus and non-bus networks is provided. The distributor is based on the following three effective methods: 1) a method for determining network priority based on a multi-element cost function; 2) a layer adjustment strategy based on a lookup table, the layer adjustment strategy comprising a layer adjustment technology with a limited number of layers and a layer adjustment technology with an unlimited number of layers; and 3) a bus maximum time series optimization algorithm. The method can guarantee that the number of through holes generated is less, the bus length deviation can be effectively optimized, and therefore the high-quality layer distribution result is obtained.

Description

Consider the layer distribution method of bus and non-bus line network

Technical field

The invention belongs to the technical field of integrated circuit computer-aided design, and in particular relates to a layer allocation method considering bus and non-bus line network.

Background technique

In the current VLSI design, with the development of process technology, the timing problems in the circuit are becoming more and more prominent, which increasingly affects the performance and yield of the new generation of chips. At the same time, with the emergence of the system-level chip concept, the widespread application of intellectual property modules has become the mainstream of chip design, which makes the number of buses between different modules on the chip also increase rapidly. Especially in the multi-core system-level chip design, the bus has become a decisive factor in performance and power consumption. For the bus, it carries multiple signals and consists of a source pin group and one or more sink pin groups. If the line length of each signal between the source pin group and the sink pin group of the bus is inconsistent, it will lead to inconsistent transmission time of each signal to the same functional module, aggravate the timing disorder, and seriously affect the performance of the chip.

technical problem

Layer allocation is an important stage of overall wiring. In this stage, the 2D wiring results of each net need to be allocated to the appropriate metal layer, and the different layers are connected through vias. The layer allocation scheme has a great influence on the interconnection delay, which is one of the important factors that determine the performance of the chip. The existing layer distributors do not consider the timing matching problem of the bus, which leads to the deterioration of the timing, which is far from the development trend of the actual chip.

Technical solutions

In view of this, the purpose of the present invention is to provide a layer allocation method that considers buses and non-bus line networks to effectively optimize the problem of bus timing disorder.

In order to achieve the above objectives, the present invention adopts the following technical solutions:

A layer allocation method considering bus and non-bus line network includes the following steps:

Step S1: Consider the heuristic cost function of the line length and the number of pins, and determine the layer allocation order of the first stage line network;

Step S2: Perform through-hole minimization layer assignment based on the through-hole minimization layer assignment algorithm, and obtain the initial layer assignment result;

Step S3: Build a deviation lookup table based on the initial layer allocation result;

Step S4: According to the deviation look-up table, remove all the deviation bus line nets and all non-bus line nets;

Step S5: Consider the heuristic cost function combining the four elements of line length, pin number, signal number, and bus line length deviation, and determine the layer allocation sequence of the second-stage line network;

Step S6: Perform through-hole minimization layer assignment based on the through-hole minimization layer assignment algorithm, and obtain the layer assignment result;

Step S7: Use the bus line network application bus maximum timing optimization algorithm to optimize the bus line length deviation, and obtain the optimized layer assignment result;

Step S8: Determine whether there is a bus line length deviation, if there is no deviation, output the optimized layer allocation result and use it as the final layer allocation result; if there is a deviation, adjust the layer adjustment strategy based on the lookup table to obtain the final layer allocation result .

Further, the step S1 is specifically: the layer allocation priority of the first-stage wire net only needs to evaluate the number of pins and the line length, and the calculation formula of the priority P1 is as follows:

Wherein, P _cost is the number of pins of the net N _i, e ¹ _ij is the basic cost of the edge, e is the edge of the net N _i.

Further, the step S5 is specifically: the purpose of the layer allocation in the second stage is to optimize the bus line length deviation by reasonably using the through holes, so as to obtain less line length deviation while not generating too many through holes. , The calculation formula of priority P 2 is as follows:

Wherein, α and β are coefficients user-defined, e ¹ _ij is the edge of the basic cost of, e is edge nets N _i a, BD _i is the i-th line length deviations bus, P _cost is net N _i of The number of pins, q is the signal number of the i- th bus B _i.

Further, the layer allocation algorithm for minimizing through holes is specifically:

(1) Use depth-first search (DFS) to pre-process the wire network, and disassemble the loop 2D wiring results, thereby transforming them into a wiring tree;

(2) Randomly select a node as the root node, and then use depth-first search to form a directed graph, and obtain the layer assignment order of all edges under dynamic programming;

(3) According to the reverse order of the layer assignment order of the edges of the directed graph, the traversal order of the nodes is obtained;

(4) Traverse all the distribution of the parent edge of the node, calculate the minimum number of through holes of the node, and determine the layer where the parent edge of the node should be placed;

(5) Go back to the layer where the parent node of all nodes is located, and construct the final layer assignment result.

Further, the layer adjustment strategy based on the lookup table includes a layer adjustment strategy with a limit on the number of layers and a layer adjustment strategy with no limit on the number of layers.

Further, the layer adjustment strategy of the layer number restriction is specifically:

(1) Find out the sink pins that need to be adjusted from the deviation lookup table;

(2) Traverse the edge of the source pin to the sink pin that needs to be adjusted, and find a node with a degree greater than 1;

(3) Calculate the maximum layer number, minimum layer number and the number of through holes used by nearby edges of a signal of the node;

(4) Move the connected edge between the smallest layer number and the largest layer number to ensure that the number of through holes does not exceed the original number of through holes;

(5) Select the layer with the smallest deviation and adjust the edges to this layer.

Further, the layer adjustment strategy with no limit on the number of layers is specifically:

(1) A 2D wiring topology based on the wire network, with the source pin as the root node, and using depth-first search to generate a directed graph;

(2) According to the 2D wiring length of the wire net, sort each sink pin, the order is from small to large in line length;

(3) Adjust the layers successively on the edge that a certain sink pin passes through to the source pin. Set the unadjusted layer as the original layer and the adjusted layer as the new layer;

(4) Calculate the deviation from the maximum signal position through the deviation look-up table, and calculate the required number of through holes;

(5) Find an adjusted new layer; if the new layer has redundant wiring resources, it can directly adjust it to the new layer, then delete the edge on the original layer and update the through hole where the node is located to keep it Connectivity; if the new layer has no redundant wiring resources, in order to prevent overflow, select the edge of the network on the new layer to adjust to the original layer, then adjust the edge to the new layer, and finally adjust the through holes of the two edges To maintain connectivity.

(6) Update the entire deviation lookup table to ensure the accuracy of the deviation lookup table.

Further, the bus maximum timing optimization algorithm is specifically:

(1) Calculate the line length deviation of each bus;

(2) Sort them according to the bus line length deviation from large to small;

(3) Transfer the wiring resources occupied by non-bus resources to the bus line network;

(4) The current bus line network uses the layer allocation without overflow constraints;

(5) If the bus deviation of the new layer allocation result is better than the original bus line length deviation, then the layer allocation result will replace the original layer allocation result.

Beneficial effect

Compared with the prior art, the present invention has the following beneficial effects:

On the premise of ensuring that a small number of through holes are generated, the present invention makes reasonable use of the influence of through holes on the timing to minimize the deviation of the bus line length, thereby effectively optimizing the problem of bus timing disorder.

Description of the drawings

Figure 1 is an overall wiring model in an embodiment of the present invention (a) overall wiring structure diagram, (b) overall wiring grid diagram;

Figure 2 is a 2.5D bus wiring process with a 3-pin wire net in an embodiment of the present invention (a) 3D wiring structure, (b) 2D wiring structure, (c) 2D wiring results, (d) layer allocation ；

Figure 3 is a bus composed of two 5-pin bus wire nets in an embodiment of the present invention;

Figure 4 is a flow chart of the method of the present invention;

Figure 5 is a layer allocation method for minimizing vias in an embodiment of the present invention (a) 2D wiring result, (b) 2D wiring result after preprocessing, (c) directed graph formed by depth-first search, (d) The sequence of layer adjustment, (e) the layer allocation result of side e _10;

Figure 6 is a layer adjustment strategy for layer number limitation in an embodiment of the present invention (a) side e ₁ before layer adjustment, (b) side e ₁ after layer adjustment;

FIG. 7 is an algorithm of a layer adjustment strategy with no limit on the number of layers in an embodiment of the present invention;

Figure 8 is a layer adjustment strategy with unlimited number of layers in an embodiment of the present invention (a) 2D wiring results, (b) directed graph formed by depth-first search, (c) layer adjustment order, (d) side e ₅ and Side e ₁₀ layer adjustment;

Figure 9 is the bus maximum timing optimization algorithm.

Embodiments of the present invention

The present invention will be further described below in conjunction with the drawings and embodiments.

Referring to Fig. 4, the present invention provides a layer allocation method considering bus and non-bus line network, including the following steps:

Step S8: Determine whether there is a deviation of the bus line length. If there is no deviation, output the optimized layer allocation result and use it as the final layer allocation result; if there is a deviation, adjust a layer adjustment strategy based on a lookup table to obtain the final Layer allocation result.

In this embodiment, in the VLSI physical design and wiring stage, the wiring area of the chip is distributed in multiple metal layers. The overall wiring usually divides each metal layer into several rectangles of the same size, and each rectangle is called G-Cell , as shown in Figure 1 (a). Therefore, in the overall wiring stage, the wiring area of the K layer is usually represented by a grid graph G ^k = ( V ^k , E ^k ), where the node v ^k _i ∈ V ^k represents the wiring unit, and e ^k _ij ∈ E ^k represents the adjacent The connecting edge of the wiring unit pair ( v ^k _i , v ^k _{j ).} E ^{k is} composed of two parts, namely routing resource edge E ^k _e and through-hole resource edge E ^k _v . Each wiring resource edge e ^k _ij ∈ E ^k _e indicates that the connected wiring unit pair ( v ^k _i , v ^k _j ) is located in the same layer, and each through-hole resource edge e ^k _ij ∈ E ^k _v represents its connection The wiring unit pairs ( v ^k _i , v ^k ^' _i ) are located on different layers. Figure 1 (b) shows an overall wiring model including 4 metal layers, and each metal layer is divided into 33 G-Cells. In addition, each metal layer has only one preferred direction, and adjacent metal layers are connected through vias.

Layer allocation is the final stage of 2.5D overall wiring. The so-called 2.5D wiring: First, it maps the multi-layer wiring resources and pins to the 2D plane, as shown in Figure 2 (b); then, completes the 2D wiring on the 2D plane, as shown in Figure 2. As shown in (c); finally, use layer assignment to assign all edges to each layer, as shown in Figure 2 (d). Therefore, the task of layer allocation is to allocate each side of the 2D wiring result to a suitable metal layer to obtain the final 3D wiring result. Therefore, we assume that the 2D model of G ^k = ( V ^k , E ^k ) is represented by G ¹ = ( V ¹ , E ¹ ), where node v ¹ _i ∈ V ¹ represents the wiring grid unit on the 2D plane, e ¹ _ij ∈ E ¹ represents the connecting edges of adjacent wiring grid cell pairs ( v ¹ _i , v ¹ _{j) on the 2D plane.} Assume that S ¹ represents the 2D wiring result of G ¹ = ( V ¹ , E ¹ ), and assume that S ^k represents the 3D overall wiring result of G ^k = ( V ^k , E ^{k ).} Figure 2 (d) is the result of a layer allocation in Figure 2 (c).

FIG on the grid ^{^{G k = (V k, E}} k), i.e. the capacity of mesh edges c (e ^k _ij) representative of the k-th layer between G-Cell ^k _i G-Cell ^k _j and the adjacent available The number of wiring tracks, and d ( e ^k _ij ) represents the number of wiring tracks actually used. When the number of tracks actually used exceeds the number of tracks available, edge overflow occurs, that is, o ( e ^k _ij ). Therefore, according to d ( e ^k _ij ) and c ( e ^k _ij ), the overflow amount of the edge can be obtained, and the calculation formula for edge overflow is as follows:

(1)

The 2D grid graph G ¹ = ( V ¹ , E ¹ ) is the projection of G ^k = ( V ^k , E ^k ) on the 2D plane, and the grid edge capacity c ( e ¹ _ij ) represents 1 ~ K ^{The sum} of c ( e ^k _ij ) of all G-Cell ^k _i and G-Cell _{k j} on the layer. Similarly, d ( e ¹ _ij ) also represents the sum of all d ( e ^k _ij ) on the 1 ~ K layer . Therefore, the calculation formula for the overflow quantity o ( e ¹ _ij ) on the 2D grid graph is as follows:

(2)

For the bus ( B _i ), there are r -bit signals and q bus pin groups ( PG ⁱ ). Among them, one bus pin group is a source pin group ( PG ⁱ ₀ ), and q-1 bus pin groups are a sink pin group ( PG ⁱ _j ). In order to meet the consistency of the timing, it is necessary to make the time for each bit signal at the source pin to be transmitted to the sink pin group as much as possible, that is, the length of all pin pairs between the source pin group and the sink pin group. equal. Therefore, in the overall wiring stage, the bus can be regarded as a combination of q bus wire nets ( BN _i ), each bus wire net is a signal of the bus, and all the pins of the bus wire net ( BNP _j ) form the bus Pin group. When the lengths of the bus wire net pin pairs between the two bus pin groups are inconsistent, a bus wire length deviation occurs. The bus line length deviation calculation is defined as follows:

(3)

Where WPG ⁱ _j <k> is the line length of the k- _th pair of pins between the source pin group ( PG ⁱ ₀ ) of the i- th bus and the j- th sink pin group ( PG ⁱ j), that is, the i- th The line length from the source pin of the k- th bus net to the j- th sink pin in the bus. MWPG ⁱ _j is the set of all of the pins between the PG ⁱ ₀ i-bus line network and PG ⁱ _j is the maximum line length. Figure 3 shows a bus with 5 PGs on a 2D plane with 2 signals, that is, it is composed of 2 bus lines.

When G ¹ = ( V ¹ , E ¹ ), there is no through-hole resource edge E ^k _v . However, after dispensing the layers S ¹ between the different metal layers are connected by vias to maintain connectivity, i.e., the presence of the through holes resources on edge E ^k _v ^{^{G k = (V k, E}} k). The existence of the through hole will affect the line length and the production cost of the chip, thereby affecting the timing. The calculation formula for the influence of the through hole on the line length is as follows:

(4)

Where M and N are the number of G-Cells in the horizontal and vertical directions of a single metal layer , K is the number of metal layers, and V _cost is the cost of through holes.

Considering the layer assignment problem of bus and non-bus line network, it can be described as: given overall wiring diagram G ^k = ( V ^k , E ^k ), 2D wiring grid diagram G ¹ = ( V ¹ , E ¹ ), each side e ^k _ij ∈ E ^k channel capacity c ( e ^k _ij ), a non-bus line network set NB = { NB ₁ , NB ₂ , … , NB _m } and a bus set B = { B ₁ , B ₂ , … , B _n }, and its 2D wiring result S ¹ = { SNB ¹ ₁ , …, SNB ¹ _m , SBN ¹ ₁ , …, SBN ¹ _z } on G ¹ = ( V ¹ , E ^{1 ).} For each non-bus network NB _j ∈ NB , 1 ≤ j ≤ m , given its 2D wiring result SNB ¹ _j on G ¹ = ( V ¹ , E ¹ ). For each bus B _i ∈ B , 1≤ i ≤ n , given the number of bits q of its signal, each signal can be regarded as a separate bus line network BN _i , B _i = { BN ⁱ ₁ , BN ⁱ ₂ ,..., BN ⁱ _q }, and the 2D wiring result SBN ¹ _i on G ¹ = ( V ¹ , E ¹ ).

According to the S ^{1 of the} line network on G ¹ = ( V ¹ , E ¹ ), under the premise that the 2D topology result remains unchanged and the overflow number o ( e ¹ _ij ) does not increase, each edge of S ^{1 is allocated} Give G ^k = ( V ^k , E ^k ) to the corresponding layer, and ensure that all its pins are connected through through holes to obtain the final 3D wiring result S ^k = { SNB ^k ₁ , …, SNB ^k _m , SBN ^k ₁ , …, SBN ^k _z }.

In this embodiment, for different optimization goals, for each network NB _j and BN _i , it is necessary to calculate the priority of its layer allocation. The priority is determined by the four elements of line length, number of pins, bus line length deviation and the number of signals. The reasons are as follows: (1) Wire length: The longer the wire length of S ¹ is, the more wiring resources it needs to occupy, resulting in low utilization of better wiring resources. In addition, the longer the wire length, the greater the probability that it will encounter the exhaustion of wiring resources and the need to change layers, and the greater the probability of turning. Even if the best wiring resources are used, many through holes will be generated. Therefore, wire nets with larger wire lengths tend to be post-processed. (2) Number of pins: Because wire nets with more pins need to connect pins frequently, their optimal wiring options are reduced, so more through holes are often produced. If they have a lower priority, a large number of unnecessary vias will be generated. Therefore, wire nets with more pins are often processed first. (3) Bus line length deviation: The larger the line network deviation of each signal in B _i is, the more priority it needs to be processed, so that a shorter line length can be obtained. (4) Number of signals: The more signals of B _i , the fiercer the competition for wiring resources, and better wiring resources need to be occupied first, otherwise the deviation of the bus line length will be more serious. Therefore, the bus with more signals needs priority processing. The line length and the number of pins are more likely to affect the number of through holes, and the bus line length deviation and signal number factors are to control the priority of the bus line network.

The purpose of layer allocation in the first stage is to obtain a smaller number of through holes. Therefore, the first stage of the layer allocation priority of the line network only needs to evaluate the number of pins and the line length, and the calculation formula of the priority P1 is as follows:

(5)

Wherein, P _cost N _i is the number of pins, e ¹ _ij is the basic cost of the edge, e is the edge of the net N _i.

The purpose of layer allocation in the second stage is to optimize the bus line length deviation by rationally using through holes, so as to obtain less line length deviation without generating too many through holes. The calculation formula of priority P 2 is as follows:

(6)

In this embodiment, the purpose of the layer allocation algorithm for minimizing through holes is to obtain a layer allocation result with a minimum number of through holes for the current network. The basic idea of the algorithm is: according to the current channel capacity, without violating the constraint of edge overflow, based on dynamic programming, layer allocation is performed side by side, and finally the layer allocation scheme with the least number of through holes is selected as the final The result of the layer assignment. Specifically:

(5) Go back to the layer where the parent node of all nodes is located, and construct the final layer assignment result. The following example is used to explain the layer assignment algorithm for minimizing vias.

For each wiring tree, it consists of three types of nodes: root node (RN), leaf node (L( V ¹ _i )), and intermediate node (MN( V ¹ _i )). As shown in Figure 5 (c), E is the root node, A and D are leaf nodes, and C and B are intermediate nodes. For each node V ¹ _i ∈ V ¹ , it has two kinds of child nodes ch_v ( V ¹ _i ) and parent nodes pa_v ( V ¹ _i ). Assume that the edge connecting its child node is called the child edge ch_e ( V ¹ _i ), and the edge connecting its parent node is called the parent edge pa_e ( V ¹ _i ). As shown in Figure 5(d), the parent node of v ₉ is v ₁₀ , and the child nodes are v ₄ and v ₅ . The parent side of v ₉ is e ₃ , and the child sides are e ₄ and e ₇ . Therefore, the number of through holes for each node Via ( V ¹ _i ) needs to be connected to three types of objects, which are the through holes that connect all of its child nodes pa_e ( ch_v ( V ¹ _i )) and the parent side pa_e ( V ¹ _i ) through holes and through holes connected to its own pins. In addition, each node needs to record the best layer number ml ( V ¹ _i ) of its parent edge and the minimum number of through holes mv ( V ¹ _i ) of the subtree with V ¹ _{i as the root node.} The calculation formula of mv ( V ¹ _i ) is as follows:

(7)

Among them, K is the maximum number of layers, k is the number of the layer where the parent edge of the current node is located, and Via ( V ¹ _i ) is the number of through holes of the current node.

Given a wire net with 5 pins, the 2D wiring results have loops, as shown in Figure 5 (a). First, use depth-first search (DFS) to disassemble the loop to obtain a wiring tree, as shown in Figure 5 (b); secondly, select node E as the root node of the wiring tree, and use depth-first search for it , Get a directed graph, as shown in Figure 5 (c); then, according to the reverse order of the directed graph, get the traversal order of all its nodes, as shown in Figure 5 (d); then, calculate all nodes The mv ( V ¹ _i ) and ml ( V ¹ _i ) values of, take node v ₉ as an example. Given that mv ( v ₄ ) = 3 and mv ( v ₅ ) = 1, the parent edge e ₁₀ can be allocated to metal layer 4 or metal layer 2. When ml ( v ₉ ) = 4, as shown in Figure 5(e-1), mv ( v ₉ ) = mv ( v ₅ ) + mv ( v ₄ ) + Via ( v ₉ ) = 1 + 3 + 3 = 7 ; When ml ( V ¹ _i ) = 2, as shown in Figure 5(e-2), mv ( v ₉ ) = mv ( v ₅ ) + mv ( v ₄ ) + Via ( v ₉ ) = 1 + 3 + 1 = 5, so ml ( v ₉ ) = 2 can be obtained; finally, according to all ml ( V ¹ _i ) values, construct a layer assignment result with the least number of through holes for the current net.

In this embodiment, the layer adjustment strategy based on the lookup table includes a layer adjustment strategy with a limit on the number of layers and a layer adjustment strategy with no limit on the number of layers.

The purpose of the layer adjustment strategy of the layer limit is to adjust the layer of the bus line network with the shorter line length from the source pin to the sink pin in the bus according to the deviation look-up table without adding additional vias, so that the bus line is longer The deviation is reduced; specifically:

The adjusted layer should meet the following constraints: a. The overflow constraint will not be violated; b. The number of through holes required will not exceed the original number of through holes. The following example is used to explain the layer adjustment strategy of the layer limit.

For a bus with a signal number of 2 bits, as shown in Figure 6, it has 1 source pin and 2 sink pins, and three sides e ₁ , e ₂ and e ₃ need to be allocated. Since we use the layer assignment to minimize the number of through-holes to minimize the number of through-holes as the optimization goal, if we first assign the red signal 1 to the layer, in order to get the least number of through-holes, the source pin and sink pin 1 The connected edge e ₁ will be allocated to the metal layer 1, and a through hole is required. Because if e ₁ is allocated to metal layer 3, then it will need 3 vias. In addition, we are placing e ₂ and e ₃ on the metal layer 4. Due to the exhaustion of the wiring resources of the first layer, when we allocate the layers of the blue signal 2, its e ₁ can only be placed on the metal layer 3, as shown in Figure 6 (a). Because the line length between the red signal 1 and the blue signal 2 from the source pin to the sink pin 1 is inconsistent, a timing mismatch occurs. If we use the layer adjustment technology of the layer number limit for the red signal 1, first, we find from the deviation lookup table that there is a bus line length deviation from the source pin to the sink pin 1. Second, find a node with a degree of 2; then, It is calculated that the largest layer number used by the red signal 1 on the node is 4, the smallest layer number is 1, and the number of original vias from the source pin to the sink pin 1 is 4; then, let the connected edge e _{1 be} on the metal layer Move from 1 to metal layer 4; finally, it is calculated that e ₁ moves to metal layer 3 with a smaller deviation of the bus line length than metal layer 1, and does not violate the overflow constraint and the number of vias. The result of layer adjustment is shown in Figure 6(b).

The purpose of the layer adjustment strategy with no limit on the number of layers is to optimize the signal with serious bus timing disorder by using the influence of the vias on the timing, and to optimize the bus line length deviation by adding a certain amount of vias. As shown in Fig. 7, the layer adjustment strategy with no limit on the number of layers is specifically:

(1) A 2D wiring topology based on the wire net, with the source pin as the root node, using depth-first search to generate a directed graph;

(2) According to the 2D wiring length of the wire net, sort each sink pin, and the order is from small to large in line length;

(3) Perform layer adjustment on the edge that a certain sink pin passes through to the source pin. Set the unadjusted layer as the original layer and the adjusted layer as the new layer;

(5) Randomly find an adjusted new layer: if the new layer has redundant wiring resources, it can directly adjust it to the new layer, and then delete the edges on the original layer and update the through hole where the node is located. Maintain connectivity; if the new layer has no redundant wiring resources, in order to prevent overflow, select the edge of the network on the new layer to adjust to the original layer, then adjust the edge to the new layer, and finally adjust the through holes of the two edges Circumstance, so that it maintains connectivity.

In this embodiment, the method of selecting the line network to be changed is as follows: 1) If there is a non-bus line network on the new layer, then select the non-bus line network; 2) If there is only a bus line network on the new layer, then select Unadjusted 3) Other conditions, no adjustment.

The condition for this strategy to stop is when the adjusted number of through holes is less than its user-defined threshold or all edges have been adjusted. The following example is used to explain the layer adjustment technique of the layer limit.

Given a wire net with 5 pins, the 2D wiring results are shown in Figure 8(a). For the bus line network, assuming E is the source pin, we will select the source pin E as the root node of the depth-first search. According to the direction of the depth-first search traversal, we will get a 2D wiring as shown in Figure 8(b) Directed graph; Next, according to the length of the sink pin to the source pin on the 2D wiring diagram, we get the adjustment sequence of the sink pin: C → D → B → A. In other words, we first adjust all sides from sink pin C to source pin E , namely e ₁ → e ₂ → e ₃ . The other sink pins can be obtained in the same way, and finally the layer adjustment sequence as shown in Figure 8(c) is obtained. Finally, calculate the required number of through holes according to formula 8, and adjust according to the layer adjustment sequence of the edges. Figure 8 (d-2) is the layer adjustment result obtained by adjusting e ₅ and e _{10 in} Figure 8 (d-1) on the left. The calculation formula for the required number of through holes is as follows:

(8)

Where WPG ⁱ _j <k> is the line length of the k- _th pair of pins between the source pin group ( PG ⁱ ₀ ) of the i- th bus and the j- th sink pin group ( PG ⁱ j), that is, the i- th The line length from the source pin of the k- th bus net to the j- th sink pin in the bus. MWPG ⁱ _j is the set of all of the pins between the PG ⁱ ₀ i-bus line network and PG ⁱ _j is the maximum line length. V _cost is the through hole cost.

In this embodiment, the purpose of the bus maximum timing optimization algorithm is to focus on optimizing the line length of the bus line network with serious timing disorder. The basic idea of the algorithm is: if a non-bus line network occupies better wiring resources, then the non-bus line network will give up the wiring resources to the bus line network to optimize the line network with the longest line in the bus. As shown in Figure 9, the bus maximum timing optimization algorithm is specifically:

(1) Calculate the line length deviation of each bus;

(2) Sort them according to the bus line length deviation from large to small;

(4) Assign the current bus line network to layers without overflow constraints;

(5) If the bus deviation of the new layer allocation result is better than the original bus line length deviation, then the layer allocation result will replace the original layer allocation result. To

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

A layer allocation method considering bus and non-bus line network is characterized in that it includes the following steps:

Step S1: Consider the heuristic cost function of the line length and the number of pins, and determine the layer allocation order of the first stage line network;

Step S2: Perform through-hole minimization layer assignment based on the through-hole minimization layer assignment algorithm, and obtain the initial layer assignment result;

Step S3: Build a deviation lookup table based on the initial layer allocation result;

Step S4: According to the deviation look-up table, remove all the deviation bus line nets and all non-bus line nets;

Step S5: Consider the heuristic cost function combining the four elements of line length, pin number, signal number, and bus line length deviation, and determine the layer allocation sequence of the second-stage line network;

Step S6: Perform through-hole minimization layer assignment based on the through-hole minimization layer assignment algorithm, and obtain the layer assignment result;

Step S7: Use the bus line network application bus maximum timing optimization algorithm to optimize the bus line length deviation, and obtain the optimized layer assignment result;

Step S8: Determine whether there is a bus line length deviation, if there is no deviation, output the optimized layer allocation result and use it as the final layer allocation result; if there is a deviation, adjust the layer adjustment strategy based on the lookup table to obtain the final layer allocation result .
A layer allocation method considering bus and non-bus network according to claim 1, characterized in that

The step S1 is specifically: the layer allocation priority of the first-stage wire net only needs to evaluate the number of pins and the line length, and the calculation formula of the priority P1 is as follows:

(5)

Wherein, P cost is the number of pins of the net N i, e 1 ij is the basic cost of the edge, e is the edge of the net N i.
A layer allocation method considering bus and non-bus network according to claim 1, characterized in that

The step S5 is specifically: the purpose of the layer allocation in the second stage is to optimize the bus line length deviation by rationally using the through holes, so as to obtain less line length deviation without generating too many through holes, priority The calculation formula of P 2 is as follows:

(6)

Wherein, α and β are coefficients user-defined, e 1 ij is the edge of the basic cost of, e is edge nets N i a, BD i is the line length deviation of i-th bus B i is, P cost is net N The number of pins of i , and q is the number of signals of the i- th bus B i.
The layer allocation method considering bus and non-bus line network according to claim 1, characterized in that the layer allocation algorithm for minimizing through holes is specifically:

Use depth-first search (DFS) to pre-process the wire network, and disassemble the loop 2D wiring results, thereby transforming them into a wiring tree;

Randomly select a node as the root node, and then use depth-first search to form a directed graph, and obtain the layer assignment order of all edges under dynamic programming;

According to the reverse order of the layer assignment order of the edges of the directed graph, the traversal order of the nodes is obtained;

Traverse all the distributions of the parent side of the node, calculate the minimum number of through holes for the node, and determine the layer where the parent side of the node should be placed;

Go back to the layer of the parent node of all nodes and construct the final layer assignment result.
A layer allocation method considering bus and non-bus line networks according to claim 1, wherein the layer adjustment strategy based on the lookup table includes a layer adjustment strategy with a limit on the number of layers and a layer adjustment with no limit on the number of layers. Strategy.
The layer allocation method considering bus and non-bus line network according to claim 5, wherein the layer adjustment strategy of the layer number limitation is specifically:

(1) Find out the sink pins that need to be adjusted from the deviation lookup table;

(2) Traverse the edge of the source pin to the sink pin that needs to be adjusted, and find a node with a degree greater than 1;

(3) Calculate the maximum layer number, minimum layer number and the number of through holes used by nearby edges of a signal of the node;

(4) Move the connected edge between the smallest layer number and the largest layer number to ensure that the number of through holes does not exceed the original number of through holes;

(5) Select the layer with the smallest deviation and adjust the edges to this layer.
The layer allocation method considering bus and non-bus line network according to claim 5, wherein the layer adjustment strategy of the layer number part restriction is specifically:

(1) A 2D wiring topology based on the wire net, with the source pin as the root node, using depth-first search to generate a directed graph;

(2) According to the 2D wiring length of the wire net, sort each sink pin, the order is from small to large in line length;

(3) Adjust the layers successively on the edge that a certain sink pin passes through to the source pin. Set the unadjusted layer as the original layer and the adjusted layer as the new layer;

(4) Calculate the deviation from the maximum signal position through the deviation look-up table, and calculate the required number of through holes;

(5) Randomly find an adjusted new layer: If the new layer has redundant wiring resources, it can directly adjust it to the new layer, and then delete the edge on the original layer and update the through hole where the node is located. Maintain connectivity; if the new layer has no redundant wiring resources, select the edge of the network on the new layer to adjust to the original layer, then adjust the edge to the new layer, and finally adjust the through holes of the two edges to make it Maintain connectivity.

(6) Update the entire deviation lookup table to ensure the accuracy of the deviation lookup table.
The method for layer allocation considering buses and non-bus line networks according to claim 1, wherein the bus maximum timing optimization algorithm is specifically:

(1) Calculate the line length deviation of each bus;

(2) Sort them according to the bus line length deviation from large to small;

(3) Transfer the wiring resources occupied by non-bus resources to the bus line network;

(4) Assign the current bus line network to layers without overflow constraints;

(5) If the bus deviation of the new layer allocation result is better than the original bus line length deviation, then the layer allocation result will replace the original layer allocation result.