JP2000331038A - Rough wiring route layer assignment system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the number of required through holes at the time of detailed wiring by accurately predicting the number of the through holes with respect to multi-layered wiring design of an integrated circuit or a printed board. SOLUTION: A route intersection extraction means 22 extracts intersection information indicating intersections of rough wiring routes which exist in an area selected by an area extraction means 21. A non-intersecting route set extraction means 23 refers to intersection information to classify and extract non-intersecting route sets, of which the number is equal to or smaller than the number of wiring layers, from the set of rough wiring routes in the area, and rough wiring routes which don't belong to any non-intersecting route sets are extracted as elements of a remaining route set. A layer assigning means 24 refers to intersection information, non-intersecting route sets, and the remaining route set to perform layer assignment for detailed wiring elated to the area. An assignment adjustment means 25 discriminates whether assignment by the layer assignment means 24 can be executed or not and adjusts layer assignment if it is decided that this assignment cannot be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a general wiring path layer allocation method for performing general wiring path layer allocation (layer allocation for detailed wiring) in automatic wiring design of an integrated circuit and a printed circuit board.

[0002]

2. Description of the Related Art In an automatic wiring design of an integrated circuit and a printed circuit board, a general wiring method based on coarse grid division is widely used.

FIG. 3 shows a conceptual diagram of schematic wiring based on coarse grid division. In FIG. 3, reference numeral 5 represents a schematic lattice, 6 represents a region, 7 represents a schematic wiring path, 8 represents a terminal, and 9 represents a virtual terminal. Here, the "virtual terminal" refers to a virtual terminal introduced to represent a passing point of a schematic wiring path passing through a boundary of a region, and is widely used in a schematic wiring method based on coarse grid division. The concept is

[0004] An example of a conventional technique using a rough wiring method based on coarse grid division is described in Japanese Patent No. 2836516.

The prior art (automatic wiring method) described in this publication includes a wiring area dividing means, a virtual terminal generating means,
It comprises an alignment rule extracting means, a virtual terminal arranging means, and a virtual terminal allocating means.

An operational feature of the prior art having such a configuration is that the number of intersections in the divided area of the general wiring path can be determined by the alignment rule extracting means, the virtual terminal arranging means, and the virtual terminal allocating means. The point is to realize virtual terminal assignment that can be reduced as much as possible. This is the number of intersections of wiring paths and vias (through holes) required for detailed wiring design.
Based on intuition that there is a correlation with the number of

That is, the prior art intends to reduce the number of intersections of the schematic wiring paths, thereby suppressing the generation of vias at the time of detailed wiring design, and increasing the ease of detailed wiring design.

Here, “via (through hole)” means
In an integrated circuit or a printed circuit board, it refers to a wiring structure that realizes electrical connection between different wiring layers.

However, in the prior art relating to automatic wiring design including the prior art, the layer allocation for allocating the general wiring path to an appropriate layer for detailed wiring has not been performed.

[0010]

As described above, in the prior art relating to automatic wiring design, since the layers are not allocated, the following problems have arisen.

A first problem is that it cannot sufficiently cope with a multilayer wiring of two or more layers, particularly three or more layers.

The reason why such a problem arises is that there is a degree of freedom in the layer assignment of the wiring path, especially in the case of a multi-layer wiring of three or more layers, except for the obvious case such as the wiring according to the two-layer vertical and horizontal principle. This is because it is difficult to obtain the optimum detailed wiring without the layer assignment that has been properly considered.

A second problem is that it is not possible to accurately estimate the number of vias based on the number of intersections of the schematic wiring paths (estimate the number of vias at a stage before execution of detailed wiring).

The reason why such a problem occurs is that even if the number of intersections of the schematic wiring paths crossing in the area can be recognized, detailed wiring is necessary depending on how to assign layers of virtual terminals. This is because there is a degree of freedom in the number of vias.

In view of the foregoing, it is an object of the present invention to make it possible to accurately predict the required number of vias from the approximate number of intersections of wiring paths in the design of multilayer wiring of an integrated circuit or a printed circuit board. It is an object of the present invention to provide a schematic wiring path layer assignment method capable of reducing the number (realizing layer assignment of a schematic wiring path for minimizing the number of vias required for detailed wiring).

[0016] As a patent gazette for the prior art relating to vias, there is Japanese Patent No. 2522420.
However, the technique (automatic wiring design apparatus) described in this publication considers “movement of via holes” in an automatic wiring design apparatus that moves an existing wiring and inserts a new wiring, and the present invention is focused on. And the configuration is different. Therefore, the present invention cannot be conceived even if the conventional technology itself is combined with the conventional technology described in Japanese Patent No. 2836516, as well as the conventional technology itself.

[0017]

According to the general wiring route layer assignment method of the present invention, a region to be processed is selected from a result of the general wiring based on coarse grid division, and information on a general wiring route passing through the region is extracted. A region extracting unit, and a path for extracting intersection information indicating intersections of the schematic wiring routes existing in the processing target region selected by the region extracting unit based on the information on the schematic wiring route extracted by the region extracting unit. Intersection extraction means, classifying and extracting a number of non-intersecting path sets equal to or less than the number of wiring layers from a set of schematic wiring paths in the area to be processed with reference to the intersection information extracted by the path intersection extraction means, At the time of extraction, the number of elements of the non-intersecting path set is maximized, and a non-intersecting path set is extracted as an element of the remaining path set for a schematic wiring path that does not belong to any of the non-intersecting path sets. Extracting means, the intersection information extracted by the route intersection extracting means and the information indicating the non-intersecting route set and the remaining route set extracted by the non-intersecting route set extracting means, each non-intersecting route set, Layer assignment means for assigning layers for detailed wiring related to a processing target area by assigning to different layers and sequentially assigning only one via to each schematic wiring path included in the remaining path set; It is determined whether or not the layer allocation performed by the layer allocation means is executable. If it is determined that the layer allocation is not executable, the number of vias required for one adjustment of the layer allocation is reduced to at most one. Allocation adjustment means for adjusting the layer allocation so as to suppress it.

More generally, in the general wiring route layer assignment method of the present invention, a region to be processed is selected from the result of the general wiring based on the coarse grid division, and information on the general wiring route passing through the region is selected. The area extracting means to be extracted, the path intersection extracting means for extracting intersection information indicating the intersection of the schematic wiring paths existing in the processing target area selected by the area extracting means, and the path intersection extracting means By referring to the intersection information, the number of non-intersecting path sets equal to or less than the number of wiring layers is classified from the set of schematic wiring paths in the processing target area.
A non-intersecting route set extracting means for extracting, as a component of a residual route set, a schematic wiring route which does not belong to any non-intersecting route set; intersection information extracted by the route intersecting extracting means; Layer assigning means for assigning a layer for detailed wiring related to a processing target region with reference to information indicating the non-intersecting route set and the remaining route set extracted by the set extracting means, and a layer assigned by the layer assigning means It is determined whether or not the allocation is feasible, and when it is determined that the allocation is not feasible, it can be expressed as having an allocation adjusting means for adjusting the layer allocation.

In addition, such a general wiring path layer assignment method uses a computer to select an area to be processed from a general wiring result based on coarse grid division and extract information on a general wiring path passing through the area. Extracting means for extracting intersection information indicating intersections of the schematic wiring paths existing in the processing target area selected by the area extracting means, and referring to the intersection information extracted by the path intersection extracting means. Classifies and extracts the number of non-intersecting route sets equal to or less than the number of wiring layers from the set of schematic routing routes in the area to be processed. Non-intersecting path set extracting means, the intersection information extracted by the path intersecting extracting means, and the non-intersecting path set extracting means A layer assignment unit for assigning a layer for detailed wiring with respect to a region to be processed by referring to information indicating the intersection route set and the remaining route set, and whether the layer assignment performed by the layer assignment unit is executable It is also possible to realize as a recording medium on which a program for functioning as an assignment adjusting means for adjusting the layer assignment is recorded when it is judged as “executable”.

[0020]

Next, the present invention will be described in detail with reference to the drawings.

(1) First Embodiment FIG. 1 is a block diagram showing a configuration of a schematic wiring path layer assignment method according to a first embodiment of the present invention.

Referring to FIG. 1, the schematic wiring path layer assignment method according to the present embodiment includes an input device 1 realized by a keyboard, a disk, or the like, a layer assignment device 2 operated by program control, and various types of information. It comprises a storage device 3 for storing and an output device 4 realized by a display, a disk or the like.

The layer allocating device 2 includes a region extracting means 21
Route intersection extracting means 22, non-intersecting route set extracting means 23, layer assigning means 24, assignment adjusting means 25
And It should be noted that the input to the layer assignment device 2 is a schematic wiring result based on the coarse grid division input by the input device 1.

The storage device 3 includes a route intersection storage unit 31 and a route set storage unit 32.

FIG. 2 is a flowchart showing processing of the general wiring path layer assignment method according to the present embodiment. This processing includes an area selection / schematic wiring path information extraction step A1,
A schematic wiring path intersection extraction / intersection information storage step A2;
It comprises a non-intersecting route set and residual route set classification / storage step A3, a layer assignment step A4, a feasibility determination step A5, and a layer assignment adjustment step A6.

FIG. 3 is a diagram showing the concept of schematic wiring as mentioned above. FIG. 3 shows a schematic lattice 5, a region 6, a schematic wiring path 7, a terminal 8, and a virtual terminal 9.

FIGS. 4 to 12 are diagrams for explaining a specific operation of the schematic wiring path layer assignment method according to the present embodiment.

Next, the operation of the schematic wiring path layer assignment method according to the present embodiment configured as described above will be described.

First, the operation of each means in the layer assignment device 2 will be described.

The region extracting means 21 selects (extracts) a region to be processed in accordance with an appropriate criterion from the general wiring result (the result of the general wiring based on the coarse grid division) given by the input device 1, and selects the selected region. The information (schematic wiring path information) of the schematic wiring path passing through the (area to be processed) is extracted. Here, the “appropriate criterion” is a heuristic or an empirical criterion. For example, a criterion for preferentially selecting a region such as the following a or b from unprocessed regions is considered. (Either of them is to be processed first in a difficult area where the degree of freedom of layer assignment is low). a. A region with the largest number of schematic wiring paths in the region b. Attempt to extract a non-intersecting route set, and the area where the remaining route set has the largest number of elements in the trial

The route intersection extracting means 22 includes the area extracting means 2
1 (the area extraction means 21)
Information on the schematic wiring route for the area selected by
Is performed, the intersection of the schematic wiring paths passing through the area is extracted, and the intersection information indicating the intersection is stored in the path intersection storage unit 31 in the storage device 3.

FIG. 4 shows an example of intersection of schematic wiring paths in a region (region R). In the example of FIG. 4, the general wiring path na and the general wiring path nb cross each other in the region R (al, a2, b1, and b2 are virtual terminals).

The non-intersecting route set extracting means 23 scans the intersection information stored in the route intersecting storage unit 31 by the route intersecting extracting means 22, and outputs all the schematic wiring routes in the area to be processed in a wiring layer given in advance. It is classified into less than or equal to a set of non-intersecting routes (a set of schematic wiring routes that do not intersect each other). If there is a general wiring path that does not fall into such a classification, a set of such general wiring paths is extracted (classified) as a residual path set.

As will be described later, the number of vias required for detailed wiring as a result of layer allocation by the layer allocation device 2 does not fall below the number of schematic wiring paths included in the remaining path set. Therefore, the purpose (target) of the non-intersecting route set extracting means 23 is to classify as many general wiring routes as possible into any of the non-intersecting route sets (maximizing the number of elements of the non-intersecting route set).

Further, the non-intersecting route set extracting means 23
The non-intersecting route set and the remaining route set are both stored in the route set storage unit 32 in the storage device 3.

For example, in the region shown in FIG. 8 (six schematic wiring routes na, nb, nc, nd, ne, and nf
When a non-intersecting route set is extracted for the region R) through which the number of wiring layers is 2 and the obtained non-intersecting route set is a set of schematic wiring routes as shown in FIG. 9 and FIG. (Non-intersecting route set {nc, nf} and non-intersecting route set {na, nb, ne}). The residual route set in this case is as shown in FIG.
d｝).

The layer allocating apparatus 2 sequentially processes the areas selected by the area extracting means 21.
If the adjacent area (the area adjacent to the current processing target area) has already been processed, the virtual terminal having the assigned layer determined exists on the boundary between the current processing target area and the adjacent area. . Therefore, the non-intersecting route set extracting means 23 extracts the non-intersecting route set and the remaining route set as described above after fixing the virtual terminal in which the assigned layer is determined.

The layer assignment unit 24 scans the information stored in the route set storage unit 32 by the non-intersecting route set extraction unit 23 (see also the intersection information in the route intersection storage unit 31). For this purpose, each non-intersecting path set is assigned to a different appropriate layer. At this point,
The number of vias required for detailed wiring is predicted to be zero.

For example, FIG. 5 shows details of the case where {na} and {nb} correspond to different non-intersecting path sets in a region R where the general wiring path na and the general wiring path nb cross each other. A wiring example (an example of detailed wiring obtained by assigning each non-intersecting path set to a different layer without using a via) is shown (the number of wiring layers is set to 2). In this case, the layer assignment unit 24 assigns the non-intersecting route set {na} to the second layer and the non-intersecting route set {nb} to the first layer. Thus, it is possible to perform detailed wiring without using vias even in the general wiring paths (na and nb) crossing each other.

Next, the layer allocating means 24 determines each schematic wiring route (each element of the remaining route set) included in the remaining route set.
Are sequentially taken out, and layers are assigned to the schematic wiring path so that the virtual terminals at both ends of the schematic wiring path are in different layers. Here, the number of vias required for one layer assignment of the remaining route (the schematic wiring route included in the remaining route set) is one.

For example, in FIG. 6, {nb} corresponds to a non-intersecting path set and {na} corresponds to a residual path set in a region R where the general wiring path na and the general wiring path nb cross each other. In this case, a detailed wiring example (an example of a detailed wiring using one via) is shown (the number of wiring layers is 2). That is, in this case, the layer allocating unit 24 allocates the non-intersecting path set {nb} to the first layer, and sets one virtual terminal (the element of the residual path set {na}) of the residual path na (virtual on the na1 side). The terminal is allocated to the first layer, and the other virtual terminal (virtual terminal on the na2 side) is allocated to the second layer. Thereby, the detailed wiring of the schematic wiring path na is
As shown in FIG. 6, na1 in the first layer portion and via v1
And the connection with na2 of the second layer portion. This example also shows that the number of vias required for one layer assignment of the remaining route is one.

As described above, the number of vias required for layer assignment by the layer assignment means 24 is the same as the total number of remaining paths (elements of the set of remaining paths).

The layer allocating device 2 sequentially processes the areas selected by the area extracting means 21.
If the adjacent area has already been processed, the virtual terminal having the determined allocation layer exists on the boundary between the current area to be processed and the adjacent area. Therefore, the layer allocating unit 24 performs the above-described layer allocation after fixing the virtual terminal in which the allocated layer is determined.

The allocation adjusting means 25 determines whether or not the layer allocation of the general wiring route obtained by the layer allocating means 24 is executable (executability in detailed wiring). Here, when it is determined that “executable”, the determination is performed again after appropriate adjustment of the layer allocation. On the other hand, when it is determined to be “executable”, the result of the layer assignment is output to the output device 4, and the layer assignment of the schematic wiring path to the area to be processed at the present time is ended.

Here, as the contents of the determination of the feasibility, the following can be considered (determination contents based on the boundary capacity of the area boundary). Note that the upper limit of the number of virtual terminals that can be allocated is determined by the dimensional restriction at the region boundary in each layer, and this upper limit is referred to as “boundary capacitance”.

That is, if the number of virtual terminals allocated to the area boundary of each layer by the layer allocation means 24 is equal to or less than the boundary capacity, the layer allocation is determined to be “executable”. On the other hand, when the allocated number of virtual terminals exceeds the boundary capacity, it is determined that “executable”.

As the procedure of the above-mentioned assignment adjustment, the following procedures a to c (adjustment procedure by moving the virtual terminal to a different layer based on the boundary capacitance of the area boundary) can be considered. .

A. Focusing on all the area boundaries sequentially,
It is determined whether or not the boundary capacity is exceeded for each region boundary.

B. If there is no excess of the boundary capacity at the region boundary, it is determined that the region boundary is “executable”. If the number of virtual terminals allocated at the area boundary is equal to the boundary capacity, it is determined that the allocation is saturated, and the allocation is fixed.
On the other hand, when there is an excess of the boundary capacitance, the excess is eliminated by moving the excess virtual terminal to the area boundary of another layer. Here, it is assumed that the destination area boundary is limited to an area boundary whose assignment is not fixed (this prevents a new capacity excess from being caused by the movement of the virtual terminal).

C. The adjustment of the allocation ends when the number of virtual terminals and the boundary capacitance become equal, and the allocation of the area boundary is fixed. Here, the number of vias newly required by adjusting the assignment of the virtual terminal is at most (at most) one per one movement of the virtual terminal.

The processing of the above-described assignment adjusting means 25 will be specifically described with reference to FIGS. 5, 6, and 7 (a diagram showing an example of detailed wiring using two vias).

If the general wiring route to which the virtual terminal movement (movement by the adjustment of the assignment adjusting means 25) is included in the non-intersecting path set, the virtual terminal movement causes the general wiring route to move. State is na in FIG.
From the state of na (na1, v1, and na2) in FIG.
, And the required number of vias increases by one.

On the other hand, if the schematic wiring path to which the virtual terminal movement is applied is included in the remaining path set, the virtual terminal movement causes the virtual terminal assignment layers at both ends of the general wiring path to be the same. When this happens, na (n
a1, v1, and na2) to the state of na in FIG. 7 (a state in which na1 and na3 belonging to the same layer and na2 belonging to different layers are connected by vias v1 and v2), and the required number of vias Increases by one. Further, in this case, when the number of wiring layers is three or more and the allocation layers of the virtual terminals at both ends of the general wiring path are different even after the movement of the virtual terminals, the state transition is performed in the state of na in FIG. (Although the layer to which na1 or na2 belongs will change), the number of vias required does not increase.

In this way, the number of vias newly required by the adjustment of the allocation adjusting means 25 is at most the same as the number of schematic wiring paths to which the allocation adjustment has been applied.

The number of vias resulting from the layer allocation by the layer allocation device 2 is summarized as follows.
And b. a. The number of elements of the remaining route set extracted by the non-intersecting route set extracting means 23 does not fall below. b. If there is a schematic wiring path to which the allocation adjustment has been applied by the allocation adjusting means 25, at most, the sum of the number of remaining paths and the number of the schematic wiring paths to which the allocation adjustment has been applied is the number of vias required.

Second, referring to FIGS. 1 and 2, the overall operation of the schematic wiring path layer assignment method according to the present embodiment will be described.

First, the area extracting means 21 in the layer allocating apparatus 2 selects an area to be processed according to an appropriate criterion from the schematic wiring result given by the input device 1, and the general wiring passing through the selected area. The route information is extracted (step A1 in FIG. 2).

Next, the route intersection extracting means 22 scans the information on the schematic wiring paths relating to the area selected by the area extracting means 21 and extracts the intersections between the general wiring paths passing through the area. Intersection information indicating the intersection is stored in the storage device 3.
Is stored in the route intersection storage unit 31 (step A2).

The non-intersecting route set extracting means 23 scans the intersection information stored in the route intersecting storage unit 31 by the route intersecting extracting means 22, and obtains all schematic wiring routes in the area to be processed in a wiring layer given in advance. If there is a general wiring route that does not fall into such a classification even after trying to classify all the general wiring routes into the non-crossing route set as much as possible, classify them as remaining routes. As a set element, both the non-intersecting route set and the remaining route set are stored in the non-intersecting route set storage unit 32 in the storage device 3 (step A3).

Further, the layer assignment unit 24 scans the information (information indicating the non-intersecting route set and the remaining route set) stored in the route set storage unit 32 by the non-intersecting route set extracting unit 23 (the route intersection storage unit). 31 is also referred to), and layers are allocated for detailed wiring (step A4). That is, first, each non-intersecting path set is assigned to an appropriate layer. Second, the schematic wiring paths included in the residual path set are sequentially extracted, and the virtual terminals at both ends of each of the schematic wiring paths are in different layers (so that the required number of vias is 1). The schematic wiring paths (virtual terminals at both ends of each of the schematic wiring paths) are assigned to appropriate layers.

Finally, the assignment adjusting means 25 determines whether or not the layer assignment of the schematic wiring path obtained by the layer assigning means 24 is executable (step A).
5).

If it is determined in step A5 that “executable”, the allocation adjusting means 25 appropriately adjusts the layer allocation (see “Adjustment by moving virtual terminals based on boundary capacity of area boundary as described above”). "Etc.) (Step A
6) The determination in step A5 is performed again for the layer assignment after the adjustment.

On the other hand, if it is determined in step A5 that the execution is "executable", the allocation adjusting means 25 outputs the result of the layer allocation to the output device 4 (the output device 4 outputs the layer allocation to the outside). The result is output), and the layer assignment of the schematic wiring path to the area (current processing area) ends.

If there is any unprocessed area, the layer allocating apparatus 2 returns to the starting point in FIG. 2 and repeats the above series of processing.

Third, using the examples shown in FIGS.
A specific operation of the schematic wiring path layer assignment method according to the present embodiment will be described.

Here, as shown in FIG. 8, a region R through which six schematic wiring routes na, nb, nc, nd, ne and nf pass is considered as a region to be processed.

In this case, the route intersection extracting means 22 determines C (na, nd), C (n
a, nc), C (na, nf), C (nb, nc), C
(Nb, nd), C (nb, nf), C (nc, n
d) and eight of C (ne, nf) are extracted. Here, for example, “C (na, nd)” is the approximate wiring path n
The crossing (crossing) between a and the general wiring path nd is shown.

Next, the intersection information indicating the eight intersections is scanned by the non-intersecting route set extracting means 23, and the entire schematic wiring route is set to the first non-intersecting route set as shown in FIG.
That is, it is classified into {nc, nf}, a second non-intersecting route set as shown in FIG. 10, ie, {na, nb, ne}, and a residual route set as shown in FIG. 11, ie, {nd}. You.

Here, assuming that the number of wiring layers is two, the first non-intersecting route set {n
c, nf} are assigned to the first layer, the second non-intersecting path set {na, nb, ne} is assigned to the second layer, and finally the residual path set {nd} is a virtual path at both ends of the residual path nd. The terminals are assigned to be in different layers (in this example, one virtual terminal (virtual terminal on the nd1 side in FIG. 12))
Are assigned to the first layer, and the other virtual terminal (nd2
Side virtual terminal) is assigned to the second layer).

In this example, it is assumed that the boundary capacity is not exceeded, and that the above-mentioned layer allocation is determined to be “executable” by the allocation adjusting means 25, and the result of the layer allocation is output from the output device 4. .

FIG. 12 shows an example of detailed wiring corresponding to the output result. It can be seen that the via v is generated only in the wiring corresponding to the remaining path nd. Eventually, in this example, the required number of vias is equal to one, which is the number of elements in the remaining route set.

(2) Second Embodiment FIG. 13 is a block diagram showing a configuration of a schematic wiring path layer assignment method according to a second embodiment of the present invention.

Referring to FIG. 13, the schematic wiring path layer assignment method according to the second embodiment of the present invention is different from the schematic wiring path layer assignment method according to the first embodiment shown in FIG. And a recording medium 100 in which a schematic wiring path layer assignment processing program is recorded. The recording medium 100 may be a magnetic disk, a semiconductor memory, or another recording medium.

The general wiring route layer assignment processing program is executed by a layer assignment device 2 (area extraction means 21, route intersection extraction means 2) realized by a computer from the recording medium 100.
2, non-intersecting route set extraction means 23, layer assignment means 2
4, and the input device 1,
Storage device 3 having route intersection storage portion 31 and route set storage portion 32, and device connecting output device 4)
The operation of the computer is read by the area extracting unit 21, the route intersection extracting unit 22, the non-intersecting route set extracting unit 23, the layer assigning unit 24, and the assignment adjusting unit 2.
Control is performed as 5. Area extraction means 21, route intersection extraction means 22, non-intersecting path set extraction means 23, layer assignment means 2 under the control of the schematic wiring path layer assignment processing program
4 and the operation of the assignment adjusting means 25 are the same as those of the area extracting means 21 and the route intersection extracting means 2 in the first embodiment.
2, non-intersecting route set extraction means 23, layer assignment means 2
4 and the operation of the assignment adjusting means 25 are completely the same, and a detailed description thereof will be omitted.

[0075]

As described above, according to the present invention,
The following effects are produced.

The first effect is that it can appropriately cope with a multilayer wiring of two or more layers.

The reason why such an effect occurs is that, according to the given number of wiring layers, the layer allocation of the general wiring path that reduces the required number of vias can be performed, and the easiness of detailed wiring can be improved. is there. In particular, in the case of a multilayer wiring having three or more layers, the degree of freedom of layer assignment is high, and the significance of the above-described effects becomes large.

Here, specific factors for reducing the number of vias include the following a to c.

A. When the non-intersecting route set is extracted by the non-intersecting route set extracting means, the required number of vias can be reduced by maximizing the number of elements of the non-intersecting route set.

B. The layer assignment means assigns each non-intersecting route set to a different layer, and for each schematic wiring route included in the remaining route set, a layer assignment that requires only one via is sequentially performed, so that the required number of vias is obtained. Can be reduced.

C. At the time of layer allocation adjustment performed when it is determined as “impossible” in the determination of feasibility by the allocation adjusting unit with respect to the result of the layer allocation by the layer allocation unit, it is necessary to perform one adjustment of the layer allocation. Since the number of vias is suppressed to at most one, the number of required vias can be reduced.

The second effect is that a layer can be assigned for detailed wiring of a schematic wiring path based on accurate prediction of the number of vias (prediction of the number of vias in a stage before execution of detailed wiring). .

The reason why such an effect occurs is that the concept of “non-intersecting route set” and “remaining route set” is adopted to accurately predict the number of vias due to crossing of general wiring routes in accordance with the number of wiring layers. This is because it can be performed.

Note that the above-described “high-precision prediction of the number of vias” not only reduces the number of vias, but also suppresses an increase in the processing time required for detailed wiring and an increase in processing time due to rework of processing. Will be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a schematic wiring path layer assignment method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing processing of a schematic wiring path layer assignment method shown in FIG. 1;

FIG. 3 is a diagram showing a schematic wiring grid, terminals, virtual terminals, schematic wiring paths, and regions.

FIG. 4 is a diagram for explaining a specific operation in the schematic wiring path layer assignment method shown in FIG. 1 (a diagram showing intersections of schematic wiring paths in a region);

FIG. 5 is a diagram for explaining a specific operation in the schematic wiring path layer assignment method shown in FIG. 1 (a diagram showing an example of detailed wiring without using vias);

FIG. 6 is a diagram for explaining a specific operation in the schematic wiring path layer assignment method shown in FIG. 1 (a diagram showing an example of detailed wiring using one via).

FIG. 7 is a diagram (an example of a detailed wiring using two vias) for explaining a specific operation in the schematic wiring path layer assignment method shown in FIG. 1;

FIG. 8 is a diagram (a diagram showing an area through which six schematic wiring paths pass) for explaining a specific operation in the schematic wiring layer assignment method shown in FIG. 1;

9 is a diagram (a diagram showing a first non-intersecting route set) for explaining a specific operation in the schematic wiring route layer assignment system shown in FIG. 1;

FIG. 10 is a diagram (a diagram showing a second non-intersecting route set) for explaining a specific operation in the schematic wiring route layer assignment method shown in FIG. 1;

11 is a diagram (showing a set of remaining routes) for explaining a specific operation in the schematic wiring route layer assignment method shown in FIG. 1;

12 is a diagram (a diagram showing a specific example of detailed wiring corresponding to a result of layer allocation) for describing a specific operation in the schematic wiring path layer allocation method shown in FIG. 1;

FIG. 13 is a block diagram showing a configuration of a schematic wiring path layer assignment method according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input device 2 Layer assignment device 3 Storage device 4 Output device 5 Schematic lattice 6 Area 7 Schematic wiring path 8 Terminal 9 Virtual terminal 21 Area extraction means 22 Path intersection extraction means 23 Non-intersection path set extraction means 24 Layer assignment means 25 Assignment adjustment Means 31 Route intersection storage unit 32 Route set storage unit 100 Recording medium

Claims (6)

[Claims] 1. An area extracting means for selecting an area to be processed from a result of the rough wiring based on the coarse grid division and extracting information on a rough wiring path passing through the area, and a processing object selected by the area extracting means Path intersection extracting means for extracting intersection information indicating intersections of the schematic wiring paths existing in the area, and a set of schematic wiring paths in the processing target area with reference to the intersection information extracted by the path intersection extracting means Classify and extract the number of non-intersecting path sets less than the number of wiring layers from
A non-intersecting route set extracting means for extracting a general wiring route which does not belong to any non-intersecting route set as an element of a residual route set; intersection information extracted by the route intersecting extracting means; and the non-intersecting route set extracting means Allocating means for allocating layers for detailed wiring related to an area to be processed with reference to the information indicating the non-intersecting path set and the remaining path set extracted by A general wiring path layer assignment method, comprising: an assignment adjustment unit that determines whether or not the assignment is possible and adjusts the layer assignment when it is determined that the execution is impossible. 2. A region extracting means for selecting a region to be processed from a result of the rough wiring based on the coarse grid division and extracting information on a rough wiring route passing through the region, and the rough wiring extracted by the region extracting means Path intersection extraction means for extracting intersection information indicating intersections of general wiring paths existing in the processing target area selected by the area extraction means based on path information; and intersections extracted by the path intersection extraction means Referring to the information, classify and extract the number of non-intersecting path sets equal to or less than the number of wiring layers from the set of schematic wiring paths in the processing target area, and maximize the number of elements of the non-intersecting path set at the time of the extraction. A non-intersecting route set extracting means for extracting a general wiring route which does not belong to any non-intersecting route set as an element of a residual route set; With reference to the difference information and the information indicating the non-intersecting route set and the remaining route set extracted by the non-intersecting route set extracting means, each non-intersecting route set is assigned to a different layer, and each outline included in the remaining route set is assigned. By sequentially allocating only one via for the wiring path, a layer allocating means for allocating a layer for detailed wiring with respect to a processing target area, and a layer allocating performed by the layer allocating means can be executed. Determining whether or not there is, and when determining that the execution is impossible, an allocation adjusting means for adjusting the layer allocation such that the number of vias required per adjustment of the layer allocation is suppressed to at most one. A schematic wiring path layer assignment method, comprising: 3. The feasibility of layer assignment is determined based on the boundary capacity of the area boundary, and if the determination is “impossible” in the determination, the virtual terminal is changed based on the boundary capacity of the area boundary. 3. The schematic wiring path layer assignment method according to claim 2, further comprising an assignment adjustment unit that adjusts layer assignment by moving to a layer. 4. An input device for inputting a schematic wiring result based on a coarse grid division given to a region extracting means, a path intersection storing section for storing intersection information extracted by the path intersection extracting means, and a non-intersecting path set extracting means. And a storage device including a route set storage unit for storing information indicating the non-intersecting route set and the remaining route set extracted by the method, and outputs the result of the layer assignment for which the feasibility has been determined and adjusted by the assignment adjusting unit. 4. The general wiring path layer assignment method according to claim 1, further comprising an output device. 5. A computer which selects a region to be processed from a result of the rough wiring based on the coarse grid division and extracts information of a rough wiring route passing through the region, and the computer selects the region to be processed. Path intersection extracting means for extracting intersection information indicating intersections of the schematic wiring paths existing in the processing target area, and referring to the intersection information extracted by the path intersection extracting means, to determine a general wiring path in the processing target area. A non-intersecting path set extracting means for classifying and extracting a number of non-intersecting path sets equal to or less than the number of wiring layers from the set, and extracting, as an element of a residual path set, a schematic wiring path which does not belong to any of the non-intersecting path sets; Refer to the intersection information extracted by the route intersection extracting means and the information indicating the non-intersecting route set and the residual route set extracted by the non-intersecting route set extracting means. Layer allocation means for performing layer allocation for detailed wiring for a region to be processed, and determines whether or not the layer allocation performed by the layer allocation means is executable, and determines "executable". A recording medium on which a program for functioning as an assignment adjusting means for adjusting the layer assignment is recorded. 6. A computer which selects a region to be processed from a result of the rough wiring based on the coarse grid division and extracts information of a rough wiring route passing through the region, and the computer extracts the information of the rough wiring route. A route intersection extracting unit for extracting intersection information indicating an intersection of the general wiring routes existing in the region to be processed selected by the region extracting unit based on the information of the general wiring route; Referring to the intersection information, classify and extract the number of non-intersecting path sets equal to or less than the number of wiring layers from the set of schematic wiring paths in the processing target area, and maximize the number of elements of the non-intersecting path set at the time of the extraction. A non-intersecting route set extracting means for extracting a general wiring route which does not belong to any non-intersecting route set as an element of a residual route set, With reference to the issued intersection information and the information indicating the non-intersecting route set and the remaining route set extracted by the non-intersecting route set extracting means, each non-intersecting route set is assigned to a different layer, and included in the remaining route set. By assigning only one via to each schematic wiring path sequentially, layer assigning means for assigning layers for detailed wiring relating to the area to be processed, and layer assignment performed by the layer assigning means are performed. Determines whether or not it is executable, and "executes"
A recording medium on which is recorded a program for functioning as an assignment adjusting means for adjusting the layer assignment so that the number of vias required per adjustment of the layer assignment is limited to one at most.