WO2021164010A1

WO2021164010A1 - Array substrate and display panel

Info

Publication number: WO2021164010A1
Application number: PCT/CN2020/076232
Authority: WO
Inventors: 魏旃; 王世君; 冯博; 穆文凯; 王洋; 刘屹; 田丽
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2020-02-21
Filing date: 2020-02-21
Publication date: 2021-08-26
Also published as: CN113544581A

Abstract

Disclosed are an array substrate and a display panel. The array substrate comprises: a base substrate, the base substrate comprising a display region and a frame region surrounding the display region; the frame region comprises: a first frame sub-region extending along a first direction, a second frame sub-region extending along a second direction, and an arc-shaped sub-region connected between the first frame sub-region and the second frame sub-region, wherein the first frame sub-region and the second frame sub-region are adjacently arranged, and the first direction is perpendicular to the second direction. The array substrate comprises a plurality of cascaded gate shift registers located in the frame region, and the width, in the second direction, of at least one gate shift register located in the arc-shaped sub-region is less than the width, in the second direction, of the gate shift registers located in the first frame sub-region and the second frame sub-region, reducing the display region area occupied by the gate shift registers located in the arc-shaped sub-region, and increasing the screen-to-body ratio of the array substrate.

Description

Array substrate and display panel

Technical field

The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel.

Background technique

In the related art, the display panel includes a display area and a frame area surrounding the display area, and a gate driving circuit is provided at at least one side of the frame area to provide driving signals to each gate line in the display area.

Summary of the invention

In a first aspect, embodiments of the present disclosure provide an array substrate, which includes: a base substrate having a display area and a frame area surrounding the display area;

The frame area includes: a first frame sub-area extending in a first direction, a second frame sub-area extending in a second direction, and connected between the first frame sub-area and the second frame sub-area The arc-shaped sub-area of, wherein the first frame sub-area and the second frame sub-area are arranged adjacently, and the first direction and the second direction are perpendicular to each other;

The array substrate includes a plurality of cascaded gate shift registers located in the frame area, and the width of at least one gate shift register located in the arc-shaped sub-region in the second direction is smaller than that located in the second direction. The width in the second direction of the gate shift register in the first frame sub-region and the second frame sub-region.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the gate shift registers in the arc-shaped sub-regions have the same size.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, in the arc-shaped sub-region, the gate shift register far from the first frame sub-region is in the second direction The width of is smaller than the width of the gate shift register near the first frame sub-region in the second direction.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, all the gate shift registers have the same circuit connection structure;

The length of at least one gate shift register located in the arc-shaped sub-region in the first direction is greater than the gate shift located in the first frame sub-region and the second frame sub-region The length of the register in the first direction.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the width of the gate shift register located in the first frame subregion in the second direction is smaller than that of the second The width of the gate shift register in the second direction in the frame sub-region.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the length of the gate shift register located in the first frame subregion in the first direction is greater than that of the gate shift register located in the first frame. The length of the gate shift register in the first direction in the sub-region of the second frame.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the gate shift register located in the arc-shaped sub-region and the gate shift register located in the first frame sub-region and the second frame sub-region are different from each other. The circuit connection structure of the gate shift register in the frame sub-region is different;

The area occupied by each of the gate shift registers in the arc-shaped sub-region is smaller than the area occupied by each of the gate shift registers in the first frame sub-region and the second frame sub-region.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the frame area further includes: a third frame sub-area, and the third frame sub-area extends along the second direction and is incompatible with The second frame sub-regions are relatively arranged;

The array substrate further includes a source drive circuit located in the third frame sub-region, and the source drive circuit is electrically connected to a plurality of data lines located in the display area.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the frame area further includes: a fourth frame sub-area, and the fourth frame sub-area is arranged opposite to the first frame sub-area ；

The fourth frame sub-region includes a plurality of the gate shift registers.

In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the display area includes: a plurality of gate lines, and the gate lines extend along the second direction;

The gate shift register in the first frame sub-region and the gate shift register in the fourth frame sub-region are electrically connected to the gate lines in different rows, respectively.

In a second aspect, embodiments of the present disclosure also provide a display panel, including the array substrate provided in any one of the embodiments of the first aspect, and a plurality of sub-pixels located in the display area.

Description of the drawings

FIG. 1 is a schematic diagram of the structure of an array substrate in the related art;

2 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a partially enlarged structure provided by an embodiment of the disclosure;

4 is a schematic structural diagram of a gate shift register in a first frame sub-region or a second frame sub-region provided by an embodiment of the present disclosure;

5 is a schematic structural diagram of a gate shift register in an arc-shaped sub-region provided by an embodiment of the disclosure;

6a and 6b are schematic diagrams of another partially enlarged structure provided by an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another array substrate provided by an embodiment of the disclosure;

FIG. 8 is a schematic structural diagram of yet another array substrate provided by an embodiment of the disclosure.

Detailed ways

The array substrate in the related art, as shown in FIG. 1, includes a display area A0 and a frame area B0 surrounding the display area A0. A plurality of cascaded gate shift registers S0 are provided in the frame area B0 to display The corresponding gate line (not specifically shown in the figure) in the area A0 is driven. However, based on the design of a chamfered area (area in the dashed line frame) in the frame area B0, due to the limitation of the outer frame shape of the frame area B0, when the gate shift register S0 is provided in the chamfered area, the gate shifts The bit register S0 occupies the area of the display area A0, which reduces the screen-to-body ratio of the array substrate and is not conducive to the realization of a narrow frame.

Based on the above-mentioned problems existing in the array substrate in the related art, embodiments of the present disclosure provide an array substrate and a display panel. In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the specific implementations of the array substrate and the display panel provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. And if there is no conflict, the embodiments in the application and the features in the embodiments can be combined with each other.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. "Include" or "include" and other similar words mean that the element or item appearing before the word covers the elements or items listed after the word and their equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

The shapes and sizes of the components in the drawings do not reflect the true proportions, and are only intended to illustrate the present disclosure.

Specifically, an embodiment of the present disclosure provides an array substrate. As shown in FIGS. 2 and 3, the array substrate includes: a base substrate having a display area A and a frame area B surrounding the display area A;

The frame area B includes: a first frame sub-area B1 extending along the first direction, a second frame sub-area B2 extending along the second direction, and connected between the first frame sub-area B1 and the second frame sub-area B2 The arc-shaped sub-area B3 of, wherein the first frame sub-area B1 and the second frame sub-area B2 are arranged adjacently, and the first direction and the second direction are perpendicular to each other;

The array substrate includes a plurality of cascaded gate shift registers S located in the frame area B, and the width W3 of the at least one gate shift register S located in the arc-shaped sub-area B3 in the second direction is smaller than that located in the first The widths W1/W2 of the gate shift register S in the frame sub-region B1 and the second frame sub-region B2 in the second direction.

Specifically, in the array substrate provided by the embodiment of the present disclosure, by designing the size of the gate shift register of each sub-region in the arc-shaped sub-region, the gate shift register in the arc-shaped sub-region is The width in the second direction is smaller than the width in the second direction of the gate shift register located in the first frame sub-region and the second frame sub-region, thereby reducing the gate shift register occupancy in the arc-shaped sub-region The area of the display area can increase the screen-to-body ratio of the array substrate, and is beneficial to realize a narrow frame design.

It should be noted that, in the array substrate provided by the embodiment of the present disclosure, the length of the gate shift register in the first direction and the width in the second direction refer to the area occupied by the circuit structure of the gate shift register. The length in the first direction and the width in the second direction. Among them, the gate shift register includes a plurality of electrically connected transistors and capacitors. The shape of the area occupied by these transistors and capacitors is approximately rectangular, and the size of the area occupied by the gate shift register in the arc-shaped sub-region is adjusted. This can be achieved by changing the position and shape of the transistors and capacitors on the base substrate. Among them, the connection relationship between the transistors and the capacitors in the arc-shaped sub-regions may not change. By changing the position and/or of the transistors The shape of the capacitor can change the size of the area occupied by the gate shift register.

As shown in FIG. 4, it is a schematic diagram of the structure of the gate shift register in the first frame sub-region or the second frame sub-region. It can be seen from FIG. 4 that a plurality of transistors TFT are located in the same row and are arranged in sequence along the second direction. , And from the structure diagram of the gate shift register in the arc-shaped sub-region shown in FIG. 5, it can be seen that a plurality of transistors TFT are arranged in two rows in the second direction. Therefore, the arc shape can be reduced by this arrangement. The width in the second direction of the area occupied by the transistor TFT in the gate shift register in the sub-area increases its length in the first direction. In addition, the shape of the capacitor C in the gate shift register in the first frame sub-region or the second frame sub-region and the capacitor C in the gate shift register in the arc-shaped sub-region are also different. The capacitor C in the gate shift register in the sub-region or the second frame sub-region is rectangular, which increases the width of the gate shift register in the region in the second direction; while the capacitor in the arc-shaped sub-region is L-shaped , So that the width of the gate shift register in this area in the second direction is smaller. Among them, by changing the shape of the capacitor C in the gate shift register, and the shape and position of one or several transistors TFT, the width of the gate shift register in the arc-shaped sub-region in the second direction can be reduced. , But it can also ensure that the capacitance value and the driving ability of the transistor remain unchanged.

Wherein, since the gate shift register in the arc-shaped sub-region has a relatively large length in the first direction, the number of gate shift registers that can be contained in the first frame sub-region extending along the first direction is limited. Therefore, part of the gate shift register can be prevented from being located in the second frame sub-area that is adjacent to the first frame sub-area and extends in the second direction.

It should be noted that the frame area may include a plurality of arc-shaped sub-regions, and the arc-shaped sub-regions may be at any top corner of the array substrate. In FIG. 2, the gate shift register is located at the upper right corner. The arc-shaped sub-region of is taken as an example for description. Of course, the gate shift register may also be located in arc-shaped sub-regions in other positions, all of which are within the protection scope of the present disclosure. Among them, the position of the top corner of the row of substrates where the arc-shaped sub-region is located depends on the side of the frame area on which the gate shift register is located. If it is located on the right side of the display area, the arc-shaped sub-region may be It is located at the upper right corner and/or lower right corner of the array substrate. Of course, this is also related to the location and area occupied by the source drive circuit. If the lower right corner is located, the arc-shaped sub-region is located at the upper right corner of the array substrate. That is, the position of the arc-shaped sub-region needs to be designed in comprehensive consideration of the layout of other circuits in the array substrate. When the source driving circuit is located on the lower frame of the array substrate, it is preferable to set the arc-shaped sub-area at the upper right corner and/or the upper left corner. Of course, when the source driving circuit does not occupy the lower right corner and the lower left corner area, it is also The arc-shaped sub-region can be set at the lower right corner and/or the lower left corner, and can be selected according to the actual situation, which is not specifically limited here.

Wherein, the width of the gate shift register in the arc-shaped sub-region in the second direction is approximately greater than the width of the gate shift register in the first frame sub-region and/or the second frame sub-region in the second direction. Reduce 69.85 (about 60% to 80% of the size of a single pixel in the display area), the length of the gate shift register in the arc-shaped sub-region in the first direction is longer than that of the first frame sub-region and/or The length of the gate shift register in the second frame subregion in the first direction is increased by approximately 83.3 frames (approximately 80% to 90% of the size of a single pixel).

Optionally, in the array substrate provided by the embodiment of the present disclosure, the size of each gate shift register in the arc-shaped sub-region may be the same or different. When the sizes of the gate shift registers in the arc-shaped sub-region are different, the width of the gate shift register in the arc-shaped sub-region that is far from the first frame sub-region in the second direction can be smaller than that of the gate shift register that is close to the first frame. The width of the gate shift register of a frame sub-region in the second direction. This setting is beneficial to the excessive boundary of the arc-shaped sub-region and reduces the occupied area of the display area.

Specifically, in the array substrate provided by the embodiment of the present disclosure, the width of each gate shift register in the arc-shaped sub-region can be gradually changed with the change of the position, of course, it can be changed according to each gate shift register. In the position, the width of the two or more gate shift registers in the adjacent position in the second direction is set to be the same. As shown in FIG. 6a, in the arc-shaped sub-region, the array substrate includes gate shift registers S1, S2, S3, S4, S5, and S6 in the direction in which the first frame sub-region points to the second frame sub-region, And the width of each gate shift register in the second direction is successively decreasing, that is, W31﹥W32﹥W33﹥W34﹥W35﹥W36. As shown in Figure 6b, the widths of the gate shift register S1 and the gate shift register S2 in the second direction can also be set to W31, and the gate shift register S3 and the gate shift register S4 can be set in the second direction. The widths in the two directions are both set to W32, and the widths of the gate shift register S5 and the gate shift register S6 in the second direction are both set to W33, where W31﹥W32﹥W33. Of course, how to set the gate shift registers in the arc-shaped sub-regions needs to be selected according to the actual design, which is not specifically limited here.

Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 3, the circuit connection structure of all the gate shift registers S is the same;

The length L3 of the at least one gate shift register S located in the arc-shaped sub-region B3 in the first direction is greater than the length L1 and the second gate shift register S located in the first frame sub-region B1 in the first direction. The length L2 of the gate shift register S of the region B2 in the first direction.

Specifically, in the array substrate provided by the embodiment of the present disclosure, when the circuit connection structure of all the gate shift registers is the same, the area occupied by each gate shift register is the same, and the area of each gate shift register can be adjusted by Layout of the device to adjust the length of the gate shift register in each sub-region in the first direction and the width in the second direction. For example, when the width of the gate shift register located in the arc-shaped sub-region in the second direction is smaller than the width of the gate shift register located in the first frame sub-region and the second region in the second direction, then The length of the gate shift register located in the arc-shaped sub-region in the first direction needs to be greater than the length of the gate shift register located in the first frame sub-region and the second region in the first direction, so as to ensure that each The gate shift register has a reasonable layout.

Wherein, the same circuit connection structure of the gate shift registers means that the transistors and capacitors included in each gate shift register have the same electrical connection relationship, and their shapes and positions can be different, that is, they can pass through The positions and shapes of the transistors and capacitors in each subregion are designed to change the size of the gate shift register in each subregion in the first direction and in the second direction.

Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 3, the width W1 of the gate shift register S located in the first frame sub-region B1 in the second direction is smaller than that of the second frame sub-region B2 The width W2 of the gate shift register S in the second direction.

Specifically, in the array substrate provided by the embodiment of the present disclosure, since the first frame sub-region extends along the first direction, in order to realize a narrow frame arrangement, the width of the first frame sub-region in the second direction should be as small as possible. Therefore, the width of the gate shift register located in the first frame sub-region in the second direction can be smaller than the width of the gate shift register located in the second frame sub-region in the second direction. The narrow border design of the border sub-area.

Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 3, the length L1 of the gate shift register S located in the first frame subregion B1 in the first direction is greater than that of the gate shift register S located in the second frame subregion. The length L2 of the gate shift register S in the first direction in B2.

Specifically, in the array substrate provided by the embodiment of the present disclosure, since the second frame sub-region extends in the second direction, in order to achieve a narrow frame arrangement, the width of the second frame sub-region in the first direction should be as small as possible. Therefore, the length of the gate shift register located in the first frame sub-region in the first direction can be greater than the length of the gate shift register located in the second frame sub-region in the first direction. The narrow frame design of the second frame sub-area.

Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 3, the gate shift register S located in the arc-shaped sub-region B3 and the gate shift register S located in the first frame sub-region B1 and the second frame sub-region B2 The circuit connection structure of the gate shift register S inside is different;

The area occupied by the gate shift registers S in the arc-shaped sub-region B3 is smaller than the area occupied by the gate shift registers S in the first frame sub-region B1 and the second frame sub-region B2.

Specifically, in the array substrate provided by the embodiment of the present disclosure, the gate shift register located in the arc-shaped sub-area and the gate shift register located in the first frame sub-area and the second frame sub-area can also be used. The circuit connection structure is different. By designing the connection structure of each device in the gate area circuit in each sub-area, the area occupied by the gate shift register in the arc-shaped sub-area can be reduced, so that the area in the arc-shaped sub-area can be reduced. The width of the gate shift register in the sub-region in the second direction is reduced to reduce the area of the display area occupied by the gate shift register.

The different circuit connection structures of the gate shift registers mean that the electrical connection relationship and/or the number of transistors and capacitors included in each gate shift register may be different. For example, in order to reduce the area occupied by the gate shift register in the arc-shaped sub-region, you can choose to use a gate shift register with a smaller number of transistors in the arc-shaped sub-region, and choose to use transistors in other sub-regions. A larger number of gate shift registers.

It should be noted that the specific circuit structure of the gate shift register in each sub-region can be different, but there is a cascade relationship between gate shift registers based on different structures, and it is necessary to ensure that gate shift registers of different structures The running sequence meets the requirements of the cascading relationship, and can be specifically designed according to actual needs, which is not specifically limited here.

Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 7, the frame area further includes: a third frame sub-area B4, and the third frame sub-area B4 extends in the second direction and is connected to the second frame. The border sub-region B2 is relatively set;

The array substrate further includes a source drive circuit D located in the third frame sub-region B4, and the source drive circuit D is electrically connected to a plurality of data lines (not specifically shown in the figure) located in the display area A.

Specifically, in the array substrate provided by the embodiment of the present disclosure, the second frame sub-region and the source driving circuit may be arranged on opposite sides, so that the arrangement of the circuits of each part is more reasonable. If the source driving circuit is arranged in the third frame sub-area, the source driving circuit has already occupied a part of the side width area, and if the arc-shaped sub-area is set to be adjacent to the third frame sub-area, it will increase the wiring difficulty , And it will reduce the signal transmission reliability of each circuit, and it is easy to short-circuit, which affects the normal display. Therefore, by arranging the second frame sub-region and the source driving circuit on opposite sides, each circuit can be laid out more reasonably, so as to increase the signal transmission reliability of each circuit.

Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 8, the frame area B further includes: a fourth frame sub-area B5, and the fourth frame sub-area B5 is disposed opposite to the first frame sub-area B1 ；

The fourth frame sub-region B5 includes a plurality of gate shift registers S.

Specifically, in the array substrate provided by the embodiment of the present disclosure, in addition to the gate shift register may be arranged in the second frame sub-region, when the number of gate shift registers is large, the gate shift register may also be arranged in the fourth frame area. The gate shift register is provided, that is, the gate shift register is provided at both sides of the frame extending in the first direction, so that the high-pixel display panel can be driven.

Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 8, the display area A includes: a plurality of gate lines G, and the gate lines G extend along the second direction;

The gate shift register S in the first frame sub-region B1 and the gate shift register S in the fourth frame sub-region B5 are electrically connected to different rows of gate lines G, respectively.

Specifically, in the array substrate provided by the embodiment of the present disclosure, the gate shift registers respectively disposed in the first frame sub-region and the fourth frame sub-region can drive different gate lines, so that more rows can be driven. Pixels, suitable for driving high-pixel display panels. It is also possible to make the gate shift registers located in the first frame sub-region and the fourth frame sub-region to drive the gate lines located in the same row, that is, the double-sided driving method is adopted. The details can be selected according to actual needs, and there is no specific limitation here.

Based on the same inventive concept, embodiments of the present disclosure also provide a display panel, which includes the array substrate provided by any of the above-mentioned embodiments, and a plurality of sub-pixels located in the display area.

Among them, the array substrate has all the advantages of the array substrate provided by the above-mentioned embodiments. Therefore, implementation can be carried out with reference to the above-mentioned embodiments of the array substrate, which will not be repeated here.

Based on the same inventive concept, embodiments of the present disclosure also provide a display device, which includes the display panel provided in the above-mentioned embodiments, and a protective cover on one side of the light-emitting surface of the display panel.

Wherein, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on. Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure. The implementation of the display device can be referred to the embodiment of the above-mentioned display panel, and the repetition will not be repeated.

Embodiments of the present disclosure provide an array substrate and a display panel. The array substrate includes a base substrate, the base substrate includes a display area and a frame area surrounding the display area; the frame area includes: a first frame sub-area extending in a first direction , A second frame sub-area extending along the second direction, and an arc-shaped sub-area connected between the first frame sub-area and the second frame sub-area, wherein the first frame sub-area is adjacent to the second frame sub-area The first direction and the second direction are perpendicular to each other; the array substrate includes a plurality of cascaded gate shift registers located in the frame area, and at least one gate shift register located in the arc-shaped sub-region is in the second direction The width of is smaller than the width in the second direction of the gate shift register located in the first frame sub-region and the second frame sub-region. By designing the size of the gate shift register in the arc-shaped sub-region, the width of the gate shift register in the arc-shaped sub-region in the second direction is smaller than that of the gate shift register in the first frame. Area and the width of the gate shift register in the second frame sub-area in the second direction, thereby reducing the area of the display area occupied by the gate shift register in the arc-shaped sub-area. Increasing the screen-to-body ratio of the array substrate is conducive to the realization of a narrow frame design.

Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

An array substrate, comprising: a base substrate having a display area and a frame area surrounding the display area;

The frame area includes: a first frame sub-area extending in a first direction, a second frame sub-area extending in a second direction, and connected between the first frame sub-area and the second frame sub-area The arc-shaped sub-area of, wherein the first frame sub-area and the second frame sub-area are arranged adjacently, and the first direction and the second direction are perpendicular to each other;

The array substrate includes a plurality of cascaded gate shift registers located in the frame area, and the width of at least one gate shift register located in the arc-shaped sub-region in the second direction is smaller than that located in the second direction. The width in the second direction of the gate shift register in the first frame sub-region and the second frame sub-region.
8. The array substrate of claim 1, wherein the gate shift registers in the arc-shaped sub-regions have the same size.
The array substrate of claim 1, wherein, in the arc-shaped sub-region, the width of the gate shift register far from the first frame sub-region in the second direction is smaller than that of the gate shift register near the first frame sub-region. The width of the gate shift register in the frame sub-region in the second direction.
3. The array substrate according to any one of claims 1 to 3, wherein the circuit connection structure of all the gate shift registers is the same;

The length of at least one gate shift register located in the arc-shaped sub-region in the first direction is greater than the gate shift located in the first frame sub-region and the second frame sub-region The length of the register in the first direction.
5. The array substrate of claim 4, wherein the gate shift register located in the first frame sub-region has a width in the second direction that is smaller than that of the gate in the second frame sub-region. The width of the pole shift register in the second direction.
5. The array substrate of claim 4, wherein the length of the gate shift register located in the first frame sub-region in the first direction is greater than the length of the gate shift register located in the second frame sub-region. The length of the gate shift register in the first direction.
8. The array substrate of claims 1-3, wherein the gate shift register located in the arc-shaped sub-area and all the gate shift registers located in the first frame sub-area and the second frame sub-area The circuit connection structure of the gate shift register is different;

The area occupied by each of the gate shift registers in the arc-shaped sub-region is smaller than the area occupied by each of the gate shift registers in the first frame sub-region and the second frame sub-region.
7. The array substrate according to any one of claims 1-7, wherein the frame area further comprises: a third frame sub-area, and the third frame sub-area extends along the second direction and is connected to the first frame. The two border sub-regions are set relative to each other;

The array substrate further includes a source drive circuit located in the third frame sub-region, and the source drive circuit is electrically connected to a plurality of data lines located in the display area.
7. The array substrate according to any one of claims 1-7, wherein the frame area further comprises: a fourth frame sub-area, and the fourth frame sub-area is arranged opposite to the first frame sub-area;

The fourth frame sub-region includes a plurality of the gate shift registers.
9. The array substrate of claim 9, wherein the display area comprises: a plurality of gate lines, the gate lines extending along the second direction;

The gate shift register in the first frame sub-region and the gate shift register in the fourth frame sub-region are electrically connected to the gate lines in different rows, respectively.
A display panel, comprising the array substrate according to any one of claims 1-10, and a plurality of sub-pixels located in the display area.