CN113544581A - Array substrate and display panel - Google Patents
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- CN113544581A CN113544581A CN202080000161.4A CN202080000161A CN113544581A CN 113544581 A CN113544581 A CN 113544581A CN 202080000161 A CN202080000161 A CN 202080000161A CN 113544581 A CN113544581 A CN 113544581A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present disclosure discloses an array substrate and a display panel, the array substrate includes: the display device comprises a substrate base plate, a display panel and a display panel, wherein the substrate base plate comprises a display area and a frame area surrounding the display area; the frame area includes: the frame structure comprises a first frame subregion extending along a first direction, a second frame subregion extending along a second direction and an arc subregion connected between the first frame subregion and the second frame subregion, wherein the first frame subregion and the second frame subregion are adjacently arranged, and the first direction is vertical to the second direction; the array substrate comprises a plurality of cascaded gate shift registers located in the frame area, and the width of at least one gate shift register located in the arc-shaped sub-area in the second direction is smaller than the width of the gate shift registers located in the first frame sub-area and the second frame sub-area in the second direction, so that the area of a display area occupied by the gate shift registers located in the arc-shaped sub-area is reduced, and the screen occupation ratio of the array substrate is increased.
Description
The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display panel.
In the related art, a display panel includes: the display device comprises a display area and a frame area surrounding the display area, wherein a grid driving circuit is arranged at least one side of the frame area so as to provide driving signals for each grid line in the display area.
Disclosure of Invention
In a first aspect, an embodiment of the present disclosure provides an array substrate, including: a substrate base having a display area and a bezel area surrounding the display area;
the bezel area includes: the frame structure comprises a first frame subregion extending along a first direction, a second frame subregion extending along a second direction and an arc subregion connected between the first frame subregion and the second frame subregion, wherein the first frame subregion and the second frame subregion are adjacently arranged, and the first direction is vertical to the second direction;
the array substrate comprises a plurality of cascaded gate shift registers located in the frame area, and the width of at least one gate shift register located in the arc-shaped sub-area in the second direction is smaller than the width of the gate shift registers located in the first frame sub-area and the second frame sub-area in the second direction.
In a possible implementation manner, in the array substrate provided by the embodiment of the disclosure, the sizes of the gate shift registers in the arc-shaped sub-area are the same.
In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, in the arc-shaped sub-region, a width of the gate shift register far away from the first frame sub-region in the second direction is smaller than a width of the gate shift register near the first frame sub-region in the second direction.
In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, circuit connection structures of all the gate shift registers are the same;
the length of at least one grid shift register in the arc-shaped sub-area in the first direction is larger than the length of the grid shift registers in the first frame sub-area and the second frame sub-area in the first direction.
In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, a width of the gate shift register located in the first frame sub-region in the second direction is smaller than a width of the gate shift register located in the second frame sub-region in the second direction.
In a possible implementation manner, in the array substrate provided in the embodiment of the present disclosure, a length of the gate shift register located in the first frame sub-region in the first direction is greater than a length of the gate shift register located in the second frame sub-region in the first direction.
In a possible implementation manner, in the array substrate provided in the embodiment of the present disclosure, the gate shift register located in the arc-shaped sub-region and the gate shift register located in the first frame sub-region and the second frame sub-region have different circuit connection structures;
the area occupied by each grid electrode shift register in the arc-shaped subarea is smaller than the area occupied by each grid electrode shift register in the first frame subarea and the second frame subarea.
In a possible implementation manner, in the array substrate provided in an embodiment of the present disclosure, the bezel region further includes: a third frame sub-region extending along the second direction and disposed opposite to the second frame sub-region;
the array substrate further comprises a source electrode driving circuit located in the third frame sub-area, and the source electrode driving circuit is electrically connected with the plurality of data wires located in the display area.
In a possible implementation manner, in the array substrate provided in an embodiment of the present disclosure, the bezel region further includes: a fourth frame subregion disposed opposite to the first frame subregion;
the fourth frame subregion includes a plurality of the gate shift registers.
In a possible implementation manner, in the array substrate provided in an embodiment of the present disclosure, the display area includes: a plurality of gate lines extending in the second direction;
the grid shift register in the first frame subregion and the grid shift register in the fourth frame subregion are respectively and electrically connected with different rows of grid lines.
In a second aspect, an embodiment of the present disclosure further provides a display panel, including the array substrate provided in any one of the first aspects, and a plurality of sub-pixels located in the display area.
Fig. 1 is a schematic structural view of an array substrate in the related art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a partially enlarged structure provided in an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a gate shift register in the first frame sub-region or the second frame sub-region according to an embodiment of the disclosure;
FIG. 5 is a schematic diagram of a gate shift register in an arc-shaped sub-region according to an embodiment of the present disclosure;
fig. 6a and 6b are schematic views of another partial enlarged structure provided in the embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
As shown in fig. 1, the array substrate in the related art includes a display region a0 and a frame region B0 surrounding the display region a0, where a plurality of cascaded gate shift registers S0 are disposed in the frame region B0, and respectively drive corresponding gate lines (not specifically shown in the figure) in the display region a 0. However, due to the design that the bezel region B0 has a chamfered region (region in the dashed line frame), when the gate shift register S0 is disposed at the chamfered region due to the limitation of the outer bezel shape of the bezel region B0, the gate shift register S0 occupies the area of the display region a0, so that the screen occupation ratio of the array substrate is reduced, and the narrow bezel is not favorable for implementation.
Based on the above problems of the related art array substrate, embodiments of the present disclosure provide an array substrate and a display panel. In order to make the purpose, technical solution and advantages of the present disclosure more clear, specific embodiments of an array substrate and a display panel provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It is to be understood that the preferred embodiments described below are for purposes of illustration and explanation only and are not intended to limit the present disclosure. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the present disclosure.
Specifically, embodiments of the present disclosure provide an array substrate, as shown in fig. 2 and 3, including: a substrate having a display area A and a bezel area B surrounding the display area A;
the frame region B includes: a first frame sub-region B1 extending along a first direction, a second frame sub-region B2 extending along a second direction, and an arc sub-region B3 connected between the first frame sub-region B1 and the second frame sub-region B2, wherein the first frame sub-region B1 is disposed adjacent to the second frame sub-region B2, and the first direction and the second direction are perpendicular to each other;
the array substrate comprises a plurality of cascaded gate shift registers S positioned in a frame region B, and the width W3 of at least one gate shift register S positioned in an arc-shaped sub-region B3 in the second direction is smaller than the width W1/W2 of the gate shift registers S positioned in a first frame sub-region B1 and a second frame sub-region B2 in the second direction.
In particular, in the array substrate provided by the embodiment of the present disclosure, by designing the size of the gate shift register of each sub-region in the arc-shaped sub-region, that is, making the width of the gate shift register in the arc-shaped sub-region in the second direction smaller than the width of the gate shift register in the first frame sub-region and the second frame sub-region in the second direction, the area of the display region occupied by the gate shift register in the arc-shaped sub-region is reduced, the screen occupation ratio of the array substrate can be increased, and the narrow frame design is facilitated.
It should be noted that, in the array substrate provided by the embodiment of the present disclosure, the length of the gate shift register in the first direction and the width of the gate shift register in the second direction refer to the length of the area occupied by the circuit structure portion of the gate shift register in the first direction and the width of the area occupied by the circuit structure portion of the gate shift register in the second direction. The gate shift register comprises a plurality of transistors and capacitors which are electrically connected, the shapes of the areas occupied by the transistors and the capacitors are approximately rectangular, when the size of the area occupied by the gate shift register in the arc-shaped sub-area is adjusted, the size can be realized by changing the positions and the shapes of the transistors and the capacitors on the substrate, wherein the connection relation between the transistors and the capacitors in the arc-shaped sub-area can not be changed, and the size of the area occupied by the gate shift register can be changed by changing the positions of the transistors and/or the shapes of the capacitors.
As shown in fig. 4, which is a schematic structural diagram of the gate shift register in the first frame sub-region or the second frame sub-region, it can be seen from fig. 4 that the plurality of transistors TFT are all located in the same row and are sequentially arranged along the second direction, and as can be seen from the schematic structural diagram of the gate shift register in the arc sub-region shown in fig. 5, the plurality of transistors TFT are respectively arranged in two rows in the second direction, so that the width of the area occupied by the transistors TFT in the gate shift register in the arc sub-region in the second direction can be reduced by this arrangement, and the length of the area in the first direction can be increased. In addition, the shape of the capacitor C in the gate shift register in the first frame subregion or the second frame subregion is also different from that of the capacitor C in the gate shift register in the arc subregion, and the capacitor C in the gate shift register in the first frame subregion or the second frame subregion is rectangular, so that the width of the gate shift register in the region in the second direction is increased; and the capacitance in the arc-shaped subarea is L-shaped, so that the width of the gate shift register in the area in the second direction is smaller. The width of the gate shift register in the arc-shaped subarea in the second direction can be reduced by changing the shape of the capacitor C in the gate shift register and the shape and the position of one or more transistors TFT, but the capacitance value and the driving capability of the transistor can be ensured to be unchanged.
Because the length of the gate shift registers in the arc-shaped sub-area in the first direction is larger, the number of the gate shift registers which can be accommodated in the first frame sub-area extending along the first direction is limited, and therefore, part of the gate shift registers can be prevented from being arranged in the second frame sub-area extending along the second direction and adjacent to the first frame sub-area.
It should be noted that the frame region may include a plurality of arc-shaped sub-regions, and the arc-shaped sub-regions may be at any top corner of the array substrate, where fig. 2 illustrates an arc-shaped sub-region where the gate shift register is located at an upper right corner, and of course, the gate shift register may also be located at arc-shaped sub-regions at other positions, which are within the protection scope of the present disclosure. On one hand, the arc-shaped sub-region is located at a position of which top corner of the array substrate, and depends on a frame region of which side the gate shift register is located, for example, the arc-shaped sub-region is located at the right side of the display region, the arc-shaped sub-region may be located at the upper right corner and/or the lower right corner of the array substrate, which is also related to a position where the source driving circuit is disposed and an occupied region, and if the frame at the lower side of the array substrate is provided with the source driving circuit, and the source driving circuit occupies the position at the lower right corner, the arc-shaped sub-region is located at the position at the upper right corner of the array substrate. Namely, the positions of the arc-shaped sub-areas need to be designed by comprehensively considering the layout of other circuits in the array substrate. When the source driving circuit is located on the lower frame of the array substrate, the arc-shaped sub-region is preferably disposed at the upper right corner and/or the upper left corner, and certainly, when the source driving circuit does not occupy the lower right corner and the lower left corner region, the arc-shaped sub-region may also be disposed at the lower right corner and/or the lower left corner, which may be selected according to actual situations, and is not specifically limited herein.
The width of the gate shift register in the arc-shaped sub-area in the second direction is reduced by about 69.85 (about 60% -80% of the size of a single pixel in the display area) compared with the width of the gate shift register in the first frame sub-area and/or the second frame sub-area in the second direction, and the length of the gate shift register in the arc-shaped sub-area in the first direction is increased by about 83.3 frames (about 80% -90% of the size of the single pixel) compared with the length of the gate shift register in the first frame sub-area and/or the second frame sub-area in the first direction.
Optionally, in the array substrate provided in the embodiment of the present disclosure, the sizes of the gate shift registers in the arc-shaped sub-regions may be the same or different. When the sizes of the gate shift registers in the arc-shaped sub-area are different, the width of the gate shift register far away from the first frame sub-area in the second direction in the arc-shaped sub-area can be smaller than the width of the gate shift register near the first frame sub-area in the second direction. The arrangement is beneficial to the transition of the boundary of the arc-shaped subarea, and the occupied area of the display area is reduced.
Specifically, in the array substrate provided by the embodiment of the present disclosure, the width of each gate shift register in the arc-shaped sub-area may gradually change with the change of the located position, and certainly, the widths of two or more gate shift registers in the second direction at adjacent positions may be set to be the same according to the located position of each gate shift register. As shown in fig. 6a, in the direction in which the first frame sub-region points to the second frame sub-region within the arc-shaped sub-region, the array substrate includes gate shift registers S1, S2, S3, S4, S5 and S6, and the width of each gate shift register in the second direction is sequentially decreased, i.e., W31 > W32 > W33 > W34 > W35 > W36. As shown in fig. 6b, the widths of the gate shift register S1 and the gate shift register S2 in the second direction may be set as W31, the widths of the gate shift register S3 and the gate shift register S4 in the second direction are set as W32, and the widths of the gate shift register S5 and the gate shift register S6 in the second direction are set as W33, where W31 > W32 > W33. Of course, how to set each gate shift register in the arc-shaped sub-area is specifically selected according to the actual design, and is not limited in detail here.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 3, circuit connection structures of all the gate shift registers S are the same;
the length L3 in the first direction of at least one gate shift register S located within the arc-shaped sub-region B3 is greater than the length L1 in the first direction of the gate shift register S located in the first frame sub-region B1 and the length L2 in the first direction of the gate shift register S of the second region B2.
Specifically, in the array substrate provided by the embodiment of the present disclosure, when the circuit connection structures of all the gate shift registers are the same, the areas occupied by the gate shift registers are the same, and the lengths of the gate shift registers in the first direction and the widths of the gate shift registers in the second direction in each sub-region can be adjusted by adjusting the device layout in each gate shift register. For example, when the width of the gate shift register in the arc sub-region in the second direction is smaller than the width of the gate shift register in the first and second side frame sub-regions, the length of the gate shift register in the first direction in the arc sub-region needs to be greater than the length of the gate shift register in the first direction in the first and second side frame sub-regions, so as to ensure reasonable layout of the gate shift registers.
The fact that the circuit connection structures of the gate shift registers are the same means that the electrical connection relations between the transistors and the capacitors included in the gate shift registers are the same, and the shapes and the positions of the transistors and the capacitors can be different, that is, the sizes of the gate shift registers in the first direction and the second direction in each sub-region can be changed by designing the positions and the shapes of the transistors and the capacitors in each sub-region.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 3, a width W1 of the gate shift register S in the first frame sub-region B1 in the second direction is smaller than a width W2 of the gate shift register S in the second frame sub-region B2 in the second direction.
In particular, in the array substrate provided by the embodiment of the disclosure, since the first frame sub-region extends along the first direction, in order to realize a narrow frame setting, the width of the first frame sub-region in the second direction is as small as possible, and therefore, a narrow frame design along the first frame sub-region can be realized by making the width of the gate shift register located in the first frame sub-region in the second direction smaller than the width of the gate shift register in the second frame sub-region in the second direction.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 3, a length L1 of the gate shift register S located in the first frame sub-region B1 in the first direction is greater than a length L2 of the gate shift register S located in the second frame sub-region B2 in the first direction.
Specifically, in the array substrate provided by the embodiment of the present disclosure, since the second frame sub-region extends along the second direction, in order to implement a narrow frame setting, the width of the second frame sub-region in the first direction is as small as possible, and therefore, the length of the gate shift register located in the first frame sub-region in the first direction may be larger than the length of the gate shift register located in the second frame sub-region in the first direction, so as to implement a narrow frame design along the second frame sub-region.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 3, the gate shift register S located in the arc sub-region B3 has a different circuit connection structure from the gate shift register S located in the first frame sub-region B1 and the second frame sub-region B2;
the area occupied by the gate shift registers S in the arc-shaped sub-region B3 is smaller than the area occupied by the gate shift registers S in the first frame sub-region B1 and the second frame sub-region B2.
Specifically, in the array substrate provided in the embodiment of the present disclosure, the circuit connection structures of the gate shift register located in the arc-shaped sub-region and the gate shift register located in the first frame sub-region and the second frame sub-region may also be different, and the area occupied by the gate shift register in the arc-shaped sub-region is reduced by designing the connection structure of each device in the gate region circuit in each sub-region, so that the width of the gate shift register located in the arc-shaped sub-region in the second direction is reduced, and the area occupied by the gate shift register in the display region is reduced.
The different circuit connection structures of the gate shift registers mean that the electrical connection relationships and/or the number of the transistors and the capacitors included in the gate shift registers may be different. For example, in order to reduce the area occupied by the gate shift register in the arc-shaped sub-area, the gate shift register with a smaller number of transistors may be selected and used in the arc-shaped sub-area, and the gate shift register with a larger number of transistors may be selected and used in the other sub-area.
It should be noted that the specific circuit structures of the gate shift registers in each sub-region may be different, but based on the existence of the cascade relationship between the gate shift registers with different structures, it is required to ensure that the operating time sequence of the gate shift registers with different structures meets the requirement of the cascade relationship, and the gate shift registers may be specifically designed according to actual needs, and is not specifically limited herein.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 7, the frame region further includes: a third frame sub-region B4, the third frame sub-region B4 extending in the second direction and being disposed opposite to the second frame sub-region B2;
the array substrate further includes a source driving circuit D in the third frame sub-region B4, and the source driving circuit D is electrically connected to a plurality of data lines (not specifically shown) in the display region a.
Specifically, in the array substrate provided by the embodiment of the disclosure, the second frame sub-region and the source driving circuit may be disposed at opposite sides, so that the arrangement of each part of the circuits is more reasonable. If the source driving circuit is disposed in the third frame sub-region, wherein the source driving circuit already occupies a part of the edge width region, if the arc sub-region is disposed adjacent to the third frame sub-region, the wiring difficulty may be increased, the signal transmission reliability of each circuit may be reduced, the short circuit may occur easily, and the normal display may be affected. Therefore, the second frame subregion and the source driving circuit are arranged on the opposite side edges, so that the circuits can be more reasonably arranged, and the signal transmission reliability of the circuits is improved.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 8, the frame region B further includes: a fourth frame subregion B5, the fourth frame subregion B5 being disposed opposite to the first frame subregion B1;
the fourth frame sub-region B5 includes a plurality of gate shift registers S.
Specifically, in the array substrate provided in the embodiment of the present disclosure, in addition to the gate shift registers arranged in the second frame sub-region, when the number of the gate shift registers is large, the gate shift registers may also be arranged in the fourth frame region, that is, the gate shift registers are arranged at both the two side frames extending in the first direction, so that the high-pixel display panel can be driven.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 8, the display area a includes: a plurality of gate lines G extending in a second direction;
the gate shift register S in the first frame sub-region B1 and the gate shift register S in the fourth frame sub-region B5 are electrically connected to different rows of gate lines G, respectively.
In particular, in the array substrate provided by the embodiment of the present disclosure, the gate shift registers respectively disposed in the first frame sub-region and the fourth frame sub-region can drive different gate lines, so that more rows of pixels can be driven, and the array substrate is suitable for driving a high-pixel display panel. The gate shift registers respectively located in the first frame sub-region and the fourth frame sub-region may also drive the gate lines located in the same row, that is, a double-side driving manner is adopted. The specific value can be selected according to actual needs, and is not particularly limited herein.
Based on the same inventive concept, embodiments of the present disclosure further provide a display panel, where the display panel includes the array substrate provided in any of the above embodiments, and a plurality of sub-pixels located in a display area.
The array substrate has all the advantages of the array substrate provided by the above embodiments, and therefore, the embodiments of the array substrate can be referred to for implementation, and details are not described herein.
Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, which includes the display panel provided by the above embodiment, and a protective cover plate located on one side of the light emitting surface of the display panel.
Wherein, the display device can be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
The embodiment of the present disclosure provides an array substrate and a display panel, the array substrate including: the display device comprises a substrate base plate, a display panel and a display panel, wherein the substrate base plate comprises a display area and a frame area surrounding the display area; the frame area includes: the frame structure comprises a first frame subregion extending along a first direction, a second frame subregion extending along a second direction and an arc subregion connected between the first frame subregion and the second frame subregion, wherein the first frame subregion and the second frame subregion are adjacently arranged, and the first direction is vertical to the second direction; the array substrate comprises a plurality of cascaded gate shift registers located in a frame area, and the width of at least one gate shift register located in an arc-shaped sub-area in the second direction is smaller than the width of the gate shift registers located in a first frame sub-area and a second frame sub-area in the second direction. By designing the size of the gate shift register in the arc-shaped sub-area, the width of the gate shift register in the arc-shaped sub-area in the second direction is smaller than the width of the gate shift register in the first frame sub-area and the second frame sub-area in the second direction, so that the area of a display area occupied by the gate shift register in the arc-shaped sub-area is reduced, the screen occupation ratio of the array substrate can be increased, and the narrow-frame design is facilitated.
It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations as well.
Claims (11)
- An array substrate, comprising: a substrate base having a display area and a bezel area surrounding the display area;the bezel area includes: the frame structure comprises a first frame subregion extending along a first direction, a second frame subregion extending along a second direction and an arc subregion connected between the first frame subregion and the second frame subregion, wherein the first frame subregion and the second frame subregion are adjacently arranged, and the first direction is vertical to the second direction;the array substrate comprises a plurality of cascaded gate shift registers located in the frame area, and the width of at least one gate shift register located in the arc-shaped sub-area in the second direction is smaller than the width of the gate shift registers located in the first frame sub-area and the second frame sub-area in the second direction.
- The array substrate of claim 1, wherein the gate shift registers in the arc-shaped sub-area are the same size.
- The array substrate of claim 1, wherein within the arc-shaped sub-region, the width of the gate shift register in the second direction away from the first frame sub-region is smaller than the width of the gate shift register in the second direction close to the first frame sub-region.
- The array substrate of any one of claims 1 to 3, wherein the circuit connection structures of all the gate shift registers are the same;the length of at least one grid shift register in the arc-shaped sub-area in the first direction is larger than the length of the grid shift registers in the first frame sub-area and the second frame sub-area in the first direction.
- The array substrate of claim 4, wherein the width of the gate shift register in the first bezel sub-area in the second direction is smaller than the width of the gate shift register in the second bezel sub-area in the second direction.
- The array substrate of claim 4, wherein the length of the gate shift register in the first direction in the first bezel sub-area is greater than the length of the gate shift register in the first direction in the second bezel sub-area.
- The array substrate of claims 1-3, wherein the gate shift register in the arc sub-region has a different circuit connection structure than the gate shift register in the first and second bezel sub-regions;the area occupied by each grid electrode shift register in the arc-shaped subarea is smaller than the area occupied by each grid electrode shift register in the first frame subarea and the second frame subarea.
- The array substrate of any one of claims 1-7, wherein the border region further comprises: a third frame sub-region extending along the second direction and disposed opposite to the second frame sub-region;the array substrate further comprises a source electrode driving circuit located in the third frame sub-area, and the source electrode driving circuit is electrically connected with the plurality of data wires located in the display area.
- The array substrate of any one of claims 1-7, wherein the border region further comprises: a fourth frame subregion disposed opposite to the first frame subregion;the fourth frame subregion includes a plurality of the gate shift registers.
- The array substrate of claim 9, wherein the display area comprises: a plurality of gate lines extending in the second direction;the grid shift register in the first frame subregion and the grid shift register in the fourth frame subregion are respectively and electrically connected with different rows of grid lines.
- A display panel comprising the array substrate of any one of claims 1 to 10 and a plurality of sub-pixels located in the display area.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/076232 WO2021164010A1 (en) | 2020-02-21 | 2020-02-21 | Array substrate and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN113544581A true CN113544581A (en) | 2021-10-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202080000161.4A Pending CN113544581A (en) | 2020-02-21 | 2020-02-21 | Array substrate and display panel |
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| Country | Link |
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| CN (1) | CN113544581A (en) |
| WO (1) | WO2021164010A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105469764A (en) * | 2015-12-31 | 2016-04-06 | 上海天马微电子有限公司 | Array substrate, liquid crystal display panel and electronic equipment |
| CN107203080A (en) * | 2017-07-27 | 2017-09-26 | 厦门天马微电子有限公司 | A kind of array base palte and display panel |
| CN107644614A (en) * | 2017-10-26 | 2018-01-30 | 上海中航光电子有限公司 | A kind of array base palte, display panel and display device |
| CN109192121A (en) * | 2018-09-28 | 2019-01-11 | 武汉天马微电子有限公司 | Display panel and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6533065B2 (en) * | 2015-02-12 | 2019-06-19 | 株式会社ジャパンディスプレイ | Display device |
| CN106504696B (en) * | 2016-12-29 | 2018-12-14 | 上海天马有机发光显示技术有限公司 | Display panel and display device comprising it |
| CN107561806B (en) * | 2017-09-29 | 2020-07-03 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN107643638B (en) * | 2017-10-18 | 2020-05-15 | 厦门天马微电子有限公司 | Array substrate and display panel |
-
2020
- 2020-02-21 CN CN202080000161.4A patent/CN113544581A/en active Pending
- 2020-02-21 WO PCT/CN2020/076232 patent/WO2021164010A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105469764A (en) * | 2015-12-31 | 2016-04-06 | 上海天马微电子有限公司 | Array substrate, liquid crystal display panel and electronic equipment |
| CN107203080A (en) * | 2017-07-27 | 2017-09-26 | 厦门天马微电子有限公司 | A kind of array base palte and display panel |
| CN107644614A (en) * | 2017-10-26 | 2018-01-30 | 上海中航光电子有限公司 | A kind of array base palte, display panel and display device |
| CN109192121A (en) * | 2018-09-28 | 2019-01-11 | 武汉天马微电子有限公司 | Display panel and display device |
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| WO2021164010A1 (en) | 2021-08-26 |
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