WO2021163927A1 - 图像传感器和电子装置 - Google Patents

图像传感器和电子装置 Download PDF

Info

Publication number
WO2021163927A1
WO2021163927A1 PCT/CN2020/075876 CN2020075876W WO2021163927A1 WO 2021163927 A1 WO2021163927 A1 WO 2021163927A1 CN 2020075876 W CN2020075876 W CN 2020075876W WO 2021163927 A1 WO2021163927 A1 WO 2021163927A1
Authority
WO
WIPO (PCT)
Prior art keywords
image sensor
pixel
heat
wafer
heat resistance
Prior art date
Application number
PCT/CN2020/075876
Other languages
English (en)
French (fr)
Inventor
姚国峰
沈健
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN202080002262.5A priority Critical patent/CN112166499A/zh
Priority to PCT/CN2020/075876 priority patent/WO2021163927A1/zh
Publication of WO2021163927A1 publication Critical patent/WO2021163927A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16L—PIPES; JOINTS OR FITTINGS FOR PIPES; SUPPORTS FOR PIPES, CABLES OR PROTECTIVE TUBING; MEANS FOR THERMAL INSULATION IN GENERAL
    • F16L59/00—Thermal insulation in general
    • F16L59/02—Shape or form of insulating materials, with or without coverings integral with the insulating materials
    • F16L59/029—Shape or form of insulating materials, with or without coverings integral with the insulating materials layered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings

Definitions

  • This application relates to the field of semiconductor technology, and in particular to an image sensor and an electronic device.
  • Image sensors such as Complementary Metal Oxide Semiconductor (CMOS), are sensors that can convert optical images into digital signals, and are widely used in mobile terminals, digital products, security monitoring and other fields.
  • CMOS Complementary Metal Oxide Semiconductor
  • FIG. 1 shows a schematic diagram of a cross-sectional structure of a stacked image sensor.
  • the image sensor includes a logic chip 20 and a pixel chip 10 stacked on the logic chip 20.
  • a pixel array 12 is provided on the substrate of the pixel wafer 10 to form a pixel area for converting incident light into electrical signals.
  • the digital circuit and the analog circuit constitute multiple functional modules of the circuit area, and are responsible for providing control signals to the pixel area. And processing the output signal of the pixel area.
  • the pixel wafer 10 and the logic wafer 20 are integrated together through a bonding process.
  • Dark current refers to the current generated by the photosensitive unit of the pixel array without any light.
  • the dark current of the image sensor chip needs to be controlled as small as possible, and the size of the dark current depends on temperature. Very significant, as the temperature increases, the dark current increases exponentially. With the continuous increase in the number of pixels, the processing load of the logic chip has also increased correspondingly, resulting in serious heat generation problems in the logic chip.
  • the present application provides an image sensor and an electronic device to improve the characteristics of dark current and help improve the imaging quality of the image sensor.
  • the first aspect of the present application provides an image sensor, which includes a pixel wafer and a logic wafer.
  • a side of the pixel wafer facing the light-sensing direction is provided with a pixel array for light-sensing, and the logic wafer is stacked on the pixel wafer.
  • the logic chip is used to transmit signals with the pixel array;
  • the pixel wafer has a first substrate, the logic wafer has a second substrate, and a heat resistance component is provided between the first substrate and the second substrate.
  • the heat resistance component includes a heat uniformity element and a heat resistance element, wherein the heat uniformity element is arranged on a side of the heat resistance assembly close to the pixel chip, The heat resistance element is arranged on a side of the uniform heat element away from the photosensitive direction, and is arranged opposite to the uniform heat element.
  • the heat resistance element is provided on a side of the pixel array away from the light-sensing direction, and is used to block the conduction of heat in the logic chip to the pixel array;
  • the uniform heat element is arranged on a side of the pixel array away from the light-sensing direction, and is used to disperse the heat from the logic chip.
  • the heat resistance component is disposed on a side of the pixel chip away from the first substrate.
  • the heat uniformity element includes at least one heat conduction layer
  • the heat resistance element includes at least one heat resistance layer
  • the thermally conductive layer is a layered structure formed by using a thermally conductive material
  • the heat-resistant layer is a layered structure formed by using a thermally insulating material
  • the thermal conductivity of the thermally conductive material at room temperature is greater than 100W/(mK), and the thermal conductivity of the thermally insulating material at room temperature is less than 1W/(mK), wherein, The room temperature is 300K.
  • the heat resistance component is arranged opposite to the pixel array, and the area of the heat resistance component is greater than or equal to the area of the pixel array.
  • the pixel wafer is stacked on a side of the logic wafer facing the photosensitive direction through a bonding process.
  • the bonding process is fusion bonding or hybrid bonding.
  • the heat resistance component is located inside at least one of the pixel chip and the logic chip.
  • a first metal interconnection structure is provided in the pixel chip, a second metal interconnection structure is provided in the logic chip, and the heat resistance component is located in the first metal. Between the interconnection structure and the second metal interconnection structure.
  • the pixel chip is also electrically connected to the logic chip through a first conductive interconnect structure.
  • the first conductive interconnection structure includes an interconnection structure and a conductive member, and the interconnection structure is connected to the electrical connection unit in the pixel chip and the logic chip, respectively,
  • the conductive member is connected between the two interconnection structures, and at least part of the conductive member is located on the surface of the first substrate.
  • the interconnection structure is a first through hole filled with a conductive material and communicating with the first metal interconnection structure or the second metal interconnection structure;
  • the conductive member is a metal member.
  • the heat resistance component is located in the pixel chip, or
  • the heat resistance component is located in the logic chip.
  • a first metal interconnection structure is provided in the pixel chip, a second metal interconnection structure is provided in the logic chip, and the heat resistance component is located in the first metal.
  • the heat resistance component is located in the second metal interconnection structure.
  • two metal interconnection layers adjacent to the heat resistance component in the first metal interconnection structure are electrically connected by a second conductive interconnection structure
  • two metal interconnection layers adjacent to the heat resistance component in the second metal interconnection structure are electrically connected through the second conductive interconnection structure.
  • the second conductive interconnection structure is located on the circumferential outer side of the heat resistance component.
  • the second conductive interconnection structure is a second through hole filled with conductive material, wherein the second through hole is connected between the two metal interconnection layers .
  • the pixel wafer is electrically connected to the logic wafer through a conductive layer, wherein the conductive layer is located on the bonding interface between the pixel wafer and the logic wafer.
  • the uniform heat element is stacked on a side of the heat resistance element facing the photosensitive direction
  • the uniform heat element and the heat resistance element are arranged at intervals.
  • the uniform heat element is a suspended structure, or
  • the uniform heat element is electrically connected to the pad on the pixel wafer through an interlayer interconnection structure.
  • the interlayer interconnection structure is a through hole filled with a conductive material and connected between the pad, the first metal interconnection structure, and the uniform heating element .
  • the uniform heat element is provided with an array of opening structures to relieve stress.
  • the pixel array is formed on the first substrate and arranged close to the surface of the first substrate.
  • the image sensor is a complementary metal oxide semiconductor CMOS image sensor.
  • a second aspect of the present application provides an electronic device, which includes the image sensor as described in any one of the above.
  • the heat in the logic chip can be blocked, the heat conducted to the pixel array can be reduced, and the dark current can be reduced. size.
  • the heat resistance structure can also have a certain degree of uniform heating effect on the heat under the pixel array to a certain extent, which can improve the uniformity of the heat and dark current distribution under the pixel array to further enhance the image The imaging quality of the sensor. Therefore, the present application can improve the characteristics of the dark current, which helps to improve the imaging quality of the image sensor.
  • FIG. 1 is a schematic structural diagram of a stacked image sensor in the prior art
  • Figure 2 is a schematic diagram of a logic chip in the prior art
  • FIG. 3 is a schematic diagram of the structure of an image sensor according to the first embodiment
  • FIG. 4 is a schematic top view of the image sensor provided by the first embodiment
  • FIG. 5 is a schematic structural diagram of another image sensor provided by the first embodiment
  • FIG. 6 is a schematic structural diagram of yet another image sensor provided by the first embodiment
  • FIG. 7 is a schematic structural diagram of an image sensor provided by the second embodiment.
  • FIG. 8 is a schematic structural diagram of a uniform heat element provided in the third embodiment.
  • FIG. 9 is a schematic structural diagram of another uniform heating element provided in the third embodiment.
  • FIG. 10 is a schematic structural diagram of an image sensor provided by the fourth embodiment.
  • 10-pixel wafer 11-first substrate; 12-pixel array; 121-photosensitive unit; 13-color filter; 14-microlens; 15-first metal interconnection structure; 151, 221-metal interconnection layer 16-first dielectric layer; 17-pad; 18-first electrical connection unit; 20-logic chip; 21-second substrate; 22-second metal interconnection structure; 23-second dielectric layer; 24 -Second electrical connection unit; 30-Heat resistance component; 31-Heat uniforming element; 311-Open-hole structure; 32-Heat resistance element; 40-Bonding interface; 50-Conductive layer; 60-First conductive interconnection structure 61-interconnect structure; 62-conductive member; 70-second conductive interconnection structure; 80-interlayer interconnection structure; 90-conductive material.
  • the prior art shown in FIG. 1 is a schematic cross-sectional view of a typical stacked image sensor.
  • the substrate of the logic chip 20 ie, the second substrate 21 of the present application
  • the digital circuit and the analog circuit constitute a circuit
  • Multiple functional modules mainly include analog-to-digital conversion modules, logic modules, input/output modules, phase-locked loop modules, mobile industry processor interface modules, dynamic password modules, register modules and other functional modules.
  • a plurality of functional modules constitute the circuit area of the logic chip 20, which is responsible for providing control signals to the pixel area (not shown in the figure) of the pixel chip 10 and processing the output signal of the pixel area (that is, the electrical signal converted by the pixel area). ) To get the image signal.
  • the dark current refers to the current generated by the light-sensing unit 121 of the pixel array 12 without any light.
  • the dark current has an effect on the imaging quality of the image sensor mainly in the following two aspects:
  • the dark current will push up the average value of the entire image, especially at high temperatures, the dark current will increase significantly, and the temperature dependence of the dark current is very significant, that is, as the temperature increases, the dark current increases exponentially , Which reduces the dynamic range of the image;
  • the non-uniformity of dark current is an important source of fixed pattern noise in the image sensor, which makes the permeability of the image sensor worse.
  • the dark current of the photosensitive unit 121 of the pixel array 12 can be reduced in the manufacturing process and the uniformity can be improved, it is still necessary to eliminate or suppress the dark current noise in the post image processing to improve the image quality.
  • the dark current of the image sensor chip needs to be controlled as small as possible.
  • the processing load of the logic chip 20 is correspondingly increased, resulting in a serious heat generation problem in the logic chip 20.
  • the heat on the logic chip 20 will be conducted to the pixel chip 10, resulting in a large increase in dark current, thereby affecting the imaging quality of the image sensor.
  • different areas of the logic chip 20 also have the problem of uneven heating. For example, the area opposite to the logic module and the phase-locked loop module in the circuit area generates relatively large heat, while other areas in the circuit area generate relatively large amounts of heat. The heat is relatively small, which in turn leads to non-uniform distribution of temperature and dark current in the pixel area, and ultimately affects the image quality.
  • the embodiments of the present application improve an image sensor and an electronic device to improve the characteristics of dark current, which helps to improve the imaging quality of the image sensor.
  • the image sensor in the embodiments of the present application can be applied to smart phones, cameras, tablet computers, and other mobile terminals or fixed terminals with imaging functions.
  • the electronic devices in the embodiments of the present application may be smart phones, cameras, tablet computers, and other mobile terminals or fixed terminals with imaging functions. Therefore, in this embodiment, the application scenario of the image sensor is not further limited.
  • FIG. 3 is a schematic diagram of the structure of an image sensor provided in the first embodiment
  • FIG. 4 is a schematic top view of the image sensor provided in the first embodiment
  • FIG. 5 is a schematic diagram of another image sensor provided in the first embodiment
  • FIG. 6 is a schematic structural diagram of another image sensor provided by the first embodiment.
  • the image sensor of the embodiment of the present application includes a pixel chip 10 and a logic chip 20.
  • the pixel chip 10 is provided with a pixel array 12 for light-sensing on a side facing the light-sensing direction, and the logic chip 20 is stacked on On the side of the pixel chip 10 facing away from the light-sensing direction, the logic chip 20 is used to transmit signals with the pixel array 10.
  • the logic chip 20 may provide control signals to the pixel array 12 in the pixel chip 10 and process the signals output from the pixel array 12 to form image information.
  • the pixel wafer 10 has a first substrate 11, the logic wafer 20 has a second substrate 21, and a heat resistance component 30 is provided between the first substrate 11 and the second substrate 21.
  • the pixel wafer 10 is stacked on the logic wafer 20 to reduce the space occupied by the image sensor, which can make the structure of the image sensor more compact.
  • the image sensor in this embodiment is a stacked image sensor.
  • the image sensor in this embodiment may be a stacked CMOS image sensor or other stacked image sensors, that is, in this embodiment, the image sensor includes but is not limited to a stacked CMOS image sensor.
  • the pixel array 12 mainly includes an array structure composed of a large number of photosensitive units 121 and transistors (not marked in the figure), wherein the transistors are arranged in the pixel unit (a plurality of pixel units constitute one In the pixel array 12), the pixel array 12 is used to convert the incident light illuminating the pixel array 12 into electrical signals, which are transmitted to the logic chip 20, and processed by multiple functional modules in the circuit area of the logic chip 20 to form an image information.
  • the photosensitive unit 121 may be a photodiode or other devices capable of converting incident light into electrical signals.
  • each photosensitive unit 121 is provided with a color filter 13 and microlenses (microlenses) 14, wherein the color filter 13 and the microlens 14 They are sequentially arranged on the light incident surface (not labeled in the figure) of the photosensitive unit 121, so that the color filter 13 is arranged between the photosensitive unit 121 and the microlens 14, so that the incident light enters from above each microlens 14, While color recognition can be performed by the color filter 13 above the photosensitive unit 121, the amount of incoming light can be increased through the converging effect of the microlens 14, so as to increase the light utilization rate of the incident light, and output a higher-quality color image.
  • the arrangement of the color filter 13 and the microlens 14 can refer to the arrangement of the CMOS image sensor in the prior art, which will not be further elaborated in this embodiment.
  • micro lens 14 refers to a micro lens, and generally refers to a lens with a diameter of micrometers or even nanometers.
  • the pixel array 12 may be arranged inside the first substrate 11 and close to the surface of the first substrate 11 to improve the light utilization rate of incident light.
  • the heat resistance component 30 is provided between the first substrate 11 and the second substrate 21, which can block the heat in the logic chip 20 and reduce the conduction to the pixel array 12. The heat of the image sensor, thereby reducing the size of the dark current, improving the characteristics of the dark current pair, and improving the imaging quality of the image sensor.
  • the heat resistance component 30 conducts heat resistance to the pixel array 12, since the heat resistance component 30 has a certain coverage area, it can also disperse the heat under the pixel array 12 to a certain extent, and achieve a certain uniform heat. The effect can relatively improve the uniformity of heat and dark current distribution under the pixel array, and further help to improve the imaging quality of the image sensor.
  • the heat resistance component 30 may be a split structure or an integrated structure.
  • the structure of the heat resistance component 30 is not further limited.
  • the first substrate 11 may be a silicon substrate, an indium gallium arsenide substrate or other substrates that can form the pixel wafer 10, that is, the first substrate 11 includes but is not limited to a silicon substrate.
  • the second substrate 21 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or other substrates that can form the logic wafer 20, that is, in this embodiment, the second substrate 21 includes but is not limited to a silicon substrate.
  • SOI silicon-on-insulator
  • the present application by disposing the heat resistance component 30 between the first substrate 11 and the second substrate 21, the heat in the logic chip 20 can be blocked, the heat conducted to the pixel array 12 can be reduced, and the dark current can be reduced. At the same time, the uniformity of heat and dark current distribution under the pixel array 12 can be improved to further improve the imaging quality of the image sensor. Therefore, the present application can improve the characteristics of the dark current, which helps to improve the imaging quality of the image sensor.
  • the heat resistance assembly 30 includes a heat uniformity member 31 and a heat resistance member 32, and the uniformity heat member 31 is arranged on a side of the heat resistance assembly 30 close to the pixel chip 10.
  • the heat resistance element 32 is arranged on the side of the uniform heat element 31 away from the light-sensing direction, and is arranged opposite to the uniform heat element 31, so as to be as close as possible.
  • the temperature of the pixel chip 10 is reduced to improve the characteristics of the dark current, such as reducing the size of the dark current.
  • the uniform heat element 31 is arranged opposite to the heat resist 32, and the uniform heat element 31 is arranged on the side of the heat resist assembly 30 close to the pixel chip 10, and the heat resist 32 is opposite to the heat uniform element 31.
  • the setting can disperse the heat conducted to the pixel area and improve the consistency of temperature and dark current in the pixel area.
  • the heat resistance element 32 is provided on the side of the pixel array 10 away from the light-sensing direction to block the conduction of heat in the logic chip to the pixel array;
  • the heat-dissipating element 31 is provided on the side of the pixel array 12 away from the light-sensing direction for Dispersing the heat from the logic chip 10 can make the heat distribution under the pixel array 12 as uniform as possible, thereby improving the uniformity of the temperature under the pixel array 12, thereby increasing the uniformity of the dark current, so that the heat under the pixel array 12 The temperature and dark current are evenly distributed, thereby improving the characteristics of the dark current to improve the imaging quality of the image sensor.
  • the uniform heating element 31 when the uniform heating element 31 is arranged on the side of the pixel array 12 away from the light-sensing direction, the uniform heating element 31 can be arranged directly below the pixel array 12, or the uniform heating element 31 can also be arranged eccentrically with respect to the pixel array 12 In this embodiment, the relative position of the heat uniforming element 31 and the pixel array 12 is not further limited.
  • the intensity of the light signal received by the photosensitive unit 121 is greater than or equal to its sensing threshold, a photocurrent is generated.
  • the photocurrent and the dark current are difficult to distinguish, so the intensity of the light signal received by the photosensitive unit 121 is determined based on the photocurrent and the dark current. Therefore, in this embodiment, the accuracy of the image sensor can be improved while reducing the dark current through the thermal resistance component 30.
  • the heat resistance component 30 is arranged on the side of the pixel chip 10 away from the first substrate 11, so that the heat resistance component 30 can achieve better heat insulation and uniform heat effect on the pixel array 12 to improve the dark current.
  • the heat resistance component 30 is located on the side of the pixel wafer 10 away from the first substrate 11. It does not only mean that the heat resistance component 30 is located on the side of the boundary of the pixel wafer 10. The heat resistance component 30 It may also be located inside the pixel chip 10 or the logic chip 20.
  • the heat resistance element 32 when the heat resistance component 30 is arranged on the side of the pixel wafer 10 away from the first substrate 11, the heat resistance element 32 can be arranged close to the second substrate 21 for blocking the logic wafer 20.
  • the heat inside is conducted to the pixel array 12.
  • the heat resistance element 32 may be arranged close to the second substrate 21 and cover the side of the logic chip 20 facing the light-sensing direction, so as to shield the heat generated by active devices (such as transistors) when the logic chip 20 is working, and hinder the The heat generated by the source device is conducted to the pixel array 12.
  • the uniform heat element 31 may include at least one heat conduction layer, that is, the uniform heat element 31 may be composed of one heat conduction layer, and the heat uniform element 31 may also be composed of multiple heat conduction layers.
  • the heat resistance element 32 may include at least one heat resistance layer, that is, the heat resistance element 32 may be composed of one heat resistance layer, and the heat resistance element 32 may also be composed of multiple heat resistance layers.
  • the number of layers of the heat resistance layer and the heat conduction layer in the heat resistance component 30 can be adjusted as required to achieve a better heat insulation effect. In this embodiment, the number of layers of the uniform heat element 31 and the heat resistance element 32 is not limited.
  • the thermally conductive layer may be a layered structure formed by using a thermally conductive material
  • the heat-resistant layer may be a layered structure formed by using a thermally insulating material
  • the thermal conductive material can be a thermal conductive material with a thermal conductivity greater than 100 W/(m.K) at room temperature, such as copper, aluminum, or graphene.
  • the thermal insulation material can be a thermal insulation material with a thermal conductivity of less than 1W/(m.K) at room temperature, such as a low dielectric constant material or polyimide (PI). It should be noted that the above room temperature can be understood as 300K or 25°C.
  • the area of the heat uniformity element 31 may be greater than the area of the heat resistance element 32, or the area of the heat uniformity element 31 may be equal to the area of the heat resistance element 32.
  • the area of the heat resistance element 32 and the area of the uniform heat element 31 should be larger than the area of the pixel array 12 to improve the uniformity of temperature and dark current under the pixel array 12.
  • the area size of the uniform heat element 31 and the heat resistance element 32 in the heat resistance assembly 30 is not further limited.
  • the pixel wafer 10 may be stacked on the side of the logic wafer 20 facing the photosensitive direction through a bonding process. It should be understood that, in this embodiment, the pixel chip 10 and the logic chip 20 may adopt two independent chips or wafer structures and be integrated together through a bonding process.
  • the bonding process can be fusion bonding or hybrid bonding.
  • the above two bonding processes will be further explained in conjunction with specific embodiments.
  • the bonding process is not further limited, and only the pixel chip 10 and the logic chip 20 can be integrated, and the pixel chip 10 and the logic chip 20 can be electrically connected.
  • a bonding process of fusion bonding is taken as an example to further introduce the image sensor.
  • the heat resistance component 30 can be located on at least one of the pixel wafer 10 and the logic wafer. internal. That is, the heat resistance component 30 may be located in the pixel wafer 10 (as shown in FIG. 3). Alternatively, the thermal resistance component 30 is located in the logic chip 20 (as shown in FIG. 5). Or alternatively, the heat resistance component 30 is located in the pixel chip 10 and the logic chip 20 (as shown in FIG. 6). This can improve the dark current characteristics and improve the imaging quality of the image sensor, and at the same time can make the location of the thermal resistance component 30 and the structure of the image sensor more diversified.
  • the pixel wafer 10 is provided with a first metal interconnection structure 15 and the logic wafer 20 is provided with a second metal interconnection structure 22, and the heat resistance component 30 may be located in the first metal interconnection structure 15 or the second metal interconnection structure. Between 22. That is, the heat resistance component 30 may be located between the first metal interconnection structure 15 in the pixel wafer 10 and the bonding interface 40 of the pixel wafer 10 and the logic wafer 20 (as shown in FIG. 3). Alternatively, the heat resistance component 30 may also be located between the second metal interconnection structure 22 and the bonding interface 40 in the logic wafer 20 (as shown in FIG. 5).
  • the first metal interconnection structure 15 is used to interconnect the photosensitive units 121 in the pixel array 12.
  • the first metal interconnection structure 15 can be understood as having a predetermined number of metal interconnection layers 151.
  • the predetermined number in the first metal interconnection structure 15 is less than or equal to 4, such as 2 or 3.
  • the first metal interconnection structure 15 includes three metal interconnection layers 151.
  • the multi-layer metal interconnection layer 151 in the first metal interconnection structure 15 may be the same metal or different metals.
  • the multilayer metal interconnection layer 151 may be pure metal or an alloy.
  • the metal in the metal interconnection layer 151 may be aluminum or copper.
  • a first dielectric layer 16 is further provided in the pixel wafer 10, wherein the first dielectric layer 16 is located A substrate 11 is arranged on a side close to the logic chip 20. Moreover, the first metal interconnection structure 15 is located in the first dielectric layer 16, and the multilayer metal interconnection layers 151 of the first metal interconnection structure 15 are spaced apart from each other, and the metal interconnection layer 151 is realized by the first dielectric layer 16. The isolation between them prevents electrical signal interference, and the metal interconnection layer 151 used in the first metal interconnection structure 15 to be in contact with the air is isolated from the air, so that the metal interconnection layer 151 is transformed into a stable state.
  • the first dielectric layer 16 may be made of an insulating material, such as silicon oxide.
  • the metal interconnection layers 151 may be interlayer interconnection structures (that is, filled with conductive Material through holes, the inter-layer interconnection structure is not marked in the figure) for connection.
  • the second metal interconnection structure 22 is used to interconnect various functional modules in the logic chip 20.
  • the second metal interconnection structure 22 can be understood as having a predetermined number of metal interconnection layers 221. Generally, the predetermined number in the second metal interconnect structure 22 is less than or equal to 7, such as 5 or 4.
  • the multi-layer metal interconnection layer 221 in the second metal interconnection structure 22 may be the same metal or different metals, and it may be a pure metal or an alloy.
  • the metal in the metal interconnection layer 221 in the second metal interconnection structure 22 may be aluminum or copper.
  • a second dielectric layer 23 is further provided in the pixel wafer 10, and the second dielectric layer 23 is located on a side of the second substrate 21 close to the pixel wafer 10. Side setting.
  • the second metal interconnection structure 22 is located in the second dielectric layer 23, and the metal interconnection layers 221 of the second metal interconnection structure 22 are spaced apart from each other, and the metal interconnection layers 221 are realized through the second dielectric layer 23. The isolation prevents the interference of electrical signals, and the metal interconnection layer 221 in contact with the air in the second metal interconnection structure 22 is isolated from the air, so that the metal interconnection layer 221 is transformed into a stable state.
  • the electrical connection between the material of the second dielectric layer 23 and the metal interconnection layer 221 in the second dielectric layer 23 please refer to the above description of the first dielectric layer 16 and the metal interconnection layer 151 in the first dielectric layer 16. The electrical connection between the two is not described in detail in this embodiment.
  • the pixel wafer 10 and the logic wafer 20 are processed separately by using independent process flows.
  • the surface of the first dielectric layer 16 of the pixel wafer 10 and the surface of the second dielectric layer 23 of the logic wafer 20 need to be planarized, and then the bonding process is implemented.
  • the pixel chip 10 and the logic chip 20 are integrated in the vertical direction, and the bonded interface is the bonding interface 40.
  • the process that can be planarized includes, but is not limited to, a chemical mechanical polishing (Chemical Mechanical Polishing, abbreviated as: CMP) process.
  • CMP Chemical Mechanical Polishing
  • the CMP is one of the common semiconductor processes and is used to planarize the surface of a wafer.
  • one of the pixel wafer 10 or the logic wafer 20 may be a concave surface, and the other may be a flat surface.
  • the pixel wafer 10 and the logic wafer 20 are integrated together after fusion bonding, the pixel wafer 10 and the logic wafer 20 are still isolated from each other.
  • the pixel chip 10 is also electrically connected to the logic chip 20 through the first conductive interconnection structure 60, so that the first conductive interconnection The connection structure 60 satisfies the signal transmission between the pixel chip 10 and the logic chip 20.
  • the first conductive interconnection structure 60 includes an interconnection structure 61 and a conductive member 62.
  • the interconnection structure 61 is connected to the electrical connection units in the pixel chip 10 and the logic chip 20, respectively.
  • the piece 62 is connected between the two interconnecting structures 61.
  • the electrical connection unit in the pixel chip 10 is defined as the first electrical connection unit 18, and the electrical connection unit in the logic chip 20 is The electrical connection unit is defined as the second electrical connection unit 24.
  • the two interconnection structures 61 are electrically connected to the first electrical connection unit 18 and the second electrical connection unit 24 respectively, and the conductive member 62 is connected between the two interconnection structures 61.
  • the electrical connection unit in the pixel chip 10 and the electrical connection unit in the logic chip 20 can be electrically connected through the first conductive interconnection structure 60, so as to realize the electrical connection between the pixel chip 10 and the logic chip 20.
  • At least part of the conductive member 62 may be located on the surface of the first substrate 11.
  • all the conductive members 62 may be located on the surface of the first substrate 11, or a part of the conductive members 62 may be located on the surface of the first substrate 11.
  • the arrangement of the first conductive interconnection structure 60 can be facilitated to simplify the structure of the image sensor.
  • the interconnection structure 61 may be a first through hole (not marked in the figure) filled with a conductive material 90 and communicating with the electrical connection unit in the pixel chip 10 or the logic chip 20 ). That is, the interconnect structure 61 can be understood as a first through hole provided between the first electrical connection unit 18 and the second electrical connection unit 24 and the conductive member 62, and the first through hole is filled with the conductive material 90. .
  • the first substrate 11 is a silicon substrate, since the first through hole needs to pass through the first substrate 11, the first through hole can be understood as a silicon conductive through hole.
  • the conductive material 90 may be tungsten, copper, polysilicon, or the like. In this embodiment, the conductive material 90 is not further limited.
  • the conductive member 62 may be a metal member or a metal member made of other materials capable of conducting electricity.
  • the conductive member 62 may be aluminum or copper.
  • the first electrical connection unit 18 may be a specific area of a certain layer of the metal interconnection layer 151 connected to the first metal interconnection structure 15.
  • the second electrical connection unit 24 may be a specific area of a certain level of the metal interconnection layer 221 of the second metal interconnection structure 22.
  • the structure formation and placement positions of the first electrical connection unit 18 and the second electrical connection unit 24 are not further limited.
  • first electrical connection units 18, one or more second electrical connection units 24, and one or more first conductive interconnection structures 60 there may be one or more first electrical connection units 18, one or more second electrical connection units 24, and one or more first conductive interconnection structures 60.
  • the number of the first electrical connection unit 18, the second electrical connection unit 24 and the first conductive interconnection structure 60 is not further limited.
  • the uniform heat element 31 may be stacked on the side of the heat resister 32 facing the photosensitive direction (as shown in FIGS. 3 and 5), that is, the uniform heat element 31 may be placed on the heat resister 32.
  • the side facing the light-sensing direction is tightly attached to the heat resisting member 32, and the uniform heat member 31 may also be formed on the side of the heat resisting member 32 facing the light-sensing direction.
  • the uniform heat element 31 can also be spaced apart from the heat resistance element 32 (as shown in FIG. 6), that is, there is a certain distance between the uniform heat element 31 and the heat resistance element 32, that is, the heat resistance component 30 is Split structure. In this way, while improving the dark current characteristics and improving the imaging quality of the image sensor, the structure of the thermal resistance component 30 and the image sensor can be more diversified.
  • the uniform heating element 31 may be a suspended structure (as shown in FIG. 3, FIG. 5 and FIG. 6), that is, the suspended structure of the uniform heating element 31 can be understood as the uniform heating element 31 disposed on the first dielectric layer 16. Inside, and in a structural state that is not grounded or connected to the voltage layer.
  • a heat resistance component is arranged between the first substrate and the second substrate to block the heat in the logic chip and reduce the heat conducted to the pixel array. While reducing the size of the dark current, the pixel array can be improved. The uniformity of the distribution of heat and dark current is used to improve the dark current characteristics, which helps to improve the imaging quality of the image sensor.
  • FIG. 7 is a schematic diagram of the structure of an image sensor according to the second embodiment.
  • the difference from the above-mentioned embodiment is that, referring to FIG. Electrically connected to make the uniform heating element 31 grounded, so that part of the heat in the image sensor can be conducted to the outside of the image sensor through the leads on the pad 17, which has a better heat conduction effect, thereby further reducing the amount of heat under the pixel array 12.
  • the temperature and dark current further improve the imaging quality of the image sensor.
  • the interlayer interconnection structure 80 may be a metal interconnection filled with a conductive material 90 and connected to the pad 17 and the first metal interconnection structure 15.
  • the through hole between the layer 151 and the uniform heating element 31 realizes the electrical connection between the uniform heating element 31 and the pad 17.
  • interlayer interconnection structure 80 and the conductive material 90 reference may be made to the above description of the second through hole and the conductive material 90 in the second conductive interconnection structure 70, which will not be further elaborated in this embodiment.
  • the bonding pad 17 is located on the surface of the pixel chip 10 and is located close to the side of the pixel array 12.
  • a plurality of pads 17 are provided on the pixel wafer 10, wherein the plurality of pads 17 are evenly distributed on the edge area of the pixel wafer 10 or the image sensor (as shown in FIG. 5), so as to realize the wire bonding in the image sensor chip package. combine.
  • a heat resistance component is arranged between the first substrate and the second substrate to block the heat in the logic chip to improve the dark current characteristics and help improve the imaging quality of the image sensor.
  • the uniform heating element is electrically connected to the pads on the pixel wafer through the interlayer interconnection structure to further improve the dark current characteristics and enhance the imaging quality of the image sensor.
  • FIG. 8 is a schematic structural diagram of a heat uniforming member provided in the third embodiment
  • FIG. 9 is a schematic structural diagram of another heat uniforming member provided in the third embodiment.
  • the heat-conducting layer of the uniform heat element 31 When the heat-conducting layer of the uniform heat element 31 is selected as a thermally conductive material (such as copper) with thermal expansion and contraction, the heat-conducting layer may have stress concentration under the action of thermal expansion and contraction characteristics, thereby affecting the uniform heat element 31 And the stability of the heat resistance component 30.
  • a thermally conductive material such as copper
  • the difference from the above-mentioned embodiment is that, referring to Figs. 8 and 9, in this embodiment, in order to prevent possible stress concentration, the uniform heating element 31 is provided with arrays arranged in an array.
  • the hole structure 311 is opened to relieve stress and improve the stability of the uniform heat element 31 and the heat resistance assembly 30.
  • the opening structure 311 may be arranged in a grid array, a rectangular array, or a polygonal array, etc., and formed on the uniform heating element 31, so that the opening structure 311 is on the uniform heating element 31.
  • the upper surface is distributed regularly, so as to release the stress, and at the same time, can further improve the stability of the uniform heat element 31 and the heat resistance assembly 30.
  • the opening structure 311 may be a rectangular, square opening (as shown in FIG. 8) or a circular opening (as shown in FIG. 9).
  • the array arrangement form of the opening structure 311 and the shape of the openings are not further limited.
  • a heat resistance component is arranged between the first substrate and the second substrate, which can improve the uniformity of the heat and dark current distribution under the pixel array while reducing the size of the dark current, so as to improve the dark current characteristics. , Help to improve the imaging quality of the image sensor.
  • the stress can be relieved and the stability of the uniform heat element and the heat resistance component can be improved.
  • FIG. 10 is a schematic structural diagram of an image sensor provided by the fourth embodiment.
  • the difference from the foregoing first embodiment is that, referring to FIG. 10, in this embodiment, the pixel wafer 10 can be integrated and stacked on the logic wafer 20 by hybrid bonding.
  • the pixel wafer 10 may be electrically connected to the logic wafer 20 through a conductive layer 50, where the conductive layer 50 is located on the bonding interface 40 between the pixel wafer 10 and the logic wafer 20.
  • the pixel chip 10 and the logic chip 20 have already been electrically connected through the conductive layer 50 on the bonding interface 40. Therefore, the first conductive interconnection structure 60 is not needed to realize the electrical connection between the pixel chip 10 and the logic chip 20.
  • a part of the conductive layer 50 is formed on the side of the pixel wafer 10 opposite to the logic wafer 20, and the remaining part of the conductive layer 50 is formed on the side of the logic wafer 20 opposite to the pixel wafer 10. In this way, the bonding strength of the pixel chip 10 and the logic chip 20 can be ensured. It should be understood that part of the conductive layer 50 is embedded in the first dielectric layer 16, and the remaining part is embedded in the second dielectric layer 23.
  • the conductive layer 50 may be a layered structure formed of a metal layer or other conductive materials.
  • the metal layer may be copper, aluminum, or tungsten.
  • the heat resistance component 30 can be located in the pixel wafer 10 (as shown in FIG. 10), or the heat resistance The component 30 may also be located in the logic chip 20. In this way, while improving the dark current characteristics and improving the imaging quality of the image sensor, the arrangement of the thermal resistance component 30 can be more diversified.
  • a first metal interconnection structure 15 is provided in the pixel wafer 10
  • a second metal interconnection structure 22 is provided in the logic wafer 20
  • the thermal resistance component 30 can be a first metal interconnection structure.
  • the two metal interconnection layers 151 adjacent to the heat resistance component 30 in the first metal interconnection structure 15 are electrically connected through the second conductive interconnection structure 70, so that the second conductive interconnection structure 70 can The electrical connection between the above-mentioned two metal interconnection layers 151 is achieved.
  • the second conductive interconnection structure 70 may be located on the circumferential outer side of the thermal resistance component 30 (ie, the periphery of the thermal resistance component 30), that is, the second conductive interconnection structure 70 may be located outside the coverage area of the thermal resistance component 30 to Avoiding damage to the structure of the heat resistance assembly 30, thereby affecting the heat insulation and uniform heat effects of the heat resistance assembly 30.
  • the second conductive interconnection structure 70 may be a second through hole (not labeled in the figure) filled with a conductive material 90, wherein the second through hole is connected between two metal interconnection layers 151.
  • the two metal interconnection layers 151 described above may extend toward the periphery of the thermal resistance component 30 in the first dielectric layer 16, so that the second conductive interconnection structure 70 can be located on the periphery of the thermal resistance component 30 .
  • two of the above-mentioned electrical connection units may be provided at the positions where the two metal interconnection layers 151 are opposite to the second through holes, and the two electrical connection units are connected to the two metal interconnection layers 151 respectively, thereby A part of the metal interconnection layer 151 is formed.
  • the description of the conductive material 90 and the electrical connection unit can refer to the related description in the above-mentioned embodiment, and further details are not described in this embodiment.
  • the thermal resistance component 30 may also be located in the second metal interconnection structure 22, and the two metal interconnection layers 221 adjacent to the thermal resistance component 30 in the second metal interconnection structure 22 It is electrically connected through the second conductive interconnection structure 70. In this way, while improving the dark current characteristics and improving the imaging quality of the image sensor, the arrangement of the thermal resistance component 30 can be more diversified.
  • the arrangement of the second metal interconnection structure 22 of the thermal resistance component 30 in the logic chip 20 can refer to the above-mentioned arrangement of the first metal interconnection structure 15 of the thermal resistance component 30 in the pixel wafer 10. In this embodiment, it will not be further elaborated.
  • a heat resistance component is arranged between the first substrate and the second substrate to block the heat in the logic chip, reduce the dark current level, and improve the dark current characteristics, which helps to improve the image.
  • the imaging quality of the sensor is arranged between the first substrate and the second substrate to block the heat in the logic chip, reduce the dark current level, and improve the dark current characteristics, which helps to improve the image.
  • an embodiment of the present application provides an electronic device, which includes the image sensor as in any one of the foregoing.
  • the electronic device may specifically be a smart phone, a camera, a tablet computer, and other mobile terminals or fixed terminals with imaging functions.
  • a thermal resistance component is arranged between the first substrate and the second substrate of the image sensor to block the heat in the logic chip and reduce the heat conducted to the pixel array while reducing the size of the dark current.
  • the dark current characteristics can be improved, and the imaging quality of the image sensor and the electronic device can be improved.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or an intermediate connection.
  • the medium is indirectly connected, which can be the internal communication between two elements or the interaction between two elements.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

本申请提供一种图像传感器和电子装置，图像传感器包括像素晶片和逻辑晶片，像素晶片的朝向感光方向的一侧设置有用于感光的像素阵列，逻辑晶片堆叠设置在像素晶片的背离感光方向的一侧，逻辑晶片用于和像素阵列之间传输信号；像素晶片具有第一衬底，逻辑晶片具有第二衬底，第一衬底和第二衬底之间设有阻热组件，阻热组件用于将逻辑晶片内的热量进行阻挡，以降低暗电流的大小。本申请能够改善暗电流的特性，有助于提升图像传感器的成像品质。

Description

图像传感器和电子装置 技术领域
本申请涉及半导体技术领域，尤其涉及一种图像传感器和电子装置。
背景技术
图像传感器，如互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称:CMOS)，图像传感器是可将光学图像转化成数字信号的传感器，其广泛应用于移动终端、数码产品、安防监控等领域。
图像传感器主要包括像素区和电路区两大部分。图1所示的为一种堆叠式的图像传感器的截面结构示意图，该图像传感器包括逻辑晶片20和堆叠在逻辑晶片20之上的像素晶片10。在像素晶片10的衬底上设置有像素阵列12，构成像素区，用于将入射光转化成电信号。而在逻辑晶片20的衬底上则包含了由大量晶体管及其他器件形成的数字电路和模拟电路，该数字电路和模拟电路构成了电路区的多个功能性模块，负责向像素区提供控制信号以及处理像素区的输出信号。像素晶片10和逻辑晶片20通过键合工艺集成到一起。暗电流指的是在没有任何光照下像素阵列的感光单元产生的电流，为了得到较好的成像品质，图像传感器芯片的暗电流需要控制得尽可能小，而暗电流的大小对于温度的依赖特性非常显著，随着温度增加，暗电流呈指数上升。随着像素数量的不断增加，逻辑晶片的处理负荷也相应加大，导致逻辑晶片存在严重的发热问题。
然而，当逻辑晶片和像素晶片堆叠设置时，逻辑晶片上的热量会传导至像素晶片，导致暗电流大幅增加，最终影响了成像品质。
发明内容
本申请提供一种图像传感器和电子装置，以改善暗电流的特性，有助于提升图像传感器的成像品质。
本申请的第一方面提供一种图像传感器，其包括像素晶片和逻辑晶片，所述像素晶片的朝向感光方向的一侧设置有用于感光的像素阵列，所述逻辑晶片堆叠设置在所述像素晶片的背离所述感光方向的一侧，所述逻辑晶片用 于和所述像素阵列之间传输信号；
所述像素晶片具有第一衬底，所述逻辑晶片具有第二衬底，所述第一衬底和所述第二衬底之间设有阻热组件。
在本申请的一种具体实施例中，所述阻热组件包括匀热件和阻热件，其中，所述匀热件设置在所述阻热组件的靠近所述像素晶片的一侧设置，所述阻热件设在所述匀热件背离所述感光方向的一侧，且与所述匀热件相对设置。
在本申请的一种具体实施例中，所述阻热件设在所述像素阵列背离所述感光方向的一侧，用于阻隔所述逻辑晶片内的热量向所述像素阵列传导；
所述匀热件设在所述像素阵列背离所述感光方向的一侧，用于分散来自所述逻辑晶片的热量。
在本申请的一种具体实施例中，所述阻热组件位于所述像素晶片的背离所述第一衬底的一侧设置。
在本申请的一种具体实施例中，所述匀热件包括至少一个导热层，所述阻热件包括至少一个阻热层。
在本申请的一种具体实施例中，所述导热层为采用导热材料形成的层状结构，所述阻热层为采用隔热材料形成的层状结构。
在本申请的一种具体实施例中，所述导热材料在室温下的热导率大于100W/(m.K)，所述隔热材料在室温下的热导率小于1W/(m.K)，其中，所述室温为300K。
在本申请的一种具体实施例中，所述阻热组件与所述像素阵列相对设置，且所述阻热组件的面积大于等于所述像素阵列的面积。
在本申请的一种具体实施例中，所述像素晶片通过键合工艺堆叠在所述逻辑晶片朝向所述感光方向的一侧。
在本申请的一种具体实施例中，所述键合工艺为熔融键合或者混合键合。
在本申请的一种具体实施例中，所述像素晶片通过所述熔融键合集成堆叠在所述逻辑晶片之上时，
所述阻热组件位于所述像素晶片和所述逻辑晶片的至少一者的内部。
在本申请的一种具体实施例中，所述像素晶片内设有第一金属互连结构，所述逻辑晶片内设有第二金属互连结构，所述阻热组件位于所述第一金属互连结构与所述第二金属互连结构之间。
在本申请的一种具体实施例中，所述像素晶片还通过第一导电互连结构与所述逻辑晶片电连接。
在本申请的一种具体实施例中，所述第一导电互连结构包括互连结构和导电件，所述互连结构分别与所述像素晶片和所述逻辑晶片内的电连接单元连接，所述导电件连接在两个所述互连结构之间，且至少部分所述导电件位于所述第一衬底的表面。
在本申请的一种具体实施例中，所述互连结构为填充有导电材料并与所述第一金属互连结构或者所述第二金属互连结构连通的第一通孔；
所述导电件为金属件。
在本申请的一种具体实施例中，所述像素晶片通过所述混合键合集成堆叠在所述逻辑晶片之上时，
所述阻热组件位于所述像素晶片内，或者
所述阻热组件位于所述逻辑晶片内。
在本申请的一种具体实施例中，所述像素晶片内设有第一金属互连结构，所述逻辑晶片内设有第二金属互连结构，所述阻热组件位于所述第一金属互连结构内，或者
所述阻热组件位于所述第二金属互连结构内。
在本申请的一种具体实施例中，所述第一金属互连结构内与所述阻热组件相邻的两个金属互连层通过第二导电互连结构电连接，
或者所述第二金属互连结构内与所述阻热组件相邻的两个金属互连层通过所述第二导电互连结构电连接。
在本申请的一种具体实施例中，所述第二导电互连结构位于所述阻热组件的周向外侧。
在本申请的一种具体实施例中，所述第二导电互连结构为填充有导电材料的第二通孔，其中，所述第二通孔连接在两个所述金属互连层之间。
在本申请的一种具体实施例中，所述像素晶片通过导电层与所述逻辑晶片电连接，其中，所述导电层位于所述像素晶片和所述逻辑晶片的键合界面上。
在本申请的一种具体实施例中，所述匀热件堆叠在所述阻热件朝向所述感光方向的一侧，
或者，所述匀热件与所述阻热件间隔设置。
在本申请的一种具体实施例中，所述匀热件为悬浮结构，或者
所述匀热件通过层间互连结构与所述像素晶片上的焊盘电连接。
在本申请的一种具体实施例中，所述层间互连结构为填充有导电材料且连接在所述焊盘、所述第一金属互连结构和所述匀热件之间的通孔。
在本申请的一种具体实施例中，所述匀热件上设有呈阵列排列的开孔结构，以释放应力。
在本申请的一种具体实施例中，所述像素阵列形成在所述第一衬底上且靠近所述第一衬底的表面设置。
在本申请的一种具体实施例中，所述图像传感器为互补金属氧化物半导体CMOS图像传感器。
本申请的第二方面提供一种电子装置，其包括如上任一项所述的图像传感器。
在本申请提供的图像传感器和电子装置，通过在第一衬底和第二衬底之间设置阻热组件，能够将逻辑晶片内的热量进行阻隔，减少传导到像素阵列的热量，降低暗电流大小。在此基础上，通过阻热结构在一定程度上还能够对像素阵列之下的热量起到一定的匀热的作用，可以改善像素阵列之下热量和暗电流分布的均一性，以进一步提升图像传感器的成像品质。因此，本申请能够改善暗电流的特性，有助于提升图像传感器的成像品质。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的一种堆叠式图像传感器的结构示意图；
图2为现有技术中逻辑晶片的示意图；
图3为本实施例一提供的一种图像传感器的结构示意图；
图4为本实施例一提供的图像传感器的俯视示意图；
图5为本实施例一提供的另一种图像传感器的结构示意图；
图6为本实施例一提供的又一种图像传感器的结构示意图；
图7为本实施例二提供的一种图像传感器的结构示意图；
图8为本实施例三提供的一种匀热件的结构示意图；
图9为本实施例三提供的另一种匀热件的结构示意图；
图10为本实施例四提供的一种图像传感器的结构示意图。
附图标记说明：
10-像素晶片；11-第一衬底；12-像素阵列；121-感光单元；13-颜色滤镜；14-微透镜；15-第一金属互连结构；151、221-金属互连层；16-第一介质层；17-焊盘；18-第一电连接单元；20-逻辑晶片；21-第二衬底；22-第二金属互连结构；23-第二介质层；24-第二电连接单元；30-阻热组件；31-匀热件；311-开孔结构；32-阻热件；40-键合界面；50-导电层；60-第一导电互连结构；61-互连结构；62-导电件；70-第二导电互连结构；80-层间互连结构；90-导电材料。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
正如背景技术中所描述的，图1所示的现有技术中为一种典型的堆叠式图像传感器的截面示意图。参考图2所示，逻辑晶片20的衬底(即本申请的第二衬底21)上包含了由大量晶体管及其他器件形成的数字电路和模拟电路，且该数字电路和模拟电路构成了电路区(在图中未标示)的多个功能性模块。多个功能性模块主要包括模数转换模块、逻辑模块、输入/输出模块、锁相环模块、移动产业处理器接口模块、动态口令模块、寄存器模块等多个功能模块。多个功能模块构成了逻辑晶片20的电路区，用于负责向像素晶片10的像素区(在图中未标示)提供控制信号以及处理像素区的输出信号(即经像素区转化成的电信号)，从而得到图像信号。
暗电流指的是在没有任何光照下像素阵列12的感光单元121产生的电流，暗电流对于图像传感器成像质量的影响主要体现在以下两个方面：
第一、暗电流会推高整幅图像的平均值，尤其是在高温下，暗电流显著增大，暗电流的大小对于温度的依赖特性非常显著，即随着温度增加，暗电流呈指数上升，使得图像的动态范围减小；
第二、暗电流的非均匀性是图像传感器中固定模式噪声的一个重要来源，使图像传感器的通透性变差。
尽管在制造工艺上可降低像素阵列12的感光单元121的暗电流，并提高均匀性，但在后期图像处理时仍需消除或抑制暗电流噪声以提高图像质量。
为此，为了得到较好的成像品质，图像传感器芯片的暗电流需要控制得尽可能小。
然而，随着像素数量的不断增加，逻辑晶片20的处理负荷也相应加大，导致逻辑晶片20存在严重的发热问题。当逻辑晶片20和像素晶片10堆叠设置时，逻辑晶片20上的热量会传导至像素晶片10，导致暗电流大幅增加，从而影响图像传感器的成像品质。除此之外，逻辑晶片20的不同区域还存在着发热不均匀的问题，比如电路区内与逻辑模块和锁相环模块相对的区域产生的热量相对较大，而电路区内其他区域产生的热量相对较小，进而导致像素区的温度及暗电流的非均匀分布，最终影响了成像品质。
因此，本申请实施例提高一种图像传感器和电子装置，以改善暗电流的特性，有助于提升图像传感器的成像品质。
作为一种常见的应用场景，本申请实施例的图像传感器可以应用在智能手机、相机、平板电脑以及其他具有成像功能的移动终端或者固定终端上。相应的，本申请实施例的电子装置可以为智能手机、相机、平板电脑以及其他具有成像功能的移动终端或者固定终端。因此，本实施例中，对于图像传感器的应用场景并不做进一步限定。
下面以具体地实施例对本申请的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
实施例一
图3为本实施例一提供的一种图像传感器的结构示意图，图4为本实施例一提供的图像传感器的俯视示意图，图5为本实施例一提供的另一种图像传感器的结构示意图，图6为本实施例一提供的另一种图像传感器的结构示 意图。
参考图3至图6所示，本申请实施例的图像传感器包括像素晶片10和逻辑晶片20，像素晶片10的朝向感光方向的一侧设置有用于感光的像素阵列12，逻辑晶片20堆叠设置在像素晶片10的背离感光方向的一侧，逻辑晶片20用于和像素阵列10之间传输信号。具体的，逻辑晶片20可以向像素晶片10中的像素阵列12提供控制信号并处理从像素阵列12输出的信号，以形成图像信息。
应理解的是，本实施例中的上述感光方向可以理解为像素晶片10上光线入射的方向。
像素晶片10具有第一衬底11，逻辑晶片20具有第二衬底21，第一衬底11和第二衬底21之间设有阻热组件30。
具体的，本实施例中，像素晶片10堆叠在逻辑晶片20之上，以减小图像传感器所占用的空间，能够使得图像传感器的结构更加紧凑。
相应的，本实施例中的图像传感器为堆叠式的图像传感器。示例性的，本实施例中的图像传感器可以为堆叠式的CMOS图像传感器或者其他堆叠设置的图像传感器，即本实施例中，图像传感器包括但不仅限于堆叠式的CMOS图像传感器。
参靠图3所示，本实施例中，像素阵列12主要包括有大量的感光单元121和晶体管(在图中未标示)组成的阵列结构，其中晶体管设在像素单元(多个像素单元构成一个像素阵列12)内，像素阵列12用于将照向像素阵列12的入射光转换成电信号，并传输给逻辑晶片20，经过逻辑晶片20电路区内的多个功能模块进行处理，从而形成图像信息。
示例性的，感光单元121可以为光电二极管或者其他能够将入射光转换成电信号的器件。
为了能够输出较高质量的彩色图像，参考图3所示，本实施例中，每个感光单元121上设有颜色滤镜13和微透镜(microlenses)14，其中颜色滤镜13和微透镜14依次设在感光单元121的光线入射面(在图中未标示)上，使得颜色滤镜13设在感光单元121和微透镜14之间，使从通过每个微透镜14上方进入的入射光，可以被感光单元121上方的颜色滤镜13进行颜色识别的同时，能够通过微透镜14的汇聚作用增大进光量，以增大 入射光的光线利用率，并输出较高质量的彩色图像。具体的，颜色滤镜13和微透镜14的设置方式可以参考现有技术CMOS图像传感器的设置方式，在本实施例中，不再对其做进一步阐述。
需要说明的是，微透镜14是指微小透镜，通常指的是直径为微米甚至纳米量级的透镜。
参考图3所示，像素阵列12可以设在第一衬底11的内部且靠近第一衬底11的表面设置，以提高入射光的光线利用率。
由于暗电流为像素阵列12的感光单元121产生的，像素阵列12形成在第一衬底11上，逻辑晶片20的电路区形成在第二衬底21上。因此为了改善暗电流的特性，本实施例中通过阻热组件30设在第一衬底11和第二衬底21之间，能够将逻辑晶片20内的热量进行阻隔，减少传导到像素阵列12的热量，进而降低暗电流大小，改善暗电流对的特性，提升图像传感器的成像品质。由于阻热组件30在阻隔热量传导到像素阵列12时，由于阻热组件30具有一定的覆盖面积，在一定程度上还能够对像素阵列12之下的热量进行分散，起到一定的匀热的作用，可以相对改善像素阵列之下热量和暗电流分布的均一性，进一步有助于提升图像传感器的成像品质。
具体的，本实施例中，阻热组件30可以为分体式结构，也可以为一体式结构，在本实施例中，对于阻热组件30的结构并不做进一步限定。
示例性的，第一衬底11可以为硅衬底、铟镓砷衬底或者其他可以形成像素晶片10的衬底，即第一衬底11包括但不仅限于硅衬底。第二衬底21可以为硅衬底、绝缘体上硅衬底(SOI)或者其他可以形成逻辑晶片20的衬底，即本实施例中，第二衬底21包括但不仅限于硅衬底。
因此，本申请实施例通过在第一衬底11和第二衬底21之间设置阻热组件30，能够将逻辑晶片20内的热量进行阻隔，减少传导到像素阵列12的热量，降低暗电流大小；与此同时，可以改善像素阵列12之下热量和暗电流分布的均一性，以进一步提升图像传感器的成像品质。因此，本申请能够改善暗电流的特性，有助于提升图像传感器的成像品质。
进一步的，参考图3所示，阻热组件30包括匀热件31和阻热件32，匀热件31设置在阻热组件30的靠近像素晶片10的一侧设置。为了避免逻辑 晶片20工作时的热量传导到像素晶片10上的像素阵列12上，阻热件32设在匀热件31背离感光方向的一侧，且与匀热件31相对设置，以尽可能的降低像素晶片10的温度，从而改善暗电流的特性，比如减小暗电流的大小。在此基础上，通过匀热件31与阻热件32相对设置，且匀热件31设置在阻热组件30的靠近像素晶片10的一侧设置，且阻热件32与匀热件31相对设置，能够分散传导至像素区内的热量，提高像素区内温度和暗电流的一致性。
进一步的，阻热件32设在像素阵列10背离感光方向的一侧，用于阻隔逻辑晶片内的热量向像素阵列传导；匀热件31设在像素阵列12背离感光方向的一侧，用于分散来自逻辑晶片10的热量，能够使得像素阵列12之下的热量尽可能的分布均匀，从而提高像素阵列12之下温度的均一性，进而提高暗电流的均一性，使得像素阵列12之下的温度和暗电流均匀分布，进而改善暗电流的特性，以提高图像传感器的成像品质。
需要说明的是，匀热件31设在像素阵列12背离感光方向的一侧时，匀热件31可以设在像素阵列12的正下方，或者匀热件31也可以相对像素阵列12呈偏心设置，在本实施例中，对于匀热件31与像素阵列12的相对位置并不做进一步限定。
当感光单元121接收到的光信号强度大于等于其感测阀值，产生光电流。光电流和暗电流难以区分，所以感光单元121所接收到的光信号强度是根据光电流和暗电流共同确定的。因此，本实施例中，通过阻热组件30降低暗电流的同时，能够改善图像传感器的准确性。
其中，阻热组件30位于像素晶片10的背离第一衬底11的一侧设置，这样通过阻热组件30能够对像素阵列12起到更好的隔热、匀热的效果，以改善暗电流的特性，提升图像传感器的成像品质。
需要说明的是，阻热组件30位于像素晶片10的背离第一衬底11的一侧设置，并不单单指的是，阻热组件30位于像素晶片10的边界的一侧，阻热组件30也可以位于像素晶片10或者逻辑晶片20的内部。
具体的，参考图3所示，阻热组件30位于像素晶片10的背离第一衬底11的一侧设置时，使得阻热件32可以靠近第二衬底21设置，用于阻隔逻辑晶片20内的热量向像素阵列12传导。应理解的，阻热件32可以靠近第二衬底21设置，且覆盖在逻辑晶片20朝向感光方向的一侧，以屏蔽逻辑 晶片20工作时有源器件(比如晶体管)产生的热量，阻碍有源器件产生的热量向像素阵列12传导。
具体的，匀热件31可以包括至少一个导热层，也就是说，匀热件31可以由一层导热层组成，匀热件31也可以由多层导热层组成。相应的，阻热件32可以包括至少一个阻热层，也就是说，阻热件32可以由一层阻热层组成，阻热件32也可以由多层阻热层组成。在实际应用中，可以根据需要对于阻热组件30中阻热层和导热层的层数进行调整，以实现更好的隔热匀热效果。在本实施例中，对于匀热件31和阻热件32的层数并不做进一些限定。
进一步的，本实施例中，导热层可以为采用导热材料形成的层状结构，阻热层为采用隔热材料形成的层状结构。
在实际应用中，为了实现更好的隔热匀热效果。导热材料可以选用在室温下的热导率大于100W/(m.K)的导热材料，比如铜、铝或者石墨烯等。隔热材料可以选用在室温下的热导率小于1W/(m.K)的隔热材料，比如低介电常数材料或者聚酰亚胺(PI)。需要说明的是，上述室温可以理解为300K或者25℃。
在实际应用中，为了提高隔热匀热效果，参考图3和图4所示，阻热组件30与像素阵列12相对设置，且阻热组件30的面积大于等于像素阵列12的面积，以保证具有较好的匀热隔热效果。
需要说明的是，本实施例中，匀热件31的面积可以大于阻热件32的面积，或者，匀热件31的面积可以等于阻热件32的面积。为了保证具有较好的隔热和匀热效果，阻热件32的面积和匀热件31的面积均应大于像素阵列12的面积，以提高像素阵列12之下温度和暗电流的均一性。本实施例中，对于阻热组件30中匀热件31和阻热件32的面积大小并不做进一步限定。
具体的，本实施例中，像素晶片10可以通过键合工艺堆叠在逻辑晶片20朝向感光方向的一侧。应理解的是，本实施例中，像素晶片10和逻辑晶片20可以采用两个独立的晶片或晶圆结构，并通过键合工艺集成在一起。
其中，键合工艺可以为熔融键合(fusion bonding)或者混合键合(hybrid  bonding)，在本实施例中，将会结合具体的实施例对上述两种键合工艺做进一步阐述，在本实施例中，对于键合工艺并不做进一步限定，只有能够将像素晶片10和逻辑晶片20集成在一起，且能够实现像素晶片10和逻辑晶片20的电连接即可。
下面本实施例中，以熔融键合的键合工艺为例，对图像传感器做进一步介绍。
参考图3至图6所示，本实施例中，当像素晶片10可以通过熔融键合集成堆叠在逻辑晶片20之上时，阻热组件30可以位于像素晶片10和逻辑晶片的至少一者的内部。也就是说，阻热组件30可以位于像素晶片10内(如图3中所示)。或者，阻热组件30位于逻辑晶片20内(如图5中所示)。亦或者，阻热组件30位于像素晶片10和逻辑晶片20内(如图6中所示)。这样可以在改善暗电流特性，提升图像传感器的成像品质的同时，能够使得阻热组件30的设置位置以及图像传感器的结构更加多样化。
其中，像素晶片10内设有第一金属互连结构15，逻辑晶片20内设有第二金属互连结构22，阻热组件30可以位于第一金属互连结构15或者第二金属互连结构22之间。也就是说，阻热组件30可以位于像素晶片10内第一金属互连结构15与像素晶片10和逻辑晶片20的键合界面40之间(如图3中所示)。或者，阻热组件30也可以位于逻辑晶片20内第二金属互连结构22和键合界面40之间(如图5中所示)。或者，部分阻热组件30位于像素晶片10内且靠近键合界面40设置，部分阻热组件30位于逻辑晶片20内且靠近键合界面40设置(如图6中所示)。需要说明的是，第一金属互连结构15用于将像素阵列12内的各感光单元121进行互连。第一金属互连结构15可以理解为具有预定数量的金属互连层151。一般的，第一金属互连结构15中的预定数量小于等于4，比如2或者3。例如，如图3、图5和图6中所示，第一金属互连结构15包括3层的金属互连层151。
相应的，第一金属互连结构15中的多层金属互连层151可以为同一种金属，也可以为不同种金属。多层金属互连层151可以为纯金属，也可以为合金。例如，金属互连层151中的金属可以为铝或者铜。
为了使第一金属互连结构15的金属互连层151之间相互隔离，参考 图3至图6所示，像素晶片10内还设有第一介质层16，其中第一介质层16位于第一衬底11靠近逻辑晶片20的一侧设置。且第一金属互连结构15位于第一介质层16内，且第一金属互连结构15的多层金属互连层151之间相互间隔设置，通过第一介质层16实现金属互连层151之间的隔离，防止电信号的干扰，以及用于第一金属互连结构15中与空气接触的金属互连层151与空气隔离，使该金属互连层151转化为稳定的状态。
需要说明的是，第一介质层16可以采用绝缘材料制备而成，比如氧化硅等。
应理解的是，为了便于第一金属互连结构15内金属互连层151之间的电连接，示例性的，该金属互连层151之间可以通过层间互连结构(即填充有导电材料的通孔，该层间互连结构在图中未标示)进行连接。
相应的，第二金属互连结构22用于将逻辑晶片20内的各个功能模块进行互连。第二金属互连结构22可以理解为具有预定数量的金属互连层221。一般的，第二金属互连结构22中的预定数量小于等于7，比如5或者4。
第二金属互连结构22中的多层金属互连层221可以为同一种金属，也可以为不同种金属，其可以为纯金属，也可以为合金。例如，第二金属互连结构22中的金属互连层221中的金属可以为铝或者铜。
为了第二金属互连结构22的金属互连层221之间相互隔离，像素晶片10内还设有第二介质层23，其中第二介质层23位于第二衬底21靠近像素晶片10的一侧设置。且第二金属互连结构22位于第二介质层23内，且第二金属互连结构22的金属互连层221之间相互间隔设置，通过第二介质层23实现金属互连层221之间的隔离，防止电信号的干扰，以及用于第二金属互连结构22中与空气接触的金属互连层221与空气隔离，使该金属互连层221转化为稳定的状态。
具体的，第二介质层23的材料和第二介质层23内金属互连层221之间的电连接，可以参考上述对于第一介质层16和第一介质层16内金属互连层151之间的电连接，在本实施例中，不再加以赘述。
需要说明的是，由于像素晶片10和逻辑晶片20均采用相互独立的工艺流程分别进行加工。为了保证键合效果，在键合工艺之前，需对像素晶 片10的第一介质层16的表面和逻辑晶片20的第二介质层23的表面进行平坦化处理，然后在通过上述键合工艺实现垂直方向上的像素晶片10和逻辑晶片20的集成，键合后的界面为键合界面40。
示例性的，可以进行平坦化处理的工艺包括但不仅限于化学机械抛光(Chemical Mechanical Polishing，简称：CMP)工艺，该CMP为常见的半导体工艺制程之一，用于晶圆表面平坦化。
需要说明的是，在实际应用中，在键合工艺之前，两个需要键合的晶片之间平面与凹面的键合也可将两个晶片集成在一起。也就是说，像素晶片10或者逻辑晶片20中的其中一个可以为凹面，另一个可以为平面。
虽然像素晶片10和逻辑晶片20经过熔融键合之后集成在一起，但是，像素晶片10和逻辑晶片20之间仍相互隔绝。为了实现像素晶片10和逻辑晶片20之间的电连接，参考图3至图6所示，像素晶片10还通过第一导电互连结构60与逻辑晶片20电连接，这样能够通过第一导电互连结构60满足像素晶片10和逻辑晶片20之间信号的传输。
具体的，参考图3至图6所示，第一导电互连结构60包括互连结构61和导电件62，互连结构61分别与像素晶片10和逻辑晶片20内的电连接单元连接，导电件62连接在两个互连结构61之间。为了更好的对像素晶片10和逻辑晶片20内的电连接单元进行区分，本实施例中，将像素晶片10内的电连接单元定义为的第一电连接单元18，将逻辑晶片20内的电连接单元定义为的第二电连接单元24。这样两个互连结构61分别于第一电连接单元18和第二电连接单元24电连接，且导电件62连接在两个互连结构61之间。这样通过第一导电互连结构60可以实现像素晶片10内的电连接单元和逻辑晶片20内的电连接单元的电连接，从而实现像素晶片10和逻辑晶片20的电连接。
为了简化图像传感器的结构，参考图3至图6所示，至少部分导电件62可以位于第一衬底11的表面。也就是说，导电件62可以全部位于第一衬底11的表面，或者，部分导电件62位于第一衬底11的表面，这样在通过第一导电互连结构60实现像素晶片10和逻辑晶片20的电连接的同时，能够便于第一导电互连结构60的设置，以简化图像传感器的结构。
作为一种可能的实施方式，本实施例中，互连结构61可以为填充有 导电材料90并与像素晶片10或者逻辑晶片20内的电连接单元连通的第一通孔(在图中未标示)。也就是说，互连结构61可以理解为设在第一电连接单元18和第二电连接单元24与导电件62之间的第一通孔，且该第一通孔内填充有导电材料90。当第一衬底11为硅衬底时，由于第一通孔需穿过第一衬底11，因此，第一通孔可以理解为硅导电通孔。
示例性，导电材料90可以为钨、铜或者多晶硅等。在本实施例中，对于导电材料90并不做进一步限定。
其中，导电件62可以为金属件或者由其他能够导电的材料制备的金属件。示例性的，导电件62可以为铝或者铜。
需要说明的是，本实施例中，第一电连接单元18可以为与第一金属互连结构15相连接的某一层金属互连层151的特定区域。相应的，第二电连接单元24可以为与第二金属互连结构22的中某一层金属互连层221的特定区域。在本实施例中，对于第一电连接单元18和第二电连接单元24的结构形成和设置位置并不做进一步限定。
示例性的，第一电连接单元18可以为一个或者多个，第二电连接单元24可以为一个或者多个，第一导电互连结构60可以为一个或者多个，在本实施例中，不在对第一电连接单元18、第二电连接单元24以及第一导电互连结构60的个数做进一步限定。
具体的，本实施例中，匀热件31可以堆叠在阻热件32朝向感光方向的一侧(如图3和图5中所示)，即匀热件31可以搁设在阻热件32朝向感光方向的一侧与阻热件32紧密贴合，匀热件31也可以形成在阻热件32朝向所述感光方向的一侧。或者，匀热件31也可以与阻热件32间隔设置(如图6中所示)，即匀热件31与阻热件32之间存在一定的间距，也就是说，阻热组件30为分体式结构。这样在改善暗电流特性，提升图像传感器的成像品质的同时，能够使得阻热组件30和图像传感器的结构更加多样化。
本实施例中，匀热件31可以为悬浮结构(如图3、图5和图6中所示)，即匀热件31的悬浮结构可以理解为匀热件31设在第一介质层16内，并处于不接地或者不与电压层连接的结构状态。
本申请实施例通过在第一衬底和第二衬底之间设置阻热组件，将逻辑晶片内的热量进行阻隔，减少传导到像素阵列的热量在降低暗电流大小的同 时，能够提高像素阵列之下热量和暗电流分布的均一性，以改善暗电流特性，有助于提升图像传感器的成像品质。
实施例二
图7为本实施例二提供的一种图像传感器的结构示意图。
在上述实施例的基础上，与上述实施例以不同之处在于，参考图7所示，本实施例中，匀热件31可以通过层间互连结构80与像素晶片10上的焊盘17电连接，使得匀热件31为接地状态，这样图像传感器内的部分热量可以通过焊盘17上的引线传导至图像传感器的外部，具有更好的导热效果，从而进一步降低像素阵列12之下的温度和暗电流大小，进一步提升图像传感器的成像品质。
作为一种可能的实施方式，参考图7所示，本实施例中，层间互连结构80可以为填充有导电材料90且连接在焊盘17、第一金属互连结构15中的金属互联层151和匀热件31之间的通孔，从而实现匀热件31和焊盘17之间的电连接。
其中，层间互连结构80和导电材料90可以参考上述对于第二导电互连结构70内的第二通孔和导电材料90的描述，在本实施例中，不在做进一步阐述。
需要说明的是，本实施例中，焊盘17位于像素晶片10的表面且靠近像素阵列12的一面设置。像素晶片10上设有多个焊盘17，其中，多个焊盘17均布在像素晶片10或者图像传感器的边缘区域(如图5中所示)，以便实现图像传感器芯片封装中的引线键合。
本申请实施例通过在第一衬底和第二衬底之间设置阻热组件，在将逻辑晶片内的热量进行阻隔，以改善暗电流特性，有助于提升图像传感器的成像品质。在此基础上，匀热件通过层间互连结构与像素晶片上的焊盘电连接，以进一步改善暗电流特性以及提升图像传感器的成像品质。
实施例三
图8为本实施例三提供的一种匀热件的结构示意图，图9为本实施例三提供的另一种匀热件的结构示意图。
当匀热件31的导热层选用的为具有热胀冷缩的导热材料(比如铜)时，在热胀冷缩特性的作用下，该导热层可能会出现应力集中，从而影响匀热件31和阻热组件30的稳定性。
在上述实施例的基础上，与上述实施例不同之处在于，参考图8和图9所示，本实施例中，为了防止可能出现的应力集中，匀热件31上设有呈阵列排列的开孔结构311，以释放应力，提升匀热件31和阻热组件30的稳定性。
示例性的，参考图8和图9所示，该开孔结构311可以网格阵列、矩形阵列或者多边形阵列等排列，形成在匀热件31上，以使得开孔结构311在匀热件31上呈规律性分布，以释放应力的同时，能够进一步的提升匀热件31和阻热组件30的稳定性。其中，该开孔结构311可以为矩形、方形开孔(如图8中所示)或者圆形开孔(如图9中所示)。本实施例中，对于开孔结构311的阵列排布的形式和开孔的形状并不做进一步限定。
本申请实施例通过在第一衬底和第二衬底之间设置阻热组件，在降低暗电流大小的同时，能够提高像素阵列之下热量和暗电流分布的均一性，以改善暗电流特性，有助于提升图像传感器的成像品质。在此基础上，通过匀热件上呈阵列排列的开孔结构的设置，能够释放应力，提升匀热件和阻热组件的稳定性。
实施例四
图10为本实施例四提供的一种图像传感器的结构示意图。
在上述实施例的基础上，与上述实施例一不同之处在于，参考图10所示，本实施例中，像素晶片10可以通过混合键合集成堆叠在逻辑晶片20之上。
具体的，参考图10所示，像素晶片10可以通过导电层50与逻辑晶片20电连接，其中，导电层50位于像素晶片10和逻辑晶片20的键合界面40上。此时，像素晶片10和逻辑晶片20已经通过键合界面40上的导电层50实现了电连接，因此，无需借助第一导电互连结构60实现像素晶片10和逻辑晶片20的电连接。
参考图10所示，该导电层50的部分形成在像素晶片10上且与逻辑 晶片20相对的一面上，导电层50的其余部分形成在逻辑晶片20上且与像素晶片10相对的一面上，这样能够保证像素晶片10和逻辑晶片20的键合强度。应理解的是，导电层50的部分嵌设在第一介质层16内，其余部分嵌设在第二介质层23内。
示例性的，导电层50可以为金属层或者其他导电材料形成的层状结构。其中，金属层可以为铜、铝或者钨等。
当像素晶片10可以通过混合键合集成堆叠在逻辑晶片20之上时，作为一种可能的实施方式，阻热组件30可以位于像素晶片10内(如图10中所示)，或者，阻热组件30也可以位于逻辑晶片20内。这样在改善暗电流特性，提升图像传感器的成像品质的同时，能够使得阻热组件30的设置方式更加多样化。
作为一种可能的实施方式，参考图10所示，像素晶片10内设有第一金属互连结构15，逻辑晶片20内设有第二金属互连结构22，阻热组件30可以第一金属互连结构15内，第一金属互连结构15内与阻热组件30相邻的两个金属互连层151通过第二导电互连结构70电连接，这样通过第二导电互连结构70能够实现上述两个金属互连层151之间的电连接。
由于阻热组件30设置在第一金属互连结构15之间，因此，第一金属互连结构15内与阻热组件30相邻的两个金属互连层151之间无法设置任何层间的导电通孔。因此，第二导电互连结构70可以位于阻热组件30的周向外侧(即阻热组件30的外围)，即第二导电互连结构70可以位于阻热组件30的覆盖区域之外，以避免对阻热组件30的结构造成损害，从而影响阻热组件30的隔热和匀热效果。
示例性的，第二导电互连结构70可以为填充有导电材料90的第二通孔(在图中未标示)，其中，第二通孔连接在两个金属互连层151之间。
作为一种可能的实施方式，上述两个金属互连层151可以在第一介质层16内朝向阻热组件30的外围延伸，从而使得第二导电互连结构70可以位于阻热组件30的外围。或者，可以在上述两个金属互连层151与第二通孔相对位置处设置两个上述的电连接单元，且该两个电连接单元与上述两个金属互连层151分别相接，从而形成金属互连层151的一部分。
需要说明的是，导电材料90和电连接单元的描述可以参考上述实施 例中的相关描述，在本实施例中，不再做进一步赘述。
或者，作为另一种可能的实施方式，阻热组件30还可以位于第二金属互连结构22内，第二金属互连结构22内与阻热组件30相邻的两个金属互连层221通过第二导电互连结构70电连接。这样在改善暗电流特性，提升图像传感器的成像品质的同时，能够使得阻热组件30的设置方式更加多样化。
具体的，阻热组件30在逻辑晶片20内的第二金属互连结构22的设置方式可以参考上述对于阻热组件30设在像素晶片10内的第一金属互连结构15的设置方式，在本实施例中，不在对其做进一步阐述。
本申请实施例通过在第一衬底和第二衬底之间设置阻热组件，在将逻辑晶片内的热量进行阻隔，降低暗电流大小的同时，能够改善暗电流特性，有助于提升图像传感器的成像品质。
实施例五
进一步的，在上述实施例的基础上，本申请实施例提供了一种电子装置，其包括如上任一项中的图像传感器。
其中，本实施例中，该电子装置具体可以为智能手机、相机、平板电脑以及其他具有成像功能的移动终端或者固定终端上。
本申请实施例通过在图像传感器的第一衬底和第二衬底之间设置阻热组件，在将逻辑晶片内的热量进行阻隔，减少传导到像素阵列的热量在降低暗电流大小的同时，能够以改善暗电流特性，有助于提升图像传感器和电子装置的成像品质。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以是固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或者位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描 述，而不是指示或者暗示所指的装置或者元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。在本申请的描述中，“多个”的含义是两个或两个以上，除非是另有精确具体地规定。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (28)

  1. 一种图像传感器，其特征在于，包括像素晶片和逻辑晶片，所述像素晶片的朝向感光方向的一侧设置有用于感光的像素阵列，所述逻辑晶片堆叠设置在所述像素晶片的背离所述感光方向的一侧，所述逻辑晶片用于和所述像素阵列之间传输信号；
    所述像素晶片具有第一衬底，所述逻辑晶片具有第二衬底，所述第一衬底和所述第二衬底之间设有阻热组件。
  2. 根据权利要求1所述的图像传感器，其特征在于，所述阻热组件包括匀热件和阻热件，其中，所述匀热件设置在所述阻热组件的靠近所述像素晶片的一侧设置，所述阻热件设在所述匀热件背离所述感光方向的一侧，且与所述匀热件相对设置。
  3. 根据权利要求2所述的图像传感器，其特征在于，所述阻热件设在所述像素阵列背离所述感光方向的一侧，用于阻隔所述逻辑晶片内的热量向所述像素阵列传导；
    所述匀热件设在所述像素阵列背离所述感光方向的一侧，用于分散来自所述逻辑晶片的热量。
  4. 根据权利要求3所述的图像传感器，所述阻热组件位于所述像素晶片的背离所述第一衬底的一侧设置。
  5. 根据权利要求2-4中任意一项所述的图像传感器，其特征在于，所述匀热件包括至少一个导热层，所述阻热件包括至少一个阻热层。
  6. 根据权利要求5所述的图像传感器，其特征在于，所述导热层为采用导热材料形成的层状结构，所述阻热层为采用隔热材料形成的层状结构。
  7. 根据权利要求6所述的图像传感器，其特征在于，所述导热材料在室温下的热导率大于100W/(m.K)，所述隔热材料在室温下的热导率小于1W/(m.K)，其中，所述室温为300K。
  8. 根据权利要求1-7中任意一项所述的图像传感器，其特征在于，所述阻热组件与所述像素阵列相对设置，且所述阻热组件的面积大于等于所述像素阵列的面积。
  9. 根据权利要求1-8中任意一项所述的图像传感器，其特征在于，所述像素晶片通过键合工艺堆叠在所述逻辑晶片朝向所述感光方向的一侧。
  10. 根据权利要9所述的图像传感器，其特征在于，所述键合工艺为熔融键合或者混合键合。
  11. 根据权利要求10所述的图像传感器，其特征在于，所述像素晶片通过所述熔融键合集成堆叠在所述逻辑晶片之上时，
    所述阻热组件位于所述像素晶片和所述逻辑晶片的至少一者的内部。
  12. 根据权利要求11所述的图像传感器，其特征在于，所述像素晶片内设有第一金属互连结构，所述逻辑晶片内设有第二金属互连结构，所述阻热组件位于所述第一金属互连结构与所述第二金属互连结构之间。
  13. 根据权利要求12所述的图像传感器，其特征在于，所述像素晶片还通过第一导电互连结构与所述逻辑晶片电连接。
  14. 根据权利要求13所述的图像传感器，其特征在于，所述第一导电互连结构包括互连结构和导电件，所述互连结构分别与所述像素晶片和所述逻辑晶片内的电连接单元连接，所述导电件连接在两个所述互连结构之间，且至少部分所述导电件位于所述第一衬底的表面。
  15. 根据权利要求13所述的图像传感器，其特征在于，所述互连结构为填充有导电材料并与所述第一金属互连结构或者所述第二金属互连结构连通的第一通孔；
    所述导电件为金属件。
  16. 根据权利要求10所述的图像传感器，其特征在于，所述像素晶片通过所述混合键合集成堆叠在所述逻辑晶片之上时，
    所述阻热组件位于所述像素晶片内，或者
    所述阻热组件位于所述逻辑晶片内。
  17. 根据权利要求16所述的图像传感器，其特征在于，所述像素晶片内设有第一金属互连结构，所述逻辑晶片内设有第二金属互连结构，所述阻热组件位于所述第一金属互连结构内，或者
    所述阻热组件位于所述第二金属互连结构内。
  18. 根据权利要求17所述的图像传感器，其特征在于，所述第一金属互连结构内与所述阻热组件相邻的两个金属互连层通过第二导电互连结构电连接，
    或者所述第二金属互连结构内与所述阻热组件相邻的两个金属互连层通 过所述第二导电互连结构电连接。
  19. 根据权利要求18所述的图像传感器，其特征在于，所述第二导电互连结构位于所述阻热组件的周向外侧。
  20. 根据权利要求18或者19所述的图像传感器，其特征在于，所述第二导电互连结构为填充有导电材料的第二通孔，其中，所述第二通孔连接在两个所述金属互连层之间。
  21. 根据权利要求16-20中任意一项所述的图像传感器，其特征在于，所述像素晶片通过导电层与所述逻辑晶片电连接，其中，所述导电层位于所述像素晶片和所述逻辑晶片的键合界面上。
  22. 根据权利要求2-19中任意一项所述的图像传感器，其特征在于，所述匀热件堆叠在所述阻热件朝向所述感光方向的一侧，或者
    所述匀热件与所述阻热件间隔设置。
  23. 根据权利要求1-22中任意一项所述的图像传感器，其特征在于，所述匀热件为悬浮结构，或者
    所述匀热件通过层间互连结构与所述像素晶片上的焊盘电连接。
  24. 根据权利要求23所述的图像传感器，其特征在于，所述层间互连结构为填充有导电材料且连接在所述焊盘、所述第一金属互连结构和所述匀热件之间的通孔。
  25. 根据权利要求1-24中任意一项所述的图像传感器，其特征在于，所述匀热件上设有呈阵列排列的开孔结构，以释放应力。
  26. 根据权利要求1-25中任意一项所述的图像传感器，其特征在于，所述像素阵列形成在所述第一衬底上且靠近所述第一衬底的表面设置。
  27. 根据权利要求1-26中任意一项所述的图像传感器，其特征在于，所述图像传感器为互补金属氧化物半导体CMOS图像传感器。
  28. 一种电子装置，其特征在于，包括如权利要求1至27中任一项所述的图像传感器。
PCT/CN2020/075876 2020-02-19 2020-02-19 图像传感器和电子装置 WO2021163927A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202080002262.5A CN112166499A (zh) 2020-02-19 2020-02-19 图像传感器和电子装置
PCT/CN2020/075876 WO2021163927A1 (zh) 2020-02-19 2020-02-19 图像传感器和电子装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/075876 WO2021163927A1 (zh) 2020-02-19 2020-02-19 图像传感器和电子装置

Publications (1)

Publication Number Publication Date
WO2021163927A1 true WO2021163927A1 (zh) 2021-08-26

Family

ID=73865975

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/075876 WO2021163927A1 (zh) 2020-02-19 2020-02-19 图像传感器和电子装置

Country Status (2)

Country Link
CN (1) CN112166499A (zh)
WO (1) WO2021163927A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230029996A1 (en) * 2021-07-30 2023-02-02 SK Hynix Inc. Image sensing device and method of operating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110047808A (zh) * 2019-04-30 2019-07-23 德淮半导体有限公司 堆叠型背照式图像传感器及其制造方法
CN110164893A (zh) * 2019-05-24 2019-08-23 德淮半导体有限公司 3d堆叠式cmos图像传感器及其制备方法
CN110211984A (zh) * 2019-06-20 2019-09-06 德淮半导体有限公司 堆叠型背照式图像传感器及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109545811A (zh) * 2018-11-26 2019-03-29 豪威科技(上海)有限公司 堆叠式cmos图像传感器及其制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110047808A (zh) * 2019-04-30 2019-07-23 德淮半导体有限公司 堆叠型背照式图像传感器及其制造方法
CN110164893A (zh) * 2019-05-24 2019-08-23 德淮半导体有限公司 3d堆叠式cmos图像传感器及其制备方法
CN110211984A (zh) * 2019-06-20 2019-09-06 德淮半导体有限公司 堆叠型背照式图像传感器及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230029996A1 (en) * 2021-07-30 2023-02-02 SK Hynix Inc. Image sensing device and method of operating the same
US11956416B2 (en) * 2021-07-30 2024-04-09 SK Hynix Inc. Image sensing device and method of operating the same

Also Published As

Publication number Publication date
CN112166499A (zh) 2021-01-01

Similar Documents

Publication Publication Date Title
US20220246498A1 (en) Semiconductor device
US10916577B2 (en) Semiconductor device and method of manufacturing the same, and electronic apparatus
US10367022B2 (en) Solid-state imaging device, members for the same, and imaging system
US20220415956A1 (en) Solid-state image sensor, method for producing solid-state image sensor, and electronic device
JP5451547B2 (ja) 固体撮像装置
US11688753B2 (en) Solid-state imaging device configured by electrically bonding the respective electrodes of a plurality of semiconductor chips
JP4379295B2 (ja) 半導体イメージセンサー・モジュール及びその製造方法
CN110741476B (zh) 晶片接合的背照式成像器
US11817471B2 (en) Imaging device and electronic device configured by bonding a plurality of semiconductor substrates
TW201241999A (en) Solid-state imaging device, manufacturing method thereof, and electronic apparatus
TWI594406B (zh) 三維晶片上系統影像感測器封裝體
WO2017145815A1 (ja) 撮像装置
US9496309B2 (en) Image sensor device
WO2021163927A1 (zh) 图像传感器和电子装置
JP2023084601A (ja) 固体撮像装置及び電子機器
TW202320316A (zh) 堆疊式影像感測器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20920730

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20920730

Country of ref document: EP

Kind code of ref document: A1