WO2021158241A1 - Procédé et appareil de production de substrat de trou d'interconnexion en silicium - Google Patents

Procédé et appareil de production de substrat de trou d'interconnexion en silicium Download PDF

Info

Publication number
WO2021158241A1
WO2021158241A1 PCT/US2020/017412 US2020017412W WO2021158241A1 WO 2021158241 A1 WO2021158241 A1 WO 2021158241A1 US 2020017412 W US2020017412 W US 2020017412W WO 2021158241 A1 WO2021158241 A1 WO 2021158241A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
silicon substrate
substrate
vias
conductive material
Prior art date
Application number
PCT/US2020/017412
Other languages
English (en)
Inventor
Willibrordus Gerardus Maria Van Den Hoek
Original Assignee
Innovent Technologies, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innovent Technologies, Llc filed Critical Innovent Technologies, Llc
Publication of WO2021158241A1 publication Critical patent/WO2021158241A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0353—Holes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/05—Arrays
    • B81B2207/056—Arrays of static structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03612—Physical or chemical etching by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/128—Molten metals, e.g. casting thereof, or melting by heating and excluding molten solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0014—Shaping of the substrate, e.g. by moulding

Definitions

  • a silicon via substrate is an example of silicon substrate that includes a number of possibly closely spaced, precisely located holes or vias formed therethrough or blind vias (e.g., holes that terminate inside the substrate) therein. These vias are filled with conductive material to provide isolated conductive regions insulated from the silicon substrate by a thin insulating film in between the metal and the via side walls. These silicon substrates with filled vias are sometimes referred to as Through Silicon Via (TSV) substrates. Silicon via substrates are well-suited as starting substrates for Micro Electromechanical System (MEMS) manufacturing.
  • MEMS Micro Electromechanical System
  • a function of a silicon via substrate is to enable contact between the bond pads of a MEMS device created on one side of the silicon via substrate and “the outside world” by contacting the via surface on the other side of the silicon via substrate.
  • TSV substrates may be constructed using many methods including electrodeposition and atomic layer deposition processes.
  • Prior solutions such as U.S. Pat. No. 8,242,382 discuss methods to create metal filled vias in ceramic substrates.
  • the methods discussed in that patent are incompatible with silicon substrates because the liquid metal used to fill the vias will react with the silicon substrate, breach the through silicon via side walls, and penetrate deep into the silicon substrate.
  • the prior art solutions which discuss forming a thin silicon dioxide film on the surface of the sidewall of a via to provide electrical isolation between the substrate and the metal vias are not sufficient to prevent a liquid metal from penetrating into the silicon substrate.
  • the prior art solutions are insufficient because of the resulting deformation to the shape of the via, and the metal penetration into the silicon will create an electrical short between adjacent vias through the conducting silicon substrate.
  • An example of a method for manufacturing a silicon via substrate according to the disclosure includes depositing a dielectric coating on a silicon substrate having a plurality of open vias, each via extending from a first side of the silicon substrate to a second side of the silicon substrate, and having at least a first opening at the first side of the silicon substrate, melting an electrically conductive material, and exposing at least one surface of the coated silicon substrate to the molten electrically conductive material under conditions of elevated pressure and temperature, such that the electrically conductive material flows into the plurality of open vias in a molten state free of solid state material to fill the plurality of open vias.
  • Implementations of such a method may include one or more of the following features.
  • the plurality of open vias may be blind-vias, and the method may include removing a portion of the second side of the silicon substrate to expose the electrically conductive material in the blind-vias.
  • the electrically conductive material may be selected from a group consisting of moldaluminum, aluminum alloy, gold, gold alloy, silver, silver alloy, copper, and copper alloy.
  • the dielectric coating may be selected from a group consisting of silicon nitride, silicon carbide, zirconium oxide, zirconium nitride, zirconium carbide, yttrium oxide and yttrium carbide.
  • the plurality of open vias may be formed by at least one of laser drilling, waterjet drilling, plasma etching and mechanical drilling.
  • the method may include placing the silicon substrate and the electrically conductive material in a mold prior to melting the electrically conductive material.
  • Depositing the dielectric coating may include processing the silicon substrate having the plurality of open vias in a gas-phase material deposition system.
  • An example of a method for manufacturing a silicon via substrate according to the disclosure includes depositing an insulating coating on a silicon substrate having a plurality of open vias, each via extending from a first side of the silicon substrate to a second side of the silicon substrate, and having at least a first opening at the first side of the silicon substrate, depositing a barrier coating on the insulating coating on the silicon substrate, melting an electrically conductive material, and exposing at least one surface of the coated silicon substrate to the molten electrically conductive material under conditions of elevated pressure and temperature, such that the electrically conductive material flows into the plurality of open vias in a molten state free of solid state material to fill the plurality of open vias.
  • Implementations of such a method may include one or more of the following features.
  • the plurality of open vias may be blind-vias, and the method may include removing a portion of the second side of the silicon substrate to expose the electrically conductive material in the blind-vias.
  • the electrically conductive material may be selected from a group consisting of aluminum, aluminum alloy, gold, gold alloys, silver, silver alloys, copper, and copper alloy.
  • the barrier coating may be selected form a group consisting of tungsten, tungsten carbide, tungsten nitride, and ruthenium.
  • the insulating coating may be selected from a group consisting of silicon dioxide, silicon nitride, silicon carbide, zirconium oxide, zirconium nitride, zirconium carbide, yttrium oxide and yttrium carbide.
  • the plurality of open vias may be formed by at least one of laser drilling, waterjet drilling, plasma etching and mechanical drilling.
  • the method may include placing the silicon substrate and the electrically conductive material in a mold prior to melting the electrically conductive material.
  • Depositing the insulating coating may include processing the silicon substrate having the plurality of open vias in a gas-phase material deposition system.
  • Depositing the barrier coating may include processing the silicon substrate having the insulating coating and the plurality of open vias in a gas-phase material deposition system.
  • An example of a silicon via substrate includes a silicon substrate having a plurality of open vias, each via defined by a sidewall and extending from a first side of the silicon substrate to a second side of the silicon substrate, and having at least a first opening at the first side of the substrate, a dielectric coating deposited on at least the first side of the silicon substrate and on the sidewalls of the plurality of open vias, and an electrically conductive material disposed in each of the plurality of open vias and in direct contact with the dielectric coating, wherein the electrically conductive material has been flowed into each of the plurality of open vias in a molten state free of solid state material under conditions of elevated pressure and temperature, such that the electrically conductive material fills the plurality of open vias from the first side of the substrate.
  • Implementations of such a silicon via substrate may include a dielectric coating that is selected from a group consisting of silicon nitride, silicon carbide, zirconium oxide, zirconium nitride, zirconium carbide, yttrium oxide and yttrium carbide.
  • An example of a silicon via substrate includes a silicon substrate having a plurality of open vias, each via defined by a sidewall and extending from a first side of the silicon substrate to a second side of the silicon substrate, and having at least a first opening at the first side of the substrate, an insulating coating deposited on at least the first side of the silicon substrate and on the sidewalls of the plurality of open vias, a barrier coating deposited on the insulating coating, and an electrically conductive material disposed in each of the plurality of open vias and in direct contact with the barrier coating, wherein the electrically conductive material has been flowed into each of the plurality of open vias in a molten state free of solid state material under conditions of elevated pressure and temperature, such that the electrically conductive material fills the plurality of open vias from the first side of the substrate.
  • Implementations of such a silicon via substrate may include a barrier coating that is selected from a group consisting of tungsten, tungsten carbide, tungsten nitride, and ruthenium. Other thin film metals which do not dissolve in the molten metal during infusion may be used.
  • Items and/or techniques described herein may provide one or more of the following capabilities, as well as other capabilities not mentioned.
  • a plurality of vias may be drilled into a silicon substrate. The vias may be through-vias or bbnd-vias.
  • a dielectric coating may be deposited onto the silicon substrate and the via sidewalls in the silicon substrate.
  • a bilayer coating may be deposited onto the silicon substrate and the via sidewalls.
  • the silicon substrate may be exposed to a molten electrically conductive material at elevated pressure and temperature such that the electrically conductive material may flow into the plurality of vias in a molten state.
  • Other capabilities may be provided and not every implementation according to the disclosure must provide any, let alone all, of the capabilities discussed. Further, it may be possible for an effect noted above to be achieved by means other than that noted, and a noted item/technique may not necessarily yield the noted effect.
  • FIG. 1 is a schematic top view of a pitch pattern for an example silicon via substrate.
  • FIG. 2 is an exploded schematic perspective view of an example mold assembly.
  • FIG. 3 is a schematic perspective view of a graphite mold in accordance with an embodiment of the present invention.
  • FIG. 4 is a partial schematic cross-sectional view of the graphite mold assembly of FIG. 3.
  • FIG. 5 is a schematic perspective view of the mold assembly of FIG. 2.
  • FIGS. 6A-6D are schematic views of an example manufacturing process.
  • FIG. 7 is a partial schematic top view of a portion of an example silicon via substrate manufactured in accordance with an embodiment of the present disclosure having interconnects thereon.
  • FIG. 8A is a partial schematic cross-sectional view of an example silicon via substrate with a dielectric coating.
  • FIG. 8B is a partial schematic cross-sectional view of an example silicon via substrate with a bilayer coating.
  • FIG. 9 is an example system for gas-phase material deposition.
  • FIG. 10A is a process flow diagram of an example method for manufacturing a silicon via substrate with a dielectric layer.
  • FIG. 10B is a process flow diagram of an example method for manufacturing a silicon via substrate with a bilayer coating.
  • the first layer in the bilayer coating may be an electrical insulator and the second layer in the bilayer coating may be a barrier layer preventing the liquid metal from reacting with the silicon substrate during the via fill process.
  • the first layer may be a temperature stable dielectric film (e.g., silicon dioxide) deposited to cover the silicon sidewalls, and the second layer may be a thin conductive material that acts as a barrier preventing liquid aluminum alloy from reacting with the first layer.
  • TSV filling process may include printing techniques to fill a via with a conductive paste and atomic layer deposition techniques.
  • U.S. Pat. No. 8,242,382, to van den Hoek discusses methods to create metal filled vias in ceramic substrates. The methods discussed in that patent, however, are incompatible with silicon substrates because the liquid metal used to fill the vias will react with the silicon substrate, breach the through silicon via side walls, and penetrate deep into the silicon substrate.
  • the prior art does not provide a solution which prevents a molten conductor from reacting electrically and chemically with a silicon substrate or an electrical insulating layer which is required to prevent a conductive via from electrically shorting with the substrate.
  • Other prior methods utilize copper electrodeposition chemistries to fill silicon TSVs.
  • thermo-mechanical response of the copper coating may be improved with addition of impurities to the electrodeposition chemistries.
  • the electrodeposition bath chemistry may include accelerators, suppressors and levelers.
  • accelerators, suppressors and levelers do not enable void free metal filled vias independent of the shape of the vias, while providing a hermetic seal between the metal in the via and the silicon side wall.
  • the electrodeposition plating approach requires at least one extra layer, i.e., the deposition of the copper seed layer and plating is not capable of void free filling of vias with very high aspect ratios. Hermeticity is particularly important in the case of MEMS devices that need to operate in vacuum, since the substrate forms part of the package of the MEMS device.
  • a process for manufacturing a substrate according to the disclosure begins with a silicon substrate such as a silicon disk.
  • a silicon substrate is not limited to silicon disks or wafers. Rectangular, square (e.g., coupons), oval, and other shapes are contemplated.
  • Various silicon substrates may be utilized in the process including disks having nominal diameters of 100 mm, 150 mm, 200 mm, 300 mm, and 450 mm.
  • the disk sizes may comport with industry standard silicon wafer substrates such as defined in SEMI specifications for polished silicon wafers (e.g., SEMI Ml-1107). Other sizes, silicon substrate shapes and dimensions are also contemplated.
  • thicknesses of about 0.25 mm to about 5.0 mm may be utilized in the present invention. Larger thickness silicon substrates may more easily maintain planarity during the infiltration process and also may be polished (as described below) under less strict tolerances, due to the overall thickness of the substrate. Disks may also have larger or smaller diameters than those indicated above, for example, disks of 0 50 mm and smaller, and disks of 0450 mm and larger may also be used. The disks may have an initial surface roughness tolerance of up to about 0.8 micrometers Ra average roughness or greater, prior to infiltration and polishing.
  • the silicon substrates may be obtained from a source with one or more vias already formed therethrough or therein or drilling the disks may be the first step in the process.
  • Techniques for laser, water jet, mechanical, or other drilling or plasma etching (for example the “Bosch process”) in silicon are known.
  • a C02 laser may be used to drill holes on a square 1 mm pitch pattern.
  • the laser drilling process may produce vias having substantially cylindrical dimensions, though typically the holes will have a slight taper narrowing from the entrance. Vias having various diameters may be utilized. In general, there is no limitation to the dimensions of the vias that may be filled by the infiltration process described herein.
  • Particularly desirable via diameters may be in a range from about 0.1 microns to about 150 microns. Larger vias having diameters in a range of up to about 0.25 mm or up to about 0.76 mm may be desirable for particular applications. Additionally, length to diameter aspect ratios of up to about 4:1, up to about 10: 1, up to about 20:1 and up to about 1000:1 may provide particular advantages for some applications.
  • a via of about 0.05 mm in diameter through a 1 mm thick substrate, thus having an aspect ratio of about 20:1 may be completely filled by using the methods disclosed herein.
  • Other via disk embodiments include about 0.2 mm diameter vias through a substrate of about 5 mm thick, thus having an aspect ratio of 25 : 1. It is anticipated that the present invention will effectively fill vias in silicon substrates up to about 10 mm thick and smaller diameter holes down to about 0.01 mm for aspect ratios of 1000: 1.
  • each via is approximately 0.16 mm in diameter and the exit of each via is approximately 0.12 mm in diameter.
  • Other via shapes are also contemplated, including vias having hourglass-shaped cross sections, and vias having non-circular peripheries. Hourglass shaped cross-sections may help prevent pull-out of the filled vias after infiltration.
  • Excimer laser tools that can drill holes smaller than 100 pm (e.g., as small as about 20 pm to 30 pm) in 1.5 mm thick silicon substrates may also be utilized. Care should be taken when drilling vias with lasers, to ensure complete vias through the silicon substrate material. Very small diameter vias may be drilled from both the front and the back of the silicon substrate. In such a case, a via is drilled to a depth of approximately one-half of the silicon substrate thickness. The silicon substrate is then turned over and another hole is drilled at the exact same coordinates on the other side. Mechanical alignment tolerances are typically better that about +/- 2.5 pm and possible as low as about +/- 0.5 pm. Thicker substrates may also benefit from this drilling procedure.
  • the pitch i.e., the distance between the vias
  • the pitch may also vary, depending on the application or design requirements. For example, a pattern of vias configured as a symmetrical square array having about 0.5 mm pitch (i.e., via to via spacing) may be useful for certain applications.
  • the silicon via substrate 10 is an example of a silicon substrate having a substrate surface 12 and a plurality of vias 14 therethrough.
  • 0 0.13 mm vias are arranged in a staggered symmetrical square array, wherein each adjacent row of vias is offset.
  • the depicted arrangement has a 0.25 mm pitch between adjacent rows, and a 0.5 mm pitch between non-adjacent rows.
  • Other custom pitches and via diameters are also contemplated, as are non- uniform patterns, repetitive patterns, and patterns other than rectangular arrays (e.g., nested circular bullseye patterns).
  • FIG. 2 an exploded schematic perspective view of an example mold assembly 30 is shown.
  • the mold 30 includes end plates 32, as well as side clamp plates 34.
  • the side clamp plates 34 include a plurality of flow channels 36 to aid in distribution of the infiltrant during the manufacturing process.
  • the mold plates 52 may be square plates of Barlo B-325 graphite with circular recesses to hold the disks 10, as depicted in more detail in FIG. 3. While the mold assembly 30 is configured to process silicon substrates that are in a disk shape, other mold plates may be configured to utilize other silicon substrate shapes. Both single disk mold plates 52a and multi-disk mold plates 52b configured to hold a plurality of disks 10b may be utilized.
  • the mold plates 52 generally include a housing 66 and are sized to hold the disks 10 in place around the outer edges with a retaining ring 56 held in place by a locking element 58 and, in the case of larger disks (e.g., about 300 mm and larger), are supported by pedestals 60 at or near the middle of the disks 10.
  • the mold plates 52 also may include mating surfaces 62 to mate with adjacent mold plates. The mold plates 52 are spaced from the disks to provide a cavity 64 into which molten aluminum can flow to fill any shrink voids and allow for proper filling of the vias.
  • FIG. 4 One pair of mold plates 52 and the resulting cavities 64 are depicted in FIG. 4.
  • the mold plate housing 66 may provide approximately 0.18 mm of clearance between the mold plate 52 and the disk 10 face on each side, but other clearances are contemplated.
  • One or more inlets 68 allow for the introduction of infiltrant during processing.
  • a release agent such as DAG137 or ProDag, both made by Acheson Colloids Co. of Port Huron, MI, may also be applied to the surfaces of the graphite mold.
  • silicon disks are sandwiched between the pairs of mold plates and are assembled using graphite clamps to form a mold assembly.
  • An assembled view of the mold assembly of FIG. 2 is depicted in FIG. 5.
  • FIGS. 6A-6D schematic views of an example manufacturing process are shown.
  • the graphite mold assembly 30 is placed in a steel box or can 102, which is sized to minimize the space 104 around the mold assembly 30.
  • the mold assembly 30 and the can 102 are then pre-heated to the infiltration temperature (i.e., the temperature at which the conductive material liquefies).
  • ingots of infiltrant are heated in a crucible 106 until they reach a molten state 108.
  • the can 102 is sealed with a seal 110, and a partial vacuum environment is created therein, via the removal of air via an air passage 112.
  • a fill tube 114 is then placed into the molten infiltrant 108 and a gate valve 116 thereon is opened.
  • a melt cap can be provided at the opening of the fill tube. The vacuum within the sealed can 102 quickly draws the infiltrant 108 into the can 102 where it spreads across the top of the mold assembly 50, as depicted in FIG. 6B.
  • the seal can be removed (as depicted in FIG. 6C) and the can 102, mold assembly 30, and molten infiltrant 108 are placed within an autoclave 118 (as depicted in FIG. 6D). Thereafter, the autoclave 118 is pressurized via a pressurization inlet 120 to a range from about 850 psi to about 1000 psi to ensure complete filling of the vias. Infiltration occurs as the molten infiltrant 108 is forced into the mold assembly 30, via the inlets 68.
  • a related process is described in more detail in U.S. Patent No. 6,148,899, the disclosure of which is hereby incorporated by reference herein in its entirety.
  • the alloy is injected into the top of the mold at a pressure of about 1000 psi and a temperature of approximately 700°C.
  • molten 413.0-F, A201 or 1100 aluminum alloy may be utilized.
  • Other metallic alloys, temperatures and pressures may also be used.
  • the melting point of the metallic alloy will be approximately 50 degrees Fahrenheit (F) or more below the melting point of silicon (i.e., 2577 ° F).
  • the electrically conductive material may be aluminum, aluminum alloys, gold, gold alloys, silver, silver alloys, copper, or copper alloys.
  • An alternative process includes first placing the infiltration material ingots in the can, on top of the mold, prior to heating the ingots and can. After the ingots obtain a molten state and the can is sufficiently heated, the can, mold assembly, and molten infiltrant are placed in the autoclave and the pressurization process is performed. Other temperatures and infiltration temperatures may be utilized with satisfactory results.
  • A356.2 aluminum alloy may be injected into the mold at pressures from about 850 psi to about 1500 psi. In other embodiments, infiltration pressures range from about 1000 psi to about 1400 psi, and from about 1100 psi to about 1300 psi.
  • infiltration temperatures of about 700 °C to about 800 °C, of about 725 °C to about 775 °C, and of about 740 °C to about 760 °C, for A356.2 aluminum alloy.
  • Infiltration temperatures and pressures should be sufficient to help ensure melting of the infiltrant and filling of vias, without damage to the silicon substrate (i.e., the disks 10), which may occur with over pressurization.
  • Infiltration temperatures may differ, depending on the particular infiltrant used.
  • the mold assembly may introduce the molten conductive material from solely one side of the disk. Due to pressurization of the molten material, extremely high infiltration rates may be achieved. Additionally, due to the pressurization, the process of infiltration is extremely fast, and via openings, regardless of aspect ratio, may be completely or substantially completely filled with infiltrant.
  • factors that may limit the amount of infiltration include debris remaining within the vias, insufficient temperature to cause phase change of the metal from a solid state to a molten state, or insufficient pressurization of the molten material within the mold assembly.
  • the infiltration process takes approximately one hour. Other infiltration times are contemplated, for example about 20 minutes to about four hours, about 30 minutes to about three hours, and from about one hour to about two hours.
  • the temperature is decreased and the infiltrant begins to solidify. Once the temperature drops below the solidification temperature, the mold is removed from the autoclave and allowed to cool slowly, in certain embodiments, up to 24 hours prior to de-molding.
  • Cooling times may vary from about 8 hours to over 24 hours, from about 10 hours to about 22 hours, from about 12 hours to about 20 hours, and from about 14 hours to about 18 hours. Cooling times may also be reduced by using an active chilling element or system. Increased infiltration times and cooling times may not be desirable, as total manufacturing time would be increased, but may help ensure complete filling of vias.
  • a reservoir of molten aluminum may be maintained on top of the mold assembly 50 to back fill any volume lost due to shrinkage during the cooling process.
  • the mold may be cooled under elevated pressure such as at the injection pressure of 1000 psi. Other pressures during cooling are also contemplated. Infiltration time and cooling time may, of course, vary depending on the size and shape of the silicon substrates, number of silicon substrates within the can, conductive material utilized, etc. Once sufficiently cooled, the infiltrated silicon substrates are pried from the mold assembly. The graphite molds, if undamaged, may be re-used.
  • excess aluminum (or other metallic alloys) can be removed from the surfaces of the silicon substrates to finish the silicon substrate and leave the aluminum-filled vias exposed.
  • the amount of excess aluminum should be consistent with the depth of the cavity between the silicon substrates and the adjacent graphite mold.
  • This excess aluminum can be removed by one or more of grinding, lapping, polishing, chemical mechanical polishing and etching processes.
  • the bulk of the excess material may be removed using a grinding wheel during a Blanchard grinding process.
  • the silicon substrates then may be lapped, for example, using a single-sided lap with an oil-based slurry.
  • the final polishing step is used to achieve surface finish requirements and may utilize a slurry of de-ionized water and colloidal silica. At any point during the finishing process, the parts may be inspected for cracks, as a result of mechanical or thermal stress. Surface roughness after excess material removal processes may be up to about 0.9 pm R a . In other embodiments, surface roughness in excess of 0.9 pm Ra are also contemplated. Lapping may provide a nominal 0.8 pm R a surface roughness and certain polishing techniques may achieve very low surface roughness (about 0.05 pm Ra in some cases).
  • the filled vias are exposed and form isolated regions of electrical conductivity through the silicon substrate.
  • the excess material removal processes expose the surface of a filled via to a level substantially coplanar with the substrate proximate to the via.
  • a silicon substrate such as a silicon via disk 301 has a top surface 302 and a bottom surface 304.
  • the silicon via disk 301 is penetrated by a plurality of vias 306 extending between the top surface 302 and the bottom surface 304.
  • electrically conductive pads 308 or traces 308a-b may be placed on the terminal surfaces of the vias 306.
  • the electrically conductive pads are optional and may be added in a post-process based on application requirements for the silicon via disk 301.
  • One or more electrically conductive interconnects 308a-b may be present on the top surface 302 or the bottom surface 304.
  • One or more adhesion layers, seed layers, and other layers may also be included as required or desired prior to mounting the conductive interconnects.
  • the wiring patterns are created using standard semiconductor manufacturing technologies such as physical vapor deposition to deposit a barrier and seed layer, photolithography to define the patterns, electroplating to fill the openings with conductive material, removal of the photoresist and removal of the exposed barrier and seed layers.
  • interconnects 308a-b may connect one via to a second via or from one via 306 to another electrically conductive interconnect material such as a test probe 310 that would contact the conductive interconnects 308a-b.
  • the silicon via disk 301 may also contain filled vias 306 that do not have contact pads if the connection is not utilized.
  • Known interconnect routing process such as fan-in and fan-out routing, may be utilized on the via disks manufactured in accordance with the present disclosure. Surface roughness is also a consideration. In subsequent steps of the manufacturing process, bond pads and interconnects may be present on one or both sides of the disk
  • FIGS. 8A and 8B two approaches are provided to prevent the liquid metal from attacking the via 306 side wall and the bulk silicon substrate 300.
  • the bulk silicon substrate 300 may be a portion of the silicon via disk 301 in FIG. 7.
  • a first approach depicted in FIG. 8A includes coating the silicon substrate 300 and the through via 306 sidewalls with a thin dielectric coating 311 that both isolates the metal filled vias 306 from the substrate 300 and provides a barrier preventing the liquid metal from reacting with the silicon substrate 300 during the via fill process.
  • the dielectric coating 311 may comprise materials such as silicon nitride, silicon carbide, zirconium oxide, zirconium nitride, zirconium carbide, yttrium oxide and yttrium carbide since they provide electrical insulation and do not react with liquid aluminum alloys.
  • the thickness of the dielectric coating 311 may be in range of approximately 5 nanometers (nm) to 1000 nm and may vary based on the material of the coating and the diameter and length of the vias 306.
  • the thickness of the dielectric coating 311 is typically between 50 nm and 250 nm.
  • a second approach is depicted in FIG. 8B includes coating a silicon substrate 350 and the through via sidewalls with a first layer 312 and a second layer 314, collectively called a bilayer.
  • the silicon substrate 350 may be a portion of the silicon via disk 301.
  • the first layer 312 is an electrical insulator and the second layer 314 is a barrier layer configured to prevent liquid metal from reacting with the silicon substrate 300 during the via fill process.
  • the first layer 312 may be a thin silicon dioxide dielectric covering the silicon via sidewalls.
  • the first layer 312 may is typically between 50 nm and 250 nm thick. Other thicknesses may be used based on via dimensions, as well as the thickness of the second layer 314. Other temperature stable dielectric films may also be used as the first layer 312.
  • the second layer 314 of the bilayer may be a thin conductive material configured to act as a barrier preventing liquid aluminum alloy from reacting with the first layer 312.
  • the second layer 314 may comprise tungsten, tungsten carbide, tungsten nitride, or ruthenium.
  • the second layer 314 may be conformally deposited on top of the first layer 312 ( a thin dielectric film covering the silicon via side walls).
  • a function of the second layer 314 is to withstand exposure to the liquid metal (e.g., aluminum alloy or copper alloy).
  • the second layer 314 may have a thickness in a range of approximately 5 nm to 1000 nm and may vary based on materials and via dimensions. In an example, the second layer 314 is approximately 50 nm to 250 nm thick.
  • the first layer 312 e.g., the dielectric layer
  • the second layer 314 e.g., the conductive layer
  • the first layer 312 may be deposited by (low pressure) chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other gas-phase deposition processes.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • silicon dioxide is used as the first layer 312
  • this layer can also be grown using thermal oxidation of the silicon substate.
  • the selected deposition approach will produce films that cover the complete silicon substrate surface including the via 306 sidewalls with a film that is thick enough to ensure electrical isolation between the metal filled vias and the substrate and act as a barrier preventing the metal from penetrating through the film and reacting with the substrate.
  • the coating be conformal minimizing the required film thickness, but even poor step coverage deposition processes like physical vapor deposition may be employed as long as the required minimum thickness is attained everywhere on the surface of the substrate including inside the vias.
  • poor step coverage deposition processes like physical vapor deposition may be employed as long as the required minimum thickness is attained everywhere on the surface of the substrate including inside the vias.
  • the issues associated with poor step coverage such as leading to a reentrant via side wall profile are reduced since the void free metal filling using liquid infusion is not impeded by such a reentrant profile.
  • FIG. 9 a schematic of an example system 900 for gas-phase material deposition is shown.
  • the system 900 may be used for depositing dielectric coating 311, the first layer 312 and the second layer 314.
  • the system 900 is an example of a Low-Pressure Chemical Vapor Deposition (LPCVD) furnace.
  • LPCVD Low-Pressure Chemical Vapor Deposition
  • the system 900 is only an example and not a limitation as other commercial and proprietary systems such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Plasma- Enhanced Chemical Vapor Deposition (PECVD), Plasma-Enhanced Atomic Layer Deposition (PEALD), Metal-Organic Chemical Vapor Deposition (MOCVD), and other gas-phase processes may be used.
  • ALD Atomic Layer Deposition
  • PVD Physical Vapor Deposition
  • CVD Chemical Vapor Deposition
  • PECVD Plasma- Enhanced Chemical Vapor Deposition
  • PEALD Plasma-Enhanced Atomic Layer Deposition
  • MOCVD Metal-Organic Chemical Vapor Deposition
  • the choice of gas-phase deposition system may be related to the dimensions of the vias in the substrates 904. In general, ALD systems have better performance for smaller high aspect vias.
  • the system 900 may be a flow reactor including a process chamber 902, a plurality of substrates 904 (e.g., including a silicon substrate 300), and a substrate holder 906 configured to support the substrates 904 in a vertical orientation.
  • the vertical orientation enables deposition on both sides and through the substrates 904.
  • the process chamber 902 is configured to maintain a vacuum pressure and includes an inlet port 908a and an exhaust port 908b.
  • a vacuum pump 916 is configured to create a vacuum within the chamber 902 and enable a flow of process gases over the substrates 904.
  • the process gases may be a carrier gas 910 (e.g., nitrogen) with precursor and ligand-removal reagents, generally labeled as a precursor 912 and a reactant 914.
  • the carrier gas 910 may also be used to purge the chamber 902 between process steps.
  • the process chamber 902 may be configured to process one or more substrates 904 that are oriented in a horizontal position. In a horizontal orientation, the substrates 904 will be subject to two deposition processes (i.e., one for each side of the substrates 904).
  • Heating elements may also be used to heat the process chamber 902 to a desired process temperature.
  • Other heating elements may also be used to heat the carrier gas 910, precursors 912, reactants 914, and associated gas lines to a desired temperature.
  • Precursors 912 and reactants 914 may be inserted into the carrier gas 910 based on process requirements.
  • the composition of the precursors 912, reactant 914, as well as the gas flow rates, substrate/chamber temperature, and chamber pressure may be varied to change the properties on the resulting thin film deposited on the substrates 904.
  • a method 1000 for manufacturing a silicon via substrate with a dielectric layer includes the stages shown.
  • the method 1000 is, however, an example only and not limiting.
  • the method 1000 may be altered, e.g., by having stages added, removed, rearranged, combined, performed concurrently, and/or having single stages split into multiple stages.
  • the method 1000 includes depositing a dielectric coating on a silicon substrate having a plurality of open vias, each via extending from a first side of the silicon substrate to a second side of the silicon substrate, and having at least a first opening at the first side of the substrate.
  • a gas-phase material deposition system 900 may be a means for depositing the dielectric coating.
  • the silicon substrate may be a silicon wafer with standard dimensions (e.g., based on SEMI Ml-1107 specifications). Other sizes, substrate shapes and dimensions may also be used.
  • the silicon substrate may include a plurality of vias including through-vias (e.g., which extend through both sides of the substrate), and blind-vias (e.g., which do not extend through both sides of the substrate).
  • a C02 laser may be used to drill holes on a square 1 mm pitch pattern. The laser drilling process may produce vias having substantially cylindrical dimensions, though typically the holes will have a slight taper narrowing from the entrance. Vias having diameters of approximately 0.1 microns to 100 microns may be utilized. Larger via diameters such as in a range from about 0.025 mm to about 0.15 mm may be used. Other size vias having diameters in a range of up to about 0.25 mm or up to about 0.76 mm may be desirable for particular applications.
  • the backside of the blind-vias may be exposed by removing a portion of the substrate on the backside (e.g., via grinding, polishing, lapping, etching, etc.).
  • the silicon substrate 300 may be processed in the gas-phase material deposition system 900.
  • the system 900 may be configured to generate a dielectric coating 311 comprised of materials such as silicon nitride, silicon carbide, zirconium oxide, zirconium nitride, zirconium carbide, yttrium oxide and yttrium carbide.
  • Other coatings which provide electrical insulation and do not react with liquid aluminum or other metallic alloys may also be used.
  • silicon dioxide is not compatible with liquid aluminum and thus should not be used for generating aluminum filled vias.
  • silicon dioxide may be used for other alloys, such as silver and gold alloys, because these alloys will not diffuse through or react with silicon dioxide.
  • the method 1000 includes melting an electrically conductive material.
  • the crucible 106 may be a means for melting the electrically conductive material.
  • the electrically conductive material may be A365.2 aluminum alloy, which is heated to temperatures of about 700 °C to about 800 °C, of about 725 °C to about 775 °C, and of about 740 °C to about 760 °C. Other infiltration temperatures may be used depending on the particular infiltrant used.
  • the method 1000 includes exposing at least one surface of the coated silicon substrate to the molten electrically conductive material under conditions of elevated pressure and temperature, such that the electrically conductive material flows into the plurality of open vias in a molten state free of solid state material to fill the plurality of open vias.
  • the mold assembly 30 may be a means for exposing the at least one surface of the coated silicon substrate.
  • the silicon substrate 300 receives a dielectric coating at stage 1002 to generate the coated silicon substrate.
  • the molten electrically conductive material may be injected into the top of the mold 30 at a pressure of about 1000 psi and a temperature of approximately 700°C.
  • the molten electrically conductive material may be molten 413.0-F, A201 or 1100 aluminum alloy.
  • An alternative process may include first placing the infiltration material ingots in the can, on top of the mold, prior to heating the ingots and can. After the ingots obtain a molten state and the can is sufficiently heated, the can, mold assembly, and molten infiltrant are placed in the autoclave and the pressurization process is performed. Other temperatures and infiltration temperatures may be utilized with satisfactory results.
  • a method 1050 for manufacturing a silicon via substrate with a bilayer coating includes the stages shown.
  • the method 1050 is, however, an example only and not limiting.
  • the method 1050 may be altered, e.g., by having stages added, removed, rearranged, combined, performed concurrently, and/or having single stages split into multiple stages.
  • the method 1050 includes depositing an insulating coating on a silicon substrate having a plurality of open vias, each via extending from a first side of the silicon substrate to a second side of the silicon substrate, and having at least a first opening at the first side of the substrate.
  • a gas-phase material deposition system 900 may be a means for depositing the insulating coating.
  • the silicon substrate may be a silicon wafer with standard dimensions (e.g., based on SEMI Ml-1107 specifications). Other sizes, substrate shapes and dimensions may also be used.
  • the silicon substrate 300 may include a plurality of vias including through-vias (e.g., which extend through both sides of the substrate), and blind-vias (e.g., which do not extend through both sides of the substrate) as previously described.
  • the silicon substrate 300 may be processed in the gas-phase material deposition system 900.
  • the system 900 may be configured to generate the first layer 312 as an insulating coating comprised of materials such as silicon dioxide, silicon nitride, silicon carbide, zirconium oxide, zirconium nitride, zirconium carbide, yttrium oxide and yttrium carbide. Other coatings which provide electrical insulation may also be used.
  • the method 1050 includes depositing a barrier coating on the insulating coating on the silicon substrate 300.
  • a gas-phase material deposition system 900 may be a means for depositing the barrier coating.
  • the barrier coating is the second layer 314 of the bilayer coating.
  • the barrier coating may be a thin conductive material configured to act as a barrier preventing liquid aluminum alloy (or other metallic alloys) from reacting with the insulating coating (i.e., the first layer 312) deposited at stage 1052.
  • the barrier coating may comprise tungsten, tungsten carbide, tungsten nitride, or ruthenium.
  • the barrier coating is conformally deposited on top of the insulating coating on the silicon substrate (e.g., the thin dielectric film covering the silicon via side walls deposited at stage 1052).
  • the method 1050 includes melting an electrically conductive material.
  • the crucible 106 may be a means for melting the electrically conductive material.
  • the electrically conductive material may be A365.2 aluminum alloy, which is heated to temperatures of about 700 °C to about 800 °C, of about 725 °C to about 775 °C, and of about 740 °C to about 760 °C. Other infiltration temperatures may be used depending on the particular infiltrant used.
  • the method 1050 includes exposing at least one surface of the coated silicon substrate to the molten electrically conductive material under conditions of elevated pressure and temperature, such that the electrically conductive material flows into the plurality of open vias in a molten state free of solid state material to fill the plurality of open vias.
  • the mold assembly 30 may be means for exposing the at least one surface of the coated silicon substrate.
  • the silicon substrate 300 receives an insulating coating at stage 1052, followed by the barrier coating at stage 1054 to generate the coated silicon substrate.
  • the molten electrically conductive material may be injected into the top of the mold 30 at a pressure of about 1000 psi and a temperature of approximately 700°C.
  • the molten electrically conductive material may be molten 413.0-F, A201 or 1100 aluminum alloy. Other molten alloys may also be used.
  • An alternative process may include first placing the infiltration material ingots in the can, on top of the mold, prior to heating the ingots and can. After the ingots obtain a molten state and the can is sufficiently heated, the can, mold assembly, and molten infiltrant are placed in the autoclave and the pressurization process is performed. Other infiltrants and infiltration temperatures may be utilized with satisfactory results.
  • An example method of manufacturing a silicon via substrate includes providing a silicon substrate having defined therethrough or therein at least two vias coated with a single or bilayer that isolates the substrate from the metal filled vias and acts as a barrier against a reaction between the substrate and the metal in the metal filled via, providing an electrically conductive material, and exposing at least one surface of the substrate with vias exposed in that surface to the electrically conductive material under conditions of elevated pressure and temperature, such that the electrically conductive material flows in a molten state to substantially fill the at least two vias, thereby forming at least two isolated regions of electrical conductivity through or partially through the substrate.
  • the vias may be formed by at least one of wet chemical etching, plasma etching, electrochemical etching laser drilling, wateqet drilling, and mechanical drilling.
  • the surface of the substrate and the surface of the via side walls may be coated with an electrically insulating layer electrically isolating the vias from the substrate.
  • the insulating layer may not react or intermix with the liquid metal during the infusion step.
  • a second layer may be deposited on top of the insulating layer that does not react or intermix with the liquid metal during the infusion step.
  • the melting point of the electrically conductive material will be approximately 50 degrees Fahrenheit (F) or more below the melting point of silicon (i.e., 2577 ° F).
  • the electrically conductive material may be aluminum, aluminum alloy, gold, silver, copper, or copper alloys.
  • the method may further include placing the substrate in a mold and heating prior to pressurizing.
  • the mold may be graphite.
  • the exposing stage may include first heating the substrate and pressurizing the electrically conductive material.
  • the electrically conductive material may be removed from a surface of the substrate between the at least two vias.
  • the conductive material may be removed by grinding, lapping, polishing, chemical mechanical polishing, etching, and combinations therein.
  • the electrically conductive material may be removed from the surface of the substrate to leave an exposed surface of conductive material within a via substantially coplanar with the surface of the substrate proximate to the via.
  • a bond pad may be electrically connected to at least one via.
  • a conductive metal interconnect may be provided on one side of the substrate in a predetermined pattern.
  • An example of a silicon via substrate includes at least two vias therethrough, and an electrically conductive material disposed in each of the vias, such that the electrically conductive material flows into the vias in a molten state under conditions of elevated pressure and temperature, such that the electrically conductive material substantially fills the at least two vias, thereby forming at least two isolated regions of electrical conductivity into or through the substrate.
  • the substrate is silicon and the vias may be formed by at least one of wet chemical etching plasma etching, electrochemical etching, laser drilling, waterjet drilling, and mechanical drilling.
  • the electrically conductive material may be selected from the group consisting of aluminum, aluminum alloy, gold, silver, copper, and copper alloy.
  • a surface of the substrate between the at least two vias may be characterized by an absence of electrically conductive material.
  • the exposed surfaces of the conductive material within the at least two vias may be substantially coplanar with the surface of the substrate between the at least two vias.
  • the silicon via substrate may be a disk with a nominal diameter of 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm.
  • the silicon via substrate may have a nominal thickness of about 0.25 mm to about 5 mm.
  • the silicon via substrate may a surface roughness of up to about 0.8 micrometers Ra.
  • the two vias may have a nominal diameter of up to about 0.25 mm.
  • a length to diameter aspect ratio may be up to about 1000: 1.
  • a plurality of electrically conductive vias may be arranged in a symmetrical array with via to via spacing of up to about 5 mm.
  • the silicon via substrate may include a bond pad electrically connected to at least one via.
  • the silicon via substrate may include a layer of conductive metal interconnect disposed on one side of the substrate in a predetermined pattern.
  • An example of method according to the disclosure includes placing pre-drilled silicon substrates into a metal can in a stacked, inter-disposed assembly with a corresponding number of graphite molds.
  • Aluminum infiltration ingots are also added.
  • the can is heated to a temperature of approximately 700°C to melt the ingots.
  • the can is then placed in a vessel and a partial vacuum is applied. Thereafter, the molten aluminum is pressurized at approximately 1,000 psi for 20 to 30 minutes to force the molten aluminum into the mold to fill the vias.
  • the filled substrates are then cooled and removed from the can. They are separated from between the graphite molds and the flat surface faces are ground and polished to expose the filled vias.
  • one or more layers of electrical wiring patterns are applied thereto, using adhesive, seed layers, routing layers, etc. (e.g., conductive copper or other metal-filled inks to electrically connect specific vias). Bond pads may be attached to the reverse side. Thick or thin film deposition could alternatively be employed. [0062] Other examples and implementations are within the scope and spirit of the disclosure and appended claims.
  • “or” as used in a list of items prefaced by “at least one of’ or prefaced by “one or more of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C,” or a list of “one or more of A, B, or C,” or “A, B, or C, or a combination thereof’ means A or B or C or AB or AC or BC or ABC (i.e., A and B and C), or combinations with more than one feature (e.g., AA, AAB, ABBC, etc.).
  • a statement that a function or operation is “based on” an item or condition means that the function or operation is based on the stated item or condition and may be based on one or more items and/or conditions in addition to the stated item or condition.
  • configurations may be described as a process which is depicted as a flow diagram or block diagram. Although each may describe the operations as a sequential process, some operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional stages or functions not included in the figure. [0067] “About” and/or “approximately” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, encompasses variations of ⁇ 20% or ⁇ 10%, ⁇ 5%, or +0.1% from the specified value, as appropriate in the context of the systems, devices, circuits, methods, and other implementations described herein.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne des techniques de production de matériau d'un substrat de trou d'interconnexion en silicium. Un exemple de procédé de fabrication d'un substrat de trou d'interconnexion en silicium comprend le dépôt d'un revêtement diélectrique sur un substrat de silicium ayant une pluralité de trous d'interconnexion ouverts, chaque trou d'interconnexion s'étendant d'un premier côté du substrat en silicium à un second côté du substrat en silicium, et ayant au moins une première ouverture sur le premier côté du substrat en silicium, la fusion d'un matériau électroconducteur, et l'exposition d'au moins une surface du substrat en silicium revêtu au matériau électroconducteur fondu dans des conditions de pression et de température élevées, de telle sorte que le matériau électroconducteur s'écoule dans la pluralité de trous d'interconnexion ouverts dans un état fondu exempt de matériau à l'état solide pour remplir la pluralité de trous d'interconnexion ouverts.
PCT/US2020/017412 2020-02-07 2020-02-10 Procédé et appareil de production de substrat de trou d'interconnexion en silicium WO2021158241A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202016784953A 2020-02-07 2020-02-07
US16/784,953 2020-02-07

Publications (1)

Publication Number Publication Date
WO2021158241A1 true WO2021158241A1 (fr) 2021-08-12

Family

ID=77199390

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2020/017412 WO2021158241A1 (fr) 2020-02-07 2020-02-10 Procédé et appareil de production de substrat de trou d'interconnexion en silicium

Country Status (1)

Country Link
WO (1) WO2021158241A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090188707A1 (en) * 2008-01-30 2009-07-30 Van Den Hoek Willibrordus Gerardus Maria Method and Apparatus for Manufacture of Via Disk
US20100171217A1 (en) * 2004-09-02 2010-07-08 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US20120161326A1 (en) * 2010-12-23 2012-06-28 Electronics And Telecommunications Research Institute Composition for filling through silicon via (tsv), tsv filling method and substrate including tsv plug formed of the composition
WO2013123630A1 (fr) * 2012-02-22 2013-08-29 江苏物联网研究发展中心 Structure d'interconnexion à trous débouchants verticaux remplis de composé intermétallique pour boîtier tridimensionnel et procédé pour sa préparation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100171217A1 (en) * 2004-09-02 2010-07-08 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US20090188707A1 (en) * 2008-01-30 2009-07-30 Van Den Hoek Willibrordus Gerardus Maria Method and Apparatus for Manufacture of Via Disk
US20120161326A1 (en) * 2010-12-23 2012-06-28 Electronics And Telecommunications Research Institute Composition for filling through silicon via (tsv), tsv filling method and substrate including tsv plug formed of the composition
WO2013123630A1 (fr) * 2012-02-22 2013-08-29 江苏物联网研究发展中心 Structure d'interconnexion à trous débouchants verticaux remplis de composé intermétallique pour boîtier tridimensionnel et procédé pour sa préparation

Similar Documents

Publication Publication Date Title
US11756880B2 (en) Interconnect structures
US10790262B2 (en) Low temperature bonded structures
KR102552215B1 (ko) 마이크로 전자 어셈블리를 형성하는 방법
US11908739B2 (en) Flat metal features for microelectronics applications
US20240194625A1 (en) Metal pads over tsv
US20220165692A1 (en) Low temperature bonded structures
TWI436466B (zh) 直通矽晶穿孔結構及其製程
US5510655A (en) Silicon wafers containing conductive feedthroughs
Schaper et al. Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias
US10535594B2 (en) Interposer with extruded feed-through vias
US20080006938A1 (en) Method for bonding wafers to produce stacked integrated circuits
JP2001102436A (ja) 静電チャック及びその製造方法
TW201349389A (zh) 金屬膏充填方法及金屬膏充填裝置以及通孔插塞製作方法
WO2021158241A1 (fr) Procédé et appareil de production de substrat de trou d'interconnexion en silicium
CN112599491A (zh) 基于低热应力硅通孔的硅基板
EP2238612B1 (fr) Procédé et appareil de fabrication d'un disque à trous d'interconnexion
TW201336041A (zh) 用於電子元件之三維封裝之方法
US8927433B2 (en) Conductive via hole and method for forming conductive via hole
CN111081632A (zh) 一种减小热应力的硅通孔结构及其制造方法
US20240203823A1 (en) Integrated systems for cooling high powered devices and methods of manufacturing the same
US20240213082A1 (en) Member for semiconductor manufacturing apparatus, plug, and method of manufacturing plug
KR100475537B1 (ko) 금속배선 형성용 원판 및 그를 이용한 금속배선 형성 방법
JP5209106B2 (ja) 半導体デバイス製造方法
KR20040058962A (ko) 금속배선 형성용 원판 및 그를 이용한 금속배선 형성 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20917410

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20917410

Country of ref document: EP

Kind code of ref document: A1