WO2021147331A1 - 信息处理方法、以太网交换芯片以及存储介质 - Google Patents

信息处理方法、以太网交换芯片以及存储介质 Download PDF

Info

Publication number
WO2021147331A1
WO2021147331A1 PCT/CN2020/113727 CN2020113727W WO2021147331A1 WO 2021147331 A1 WO2021147331 A1 WO 2021147331A1 CN 2020113727 W CN2020113727 W CN 2020113727W WO 2021147331 A1 WO2021147331 A1 WO 2021147331A1
Authority
WO
WIPO (PCT)
Prior art keywords
information
core
slave
request
module
Prior art date
Application number
PCT/CN2020/113727
Other languages
English (en)
French (fr)
Inventor
蒋震
方沛昱
周伟
崔兴龙
Original Assignee
盛科网络（苏州）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 盛科网络（苏州）有限公司 filed Critical 盛科网络（苏州）有限公司
Priority to US17/792,720 priority Critical patent/US20230050185A1/en
Publication of WO2021147331A1 publication Critical patent/WO2021147331A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/16—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip

Definitions

  • This application relates to Ethernet data exchange technology, in particular to an information processing method, an Ethernet exchange chip and a storage medium.
  • the embodiments of the present application provide an information processing method, an Ethernet switching chip, and a storage medium.
  • the embodiment of the present application provides an information processing method, including:
  • the main IP core of the Ethernet switching chip receives the information processing request; the main IP core is one of the at least two IP cores included in the Ethernet switching chip;
  • the main IP core performs one of the following operations based on the received information processing request:
  • the first information updates its own global information table;
  • the received information processing request comes from one of the following: the processor of the switch provided with the Ethernet switch chip; the slave IP core of the Ethernet switch chip;
  • Information updates its own special information table; the received information processing request comes from the processor or the slave IP core of the Ethernet switching chip;
  • the fourth information corresponding to the information processing request from its own global information table or special information table and send it to the processor, or obtain the fifth information from the corresponding IP core and send it to The processor;
  • the fifth information is the information corresponding to the information processing request in the special information table of the corresponding slave IP core itself;
  • the slave IP cores are IP cores other than the master IP core among the at least two IP cores;
  • the global information table is used to store information associated with all IP cores of the Ethernet switching chip;
  • the special information table is used to store information associated with an IP core of the Ethernet switching chip.
  • the method further includes:
  • the main IP core judges the IP core associated with the information processing request according to a first preset policy, and obtains a first judgment result
  • the information processing request is a message information learning request sent from the IP core; the method further includes:
  • the main IP core responds to the received message information learning request, performs a self-learning operation corresponding to the message information learning request, and obtains a message information learning result;
  • the master IP core determines the message information learning result as the first information , Update its own global information table according to the first information, and send the first information to each slave IP core of the Ethernet switching chip, so that each slave IP core can according to the first information Update its own global information table;
  • the master IP core determines that the message information learning result is the second And send the second information to the corresponding slave IP core, so that the corresponding slave IP core can update its own special information table according to the second information.
  • the message information learning request is sent from the IP core to the master IP core:
  • the IP core did not query the message processing strategy corresponding to the received message in its own global information table or special information table;
  • the slave IP core fails to process the received message according to the message processing strategy corresponding to the received message queried in its own global information table or special information table.
  • the information processing request is an information update request sent by the processor; the method further includes:
  • the master IP core determines the analysis result as the first information, and according to the first information An information updates its own global information table, and sends the first information to each slave IP core of the Ethernet switching chip, so that each slave IP core can update its own global information according to the first information surface;
  • the main IP core determines the analysis result as the second information, and according to The second information updates its own special information table;
  • the master IP core determines the analysis result as the third information, and sends all the information.
  • the third information is given to the corresponding slave IP core, so that the corresponding slave IP core can update its own special information table according to the second information.
  • the information processing request is an information reading request sent by the processor; the method further includes:
  • the main IP core will retrieve information from its own global information table based on the information read request.
  • the acquired information corresponding to the information read request is determined to be the fourth information, and the fourth information is sent to the processor;
  • the main IP core will retrieve its own special information based on the information read request.
  • the information corresponding to the information read request obtained in the table is determined to be the fourth information, and the fourth information is sent to the processor;
  • the master IP core sends the information read request to the corresponding slave IP core to The fifth information returned by the corresponding slave IP core in response to the information read request is acquired and sent to the processor.
  • the method further includes:
  • the master IP core exchanges information with each slave IP core through a first interface set by itself and a second interface set on each slave IP core.
  • the embodiment of the present application also provides an Ethernet switching chip, the Ethernet switching chip includes at least two IP cores; one of the at least two IP cores is the main IP core; the at least two IPs The other IP cores in the core except the master IP core are slave IP cores; among them,
  • the main IP core is configured as:
  • the first information updates its own global information table;
  • the received information processing request comes from one of the following: the processor of the switch provided with the Ethernet switch chip; the slave IP core of the Ethernet switch chip;
  • Information updates its own special information table; the received information processing request comes from the processor or the slave IP core of the Ethernet switching chip;
  • the fourth information corresponding to the information processing request from its own global information table or special information table and send it to the processor, or obtain the fifth information from the corresponding IP core and send it to The processor;
  • the fifth information is the information corresponding to the information processing request in the special information table of the corresponding slave IP core itself;
  • the global information table is used to store information associated with all IP cores of the Ethernet switching chip; the special information table is used to store information associated with one IP core of the Ethernet switching chip.
  • An embodiment of the present application also provides an Ethernet switching chip, including: a processor and a memory configured to store a computer program that can run on the processor;
  • the processor is configured to execute the steps of any of the foregoing methods when running the computer program.
  • the embodiment of the present application also provides a storage medium, the medium stores a computer program, and the computer program implements the steps of any of the foregoing methods when the computer program is executed by a processor.
  • the main IP core of the Ethernet switching chip receives an information processing request, and performs one of the following operations based on the received information processing request: updating its own global information according to the first information corresponding to the information processing request Table, and send the first information to each slave IP core of the Ethernet switching chip, so that each slave IP core can update its own global information table according to the first information; process according to the information Request the corresponding second information to update its own special information table, or send the third information corresponding to the information processing request to the corresponding slave IP core, so that the corresponding slave IP core can update its own information according to the third information.
  • Special information table based on the information processing request, obtain the fourth information corresponding to the information processing request from its own global information table or special information table and send it to the processor, or obtain the fifth information from the corresponding IP core and Sent to the processor;
  • the master IP core is one of the at least two IP cores included in the Ethernet switching chip;
  • the slave IP core is the at least two IP cores Other IP cores other than the master IP core;
  • the information processing request received by the master IP core comes from the processor or the slave IP core of the Ethernet switch chip;
  • the processor is provided with the Ethernet switch chip
  • the processor of the switch the global information table is used to store information associated with all IP cores of the Ethernet switch chip;
  • the special information table is used to store information related to an IP core of the Ethernet switch chip Linked information;
  • the fifth information is the information corresponding to the information processing request in the special information table of the corresponding slave IP core itself.
  • the solution of the embodiment of the present application configures a master-slave mode for at least two IP cores included in the Ethernet switching chip, and the master IP core communicates with the processor of the switch provided with the Ethernet switching chip, and communicates through the master IP
  • the core realizes the synchronization update of the global information table of itself and each slave IP core. In this way, the operation of each IP core in the dual-core or multi-core Ethernet switching chip will not conflict, and further enable dual-core or multi-core Ethernet switching
  • the external system behavior of the chip is the same as that of a single-core Ethernet switching chip.
  • Figure 1 is a schematic diagram of the structure of a dual-core Ethernet switching chip in related technologies
  • FIG. 2 is a schematic flowchart of an information processing method according to an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a switch according to an application embodiment of this application.
  • FIG. 4 is a schematic structural diagram of an Ethernet switching chip according to an embodiment of the application.
  • FIG. 5 is a schematic diagram of the hardware structure of an Ethernet switch chip according to an embodiment of the application.
  • each IP core It's exactly the same.
  • the system behavior displayed by the chip during work should not make other terminals or servers perceive whether the chip architecture is single-core or dual-core or multi-core.
  • Core design for example, other terminals or servers perceive that there are conflicts or inconsistent delays in packets forwarded by each IP core of the chip). Therefore, information synchronization between IP cores is very necessary.
  • the Ethernet switching chip when it processes a message, it needs to maintain a message processing information table (that is, to update the message processing information table), and the message processing information table is stored in the IP core for query by the IP core
  • the message processing information table is a common resource, that is, all interfaces of the IP core query the same message forwarding strategy corresponding to the received message after receiving the message.
  • Message processing information table for the IP core of a single-core Ethernet switching chip, the message processing information table is a common resource, that is, all interfaces of the IP core query the same message forwarding strategy corresponding to the received message after receiving the message.
  • Message processing information table for the IP core of a single-core Ethernet switching chip, the message processing information table is a common resource, that is, all interfaces of the IP core query the same message forwarding strategy corresponding to the received message after receiving the message.
  • the IP core not only stores an interface attribute information table and other message processing information tables that are strongly related to the interface of the IP core. , And also store the Ethernet Layer 2 Bridge Message Forwarding Information Table (FDB, Forward Database) and other message processing information tables that are weakly related to the interface of the IP core; here, the messages that are strongly related to the interface of the IP core.
  • FDB Forwarding Information Table
  • the processing information table is only stored in the corresponding IP core, and the message processing information table that is weakly related to the interface of the IP core is stored in each IP core; therefore, the message that is strongly related to the interface of the IP core
  • the processing information table can be maintained internally by the corresponding IP core without telling other IP cores; and the packet processing information table that is weakly related to the interface of the IP core needs to be maintained synchronously by all IP cores, and the storage of each IP core needs to be maintained synchronously
  • the message processing information table must be consistent.
  • the Ethernet switching chip is taped out to cover multiple product
  • the Ethernet switching chip 100 includes an IP core 110 and an IP core 120.
  • the message processing pipeline 111 and the message processing pipeline 121 are configured to be stored according to the IP core where they are located.
  • the message processing information table performs corresponding processing on the received message, and performs corresponding processing on the received message according to the stored message processing information table; the processing engine 112 and the processing engine 122 are configured to update the message of the IP core where they are located Processing information table (In actual applications, the message processing information table can also be updated by the message processing pipeline or the processor of the switch equipped with the Ethernet switching chip. Here, the message processing information table is only updated for the processing engine. The situation is illustrated by examples).
  • the message processing pipeline 111 When the Ethernet switching chip 100 needs to forward a message on the second layer of the Ethernet, if the Ethernet switching chip 100 only contains the IP core 110, the message processing pipeline 111 will query the FDB stored in the IP core 110 for the message to be forwarded The message forwarding strategy of the message; if the message processing pipeline 111 does not find the message forwarding strategy of the message to be forwarded in the FDB, the message information learning request of the message to be forwarded is sent to the processing engine 112 to trigger the processing engine 112
  • the self-learning operation enables the processing engine 112 to obtain the message information learning result of the message to be forwarded; the processing engine 112 determines the message forwarding strategy of the message to be forwarded based on the obtained message information learning result, and adds it to the storage of the IP core 110 In the FDB, the message processing pipeline 111 subsequently forwards other received messages.
  • the Ethernet switching chip 100 also includes the IP core 120. Since the FDB is a message processing information table that needs to be maintained by the IP core 110 and the IP core 120 synchronously, the processing engine 112 determines the message to be forwarded based on the obtained message information learning results.
  • the forwarding strategy When the forwarding strategy is added to the FDB stored in the IP core 110, the obtained message information learning result needs to be sent to the processing engine 122 for the processing engine 122 to add the corresponding message forwarding strategy to the IP core 120 for storage
  • the processing engine 122 of the IP core 120 receives the message information learning request of the message processing pipeline 121 to perform a self-learning operation, it is also necessary to add the determined forwarding strategy of another message to be forwarded to the message In the processing pipeline 121, the message processing pipeline 121 needs to update the FDB twice at the same time, and these two updates may conflict (for example, when the FDB is stored in a hash (Hash) mode, there may be two FDBs in the message processing pipeline 121).
  • the forwarding strategy of a message to be forwarded conflicts with the writing position).
  • the master-slave mode is configured for at least two IP cores included in the Ethernet switching chip, and the master IP core and the processor of the switch provided with the Ethernet switching chip perform processing. Communication, and realize the synchronization update of the global information table of itself and each slave IP core through the master IP core, so that the operation of each IP core in the dual-core or multi-core Ethernet switching chip will not conflict, and further make the dual-core Or the external system behavior of a multi-core Ethernet switching chip is the same as that of a single-core Ethernet switching chip.
  • the message processing information table that needs to be maintained internally by the IP core is the special information table of the IP core
  • the message processing information table that needs to be maintained by all IP cores synchronously is The global information table of each IP core; the global information table and the special information table of an IP core are collectively referred to as the message processing information table of the IP core.
  • the embodiment of the present application provides an information processing method. As shown in FIG. 2, the method includes the following steps:
  • Step 201 The main IP core of the Ethernet switching chip receives an information processing request
  • the main IP core is one of the at least two IP cores included in the Ethernet switching chip.
  • Step 202 The main IP core performs related operations based on the received information processing request.
  • the main IP core performs one of the following operations based on the received information processing request:
  • the first information updates its own global information table;
  • the received information processing request comes from one of the following: the processor of the switch provided with the Ethernet switch chip; the slave IP core of the Ethernet switch chip;
  • Information updates its own special information table; the received information processing request comes from the processor or the slave IP core of the Ethernet switching chip;
  • the fourth information corresponding to the information processing request from its own global information table or special information table and send it to the processor, or obtain the fifth information from the corresponding IP core and send it to The processor; the fifth information is the information corresponding to the information processing request in the special information table of the corresponding slave IP core itself.
  • the slave IP core is other IP cores of the at least two IP cores except the master IP core;
  • the global information table is used to store information associated with all IP cores of the Ethernet switching chip Information;
  • the special information table is used to store information associated with an IP core of the Ethernet switching chip.
  • the global information table is used to store information associated with all IP cores of the Ethernet switching chip, which means that the global information table is a message that needs to be maintained synchronously by all IP cores of the Ethernet switching chip Processing information table; such as FDB, Ethernet Layer 3 Routing Information Base (RIB, Routing Information Base), Multi-Protocol Label Switching Table (MPLS, Multi-Protocol Label Switching), Label Mapping Table (ILM, Incoming Label Map), etc.
  • the message forwarding information table such as the time synchronization counter information table, the bandwidth evaluation information table, and other public resource information tables, and the aging state information table (AST, Aging State Table) corresponding to the FDB, and other stateful message processing information tables.
  • the special information table is used to store information associated with an IP core of the Ethernet switching chip, and means that the special information represents a message processing information table that needs to be maintained internally by the corresponding IP core; for example, an interface attribute information table, so
  • the index ID contained in the interface attribute information table is the interface ID, and a specified interface must belong to a fixed IP core.
  • the global information table needs to be maintained synchronously by all IP cores of the Ethernet switch chip, which means that the global information table of each IP core needs to be consistent, so that no matter which interface of the Ethernet switch chip receives the report
  • the corresponding IP core queries the message processing strategy corresponding to the received message the query is the same global information table.
  • the main IP core Before the main IP core receives the information processing request, that is, before step 201 is executed, the main IP core needs to be determined among all the IP cores of the Ethernet switching chip.
  • the method may further include:
  • One IP core of the Ethernet switch chip is configured as a master IP core, and other IP cores of the Ethernet switch chip except the master IP core are configured as slave IP cores to obtain a master IP core and at least one IP core. From the IP core.
  • the user can configure any IP core of the Ethernet switching chip as the main IP core as needed.
  • the corresponding IP core may include a first processing module and a second processing module; the first processing module is configured to store packets according to the IP core where it is located
  • the processing information table (including the global information table and the special information table) performs corresponding processing on the received message (for example, forwarding processing, discarding processing, or processing to modify the priority field of the message);
  • the second processing module is configured to update the Message processing information table; taking the dual-core Ethernet switching chip 100 shown in FIG. 1 as an example, the first processing module may be the message processing pipeline 111 of the IP core 110 and the message processing pipeline 121 of the IP core 120;
  • the second processing module may be the processing engine 112 of the IP core 110 and the processing engine 122 of the IP core 120.
  • the corresponding IP core may include a third processing module, which is configured to communicate with the computer through a high-speed serial computer expansion bus standard (PCIe, Peripheral Component Interconnect Express) bus after its own IP core is configured as the main IP core.
  • PCIe serial computer expansion bus standard
  • the processor performs information exchange; when the user configures the original master IP core as a slave IP core and configures an original slave IP core as a new master IP core, the third processing module of the original master IP core can be connected to the processor.
  • the PCIe bus between them is disconnected, and the third processing module of the new main IP core is connected to the processor through the PCIe bus.
  • the main IP core needs to determine the IP core associated with the information processing request, that is, determine the information
  • the processing request is aimed at the global information table of each IP core, the special information table of the master IP core, or the special information table of the slave IP core; in this way, the master IP core can perform corresponding operations according to the judgment result.
  • the method may further include:
  • the main IP core judges the IP core associated with the information processing request according to a first preset policy, and obtains a first judgment result
  • the first preset policy can be set by the user as needed, for example, the IP core associated with the information processing request is determined according to the IP core identifier and the message processing information table identifier included in the information processing request; of course, The first judgment result may indicate that the information processing request is associated with all IP cores of the Ethernet switch chip, that is, the information processing request is for the global information table of each IP core; or, the first judgment The result may indicate that the information processing request is associated with the main IP core of the Ethernet switching chip, that is, the information processing request is for the special information table of the main IP core; or, the first judgment result may be It characterizes that the information processing request is associated with a slave IP core of the Ethernet switching chip, that is, the information processing request is for the special information table of the corresponding slave IP core.
  • the information processing request received by the master IP core may be a message information learning request sent from the IP core.
  • the method may further include:
  • the main IP core responds to the received message information learning request, performs a self-learning operation corresponding to the message information learning request, and obtains a message information learning result;
  • the master IP core determines the message information learning result as the first information , Update its own global information table according to the first information, and send the first information to each slave IP core of the Ethernet switching chip, so that each IP core can update according to the first information Own global information table;
  • the master IP core determines that the message information learning result is the second And send the second information to the corresponding slave IP core, so that the corresponding slave IP core can update its own special information table according to the second information.
  • the self-learning operation corresponding to the message information learning request may be the self-learning operation of information such as the source IP address, source port, destination IP address, destination port, and transport layer protocol; accordingly, the message
  • the information learning result may include information such as the source IP address, source port, destination IP address, destination port, and transport layer protocol obtained by the main IP core through self-learning operations, and the storage location of the corresponding information in the message processing information table.
  • the slave IP core may send the message information learning request to the master IP core:
  • the IP core did not query the message processing strategy corresponding to the received message in its own global information table or special information table;
  • the slave IP core fails to process the received message according to the message processing strategy corresponding to the received message queried in its own global information table or special information table.
  • the first processing module queries the packet processing information table of the IP core where it is located for the packet corresponding to the received packet.
  • the message processing strategy is to process the received message according to the queried message processing strategy; when one of the following conditions is met, the first processing module sends a message information learning request to the second IP core where it is located.
  • the first processing module fails to query the message processing strategy corresponding to the received message in the message processing information table stored in the first processing module;
  • the processing fails.
  • the slave module Since the synchronization update of the global information table in each IP core is realized by the master IP core, when the second processing module of the slave IP core (denoted as the slave module in the subsequent description) is from the IP core where it is located When the first processing module receives the message information learning request, the slave module will send the message information learning request to the second processing module of the master IP core (denoted as the master module in the subsequent description); The main module receives not only the message information learning request sent by the first processing module of the IP core where it is located, but also the message information learning request sent by the slave module; the main module receives the message information learning request after receiving the message information learning request.
  • the first processing module For example, for the forwarding processing of Ethernet Layer 2 packets, in each IP core of the Ethernet switching chip, after the first processing module receives the packet, it will pass the receiving direction when receiving the packet.
  • the interface attribute and the destination address information carried in the received message query the forwarding strategy corresponding to the received message in the FDB of the IP core of its own, so as to forward the received message; if the first processing module The corresponding forwarding strategy is not queried in the FDB, the first processing module needs to send an FDB learning request to the second processing module of the IP core where it is located; the FDB learning request is used for the second processing module to execute The FDB entry learning operation corresponding to the FDB learning request obtains the learning result; the learning result may include: forwarding address information, destination outbound interface attributes, and the storage location of the forwarding strategy corresponding to the learning result in the FDB; After obtaining the learning result, the second processing module can add the corresponding forwarding strategy (that is, the forwarding address information and the destination outbound interface attribute included in the learning result
  • FDB is a global information table
  • the slave module when the slave module receives an FDB learning request from the first processing module of the IP core where it is located, it will send the FDB learning request to the main module; the main module receives both The FDB learning request sent by the first processing module of the IP core also receives the FDB learning request sent from the module; after receiving the FDB learning request, the main module responds to the FDB learning request and executes the FDB learning request corresponding to the FDB learning request.
  • the FDB entry learning operation to obtain the learning result; use the learning result to update the FDB of the IP core where it is located; and send the learning result to each slave module of the Ethernet switching chip; each slave module receives all After the learning result is described, the learning result can be used to update the FDB of the IP core where the user is located; in this way, the FDB of each IP core is updated synchronously, and the consistency of the FDB of each IP core is maintained.
  • the user can set the information report function for each IP core in the system software of the switch as required; in this way, the main module can also pass the message information learning result through the main IP core
  • the third processing module is sent to the processor, so that the system software obtains the message information learning result from the processor and executes corresponding operations.
  • the information processing request received by the main IP core may be an information update request sent by the processor.
  • the method may further include:
  • the master IP core determines the analysis result as the first information, and according to the first information An information updates its own global information table, and sends the first information to each slave IP core of the Ethernet switching chip, so that each IP core can update its own global information table according to the first information ;
  • the main IP core determines the analysis result as the second information, and according to The second information updates its own special information table;
  • the master IP core determines the analysis result as the third information, and sends all the information.
  • the third information is given to the corresponding slave IP core, so that the corresponding slave IP core can update its own special information table according to the second information.
  • the processor may specifically be a central processing unit (CPU, Central Processing Unit) of a switch provided with the Ethernet switching chip.
  • CPU Central Processing Unit
  • the user can update the packet processing information table of each IP core through the system software of the switch.
  • the system software can read the user's information from the first location in the memory of the switch through the processor.
  • Information update request and send the information update request to the main IP core;
  • the first location can be set by the user in the system software as needed, and the first location is used to store the user's information update request ,
  • the information update request includes at least the content requested by the user to update and the storage location of the content in the message processing information table;
  • the third processing module of the main IP core receives the system software sent by the processor
  • the information update request determines the IP core associated with the information update request according to the first preset policy, and obtains the first determination result; analyzes the information update request to obtain the analysis result (that is, determine the content that the user requests to update And the storage location of the content in the message processing information table).
  • the third processing module of the main IP core may send the analysis result to the main IP
  • the first processing module of the main IP core is used for the first processing module of the main IP core to update the global information table of the main IP core according to the analysis result.
  • the third processing module of the main IP core can The analysis result is sent to the main module, and the main module sends the analysis result to each slave module. After each slave module receives the analysis result, it sends the analysis result to the IP core where it is located.
  • the third processing module of the third processing module sends the analysis result to the first processing module of the IP core where it is located, so that the first processing module can update the IP core where it is located according to the analysis result Global information table.
  • the third processing module of the main IP core may directly send the analysis result to the The first processing module of the main IP core is used for the first processing module of the main IP core to update the special information table of the main IP core according to the analysis result.
  • the first target of the master IP core may send the analysis result to the master module, and the master module sends the analysis result to the slave module of the first target slave IP core, and the slave module of the first target slave IP core After receiving the analysis result, the module sends the analysis result to the third processing module of the first target slave IP core, and the first target sends the analysis result to the third processing module of the slave IP core.
  • the first processing module of the first target slave IP core is provided for the first processing module of the first target slave IP core to update the special information table of the IP core where it is located according to the analysis result.
  • the master IP core when it needs to send the analysis result to the corresponding slave IP core, it can directly send the information update request to the corresponding slave IP core, and the corresponding slave IP core will send the information to the corresponding slave IP core.
  • the update request is parsed to obtain the analysis result, and the corresponding operation is performed; that is, the information update request can be determined as the third information and sent to the corresponding slave IP core.
  • the information processing request received by the main IP core may be an information reading request sent by the processor.
  • the method may further include:
  • the main IP core will retrieve information from its own global information table based on the information read request.
  • the acquired information corresponding to the information read request is determined to be the fourth information, and the fourth information is sent to the processor;
  • the main IP core will retrieve its own special information based on the information read request.
  • the information corresponding to the information read request obtained in the table is determined to be the fourth information, and the fourth information is sent to the processor;
  • the master IP core sends the information read request to the corresponding slave IP core to The fifth information returned by the corresponding slave IP core in response to the information read request is acquired and sent to the processor.
  • the system software on the switch can use direct memory access (DMA, Direct Memory Access) through the processor. Memory Access) to access the Ethernet switching chip; that is, the third processing module of the main IP core can receive the information read request sent by the system software through the processor, according to the first preset strategy
  • the IP core associated with the information read request is determined, and the first determination result is obtained.
  • the third processing module of the main IP core may directly obtain the global information of the main IP core.
  • the third processing module of the main IP core may also directly receive data from the main IP core. Reads the fourth information corresponding to the information read request in the special information table of, and sends the fourth information to the processor, so that the processor can write the fourth information to the switch.
  • the third location of the memory the third location can be set by the user in the system software as needed.
  • the master IP core may send the information read request to the master module, and the master module sends the information read request to the slave module of the second target slave IP core, and the second target After receiving the information read request from the slave module of the IP core, the information read request is sent to the third processing module of the second target slave IP core, and the second target slave is the third processing module of the IP core.
  • the processing module may read the fifth information corresponding to the information read request from the special information table of the second target from the IP core, and send the fifth information to the slave of the second target from the IP core.
  • the slave module of the second target slave IP core sends the fifth information to the master module, and the master module sends the fifth information to the third processing module of the master IP core ,
  • the third processing module of the main IP core sends the fifth information to the processor, so that the processor can write the fifth information to the fourth location of the memory of the switch;
  • the fourth position can also be set in the system software by the user as needed.
  • the user can also set a second preset strategy in the system software as needed, and the second preset strategy is used to make the Ethernet switch chip actively report the operating status during the operation of the switch;
  • the operating status may specifically be the operating status of each IP core, such as statistical information on the number of messages sent and received by the ports of each IP core, etc.; for each IP core, the operating status may be in the form of a status information table as one of the corresponding IP cores. Special information table; in this way, without receiving the information read request sent by the processor, the main IP core can actively send its own state information table to the processor according to the period included in the second preset strategy, and The received status information table of the corresponding slave IP core sent by each slave IP core is sent to the processor.
  • the third processing module of the main IP core may send the state information table of the main IP core to the processor, so that the processor can write the state information table of the main IP core to the processor.
  • the master module can also receive the status information table of the slave IP core where it is sent by each slave module; the status information table of the slave IP core where it is sent by each slave module is the status information table of the slave IP core where the corresponding slave module is located.
  • the third processing module Obtained and sent by the third processing module; after the master module receives a status information table from the IP core (denoted as the third target slave IP core in the subsequent description), the third target can be sent from the IP core
  • the status information table is sent to the third processing module of the master IP core, and the third processing module of the master IP core sends the status information table of the third target slave IP core to the processor for all
  • the processor writes the third target from the state information table of the IP core into the sixth location of the memory of the switch.
  • the period for the master IP core to report its own status information table and the period for each slave IP core to report its own status information table may be the same or different. Specifically, it can be specified by the user in the second preview as needed. Set in the strategy; the fifth position and the sixth position can also be set in the system software by the user as needed.
  • the master IP core updates its own global information table according to the first information corresponding to the information processing request, and sends the first information to each slave IP core of the Ethernet switching chip to
  • each slave IP core updates its own global information table according to the first information, taking into account the delay required for information interaction, that is, in order to realize that all IP cores can update its own global information table synchronously
  • the user can also update its own global information table according to
  • a third preset strategy needs to be set in the system software, and the third preset strategy is used to enable the main IP core to be in advance when the Ethernet switching chip needs to update the global information table of each IP core synchronously. Set the time delay and start to update its own global information table.
  • the third preset strategy is used to enable the main module to start updating its own global information table of the IP core according to the first information corresponding to the information processing request after a preset time delay;
  • the preset The time delay is the difference between the first time and the second time;
  • the first time is the time when the master module sends the first information to each slave IP core of the Ethernet switching chip;
  • the first time The second time is the time when each slave module of the IP core receives the first information.
  • the user can configure a pipeline with a preset number of stages in each IP core, and the pipeline with the preset number of stages is configured to achieve the preset delay; specifically, when the IP core is configured as The main IP core, and when the main IP core needs to update its own global information table according to the first information, the main module may update the global information table of the main IP core through the pipeline of the preset number of stages, That is, it is realized that the global information table of the master IP core is updated according to the first information after the preset time delay; when the IP core is configured as a slave IP core, and the slave IP core needs to receive the master IP When the core sends the first information to update its own global information table, the slave module of the slave IP core can skip the pipeline of the preset number of stages configured by the IP core where it is located, and directly update according to the first information The global information table of the slave IP core where it is located.
  • the user can determine the size of the preset delay based on the chip design requirements; for example, the user can set the preset number of stages of the pipeline configured for each IP core to 2, that is, if each IP core is configured with a 2-stage pipeline, you can It is determined that the preset time delay is 2 clock cycles, and the clock cycle is a clock cycle of a clock module of the Ethernet switching chip.
  • the main module starts to update the global information table of the main IP core according to the first information after 2 clock cycles, and at the same time, the main module sends the first information to each IP core
  • the slave module also needs 2 clock cycles, that is, the corresponding slave module receives the first information after 2 clock cycles and directly starts to update the global information table of the slave IP core where it is located; in this way, each IP core can be updated synchronously Own global information table.
  • the Ethernet switch chip needs to complete the update of the message processing information table of each IP core within a reasonable time frame, that is, the corresponding received from the module
  • the time required for the information sent by the main module must be within a reasonable time range (for example, 20 clock cycles); the user can determine the time required for the corresponding slave module to receive the information sent by the main module based on the chip design requirements,
  • the time length is set by controlling the length of the data transmission line between the modules.
  • the corresponding module in the process of updating the message processing information table, can perform operations of adding, deleting and modifying the message processing strategy in the message processing information table.
  • each IP core of the Ethernet switching chip needs to be provided with a communication interface between the IP cores, so that the master IP core and each slave IP core can exchange information through the communication interface.
  • the method may further include:
  • the master IP core exchanges information with each slave IP core through a first interface set by itself and a second interface set on each slave IP core.
  • the user can set the number of information interactions supported by the first interface and the second interface in each clock cycle as needed; for example,
  • the first interface can transmit a piece of information sent by the master IP core to the corresponding slave IP core, and receive a piece of information sent by the corresponding slave IP core; and enable the second interface to In each clock cycle, a piece of information sent by the corresponding slave IP core is delivered to the master IP core, and a piece of information sent by the master IP core is received.
  • the user can set the maximum amount of data allowed by the first interface and the second interface to nbit according to the size of the information that the master IP core and the slave IP cores need to transmit during information exchange.
  • N is a positive integer.
  • error checking and correction ECC, Error Correcting Code
  • other error correction technology can be used to make the first interface and the second
  • the information exchange carried out by the second interface is error-free communication.
  • the main IP core of the Ethernet switching chip receives the information processing request, and performs one of the following operations based on the received information processing request: updating its own global information according to the first information corresponding to the information processing request Information table, and send the first information to each slave IP core of the Ethernet switching chip, so that each slave IP core can update its own global information table according to the first information; according to the information
  • the second information corresponding to the processing request updates its own special information table, or the third information corresponding to the information processing request is sent to the corresponding slave IP core, so that the corresponding slave IP core can update itself according to the third information
  • the slave IP core receives the fifth information returned by the corresponding slave IP core in response to the information processing request and sends it to the processor; wherein the master IP core is at least two components included in the Ethernet switch chip.
  • the slave IP core is an IP core other than the master IP core among the at least two IP cores;
  • the information processing request received by the master IP core comes from the processor Or the slave IP core of the Ethernet switch chip;
  • the processor is the processor of the switch provided with the Ethernet switch chip;
  • the global information table is used to store all the IP cores of the Ethernet switch chip Associated information;
  • the special information table is used to store information associated with an IP core of the Ethernet switching chip;
  • the fifth information is the special information table of the corresponding slave IP core itself and the The information corresponding to the information processing request; in this way, the operation of each IP core in the dual-core or multi-core Ethernet switching chip will not conflict, and the external system behavior of the dual-core or multi-core Ethernet switching chip can be compared with that of the single-core Ethernet.
  • the network switch chip is the same.
  • the switch 300 includes a dual-core Ethernet switching chip 310 and a CPU 320; the Ethernet switching chip 310 includes an IP core 311 and an IP core 312; each IP core includes a packet Text processing pipeline (that is, the above-mentioned first processing module, which may be called module one), a processing engine (that is, the above-mentioned second processing module, which may be called module two), and a CPU interaction module (that is, the above-mentioned third processing module, which may be called Is module three) and one interface (that is, the above-mentioned first interface or second interface); that is, IP core 311 includes module one 3111, module two 3112, module three 3113, and interface 3114; IP core 312 includes module one 3121, module two 3122 , Module three 3123 and interface 3124; among them,
  • the module one 3111 and the module one 3121 are configured to perform corresponding processing on the received packets according to the packet processing information table of the IP core where they are located;
  • the second module 3112 and the second module 3122 are configured to update the message processing information table of the IP core where they are located; the update includes adding a message processing strategy, modifying a message processing strategy, and deleting a message processing strategy (in actual application) ,
  • the corresponding message processing information table can also be updated through the module one 3111 or the module one 3121);
  • the module three 3113 and the module three 3123 are configured to exchange information with the CPU 320 via the PCIe bus 330 or PCIe bus 340;
  • the interface 3114 and the interface 3124 are configured to realize the information exchange between the two modules, that is, to realize the information exchange between the IP cores.
  • module two 3112 is the master module, and module two 3122 is the slave module; correspondingly, the IP core 311 is the master IP core, and the IP core 312 is the slave IP core; the IP core 311 communicates with the CPU 320 through the PCIe bus 330
  • the PCIe bus 340 connected to the IP core 312 is not connected to the CPU 320; when the master and slave modules need to be switched, that is, when the module 2 3122 is configured as the master module and the module 2 3112 is configured as the slave module, the PCIe bus 330 needs to be disconnected
  • the connection with the CPU 320 and the PCIe bus 340 to the CPU 320 enable the IP core 312 to act as the main IP core to exchange information with the CPU 320.
  • IP core 311 exchanges information with CPU 320 through PCIe bus 330, and PCIe bus 340 to which IP core 312 is connected is not connected to CPU 320 (that is, module two 3112 is the master module, module two 3122 is the slave module, and IP core 311 is the master IP core, IP core 312 is the slave IP core)” and “IP core 312 exchanges information with CPU 320 through PCIe bus 340, and PCIe bus 330 connected to IP core 311 is not connected to CPU 320 (that is, module 2 3122 is the main module, module The second 3112 is the slave module, the IP core 312 is the main IP core, and the IP core 311 is the slave IP core)”. There is no substantial difference.
  • This application example only uses “the IP core 311 communicates information with the CPU 320 through the PCIe bus 330, and IP The PCIe bus 340 to which the core 312 is connected is not connected to the CPU 320 (that is, the module two 3112 is the master module, the module two 3122 is the slave module, the IP core 311 is the master IP core, and the IP core 312 is the slave IP core)” as an example.
  • the information processing method of this application embodiment can include three types of table item maintenance: internal table item maintenance of the master IP core 311 (that is, the master IP core 311 updates its own special information table), and the slave
  • the maintenance of the internal entries of the IP core 312 that is, the update of its own special information table from the IP core 312
  • the synchronization of the entries of the master IP core 311 and the slave IP core 312 that is, the master IP core 311 and the slave IP core 312 are based on the same Information also updates its own global information table).
  • the maintenance of the internal table items of the IP core can be the maintenance of the message processing information table (that is, the above-mentioned special information table) that is strongly related to the interface, such as the interface attribute information table, and the index ID contained in the interface attribute information table It is the interface ID, and for a specified interface, it must belong to a fixed IP core;
  • the table entry maintenance of the master IP core and the slave IP core synchronization can be the processing information table of the packet weakly related to the interface (that is, the above-mentioned global information table) Maintenance, such as FDB, RIB, MPLS, ILM and other message forwarding information tables, and public resource information tables such as time synchronization counter information tables, bandwidth evaluation information tables, and stateful message processing information tables such as AST corresponding to FDB ;
  • the message processing information table that needs to be maintained synchronously needs to be globally consistent, that is, the main IP core storage needs to
  • the working mechanism of the main module includes: the main module 3112 receives the information processing request from module one 3111 or the information processing request sent by the CPU 320 through module three 3113, performs corresponding information processing, and obtains the processing result; and writes the processing result Return to module one 3111 (that is, update the message processing information table of the master IP core 311 through module one 3111); and/or notify the slave module 3122 of the processing result through the interface 3114 and the interface 3124, and the slave module 3122 writes the processing result into the module One 3121 (that is, the message processing information table of the slave IP core 312 is updated through the module one 3121); and/or the processing result is reported to the CPU 320 through the module three 3113 and the PCIe bus 330.
  • the working mechanism of the slave module includes: the slave module 3122 receives the information processing request of the module one 3121, and sends the information processing request to the master module 3112 through the interface 3124 and the interface 3114; the master module 3112 receives the information processing request , Perform the corresponding information processing, and obtain the processing result; the main module 3112 writes the processing result into the module one 3111 (that is, the message processing information table of the main IP core 311 is updated through the module one 3111), and the processing result is passed through the interface 3114 and interface 3124 informs the slave module 3122 that the slave module 3122 writes the processing result back to the module one 3121 (that is, the message processing information table of the slave IP core 312 is updated through the module one 3121); and/or, the processing result is passed through the module three 3113 and the PCIe bus 330 Report to CPU 320.
  • the working mechanism of the main module and the working mechanism of the slave module may be specifically embodied in the following three application scenarios:
  • Application scenario 1 For the forwarding of Ethernet Layer 2 packets, suppose that the Ethernet switch chip 310 is a single-core Ethernet switch chip and only contains the IP core 311. Then, after the module 3111 of the IP core 311 receives the message, Query the FDB stored in the IP core 311 through the attributes of the receiving direction interface and the destination address information carried in the received message to forward the received message; but if the corresponding information is not queried in the FDB, module 1 3111 A FDB learning request needs to be sent to the second module 3112.
  • the learning sub-module in the second module 3112 receives the FDB learning request, performs the corresponding FDB entry learning operation, and obtains the learning result; the learning result includes: forwarding address information, purpose Outbound interface attributes and the location information that the learning result should be stored in FDB; module two 3112 returns the obtained learning result to module one 3111, and module one will combine the information in the learning result (i.e. forwarding address information and destination outbound interface attribute) ) Is added to the location stored in the FDB included in the learning result to complete the update of the FDB; the updated FDB is used to forward the received message when the subsequent module 3111 receives the message.
  • the learning result includes: forwarding address information, purpose Outbound interface attributes and the location information that the learning result should be stored in FDB
  • module two 3112 returns the obtained learning result to module one 3111, and module one will combine the information in the learning result (i.e. forwarding address information and destination outbound interface attribute) ) Is added to the location stored in the FDB included in the learning result to complete
  • the Ethernet switch chip 310 Since the Ethernet switch chip 310 only contains the IP core 311, the process of module two 3112 returning the learning results to the module one 3111 is very simple; however, the Ethernet switch chip 310 is actually a dual-core Ethernet switch chip, including the IP core 311 and IP core 312; since each IP core has a module two, and FDB is a message processing information table that needs to be maintained globally, if module one 3111 triggers the entry learning operation of module two 3112, the learning result is obtained, module When the second 3112 returns the learning result to the module one 3111, it needs to send the learning result to the module two 3122, and the module two 3122 sends the learning result to the module one 3121, so that the module one 3121 can update its own information synchronously with the module one 3111.
  • module two 3122 is also processing the FDB learning request sent by module one 3121 and obtains another learning result
  • module two 3122 returns another learning result to module one 3121
  • the FDB of the master IP core 311 and the FDB of the slave IP core 312 should be updated by using the working mechanism of the master module and the working mechanism of the slave module.
  • the module one 3111 of the main IP core 311 triggers the FDB entry learning operation of the main module 3112, the main module 3112 completes the FDB entry learning operation, obtains the learning result, and returns the learning result to the module one 3111 At the same time, the learning result is sent to the slave module 3122, and the slave module 3122 sends the learning result to the module one 3121.
  • the module 1 3121 of the IP core 312 sends an FDB learning request to the slave module 3122, and the slave module 3122 sends the received FDB learning request to the master module 3112, and the master module 3112 completes the corresponding FDB entry learning Operate to obtain the learning result; the master module 3112 sends the learning result to the module one 3111, and at the same time, sends the learning result to the slave module 3122, and the slave module 3122 returns the learning result to the module one 3121.
  • Application scenario 2 During the operation of the switch 300, the system software on the switch 300 will provide users with the operating status of the switch 300.
  • the operating status of the switch 300 includes at least the operating status of the Ethernet switch chip 310 and the operation of the Ethernet switch chip 310. The status needs to be actively provided by the Ethernet switch chip 310 to the system software.
  • the system software summarizes the operating status of the Ethernet switch chip 310 and then displays it to the user; the operating status of the Ethernet switch chip 310 includes each IP
  • the operating status of the core such as statistics on the number of packets sent and received on the port.
  • the period and time that the master IP core 311 and the slave IP core 312 provide the operating state can be the same or different, and the user can set it according to needs.
  • the master IP core 311 and the slave IP core 312 send the corresponding operating status information (that is, the above-mentioned status information table) from the respective module one to the respective module three, but since the module three 3113 of the master IP core 311 can communicate with the CPU 320
  • the module 3123 of the slave IP core cannot exchange information with the CPU 320; therefore, the module 3113 can directly send the operating status information in the module 1 3111 to the CPU 320 through the PCIe bus 330, so that the CPU 320 can transfer the master IP
  • the operating status information of the core is written into the system memory (that is, the memory of the switch 300) in the designated location of the system software; and the module 3123 needs to send the operating status information of the IP core to the slave module 3122, and the slave module 3122 will The operating status information of the IP core is sent to the main module 3112 through the interface 3124 and the interface 3114.
  • the main module 3112 then sends the operating status information of the IP core to the module three 3112, and the module three 3112 will pass the operating status information of the IP core through PCIe
  • the bus 330 is sent to the CPU 320, so that the CPU 320 writes the operating status information of the IP core into a location designated by the system software in the system memory.
  • Application scenario 3 The CPU 320 establishes a connection with the Ethernet switch chip 310 through the PCIe bus, so that the system software can access the Ethernet switch chip 310 by way of DMA.
  • the module three 3113 of the main IP core 311 is responsible for receiving the DMA request sent by the system software through the CPU 320, and the DMA request includes at least a read request and a write request.
  • the DMA request is a read request
  • the read request is for a message processing information table maintained synchronously by the master IP core 311 and the slave IP core 312, or the read request is for a message maintained internally by the master IP core 311
  • the message processing information table, module three 3113 only needs to read the corresponding information in the message processing information table of the main IP core 311 through module one 3111, and send the read information to the CPU 320 for the CPU 320 to read The information is written to the location specified by the system software in the system memory. If the read request is for the message processing information table maintained internally by the slave IP core 312, module three 3113 needs to send the read request to the master module 3112, and the master module 3112 sends the read request to the slave module 3122.
  • the module 3122 then sends the read request to the module three 3123, and the module three 3123 processes the read request.
  • the module one 3121 reads the corresponding information from the message processing information table of the IP core 312, and reads The obtained result information is sent to the slave module 3122, and the slave module 3122 sends the result information to the main module 3112.
  • the master module 3112 then returns the result information to the module three 3113, and the module three 3113 sends the result information to
  • the CPU 320 allows the CPU 320 to write the result information into a location designated by the system software in the system memory.
  • module three 3113 obtains the data to be written from the location specified by the system software in the system memory (here, the data to be written may be regarded as the write request, and the write request includes the user through the System software input data). First, module three 3113 sends the data to be written to the main module 3112, and at the same time, sends the data to be written into a pipeline with a specified number of stages. The exit of the pipeline is module one.
  • the main module 3112 sends the data to be written to the slave module 3122 through the interface 3114 and the interface 3124, and the slave module 3122 sends the data to be written to the module three 3123, and the module three 3123 skips the designation of the configuration from the IP core
  • the pipeline of stages directly sends the data to be written to module one 3121 to directly update the message processing information table of the IP core 312; here, it is assumed that the time when the main module 3112 sends the data to be written to the interface 3114 Is time one, the time when the module one 3121 receives the data to be written is time two, and the time difference between time two and time one is X clock cycles of the Ethernet switch chip 310, then it can be determined that the main IP core
  • the number of stages in the pipeline of the specified number of stages is X.
  • the master IP core 311 and the slave IP core 312 can implement synchronous maintenance of the message processing information table. If the write request is for the message processing information table maintained internally by the main IP core 311, after module three 3113 obtains the data to be written from the location specified by the system software in the system memory, it can skip the configuration in the main IP core 311 The pipeline with the specified number of stages directly sends the data to be written to the module one 3111, so that the module one 3111 directly updates the message processing information table maintained internally by the corresponding main IP core 311.
  • module three 3113 obtains the data to be written from the location specified by the system software in the system memory, it sends the data to be written to the host Module 3112, the master module sends the data to be written to the slave module 3122 through the interface 3114 and the interface 3124, and the slave module 3122 sends the data to be written to the module three 3123, and the module three 3123 skips the slave IP core
  • the configured pipeline with the specified number of stages directly sends the data to be written to the module one 3121, so that the module one 3121 updates the corresponding message processing information table maintained internally from the IP core 312.
  • Ethernet switch chip 310 and the information processing method provided by this application embodiment have the following advantages:
  • the embodiment of the present application also provides an Ethernet switching chip.
  • the Ethernet switching chip 400 includes at least two IP cores; the at least two IP cores One of the IP cores in the IP core is the master IP core 401; the other IP cores in the at least two IP cores except the master IP core are the slave IP cores 402; wherein,
  • the main IP core 401 is configured as:
  • the first information updates its own global information table;
  • the received information processing request comes from one of the following: the processor of the switch provided with the Ethernet switch chip; the slave IP core 402 of the Ethernet switch chip;
  • the third information updates its own special information table; the received information processing request comes from the processor or the slave IP core 402 of the Ethernet switch chip;
  • the fourth information corresponding to the information processing request from its own global information table or special information table and send it to the processor, or obtain the fifth information from the corresponding IP core 402 and send it To the processor;
  • the fifth information is the information corresponding to the information processing request in the special information table of the corresponding slave IP core 402 itself;
  • the global information table stores information associated with all IP cores of the Ethernet switch chip; the special information table is used to store information associated with one IP core of the Ethernet switch chip.
  • the main IP core 401 is configured as:
  • the information processing request is a message information learning request sent from the IP core 402, and the main IP core 401 is configured to:
  • the message information learning result is determined as the first information, and according to the first information Update its own global information table with information, and send the first information to each slave IP core 402 of the Ethernet switching chip, so that each IP core 402 can update its own global information according to the first information Information Sheet;
  • the message information learning result is determined to be the second information, and sent The second information is given to the corresponding slave IP core 402, so that the corresponding slave IP core 402 can update its own special information table according to the second information.
  • the message information learning request is sent from the IP core 402 to the master IP core 401:
  • the IP core 402 fails to query the message processing strategy corresponding to the received message in its own global information table or special information table;
  • the slave IP core 402 fails to process the received message according to the message processing strategy corresponding to the received message queried in its own global information table or special information table.
  • the information processing request is an information update request sent by the processor, and the main IP core 401 is configured to:
  • the analysis result is determined to be the first information, and its own information is updated according to the first information.
  • Global information table and sending the first information to each slave IP core 402 of the Ethernet switching chip, so that each IP core 402 can update its own global information table according to the first information;
  • the analysis result is determined to be the second information, and according to the second information Information updates its own special information table;
  • the analysis result is determined to be the third information, and the third information is sent
  • the corresponding slave IP core 402 is provided for the corresponding slave IP core 402 to update its own special information table according to the second information.
  • the information processing request is an information read request sent by the processor, and the main IP core 401 is configured to:
  • the first judgment result indicates that the information read request is associated with all IP cores of the Ethernet switch chip, based on the information read request, the information obtained from its own global information table Determining that the information corresponding to the read request is the fourth information, and sending the fourth information to the processor;
  • the first judgment result indicates that the information read request is associated with the main IP core 401 of the Ethernet switch chip, based on the information read request, the information obtained from its own special information table Determining that the information corresponding to the information read request is the fourth information, and sending the fourth information to the processor;
  • the information read request is sent to the corresponding slave IP core 402 to obtain the
  • the fifth information returned from the IP core 402 in response to the information read request is sent to the processor.
  • the main IP core 401 is configured as:
  • the master IP core 401 and the slave IP core 402 can be implemented by processors in the Ethernet switch chip 400.
  • Ethernet switch chip 400 provided in the above embodiments are illustrated only by the division of the above program modules. In actual applications, the above processing can be allocated to different program modules according to needs. , That is, divide the internal structure of the device into different program modules to complete all or part of the processing described above.
  • Ethernet switch chip 400 provided in the foregoing embodiment belongs to the same concept as the method embodiment, and its specific implementation process is detailed in the method embodiment, which will not be repeated here.
  • the embodiment of the present application also provides an Ethernet switch chip.
  • the Ethernet switch chip 50 includes a memory 52 and a processor 51. And a computer program stored on the memory 52 and running on the processor 51; when the processor 51 executes the program, the method provided by one or more of the above technical solutions is implemented.
  • the main IP core of the Ethernet switch chip 50 performs the following operations through the processor 71: receiving an information processing request; performing one of the following operations based on the received information processing request: according to the information processing request corresponding to the first
  • An information updates its own global information table, and sends the first information to each slave IP core of the Ethernet switching chip, so that each slave IP core can update its own global information according to the first information Table; update its own special information table according to the second information corresponding to the information processing request, or send the third information corresponding to the information processing request to the corresponding slave IP core for the corresponding slave IP core according to the
  • the third information updates its own special information table; based on the information processing request, the fourth information corresponding to the information processing request is obtained from its own global information table or special information table and sent to the processor, or from Correspondingly obtain the fifth information from the IP core and send it to the processor;
  • the master IP core is one of the at least two IP cores included in the Ethernet switching chip;
  • the slave IP core is all The other IP cores of
  • the various components in the Ethernet switch chip 50 are coupled together through the bus system 53.
  • the bus system 53 is configured to implement connection and communication between these components.
  • the bus system 53 also includes a power bus, a control bus, and a status signal bus.
  • various buses are marked as the bus system 53 in FIG. 5; at the same time, the Ethernet switching chip 50 may also include a communication interface 54 configured to exchange information with other devices .
  • the memory 52 in the embodiment of the present application is configured to store various types of data to support the operation of the Ethernet switch chip 50. Examples of these data include: any computer program for operating on the Ethernet switch chip 50.
  • the method disclosed in the foregoing embodiment of the present application may be applied to the processor 51 or implemented by the processor 51.
  • the processor 51 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 51 or instructions in the form of software.
  • the aforementioned processor 51 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like.
  • the processor 51 may implement or execute various methods, steps, and logical block diagrams disclosed in the embodiments of the present application.
  • the general-purpose processor may be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor.
  • the software module may be located in a storage medium, and the storage medium is located in the memory 52.
  • the processor 51 reads the information in the memory 52 and completes the steps of the foregoing method in combination with its hardware.
  • the Ethernet switch chip 50 may be implemented by one or more application specific integrated circuits (ASIC, Application Specific Integrated Circuit), DSP, programmable logic device (PLD, Programmable Logic Device), and complex programmable logic device.
  • ASIC Application Specific Integrated Circuit
  • DSP digital signal processor
  • PLD programmable logic device
  • PLD Programmable Logic Device
  • complex programmable logic device Logic device (CPLD, Complex Programmable Logic Device), field programmable gate array (FPGA, Field-Programmable Gate Array), general-purpose processor, controller, microcontroller (MCU, Micro Controller Unit), microprocessor (Microprocessor) , Or implemented by other electronic components, configured to perform the foregoing method.
  • CPLD Complex Programmable Logic Device
  • FPGA field programmable gate array
  • MCU Microcontroller
  • Microprocessor Microprocessor
  • the memory (memory 52) of the embodiment of the present application may be a volatile memory or a non-volatile memory, and may also include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (ROM, Read Only Memory), programmable read-only memory (PROM, Programmable Read-Only Memory), and erasable programmable read-only memory (EPROM, Erasable Programmable Read- Only Memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory , CD-ROM, or CD-ROM (Compact Disc Read-Only Memory); magnetic surface memory can be magnetic disk storage or tape storage.
  • the volatile memory may be a random access memory (RAM, Random Access Memory), which is used as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • SSRAM synchronous static random access memory
  • Synchronous Static Random Access Memory Synchronous Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM synchronous connection dynamic random access memory
  • DRRAM Direct Rambus Random Access Memory
  • the memories described in the embodiments of the present application are intended to include, but are not limited to, these and any other suitable types of memories.
  • the embodiment of the present application also provides a storage medium, that is, a computer storage medium, specifically a computer-readable storage medium, such as a memory 52 storing a computer program, which can be exchanged by the Ethernet
  • the processor 51 of the chip 50 executes to complete the steps described in the foregoing method.
  • the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disk, or CD-ROM.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Databases & Information Systems (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • Software Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

本申请公开了一种信息处理方法、以太网交换芯片以及存储介质。其中，方法包括：主IP核心基于接收的信息处理请求执行以下操作之一：根据信息处理请求对应的第一信息更新自身的全局信息表，并发送第一信息给每个从IP核心；根据信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与信息处理请求对应的第三信息给相应从IP核心；基于信息处理请求，从自身的全局信息表或专项信息表中获取第四信息发送给处理器，或者，从相应从IP核心获取第五信息并发送给所述处理器。

Description

信息处理方法、以太网交换芯片以及存储介质
相关申请的交叉引用
本申请基于申请号为202010075094.4、申请日为2020年01月22日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及以太网数据交换技术，具体涉及一种信息处理方法、以太网交换芯片以及存储介质。
背景技术
随着超大规模云网络、存储网络及高性能计算机群(HPC，High Performance Computing)等技术的发展，网络上的数据交换量越来越大，单芯片的数据处理能力也在不断地提升：从千兆(Gbps)数量级提升到了兆兆(Tbps)数量级。但是当前生产工艺制造的单芯片尺寸为14nm/12nm或7nm/6nm，其知识产权核心(IP core，Intellectual Property core)可以运行的时钟频率最高分别在1.05GHz或1.7GHz。仅具备一个IP核心的单芯片无法满足芯片市场高达25.6Tbps的报文处理带宽的需求。从制造工程的角度来看，为了满足芯片市场对报文处理带宽的需求，在具备单一IP核心的单芯片的时钟频率受限的情况下，设计具备双IP核心或具备多个IP核心的单芯片是很有必要的。
然而，相关技术中，双核心或多核心的单芯片的信息处理方法尚需优化。
发明内容
有鉴于此，本申请实施例提供了一种信息处理方法、以太网交换芯片以及存储介质。
本申请实施例的技术方案是这样实现的：
本申请实施例提供了一种信息处理方法，包括：
以太网交换芯片的主IP核心接收信息处理请求；所述主IP核心为所述以太网交换芯片包含的至少两个IP核心中的一个IP核心；
所述主IP核心基于接收的信息处理请求执行以下操作之一：
根据所述信息处理请求对应的第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；接收的信息处理请求来自以下之一：设置有所述以太网交换芯片的交换机的处理器；所述以太网交换芯片的从IP核心；
根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；
基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给所述处理器，或者，从相应从IP核心获取第五信息并发送给所述处理器；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息；其中，
所述从IP核心为所述至少两个IP核心中除所述主IP核心外的其它IP核心；所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息。
上述方案中，所述方法还包括：
所述主IP核心根据第一预设策略判断所述信息处理请求关联的IP核心，得到第一判断结果；
根据所述第一判断结果，基于接收的信息处理请求执行相应操作。
上述方案中，所述信息处理请求为从IP核心发送的报文信息学习请求；所述方法还包括：
所述主IP核心响应接收的报文信息学习请求，执行所述报文信息学习请求对应的自学习操作，得到报文信息学习结果；
在所述第一判断结果表征所述报文信息学习请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心将所述报文信息学习结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；
在所述第一判断结果表征所述报文信息学习请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述报文信息学习结果确定为所述第二信息，并发送所述第二信息给相应从IP核心，以供所述相应从IP核心根据所述第二信息更新自身的专项信息表。
上述方案中，当满足以下条件之一时，从IP核心发送所述报文信息学习请求给所述主IP核心：
从IP核心未在自身的全局信息表或专项信息表中查询到与接收的报文相对应的报文处理策略；
从IP核心根据在自身的全局信息表或专项信息表中查询到的与接收的报文相对应的报文处理策略对所述接收的报文进行相应处理时处理失败。
上述方案中，所述信息处理请求为所述处理器发送的信息更新请求；所述方法还包括：
解析所述信息更新请求，得到解析结果；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心将所述解析结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心将所述解析结果确定为所述第二信息，并根据所述第二信息更新自身的专项信息表；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述解析结果确定为所述第三信息，并发送所述第三信息给相应从IP核心，以供所述相应从IP核心根据所述第二信息更新自身的专项信息表。
上述方案中，所述信息处理请求为所述处理器发送的信息读取请求；所述方法还包括：
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心基于所述信息读取请求，将从自身的全局信息表中获取的所述信息读取请求对应的信息确定为所述第四信息，并将所述第四信息发送给所述处理器；
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心基于所述信息读取请求，将从自身的专项信息表中获取的所述信息读取请求对应的信息确定为所述第四信息，并将所述第四信息发送给所述处理器；
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述信息读取请求发送给相应从IP核心，以获取所述相应从IP核心响应所述信息读取请求所返回的第五信息并发送给所述处理器。
上述方案中，所述方法还包括：
所述主IP核心通过自身设置的第一接口以及各从IP核心上设置的第二接口与各从IP核心进行信息交互。
本申请实施例还提供了一种以太网交换芯片，所述以太网交换芯片包含至少两个IP核心；所述至少两个IP核心中的一个IP核心为主IP核心；所述至少两个IP核心中除所述主IP核心外的其它IP核心为从IP核心；其中，
所述主IP核心，配置为：
接收信息处理请求；
基于接收的信息处理请求执行以下操作之一：
根据所述信息处理请求对应的第一信息更新自身的全局信息表；并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；接收的信息处理请求来自以下之一：设置有所述以太网交换芯片的交换机的处理器；所述以太网交换芯片的从IP核心；
根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；
基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给所述处理器，或者，从相应从IP核心获取第五信息并发送给所述处理器；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息；其中，
所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息。
本申请实施例还提供了一种以太网交换芯片，包括：处理器和配置为存储能够在处理器上运行的计算机程序的存储器；
其中，所述处理器配置为运行所述计算机程序时，执行上述任一方法的步骤。
本申请实施例还提供了一种存储介质，所述介质存储有计算机程序，所述计算机程序被处理器执行时实现上述任一方法的步骤。
本申请实施例提供的技术方案，以太网交换芯片的主IP核心接收信息处理请求，基于接收的信息处理请求执行以下操作之一：根据所述信息处理请求对应的第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给处理器，或者，从相应从IP核心获取第五信息并发送给所述处理器；其中，所述主IP核心为所述以太网交换芯片包含的至少两个IP核心中的一个IP核心；所述从IP核心为所述至少两个IP核心中除所述主IP核心外的其它IP核心；所述主IP核心接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；所述处 理器为设置有所述以太网交换芯片的交换机的处理器；所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息。本申请实施例的方案，为以太网交换芯片包含的至少两个IP核心配置了主从模式，由主IP核心与设置有所述以太网交换芯片的交换机的处理器进行通信，并通过主IP核心实现自身和各从IP核心的全局信息表的同步更新，如此，可以使双核心或多核心以太网交换芯片中各IP核心的操作不会发生冲突，进一步使得双核心或多核心以太网交换芯片对外的系统行为与单核心以太网交换芯片相同。
附图说明
图1为相关技术中双核心以太网交换芯片的结构示意图；
图2为本申请实施例信息处理方法的流程示意图；
图3为本申请应用实施例交换机的结构示意图；
图4为本申请实施例以太网交换芯片的结构示意图；
图5为本申请实施例以太网交换芯片的硬件结构示意图。
具体实施方式
以下结合说明书附图及实施例对本申请的技术方案作进一步详细的阐述。
随着芯片生产工艺的进步，流片(Tape out)费用越来越高。为了在节省成本的前提下丰富产品线，需要在一次Tape out中同时设计并生产出高带宽(单核心)和超高带宽(双核心或多核心)的以太网交换芯片。由于每个裸晶(Die)上可以封装一个IP核心，因此，通过使用裸晶互联(D2D，Die to Die)技术，能够实现一次Tape out覆盖多个产品线：单核心以太网交换芯片使用一个Die封装；双核心或多核心以太网交换芯片使用两个或多个Die封装。这里，为了支持双核心或多核心以太网交换芯片包含的各IP核心既能够分离封装成两块或多块不同的以太网交换芯片独立工作，也能够合并封装成一个芯片，各IP核心的结构是完全一致的。对于具备双核心或多核心的以太网交换芯片，从芯片的应用角度来说，芯片在工作时所展现出来的系统行为不应当使其它终端或服务器感知到芯片架构是单核心还是双核心或多核心设计(比如其它终端或服务器感知到芯片的各IP核心转发报文有冲突或时延不一致的情况)。因此，各IP核心间的信息同步是非常必要的。具体地，以太网交换芯片在处理报文时，需要维护报文处理信息表(即更新报文处理信息表)，所述报文处理信息表存储于IP核心，用于供所述IP核心查询接收的报文对应的报文处理策略，并利用查询到的报文 处理策略对接收的报文进行相应处理(例如转发、丢弃等)。对于单核心以太网交换芯片的IP核心，报文处理信息表是公共资源，即所述IP核心的所有接口在接收报文后查询接收的报文对应的报文转发策略时查询的是相同的报文处理信息表，所述IP核心可以维护自身存储的报文处理信息表。但对于双核心或多核心以太网交换芯片的至少两个IP核心中的每个IP核心，所述IP核心中不仅存储有接口属性信息表等与IP核心的接口强相关的报文处理信息表，还存储有以太网二层网桥报文转发信息表(FDB，Forward Database)等与IP核心的接口弱相关的报文处理信息表；这里，所述与IP核心的接口强相关的报文处理信息表仅存储在相应的IP核心中，而所述与IP核心的接口弱相关的报文处理信息表存储在每个IP核心中；因此，所述与IP核心的接口强相关的报文处理信息表可以由相应的IP核心进行内部维护，无需告知其它IP核心；而所述与IP核心的接口弱相关的报文处理信息表需要所有IP核心同步维护，各IP核心存储的需要同步维护的报文处理信息表必须保持一致。然而，由于以太网交换芯片是一次Tape out覆盖多个产品线生产的，各IP核心分别独立封装，即各IP核心之间无法存在共享公共资源区域来支持为了同步维护报文处理信息表进行的互操作。
以图1所示的双核心以太网交换芯片为例，以太网交换芯片100包含IP核心110和IP核心120，报文处理流水线111和报文处理流水线121配置为根据自身所处IP核心存储的报文处理信息表对接收的报文进行相应处理，并根据存储的报文处理信息表对接收的报文进行相应处理；处理引擎112和处理引擎122配置为更新自身所处IP核心的报文处理信息表(实际应用时，报文处理信息表也可以是由报文处理流水线或设置有所述以太网交换芯片的交换机的处理器更新的，这里仅针对处理引擎更新报文处理信息表的情况进行举例说明)。在以太网交换芯片100需要对以太网二层的一个报文进行转发时，如果以太网交换芯片100仅包含IP核心110，报文处理流水线111会在IP核心110存储的FDB中查询待转发报文的报文转发策略；如果报文处理流水线111没有在FDB中找到待转发报文的报文转发策略，则发送待转发报文的报文信息学习请求给处理引擎112，触发处理引擎112的自学习操作，使处理引擎112得到待转发报文的报文信息学习结果；处理引擎112基于得到的报文信息学习结果确定待转发报文的报文转发策略，并添加到IP核心110存储的FDB中，供报文处理流水线111后续对其它接收的报文进行转发处理。但是，以太网交换芯片100还包含IP核心120，由于FDB是需要IP核心110和IP核心120同步维护的报文处理信息表，处理引擎112基于得到的报文信息学习结果确定待转发报文的转发策略，并添加到IP核心110存储的FDB中的同时，还需将得到的报文信息学习结果发送到处理引擎122，以供处理引擎122将相应的报文转发策略添加到IP核心120存储的FDB；此时，如果IP核心120的处理引擎122接收了报文处理流水线121的报文信息学习请求进行自学习操作，也需要将确定的 另一个待转发报文的转发策略添加到报文处理流水线121中，报文处理流水线121需要同时更新两次FDB，这两次更新可能会有冲突(例如当FDB使用哈希(Hash)方式存储，则可能出现报文处理流水线121的FDB的两个待转发报文的转发策略写位置冲突)。
基于此，在本申请的各种实施例中，为以太网交换芯片包含的至少两个IP核心配置了主从模式，由主IP核心与设置有所述以太网交换芯片的交换机的处理器进行通信，并通过主IP核心实现自身和各从IP核心的全局信息表的同步更新，如此，可以使双核心或多核心以太网交换芯片中各IP核心的操作不会发生冲突，进一步使得双核心或多核心以太网交换芯片对外的系统行为与单核心以太网交换芯片相同。
需要说明的是，在本申请的各种实施例中，需要一个IP核心内部维护的报文处理信息表为所述IP核心的专项信息表，需要所有IP核心同步维护的报文处理信息表为每个IP核心的全局信息表；一个IP核心的全局信息表和专项信息表统称为所述IP核心的报文处理信息表。
本申请实施例提供一种信息处理方法，如图2所示，所述方法包括以下步骤：
步骤201：以太网交换芯片的主IP核心接收信息处理请求；
这里，所述主IP核心为所述以太网交换芯片包含的至少两个IP核心中的一个IP核心。
步骤202：所述主IP核心基于接收的信息处理请求执行相关操作。
具体地，所述主IP核心基于接收的信息处理请求，执行以下操作之一：
根据所述信息处理请求对应的第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；接收的信息处理请求来自以下之一：设置有所述以太网交换芯片的交换机的处理器；所述以太网交换芯片的从IP核心；
根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；
基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给所述处理器，或者，从相应从IP核心获取第五信息并发送给所述处理器；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息。
这里，所述从IP核心为所述至少两个IP核心中除所述主IP核心外的其它IP核心；所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息。
具体地，所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息，指所述全局信息表是需要所述以太网交换芯片的所有IP核心同步维护的报文处理信息表；例如FDB、以太网三层路由交换信息表(RIB，Routing Information Base)、多协议标签交换表(MPLS，Multi-Protocol Label Switching)、标签映射表(ILM，Incoming Label Map)等报文转发信息表，再例如时间同步计数器信息表、带宽评估信息表等公共资源信息表，以及与FDB对应的老化状态信息表(AST，Aging State Table)等有状态报文处理信息表。所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息，指所述专项信息表示需要相应IP核心内部维护的报文处理信息表；例如接口属性信息表，所述接口属性信息表包含的索引ID即为接口ID，而对于一个指定的接口一定属于一个固定的IP核心。另外，所述全局信息表需要所述以太网交换芯片的所有IP核心同步维护，指每个IP核心的全局信息表需要保持一致，这样，无论所述以太网交换芯片的哪一个接口接收了报文，相应的IP核心查询接收的报文对应的报文处理策略时查询的是相同的全局信息表。
实际应用时，在所述主IP核心接收信息处理请求前，即在执行步骤201之前，需要在所述以太网交换芯片的所有IP核心中确定主IP核心。
基于此，在一实施例中，所述方法还可以包括：
将所述以太网交换芯片的一个IP核心配置为主IP核心，并将所述以太网交换芯片除所述主IP核心外的其它IP核心配置为从IP核心，得到一个主IP核心和至少一个从IP核心。
实际应用时，可以由用户根据需要将所述以太网交换芯片的任意一个IP核心配置为主IP核心。
实际应用时，针对所述以太网交换芯片的每个IP核心，相应IP核心可以包括第一处理模块和第二处理模块；所述第一处理模块配置为根据自身所处IP核心存储的报文处理信息表(包括全局信息表和专项信息表)对接收的报文进行相应处理(例如转发处理、丢弃处理或修改报文优先级字段等处理)；所述第二处理模块配置为更新所述报文处理信息表；以图1所示的双核心以太网交换芯片100为例，所述第一处理模块可以是IP核心110的报文处理流水线111以及IP核心120的报文处理流水线121；所述第二处理模块可以是IP核心110的处理引擎112以及IP核心120的处理引擎122。相应IP核心可以包括第三处理模块，所述第三处理模块配置为在自身所处IP核心被配置为主IP核心后通过高速串行计算机扩展总线标准(PCIe，Peripheral Component Interconnect express)总线与所述处理器进行信息交互；在用户将原主IP核心配置为从IP核心，并将一个原从IP核心配置为新主IP核心时，可以将原主IP核心的第三处理模块与所述处理器之间的PCIe总线断开，并使新主IP核心的第三处理模块通过PCIe总线与所述处理器建立连接。
实际应用时，在所述主IP核心基于接收的信息处理请求执行相应操作之前，即在执行步骤202之前，所述主IP核心需要判断所述信息处理请求关联的IP核心，即判断所述信息处理请求针对的是每个IP核心的全局信息表、主IP核心的专项信息表还是从IP核心的专项信息表；这样，所述主IP核心可以根据判断结果执行相应的操作。
基于此，在一实施例中，所述方法还可以包括：
所述主IP核心根据第一预设策略判断所述信息处理请求关联的IP核心，得到第一判断结果；
根据所述第一判断结果，基于接收的信息处理请求执行相应操作。
实际应用时，所述第一预设策略可以由用户根据需要设置，比如根据所述信息处理请求包含的IP核心标识和报文处理信息表标识判断所述信息处理请求关联的IP核心；当然，所述第一判断结果可以表征所述信息处理请求关联所述以太网交换芯片的所有IP核心，即所述信息处理请求针对的是每个IP核心的全局信息表；或者，所述第一判断结果可以表征所述信息处理请求关联所述以太网交换芯片的所述主IP核心，即所述信息处理请求针对的是所述主IP核心的专项信息表；或者，所述第一判断结果可以表征所述信息处理请求关联所述以太网交换芯片的一个从IP核心，即所述信息处理请求针对的是相应从IP核心的专项信息表。
实际应用时，所述主IP核心接收的信息处理请求可以是从IP核心发送的报文信息学习请求。
基于此，在一实施例中，所述信息处理请求为从IP核心发送的报文信息学习请求时，所述方法还可以包括：
所述主IP核心响应接收的报文信息学习请求，执行所述报文信息学习请求对应的自学习操作，得到报文信息学习结果；
在所述第一判断结果表征所述报文信息学习请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心将所述报文信息学习结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个IP核心根据所述第一信息更新自身的全局信息表；
在所述第一判断结果表征所述报文信息学习请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述报文信息学习结果确定为所述第二信息，并发送所述第二信息给相应从IP核心，以供所述相应从IP核心根据所述第二信息更新自身的专项信息表。
实际应用时，所述报文信息学习请求对应的自学习操作，可以是源IP地址、源端口、目的IP地址、目的端口以及传输层协议等信息的自学习操作；相应地，所述报文信息学习结果可以包括所述主IP核心通过自学习操作得到的源IP地址、源端口、目的IP地址、目的端口以及传输层协议等信息以及相应信息在报文处理信息表中的存储位置。
实际应用时，当满足以下条件之一时，从IP核心可以发送所述报文信息学习请求给所述主IP核心：
从IP核心未在自身的全局信息表或专项信息表中查询到与接收的报文相对应的报文处理策略；
从IP核心根据在自身的全局信息表或专项信息表中查询到的与接收的报文相对应的报文处理策略对所述接收的报文进行相应处理时处理失败。
具体地，实际应用时，在所述以太网交换芯片的每个IP核心中，所述第一处理模块在自身所处IP核心的报文处理信息表中查询与接收的报文相对应的报文处理策略，以根据查询到的报文处理策略对接收的报文进行相应处理；当满足以下条件之一时，所述第一处理模块发送报文信息学习请求给自身所处IP核心的第二处理模块：
所述第一处理模块未在自身存储的报文处理信息表中查询到与接收的报文相对应的报文处理策略；
所述第一处理模块根据查询到的报文处理策略对接收的报文进行相应处理时处理失败。
由于所述全局信息表在各个IP核心中的同步更新是通过主IP核心实现的，因此，当从IP核心的第二处理模块(后续的描述中记作从模块)从自身所处IP核心的第一处理模块接收到报文信息学习请求时，所述从模块会将报文信息学习请求发送到主IP核心的第二处理模块(后续的描述中记作主模块)；也就是说，所述主模块既接收自身所处IP核心的第一处理模块发送的报文信息学习请求，也接收从模块发送的报文信息学习请求；所述主模块在接收到所述报文信息学习请求后，可以响应所述报文信息学习请求，执行所述报文信息学习请求对应的自学习操作，得到报文信息学习结果；根据所述报文信息学习结果更新自身所处IP核心的报文处理信息表；和/或，将所述报文信息学习结果发送给相应从模块，以供所述相应从模块根据所述报文信息学习结果更新自身所处IP核心的报文处理信息表。
举例来说，对于以太网二层报文的转发处理，在所述以太网交换芯片的每个IP核心中，所述第一处理模块接收到报文后，会通过接收报文时的收方向接口属性以及接收的报文中携带的目的地址信息，在自身所述IP核心的FDB中查询接收的报文对应的转发策略，以对接收的报文进行转发处理；如果所述第一处理模块未在FDB中查询到相应的转发策略，所述第一处理模块需要向自身所处IP核心的第二处理模块发送一个FDB学习请求；所述FDB学习请求用于供所述第二处理模块执行所述FDB学习请求对应的FDB表项学习操作，得到学习结果；所述学习结果可以包括：转发地址信息、目的出接口属性以及所述学习结果对应的转发策略在FDB中的存储位置；所述第二处理模块得到所述学习结果后，可以根据所述学习结果，将相应的转发策略(即所述学习结果包含的所述转发地址信息和所述目的出接口属性)按照所述存储位置添加到FDB，以完成FDB的更新(所述第二 处理模块也可以将所述学习结果返回给所述第一处理模块，由所述第一处理模块完成FDB的更新)；在FDB中更新的转发策略可以用于后续接收报文的转发。由于FDB是全局信息表，因此，从模块从自身所处IP核心的第一处理模块接收到FDB学习请求时，会将FDB学习请求发送到所述主模块；所述主模块既接收自身所处IP核心的第一处理模块发送的FDB学习请求，也接收从模块发送的FDB学习请求；所述主模块在接收到FDB学习请求后，响应所述FDB学习请求，执行所述FDB学习请求对应的FDB表项学习操作，得到学习结果；利用所述学习结果更新自身所处IP核心的FDB；并将所述学习结果发送给所述以太网交换芯片的每个从模块；各从模块接收到所述学习结果后，可以利用所述学习结果更新自身所处IP核心的FDB；如此，实现了各IP核心的FDB同步更新，保持了各IP核心的FDB的一致性。
实际应用时，用户可以根据需要，在所述交换机的系统软件中设置针对各IP核心的信息报告功能；这样，所述主模块还可以将所述报文信息学习结果通过所述主IP核心的第三处理模块发送给所述处理器，以供所述系统软件从所述处理器获取所述报文信息学习结果并执行相应的操作。
实际应用时，所述主IP核心接收的信息处理请求可以是所述处理器发送的信息更新请求。
基于此，在一实施例中，所述信息处理请求为所述处理器发送的信息更新请求时，所述方法还可以包括：
解析所述信息更新请求，得到解析结果；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心将所述解析结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个IP核心根据所述第一信息更新自身的全局信息表；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心将所述解析结果确定为所述第二信息，并根据所述第二信息更新自身的专项信息表；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述解析结果确定为所述第三信息，并发送所述第三信息给相应从IP核心，以供所述相应从IP核心根据所述第二信息更新自身的专项信息表。
实际应用时，所述处理器具体可以是设置有所述以太网交换芯片的交换机的中央处理器(CPU，Central Processing Unit)。
实际应用时，用户可以通过所述交换机的系统软件更新各IP核心的报文处理信息表，所述系统软件具体可以通过所述处理器从所述交换机的内存的第一位置读取到用户的信息更新请求，并将所述信息更新请求发送到所述主IP核心；所述第一位置可以由用户根据需要在所述系统软件中设置， 所述第一位置用于存储用户的信息更新请求，所述信息更新请求至少包含用户请求更新的内容以及所述内容在报文处理信息表中的存储位置；所述主IP核心的第三处理模块接收所述系统软件通过所述处理器发送的信息更新请求，根据所述第一预设策略判断所述信息更新请求关联的IP核心，得到第一判断结果；并对所述信息更新请求进行解析，得到解析结果(即确定用户请求更新的内容以及所述内容在报文处理信息表中的存储位置)。在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心的第三处理模块可以将所述解析结果发送给所述主IP核心的第一处理模块，以供所述主IP核心的第一处理模块根据所述解析结果更新所述主IP核心的全局信息表，同时，所述主IP核心的第三处理模块可以将所述解析结果发送给所述主模块，由所述主模块将所述解析结果发送给每个从模块，各从模块接收到所述解析结果后，将所述解析结果发送给自身所处IP核心的第三处理模块，所述第三处理模块再将所述解析结果发送给自身所处IP核心的第一处理模块，以供所述第一处理模块根据所述解析结果更新自身所处IP核心的全局信息表。在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心的第三处理模块可以直接将所述解析结果发送给所述主IP核心的第一处理模块，以供所述主IP核心的第一处理模块根据所述解析结果更新所述主IP核心的专项信息表。在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的一个从IP核心(后续的描述中记作第一目标从IP核心)的情况下，所述主IP核心的第三处理模块可以将所述解析结果发送给所述主模块，由所述主模块将所述解析结果发送给所述第一目标从IP核心的从模块，所述第一目标从IP核心的从模块接收到所述解析结果后，将所述解析结果发送给所述第一目标从IP核心的第三处理模块，所述第一目标从IP核心的第三处理模块再将所述解析结果发送给所述第一目标从IP核心的第一处理模块，以供所述第一目标从IP核心的第一处理模块根据所述解析结果更新自身所处IP核心的专项信息表。当然，在所述主IP核心需要将所述解析结果发送给相应从IP核心时，可以直接将所述信息更新请求发送给所述相应从IP核心，由所述相应从IP核心对所述信息更新请求进行解析得到解析结果，并执行相应操作；即可以将所述信息更新请求确定为所述第三信息发送给所述相应从IP核心。
实际应用时，所述主IP核心接收的信息处理请求可以是所述处理器发送的信息读取请求。
基于此，在一实施例中，所述信息处理请求为所述处理器发送的信息读取请求时，所述方法还可以包括：
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心基于所述信息读取请求，将从自身的全局信息表中获取的所述信息读取请求对应的信息确定为所述第四信 息，并将所述第四信息发送给所述处理器；
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心基于所述信息读取请求，将从自身的专项信息表中获取的所述信息读取请求对应的信息确定为所述第四信息，并将所述第四信息发送给所述处理器；
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述信息读取请求发送给相应从IP核心，以获取所述相应从IP核心响应所述信息读取请求所返回的第五信息并发送给所述处理器。
具体地，实际应用时，由于主IP核心的第三处理模块通过PCIe总线和所述处理器进行信息交互，所述交换机上的系统软件可以通过所述处理器以直接内存存取(DMA，Direct Memory Access)的方式访问所述以太网交换芯片；即所述主IP核心的第三处理模块可以接收所述系统软件通过所述处理器发送的信息读取请求，根据所述第一预设策略判断所述信息读取请求关联的IP核心，得到第一判断结果。在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心的第三处理模块可以直接从所述主IP核心的全局信息表中读取所述信息读取请求对应的第四信息，并将所述第四信息发送给所述处理器，以供所述处理器将所述第四信息写入所述交换机的内存的第二位置；所述第二位置可以由用户根据需要在所述系统软件中设置。在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心的第三处理模块也可以直接从所述主IP核心的专项信息表中读取所述信息读取请求对应的第四信息，并将所述第四信息发送给所述处理器，以供所述处理器将所述第四信息写入所述交换机的内存的第三位置；所述第三位置可以由用户根据需要在所述系统软件中设置。在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的一个从IP核心(后续的描述中记作第二目标从IP核心)的情况下，所述主IP核心的第三处理模块可以将所述信息读取请求发送给所述主模块，由所述主模块将所述信息读取请求发送给所述第二目标从IP核心的从模块，所述第二目标从IP核心的从模块接收到所述信息读取请求后，将所述信息读取请求发送给所述第二目标从IP核心的第三处理模块，所述第二目标从IP核心的第三处理模块可以从所述第二目标从IP核心的专项信息表中读取所述信息读取请求对应的第五信息，并将所述第五信息发送给所述第二目标从IP核心的从模块，由所述第二目标从IP核心的从模块将所述第五信息发送给所述主模块，所述主模块再将所述第五信息发送给所述主IP核心的第三处理模块，由所述主IP核心的第三处理模块将所述第五信息发送给所述处理器，以供所述处理器将所述第五信息写入所述交换机的内存的第四位置；所述第四位置也可以由用户根据需要在所述系统软件中设置。
实际应用时，用户还可以根据需要在所述系统软件中设置第二预设策略，所述第二预设策略用于在所述交换机运行过程中使所述以太网交换芯片主动报告运行状态；所述运行状态具体可以是各个IP核心的运行状态，例如各个IP核心的端口收发报文数量统计信息等；针对每个IP核心，所述运行状态可以状态信息表的形式作为相应IP核心的一个专项信息表；这样，无需接收所述处理器发送的信息读取请求，所述主IP核心可以按所述第二预设策略包含的周期主动向所述处理器发送自身的状态信息表，并将接收的各从IP核心发送的相应从IP核心的状态信息表发送给所述处理器。具体地，所述主IP核心的第三处理模块可以将所述主IP核心的状态信息表发送给所述处理器，以供所述处理器将所述主IP核心的状态信息表写入所述交换机的内存的第五位置。同时，所述主模块还可以接收各从模块发送的自身所处从IP核心的状态信息表；各从模块发送的自身所处从IP核心的状态信息表是相应从模块所处从IP核心的第三处理模块获取并发送的；所述主模块接收到一个从IP核心(后续的描述中记作第三目标从IP核心)的状态信息表后，可以将所述第三目标从IP核心的状态信息表发送到所述主IP核心的第三处理模块，由所述主IP核心的第三处理模块将所述第三目标从IP核心的状态信息表发送给所述处理器，以供所述处理器将所述第三目标从IP核心的状态信息表写入所述交换机的内存的第六位置。
这里，需要说明的是，所述主IP核心报告自身的状态信息表的周期以及各个从IP核心报告自身的状态信息表的周期可以相同或不同，具体可以由用户根据需要在所述第二预设策略中设置；所述第五位置和所述第六位置也可以由用户根据需要在所述系统软件中设置。
实际应用时，在所述主IP核心根据所述信息处理请求对应的第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表时，考虑到信息交互所需的时延，即为了实现所有IP核心同步更新自身的全局信息表，用户还可以根据需要在所述系统软件中设置第三预设策略，所述第三预设策略用于在所述以太网交换芯片需要同步更新各IP核心的全局信息表时，使所述主IP核心在预设时延后开始更新自身的全局信息表。
具体地，所述第三预设策略用于使所述主模块在预设时延后开始根据所述信息处理请求对应的第一信息更新自身所述IP核心的全局信息表；所述预设时延为第一时刻与第二时刻的差值；所述第一时刻为所述主模块将所述第一信息发送给所述以太网交换芯片的每个从IP核心的时刻；所述第二时刻为各从IP核心的从模块接收到所述第一信息的时刻。
实际应用时，用户可以在每个IP核心中配置一个预设级数的流水线，所述预设级数的流水线配置为实现所述预设时延；具体地，当所述IP核心被配置为主IP核心，且所述主IP核心需要根据所述第一信息更新自身的全 局信息表时，所述主模块可以通过所述预设级数的流水线更新所述主IP核心的全局信息表，即实现在预设时延后开始根据所述第一信息更新所述主IP核心的全局信息表；当所述IP核心被配置为从IP核心，且所述从IP核心需要接收所述主IP核心发送的所述第一信息来更新自身的全局信息表时，所述从IP核心的从模块可以跳过自身所处IP核心配置的预设级数的流水线，直接根据所述第一信息更新自身所处从IP核心的全局信息表。这里，用户可以基于芯片设计需求确定预设时延的大小；例如，用户可以设置每个IP核心配置的流水线的预设级数为2，即每个IP核心配置了一个2级流水线，则可以确定所述预设时延为2个时钟周期，所述时钟周期为所述以太网交换芯片的时钟模块的时钟周期。也就是说，所述主模块在2个时钟周期后开始根据所述第一信息更新所述主IP核心的全局信息表，同时，所述主模块将所述第一信息发送给各IP核心的从模块也需要2个时钟周期，即相应从模块在2个时钟周期后接收到所述第一信息并直接开始更新自身所处从IP核心的全局信息表；如此，可以实现各IP核心同步更新自身的全局信息表。
实际应用时，为了优化所述以太网交换芯片的报文处理性能，所述以太网交换芯片需要在合理的时间范围内完成各IP核心的报文处理信息表的更新，即相应从模块接收到所述主模块发送的信息所需的时长需在合理的时间范围内(例如20个时钟周期)；用户可以基于芯片设计需求确定相应从模块接收到所述主模块发送的信息所需的时长，并通过控制各模块间的数据传输线的长度等方式设置所述时长。
实际应用时，在更新报文处理信息表的过程中，相应模块可以对所述报文处理信息表中的报文处理策略进行增加、删除和修改的操作。
实际应用时，所述以太网交换芯片的各个IP核心上需要设置IP核心之间的通信接口，以使所述主IP核心和各从IP核心可以通过所述通信接口进行信息交互。
基于此，在一实施例中，所述方法还可以包括：
所述主IP核心通过自身设置的第一接口以及各从IP核心上设置的第二接口与各从IP核心进行信息交互。
实际应用时，为了保证所述以太网交换芯片的工作效率，用户可以根据需要对所述第一接口和所述第二接口在每个时钟周期支持的信息交互次数进行设置；例如，可以使得所述第一接口能够在每一个时钟周期将所述主IP核心发送的一份信息传递给相应从IP核心，以及接收所述相应从IP核心发送的一份信息；并使得所述第二接口能够在每一个时钟周期将相应从IP核心发送的一份信息传递给所述主IP核心，以及接收所述主IP核心发送的一份信息。
实际应用时，用户可以根据所述主IP核心和所述各从IP核心在信息交互时需要传递的信息的大小来设置所述第一接口和所述第二接口允许通过 的最大数据量为nbit，n为正整数。
实际应用时，为了确保所述以太网交换芯片的报文转发的正确率，可以通过错误检查和纠正(ECC，Error Correcting Code)技术或其它纠错技术使得通过所述第一接口和所述第二接口进行的信息交互为无错误通信。
本申请实施例提供的信息处理方法，以太网交换芯片的主IP核心接收信息处理请求，基于接收的信息处理请求执行以下操作之一：根据所述信息处理请求对应的第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给处理器，或者，将所述信息处理请求发送给相应从IP核心，以接收所述相应从IP核心响应所述信息处理请求所返回的第五信息并发送给所述处理器；其中，所述主IP核心为所述以太网交换芯片包含的至少两个IP核心中的一个IP核心；所述从IP核心为所述至少两个IP核心中除所述主IP核心外的其它IP核心；所述主IP核心接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；所述处理器为设置有所述以太网交换芯片的交换机的处理器；所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息；如此，可以使双核心或多核心以太网交换芯片中各IP核心的操作不会发生冲突，进一步使得双核心或多核心以太网交换芯片对外的系统行为与单核心以太网交换芯片相同。
下面结合应用实施例对本申请再作进一步详细的描述。
在本应用实施例中，如图3所示，交换机300包括双核心以太网交换芯片310和CPU 320；所述以太网交换芯片310包括IP核心311和IP核心312；每个IP核心包括一个报文处理流水线(即上述第一处理模块，可称为模块一)、一个处理引擎(即上述第二处理模块，可称为模块二)、一个CPU交互模块(即上述第三处理模块，可称为模块三)和一个接口(即上述第一接口或第二接口)；即IP核心311包括模块一3111、模块二3112、模块三3113和接口3114；IP核心312包括模块一3121、模块二3122、模块三3123和接口3124；其中，
所述模块一3111和所述模块一3121，配置为根据自身所处IP核心的报文处理信息表对接收的报文进行相应处理；
所述模块二3112和模块二3122，配置为更新自身所处IP核心的报文处理信息表；所述更新包括增加报文处理策略、修改报文处理策略和删除 报文处理策略(实际应用时，也可以通过模块一3111或所述模块一3121更新相应的报文处理信息表)；
所述模块三3113和所述模块三3123，配置为通过PCIe总线330或PCIe总线340和CPU 320进行信息交互；
所述接口3114和所述接口3124，配置为实现各模块二之间的信息交互，即实现各IP核心之间的信息交互。
在本应用实施例中，模块二3112为主模块，模块二3122为从模块；相应地，IP核心311为主IP核心，IP核心312为从IP核心；IP核心311通过PCIe总线330与CPU 320进行信息交互，IP核心312连接的PCIe总线340不连接CPU 320；在需要切换主从模块，即将模块二3122配置为主模块，并将模块二3112配置为从模块时，需要断开PCIe总线330与CPU 320之间的连接，并连接PCIe总线340到CPU 320，使得IP核心312能够作为主IP核心与CPU 320进行信息交互。
这里，“IP核心311通过PCIe总线330和CPU 320进行信息交互，IP核心312连接的PCIe总线340不连接CPU 320(即模块二3112为主模块，模块二3122为从模块，IP核心311为主IP核心，IP核心312为从IP核心)”和“IP核心312通过PCIe总线340和CPU 320进行信息交互，IP核心311连接的PCIe总线330不连接CPU 320(即模块二3122为主模块，模块二3112为从模块，IP核心312为主IP核心，IP核心311为从IP核心)”并没有实质区别，本应用实施例仅以“IP核心311通过PCIe总线330和CPU 320进行信息交互，IP核心312连接的PCIe总线340不连接CPU 320(即模块二3112为主模块，模块二3122为从模块，IP核心311为主IP核心，IP核心312为从IP核心)”作为举例说明。
基于所述以太网交换芯片310，本应用实施例的信息处理方法可以包括三种表项维护情况：主IP核心311的内部表项维护(即主IP核心311更新自身的专项信息表)、从IP核心312的内部表项维护(即从IP核心312更新自身的专项信息表)以及主IP核心311和从IP核心312同步的表项维护(即主IP核心311和从IP核心312基于相同的信息同时更新自身的全局信息表)。
实际应用时，IP核心的内部表项维护可以是对与接口强相关的报文处理信息表(即上述专项信息表)的维护，例如接口属性信息表，所述接口属性信息表包含的索引ID是接口ID，而对于一个指定的接口一定属于一个固定的IP核心；主IP核心和从IP核心同步的表项维护可以是对与接口弱相关的报文处理信息表(即上述全局信息表)的维护，例如FDB、RIB、MPLS、ILM等报文转发信息表，再例如时间同步计数器信息表、带宽评估信息表等公共资源信息表，以及与FDB对应的AST等有状态报文处理信息表；为了使以太网交换芯片310无论从哪个接口接收报文都查询的是相同的报文处理信息表，需要同步维护的报文处理信息表需要全局保持一致， 即主IP核心存储的需要同步维护的报文处理信息表和从IP核心存储的需要同步维护的报文处理信息表需要保持一致。
实际应用时，可以通过主模块工作机制和从模块工作机制实现上述三种表项维护情况。
具体地，主模块工作机制包括：主模块3112接收到来自模块一3111的信息处理请求或CPU 320通过模块三3113发送的信息处理请求，进行相应的信息处理，得到处理结果；并将处理结果写回模块一3111(即通过模块一3111更新主IP核心311的报文处理信息表)；和/或，将处理结果通过接口3114和接口3124告知从模块3122，从模块3122将处理结果写入模块一3121(即通过模块一3121更新从IP核心312的报文处理信息表)；和/或，将处理结果通过模块三3113以及PCIe总线330报告给CPU 320。
相应地，从模块工作机制包括：从模块3122接收到模块一3121的信息处理请求，将所述信息处理请求通过接口3124和接口3114发送给主模块3112；主模块3112接收到所述信息处理请求，进行相应的信息处理，得到处理结果；主模块3112将处理结果写入模块一3111(即通过模块一3111更新主IP核心311的报文处理信息表)，同时将处理结果通过接口3114和接口3124告知从模块3122，从模块3122将处理结果写回模块一3121(即通过模块一3121更新从IP核心312的报文处理信息表)；和/或，将处理结果通过模块三3113以及PCIe总线330报告给CPU 320。
实际应用时，所述主模块工作机制和所述从模块工作机制具体可以体现在以下三种应用场景中：
应用场景一：对于以太网二层报文的转发，假设以太网交换芯片310为单核心以太网交换芯片，仅包含IP核心311，那么，IP核心311的模块一3111在接收到报文后，通过收方向接口属性以及接收到报文中携带的目的地址信息，查询IP核心311存储的FDB，以对接收的报文进行转发；但如果在FDB中没有查询到相应的信息，则模块一3111需要向模块二3112发送一个FDB学习请求，模块二3112中的学习子模块接收所述FDB学习请求，进行相应的FDB表项学习操作，得到学习结果；所述学习结果包括：转发地址信息、目的出接口属性以及该学习结果应当在FDB中存储的位置信息；模块二3112将得到的学习结果返回给模块一3111，由模块一将学习结果中的组合信息(即转发地址信息和目的出接口属性)添加到学习结果包含的在FDB中存储的位置，完成FDB的更新；更新后的FDB用于在后续模块一3111接收报文时对接收的报文进行转发处理。
由于以太网交换芯片310仅包含IP核心311，模块二3112将学习结果返回给模块一3111的过程是很简单的；但是，以太网交换芯片310实际上是双核心以太网交换芯片，包含IP核心311和IP核心312；由于每个IP核心都有一个模块二，并且FDB是需要全局维护的报文处理信息表，如果模块一3111触发了模块二3112的表项学习操作，得到学习结果，模块二 3112将学习结果返回给模块一3111的同时，需要将学习结果发送给模块二3122，并由模块二3122将学习结果发送给模块一3121，使得模块一3121能够与模块一3111同步更新自身所处IP核心的FDB；此时，如果模块二3122也在针对模块一3121发送的FDB学习请求进行处理，并得到了另一个学习结果，模块二3122在将另一个学习结果返回模块一3121时，可能和核心311发送的学习结果发生冲突；尤其是当FDB使用Hash方式存储时，可能会出现两个学习结果写位置冲突的情况。因此，为避免这样的问题，应当利用所述主模块工作机制和所述从模块工作机制对主IP核心311的FDB和从IP核心312的FDB进行更新。
其中，在主模块工作机制下，主IP核心311的模块一3111触发主模块3112的FDB表项学习操作，主模块3112完成FDB表项学习操作，得到学习结果，将学习结果返回给模块一3111，同时，将学习结果发送给从模块3122，由从模块3122将学习结果发送给模块一3121。
在从模块工作机制下，从IP核心312的模块一3121向从模块3122发送FDB学习请求，从模块3122将接收的FDB学习请求发送给主模块3112，由主模块3112完成相应的FDB表项学习操作，得到学习结果；主模块3112将学习结果发送给模块一3111，同时，将学习结果发送给从模块3122，由从模块3122将学习结果返回给模块一3121。
应用场景二：交换机300在运行过程中，交换机300上的系统软件会向用户提供交换机300的运行状态，交换机300的运行状态至少包含以太网交换芯片310的运行状态，以太网交换芯片310的运行状态需要由以太网交换芯片310主动提供给所述系统软件，所述系统软件对以太网交换芯片310的运行状态进行汇总处理后展示给用户；所述以太网交换芯片310的运行状态包括各IP核心的运行状态，例如端口收发报文数量的统计信息等。主IP核心311和从IP核心312提供运行状态的周期和时间可以相同或不同，用户可以根据需要自行设置。主IP核心311和从IP核心312将相应的运行状态信息(即上述状态信息表)从各自的模块一发送给各自的模块三，但由于主IP核心311的模块三3113能够与CPU 320进行信息交互，而从IP核心的模块三3123无法与CPU 320进行信息交互；因此，模块三3113可以直接将模块一3111中的运行状态信息通过PCIe总线330发送给CPU 320，以供CPU 320将主IP核心的运行状态信息写入系统内存(即交换机300的内存)中所述系统软件指定的位置；而模块三3123需要将从IP核心的运行状态信息发送到从模块3122，由从模块3122将从IP核心的运行状态信息通过接口3124和接口3114发送到主模块3112，主模块3112再将从IP核心的运行状态信息发送给模块三3112，由模块三3112将从IP核心的运行状态信息通过PCIe总线330发送给CPU 320，以供CPU 320将从IP核心的运行状态信息写入系统内存中所述系统软件指定的位置。
应用场景三：CPU 320通过PCIe总线与以太网交换芯片310建立连接， 使得所述系统软件可以通过DMA的方式访问以太网交换芯片310。主IP核心311的模块三3113负责接收所述系统软件通过CPU 320发送的DMA请求，所述DMA请求至少包括读请求和写请求。
在所述DMA请求为读请求的情况下，如果所述读请求针对主IP核心311和从IP核心312同步维护的报文处理信息表，或所述读请求针对主IP核心311内部维护的报文处理信息表，模块三3113只需通过模块一3111在主IP核心311的报文处理信息表中读取相应的信息，并将读取的信息发送给CPU 320，以供CPU 320将读取的信息写入系统内存中所述系统软件指定的位置。如果所述读请求针对从IP核心312内部维护的报文处理信息表，模块三3113需要将所述读请求发送给主模块3112，主模块3112将所述读取请求发送给从模块3122，从模块3122再将所述读取请求发送给模块三3123，由模块三3123处理所述读请求，通过模块一3121在从IP核心312的报文处理信息表中读取相应的信息，并将读取的结果信息发送给从模块3122，从模块3122将所述结果信息发送给主模块3112，主模块3112再将所述结果信息返回给模块三3113，由模块三3113将所述结果信息发送给CPU 320，以供CPU 320将所述结果信息写入系统内存中所述系统软件指定的位置。
在所述DMA请求为写请求的情况下，如果所述写请求针对主IP核心311和从IP核心312同步维护的报文处理信息表，则需要在模块一3111和模块一3121同步写入所述写请求对应的信息。具体地，模块三3113从系统内存中所述系统软件指定的位置获取待写入数据(这里，可以将所述待写入数据看做所述写请求，所述写请求中包含用户通过所述系统软件输入的数据)，首先，模块三3113将所述待写入数据发送给主模块3112，同时，将所述待写入数据送入一个指定级数的流水线中，流水线的出口是模块一3111；主模块3112将待写入数据通过接口3114和接口3124发送给从模块3122，从模块3122将所述待写入数据发送给模块三3123，模块三3123跳过从IP核心中配置的指定级数的流水线直接将所述待写入数据发送到模块一3121，以直接更新IP核心312的报文处理信息表；这里，假设主模块3112将所述待写入数据发送给接口3114的时刻为时刻一，模块一3121接收到所述待写入数据的时间为时刻二，时刻二与时刻一之间的时间差为X个以太网交换芯片310的时钟周期，则可以确定主IP核心中所述指定级数的流水线的级数为X。这样，主IP核心311和从IP核心312可以实现报文处理信息表的同步维护。如果所述写请求针对主IP核心311内部维护的报文处理信息表，模块三3113从系统内存中所述系统软件指定的位置获取待写入数据后，可以跳过主IP核心311中配置的指定级数的流水线，直接将所述待写入数据发送到模块一3111，以供模块一3111直接更新相应的主IP核心311内部维护的报文处理信息表。如果所述写请求针对从IP核心312内部维护的报文处理信息表，模块三3113从系统内存中所述系统软件指定的 位置获取待写入数据后，将所述待写入数据发送给主模块3112，主模块通过接口3114和接口3124将所述待写入数据发送给从模块3122，从模块3122再将所述待写入数据发送给模块三3123，模块三3123跳过从IP核心中配置的指定级数的流水线直接将所述待写入数据发送到模块一3121，以供模块一3121更新相应的从IP核心312内部维护的报文处理信息表。
这里，本应用实施例提供的信息处理方法的具体实现过程与图2所示的信息处理方法中步骤201至步骤202的具体实现过程相同，这里不多赘述。
本应用实施例提供的以太网交换芯片310和信息处理方法，具备以下优点：
解决了双核心或多核心以太网交换芯片中各IP核心的基本互操作冲突的问题，使得双核心或多核心以太网交换芯片对外的系统行为与单核心以太网交换芯片相同。
为了实现本申请实施例的方法，本申请实施例还提供了一种以太网交换芯片，如图4所示，所述以太网交换芯片400包含至少两个IP核心；所述至少两个IP核心中的一个IP核心为主IP核心401；所述至少两个IP核心中除所述主IP核心外的其它IP核心为从IP核心402；其中，
所述主IP核心401，配置为：
接收信息处理请求；
基于接收的信息处理请求执行以下操作之一：
根据所述信息处理请求对应的第一信息更新自身的全局信息表；并发送所述第一信息给所述以太网交换芯片的每个从IP核心402，以供所述每个IP核心402根据所述第一信息更新自身的全局信息表；接收的信息处理请求来自以下之一：设置有所述以太网交换芯片的交换机的处理器；所述以太网交换芯片的从IP核心402；
根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心402，以供所述相应从IP核心402根据所述第三信息更新自身的专项信息表；接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心402；
基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给所述处理器，或者，从相应从IP核心402获取第五信息并发送给所述处理器；所述第五信息是所述相应从IP核心402自身的专项信息表中与所述信息处理请求对应的信息；其中，
所述全局信息表存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息。
在一实施例中，所述主IP核心401，配置为：
根据第一预设策略判断所述信息处理请求关联的IP核心，得到第一判 断结果；
根据所述第一判断结果，基于接收的信息处理请求执行相应操作。
在一实施例中，所述信息处理请求为从IP核心402发送的报文信息学习请求，所述主IP核心401，配置为：
响应接收的报文信息学习请求，执行所述报文信息学习请求对应的自学习操作，得到报文信息学习结果；
在所述第一判断结果表征所述报文信息学习请求关联所述以太网交换芯片的所有IP核心的情况下，将所述报文信息学习结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心402，以供所述每个IP核心402根据所述第一信息更新自身的全局信息表；
在所述第一判断结果表征所述报文信息学习请求关联所述以太网交换芯片的一个从IP核心402的情况下，将所述报文信息学习结果确定为所述第二信息，并发送所述第二信息给相应从IP核心402，以供所述相应从IP核心402根据所述第二信息更新自身的专项信息表。
在一实施例中，当满足以下条件之一时，从IP核心402发送所述报文信息学习请求给所述主IP核心401：
从IP核心402未在自身的全局信息表或专项信息表中查询到与接收的报文相对应的报文处理策略；
从IP核心402根据在自身的全局信息表或专项信息表中查询到的与接收的报文相对应的报文处理策略对所述接收的报文进行相应处理时处理失败。
在一实施例中，所述信息处理请求为所述处理器发送的信息更新请求，所述主IP核心401，配置为：
解析所述信息更新请求，得到解析结果；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所有IP核心的情况下，将所述解析结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心402，以供所述每个IP核心402根据所述第一信息更新自身的全局信息表；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所述主IP核心401的情况下，将所述解析结果确定为所述第二信息，并根据所述第二信息更新自身的专项信息表；
在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的一个从IP核心402的情况下，将所述解析结果确定为所述第三信息，并发送所述第三信息给相应从IP核心402，以供所述相应从IP核心402根据所述第二信息更新自身的专项信息表。
在一实施例中，所述信息处理请求为所述处理器发送的信息读取请求， 所述主IP核心401，配置为：
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所有IP核心的情况下，基于所述信息读取请求，将从自身的全局信息表中获取的所述信息读取请求对应的信息确定为所述第四信息，并将所述第四信息发送给所述处理器；
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所述主IP核心401的情况下，基于所述信息读取请求，将从自身的专项信息表中获取的所述信息读取请求对应的信息确定为所述第四信息，并将所述第四信息发送给所述处理器；
在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的一个从IP核心402的情况下，将所述信息读取请求发送给相应从IP核心402，以获取所述相应从IP核心402响应所述信息读取请求所返回的第五信息并发送给所述处理器。
在一实施例中，所述主IP核心401，配置为：
通过自身设置的第一接口以及各从IP核心402上设置的第二接口与各从IP核心402进行信息交互。
实际应用时，所述主IP核心401和所述从IP核心402可由以太网交换芯片400中的处理器实现。
需要说明的是：上述实施例提供的以太网交换芯片400中的各个模块，仅以上述各程序模块的划分进行举例说明，实际应用中，可以根据需要而将上述处理分配由不同的程序模块完成，即将装置的内部结构划分成不同的程序模块，以完成以上描述的全部或者部分处理。另外，上述实施例提供的以太网交换芯片400与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
基于上述程序模块的硬件实现，且为了实现本申请实施例的方法，本申请实施例还提供了一种以太网交换芯片，如图5所示，以太网交换芯片50包括存储器52、处理器51及存储在存储器52上并可在处理器51上运行的计算机程序；所述处理器51执行所述程序时实现上述一个或多个技术方案提供的方法。
具体地，所述以太网交换芯片50的主IP核心通过所述处理器71执行以下操作：接收信息处理请求；基于接收的信息处理请求执行以下操作之一：根据所述信息处理请求对应的第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给所述处理 器，或者，从相应从IP核心获取第五信息并发送给所述处理器；其中，所述主IP核心为所述以太网交换芯片包含的至少两个IP核心中的一个IP核心；所述从IP核心为所述至少两个IP核心中除所述主IP核心外的其它IP核心；所述主IP核心接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；所述处理器为设置有所述以太网交换芯片的交换机的处理器；所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息。
需要说明的是，所述处理器51具体的执行操作的过程详见方法实施例，这里不再赘述。
当然，实际应用时，所述以太网交换芯片50中的各个组件通过总线系统53耦合在一起。可理解，总线系统53配置为实现这些组件之间的连接通信。总线系统53除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图5中将各种总线都标为总线系统53；同时，所述以太网交换芯片50还可以包括通信接口54，所述通信接口54配置为和其它设备进行信息交互。
本申请实施例中的存储器52配置为存储各种类型的数据以支持所述以太网交换芯片50的操作。这些数据的示例包括：用于在所述以太网交换芯片50上操作的任何计算机程序。
上述本申请实施例揭示的方法可以应用于所述处理器51中，或者由所述处理器51实现。所述处理器51可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过所述处理器51中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器51可以是通用处理器、数字信号处理器(DSP，Digital Signal Processor)，或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。所述处理器51可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤，可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于存储介质中，该存储介质位于存储器52，所述处理器51读取存储器52中的信息，结合其硬件完成前述方法的步骤。
在示例性实施例中，所述以太网交换芯片50可以被一个或多个应用专用集成电路(ASIC，Application Specific Integrated Circuit)、DSP、可编程逻辑器件(PLD，Programmable Logic Device)、复杂可编程逻辑器件(CPLD，Complex Programmable Logic Device)、现场可编程门阵列(FPGA，Field-Programmable Gate Array)、通用处理器、控制器、微控制器(MCU，Micro Controller Unit)、微处理器(Microprocessor)、或者其他电子元件实 现，被配置为执行前述方法。
可以理解，本申请实施例的存储器(存储器52)可以是易失性存储器或者非易失性存储器，也可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(ROM，Read Only Memory)、可编程只读存储器(PROM，Programmable Read-Only Memory)、可擦除可编程只读存储器(EPROM，Erasable Programmable Read-Only Memory)、电可擦除可编程只读存储器(EEPROM，Electrically Erasable Programmable Read-Only Memory)、磁性随机存取存储器(FRAM，ferromagnetic random access memory)、快闪存储器(Flash Memory)、磁表面存储器、光盘、或只读光盘(CD-ROM，Compact Disc Read-Only Memory)；磁表面存储器可以是磁盘存储器或磁带存储器。易失性存储器可以是随机存取存储器(RAM，Random Access Memory)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(SRAM，Static Random Access Memory)、同步静态随机存取存储器(SSRAM，Synchronous Static Random Access Memory)、动态随机存取存储器(DRAM，Dynamic Random Access Memory)、同步动态随机存取存储器(SDRAM，Synchronous Dynamic Random Access Memory)、双倍数据速率同步动态随机存取存储器(DDRSDRAM，Double Data Rate Synchronous Dynamic Random Access Memory)、增强型同步动态随机存取存储器(ESDRAM，Enhanced Synchronous Dynamic Random Access Memory)、同步连接动态随机存取存储器(SLDRAM，SyncLink Dynamic Random Access Memory)、直接内存总线随机存取存储器(DRRAM，Direct Rambus Random Access Memory)。本申请实施例描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
在示例性实施例中，本申请实施例还提供了一种存储介质，即计算机存储介质，具体为计算机可读存储介质，例如包括存储计算机程序的存储器52，上述计算机程序可由所述以太网交换芯片50的处理器51执行，以完成前述方法所述步骤。计算机可读存储介质可以是FRAM、ROM、PROM、EPROM、EEPROM、Flash Memory、磁表面存储器、光盘、或CD-ROM等存储器。
需要说明的是：“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
另外，本申请实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。

Claims (10)

  1. 一种信息处理方法，包括：
    以太网交换芯片的主知识产权IP核心接收信息处理请求；所述主IP核心为所述以太网交换芯片包含的至少两个IP核心中的一个IP核心；
    所述主IP核心基于接收的信息处理请求执行以下操作之一：
    根据所述信息处理请求对应的第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；接收的信息处理请求来自以下之一：设置有所述以太网交换芯片的交换机的处理器；所述以太网交换芯片的从IP核心；
    根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；
    基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给所述处理器，或者，从相应从IP核心获取第五信息并发送给所述处理器；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息；其中，
    所述从IP核心为所述至少两个IP核心中除所述主IP核心外的其它IP核心；所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    所述主IP核心根据第一预设策略判断所述信息处理请求关联的IP核心，得到第一判断结果；
    根据所述第一判断结果，基于接收的信息处理请求执行相应操作。
  3. 根据权利要求2所述的方法，其中，所述信息处理请求为从IP核心发送的报文信息学习请求；所述方法还包括：
    所述主IP核心响应接收的报文信息学习请求，执行所述报文信息学习请求对应的自学习操作，得到报文信息学习结果；
    在所述第一判断结果表征所述报文信息学习请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心将所述报文信息学习结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；
    在所述第一判断结果表征所述报文信息学习请求关联所述以太网交 换芯片的一个从IP核心的情况下，所述主IP核心将所述报文信息学习结果确定为所述第二信息，并发送所述第二信息给相应从IP核心，以供所述相应从IP核心根据所述第二信息更新自身的专项信息表。
  4. 根据权利要求3所述的方法，其中，当满足以下条件之一时，从IP核心发送所述报文信息学习请求给所述主IP核心：
    从IP核心未在自身的全局信息表或专项信息表中查询到与接收的报文相对应的报文处理策略；
    从IP核心根据在自身的全局信息表或专项信息表中查询到的与接收的报文相对应的报文处理策略对所述接收的报文进行相应处理时处理失败。
  5. 根据权利要求2所述的方法，其中，所述信息处理请求为所述处理器发送的信息更新请求；所述方法还包括：
    解析所述信息更新请求，得到解析结果；
    在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心将所述解析结果确定为所述第一信息，根据所述第一信息更新自身的全局信息表，并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；
    在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心将所述解析结果确定为所述第二信息，并根据所述第二信息更新自身的专项信息表；
    在所述第一判断结果表征所述信息更新请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述解析结果确定为所述第三信息，并发送所述第三信息给相应从IP核心，以供所述相应从IP核心根据所述第二信息更新自身的专项信息表。
  6. 根据权利要求2所述的方法，其中，所述信息处理请求为所述处理器发送的信息读取请求；所述方法还包括：
    在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所有IP核心的情况下，所述主IP核心基于所述信息读取请求，将从自身的全局信息表中获取的所述信息读取请求对应的信息确定为所述第四信息，并将所述第四信息发送给所述处理器；
    在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的所述主IP核心的情况下，所述主IP核心基于所述信息读取请求，将从自身的专项信息表中获取的所述信息读取请求对应的信息确定为所述第四信息，并将所述第四信息发送给所述处理器；
    在所述第一判断结果表征所述信息读取请求关联所述以太网交换芯片的一个从IP核心的情况下，所述主IP核心将所述信息读取请求发送给相应从IP核心，以获取所述相应从IP核心响应所述信息读取请求所返回 的第五信息并发送给所述处理器。
  7. 根据权利要求1所述的方法，其中，所述方法还包括：
    所述主IP核心通过自身设置的第一接口以及各从IP核心上设置的第二接口与各从IP核心进行信息交互。
  8. 一种以太网交换芯片，所述以太网交换芯片包含至少两个IP核心；所述至少两个IP核心中的一个IP核心为主IP核心；所述至少两个IP核心中除所述主IP核心外的其它IP核心为从IP核心；其中，
    所述主IP核心，配置为：
    接收信息处理请求；
    基于接收的信息处理请求执行以下操作之一：
    根据所述信息处理请求对应的第一信息更新自身的全局信息表；并发送所述第一信息给所述以太网交换芯片的每个从IP核心，以供所述每个从IP核心根据所述第一信息更新自身的全局信息表；接收的信息处理请求来自以下之一：设置有所述以太网交换芯片的交换机的处理器；所述以太网交换芯片的从IP核心；
    根据所述信息处理请求对应的第二信息更新自身的专项信息表，或者，发送与所述信息处理请求对应的第三信息给相应从IP核心，以供所述相应从IP核心根据所述第三信息更新自身的专项信息表；接收的信息处理请求来自所述处理器或所述以太网交换芯片的从IP核心；
    基于所述信息处理请求，从自身的全局信息表或专项信息表中获取所述信息处理请求对应的第四信息发送给所述处理器，或者，从相应从IP核心获取第五信息并发送给所述处理器；所述第五信息是所述相应从IP核心自身的专项信息表中与所述信息处理请求对应的信息；其中，
    所述全局信息表用于存储与所述以太网交换芯片的所有IP核心相关联的信息；所述专项信息表用于存储与所述以太网交换芯片的一个IP核心相关联的信息。
  9. 一种以太网交换芯片，包括：处理器和配置为存储能够在处理器上运行的计算机程序的存储器；
    其中，所述处理器配置为运行所述计算机程序时，执行权利要求1至7任一项所述方法的步骤。
  10. 一种存储介质，所述介质存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1至7任一项所述方法的步骤。
PCT/CN2020/113727 2020-01-22 2020-09-07 信息处理方法、以太网交换芯片以及存储介质 WO2021147331A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/792,720 US20230050185A1 (en) 2020-01-22 2020-09-07 Information Processing Method, Ethernet Switching Chip and Storage Medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010075094.4A CN111343107B (zh) 2020-01-22 2020-01-22 信息处理方法、以太网交换芯片以及存储介质
CN202010075094.4 2020-01-22

Publications (1)

Publication Number Publication Date
WO2021147331A1 true WO2021147331A1 (zh) 2021-07-29

Family

ID=71186781

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/113727 WO2021147331A1 (zh) 2020-01-22 2020-09-07 信息处理方法、以太网交换芯片以及存储介质

Country Status (3)

Country Link
US (1) US20230050185A1 (zh)
CN (1) CN111343107B (zh)
WO (1) WO2021147331A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111343107B (zh) * 2020-01-22 2022-03-04 苏州盛科通信股份有限公司 信息处理方法、以太网交换芯片以及存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101193021A (zh) * 2006-11-27 2008-06-04 华为技术有限公司 数字用户线路接入系统、方法、用户板及业务处理单元
CN101964753A (zh) * 2010-10-29 2011-02-02 烽火通信科技股份有限公司 基于单个核心交换芯片的小容量ptn设备及其业务实现方法
CN102611519A (zh) * 2010-11-25 2012-07-25 上海贝尔股份有限公司 一种对无源光网络进行链路保护的方法和装置
CN107819705A (zh) * 2017-11-28 2018-03-20 济南浪潮高新科技投资发展有限公司 一种基于Microblaze核的数据交换的实现方法
US20180124011A1 (en) * 2015-04-17 2018-05-03 Hangzhou H3C Technologies Co., Ltd. Generating System Port Identity
CN111343107A (zh) * 2020-01-22 2020-06-26 盛科网络（苏州）有限公司 信息处理方法、以太网交换芯片以及存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7584327B2 (en) * 2005-12-30 2009-09-01 Intel Corporation Method and system for proximity caching in a multiple-core system
JP5146454B2 (ja) * 2007-08-22 2013-02-20 日本電気株式会社 情報処理装置及び情報処理方法
US8917738B2 (en) * 2009-04-27 2014-12-23 Lsi Corporation Multicasting traffic manager in a network communications processor architecture
CN101651627B (zh) * 2009-09-23 2013-01-09 杭州华三通信技术有限公司 一种媒体访问控制mac地址表项学习方法和装置
CN101980170B (zh) * 2010-10-20 2012-09-05 北京星网锐捷网络技术有限公司 一种微内核系统中软件模块的通信方法、系统及装置
US8724496B2 (en) * 2011-11-30 2014-05-13 Broadcom Corporation System and method for integrating line-rate application recognition in a switch ASIC
CN104102535B (zh) * 2013-04-01 2018-10-02 华为技术有限公司 进程迁移方法和可迁移操作系统
US9459903B2 (en) * 2014-09-24 2016-10-04 Intel Corporation Techniques for routing service chain flow packets between virtual machines
CN108134855B (zh) * 2017-12-18 2021-03-09 东软集团股份有限公司 Arp表管理方法、处理器核心、存储介质、电子设备
CN108768892A (zh) * 2018-03-26 2018-11-06 西安电子科技大学 一种基于p4的可编程数据平面交换原型的设计与实现
CN109257190B (zh) * 2018-08-03 2021-04-20 锐捷网络股份有限公司 一种基于sdn的组播处理方法、控制器、交换机及系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101193021A (zh) * 2006-11-27 2008-06-04 华为技术有限公司 数字用户线路接入系统、方法、用户板及业务处理单元
CN101964753A (zh) * 2010-10-29 2011-02-02 烽火通信科技股份有限公司 基于单个核心交换芯片的小容量ptn设备及其业务实现方法
CN102611519A (zh) * 2010-11-25 2012-07-25 上海贝尔股份有限公司 一种对无源光网络进行链路保护的方法和装置
US20180124011A1 (en) * 2015-04-17 2018-05-03 Hangzhou H3C Technologies Co., Ltd. Generating System Port Identity
CN107819705A (zh) * 2017-11-28 2018-03-20 济南浪潮高新科技投资发展有限公司 一种基于Microblaze核的数据交换的实现方法
CN111343107A (zh) * 2020-01-22 2020-06-26 盛科网络（苏州）有限公司 信息处理方法、以太网交换芯片以及存储介质

Also Published As

Publication number Publication date
CN111343107B (zh) 2022-03-04
CN111343107A (zh) 2020-06-26
US20230050185A1 (en) 2023-02-16

Similar Documents

Publication Publication Date Title
WO2021147332A1 (zh) 信息处理方法、以太网交换芯片以及存储介质
EP3916566A1 (en) System and method for managing memory resources
US9025495B1 (en) Flexible routing engine for a PCI express switch and method of use
US11182197B2 (en) Guest-initiated announcement of virtual machine migration
US10282293B2 (en) Method, switch, and multiprocessor system using computations and local memory operations
WO2022001417A1 (zh) 一种数据传输方法、处理器系统及内存访问系统
US20220206969A1 (en) Data forwarding chip and server
WO2018041074A1 (zh) 一种内存设备的访问方法、装置和系统
WO2020134144A1 (zh) 数据或报文转发的方法、节点和系统
CN111464447B (zh) 一种超带宽多核心以太网交换芯片转发表同步的方法及装置
TW201945946A (zh) 驅動器至驅動器儲存系統、儲存驅動器和儲存資料的方法
WO2021147331A1 (zh) 信息处理方法、以太网交换芯片以及存储介质
US11714755B2 (en) System and method for scalable hardware-coherent memory nodes
CN112052104A (zh) 基于多机房实现的消息队列的管理方法及电子设备
WO2015035891A1 (zh) 补丁方法、设备及系统
US20080295120A1 (en) Asynchronous remote procedure calling method and computer product in shared-memory multiprocessor
WO2022141322A1 (zh) 一种片上系统及相关方法
WO2022061763A1 (zh) 一种数据存储方法及装置
WO2023216603A1 (zh) 一种内存共享方法以及装置
US20230236727A1 (en) Circuit, Chip, and Electronic Device
EP4322001A1 (en) Memory expansion method and related device
CN117319328A (zh) 一种基于riscv异构多核soc的报文处理系统
CN115996370A (zh) 数据传输方法、装置、设备、存储介质及程序

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20914792

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20914792

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 20/01/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20914792

Country of ref document: EP

Kind code of ref document: A1