WO2021146967A1 - 低密度奇偶校验码编码方法和编码器 - Google Patents

低密度奇偶校验码编码方法和编码器 Download PDF

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WO2021146967A1
WO2021146967A1 PCT/CN2020/073654 CN2020073654W WO2021146967A1 WO 2021146967 A1 WO2021146967 A1 WO 2021146967A1 CN 2020073654 W CN2020073654 W CN 2020073654W WO 2021146967 A1 WO2021146967 A1 WO 2021146967A1
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matrix
data
check
column
lower triangular
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PCT/CN2020/073654
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English (en)
French (fr)
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张旭
金晶
张睦
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华为技术有限公司
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Priority to CN202080093341.1A priority Critical patent/CN114946144B/zh
Priority to PCT/CN2020/073654 priority patent/WO2021146967A1/zh
Publication of WO2021146967A1 publication Critical patent/WO2021146967A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems

Definitions

  • This application relates to the field of chip technology, and in particular to a low density parity check code (LDPC) encoding method and encoder.
  • LDPC low density parity check code
  • NAND is currently one of the most commonly used storage media in the market, usually in the form of CF (compact flash) cards, embedded multimedia cards (eMMC), universal flash storage (UFS) and solid state drives ( Solid state drive, SSD) and flash memory (Flash) arrays exist.
  • CF compact flash
  • eMMC embedded multimedia cards
  • UFS universal flash storage
  • SSD Solid state drive
  • Flash flash memory arrays exist.
  • Data reliability, data read and write bandwidth and delay are the core indicators of all NAND devices or modules, and they are also one of the key factors for the competitiveness of corresponding products.
  • a NAND controller needs to adapt to multiple types of NAND particles, but the redundancy space size and error correction capability requirements of each particle are different, and a single codec is required to support multiple specifications (code rates), and at the same time Regardless of whether it is a consumer-level application or an enterprise-level application, the requirements for read and write bandwidth and latency are getting higher and higher, which requires LDPC codes with high throughput and low latency.
  • the variable code rate scheme is also one of the important means to improve the service life of NAND particles. This technology requires different code rates to be used in different life cycles of NAND particles.
  • the encoding matrix and related parameters are reloaded once to realize the support of multiple bit rate specifications.
  • the check matrix does not have a specific structure. If the coding matrix is used for direct coding, the calculation delay of the coding will be large, and it is usually necessary to design a multi-level pipeline to achieve high bandwidth and high computational complexity.
  • the embodiments of the present application provide an LDPC encoding method and encoder, which can solve the problems of large calculation delay and large calculation complexity using LDPC encoding.
  • a low-density parity-check code LDPC encoding method including: acquiring first data; encoding the first data according to an LDPC check matrix, and outputting the second data obtained after encoding; wherein, LDPC calibration
  • the verification matrix includes a check digit part, the check digit part is the lower triangular matrix, the sub-matrix above the diagonal of the lower triangular matrix is the zero matrix; the sub-matrix in the first M1 column of the lower triangular matrix is located on the diagonal and below the diagonal
  • the matrix is a cyclic permutation matrix CPM; the sub-matrix located on the diagonal in the last M2 column of the lower triangular matrix is a multilateral (ME) matrix, and the sub-matrix located below the diagonal is a zero matrix.
  • the check digit part provided in this application may be a lower triangular matrix, or a lower triangular matrix after row-column transformation.
  • each row or column includes at most one 1 and the rest are all 0s.
  • the number of values 1 in each row is greater than 1, and is an odd number; and, the number of values 1 in each column is greater than 1, and is an odd number.
  • the number of 1s in each row or column is 3, 5, or 7, etc.
  • the parity part of the LDPC provided in this application is to be used for data encoding
  • the data product operation can be performed through the CPM and ME matrix. Due to the low complexity of the CPM and ME matrix, low-complexity calculations can be realized when the product calculation of data encoding is performed, so that the data encoding characteristics of high bandwidth and low delay can be achieved.
  • the introduction of the ME matrix because the number of values 1 in each row/column in the ME matrix is greater than 1, and is an odd number, it can avoid the appearance of columns with small column weights such as column weight 1 or column weight 2.
  • the error-floor is low.
  • the CPM on the diagonal in the first M1 column of the lower triangular matrix is the identity matrix.
  • the identity matrix means that the value on the diagonal of the matrix is 1, and the other values are 0.
  • the identity matrix can make CPM participate in matrix multiplication operation, the operation complexity is low, so as to achieve the characteristics of high bandwidth and low delay.
  • the LDPC check matrix further includes an information bit part; encoding the first data according to the LDPC check matrix and outputting the second data obtained after encoding includes: according to the information bit part and the first data, Obtain the first intermediate variable and output the first data at the same time; according to the first intermediate variable and the CPM of the first M1 column of the lower triangular matrix, obtain the first check digit and the second intermediate variable, and output the first check digit; Two intermediate variables and the inverse matrix of the polygon matrix of the last M2 column of the lower triangular matrix, obtain and output the second check digit; wherein the second data includes the first data, the first check digit and the second check digit.
  • the first M1 column (multiple CPM matrices) in the check digit part has low complexity involved in the multiplication operation, it can also be implemented recursively with low-complexity CPM matrix multiplication Matrix inversion; at the same time, the introduction of the multilateral (ME) matrix in the last M2 column can avoid the appearance of columns with small column weights such as column weight 1 or column weight 2, so as to ensure that the error-floor of error correction is sufficiently low.
  • ME multilateral
  • encoding the first data according to the LDPC check matrix, and outputting the encoded second data further includes: before obtaining the first intermediate variable according to the information bit part and the first data, according to the configured row The number and the number of columns determine the rows and/or columns in the LDPC check matrix that do not participate in the encoding operation; in the process of obtaining the first intermediate variable, the second intermediate variable, the first check digit, and the second check digit, no The value of the row and/or column participating in the coding operation is set to 0 for operation.
  • This application can mask the rows or columns of LDPC.
  • the LDPC mother code can be reused
  • Encoding logic At the same time, the code rate of the row/column after being masked changes, so it can support encoding of different code rates, so that it can flexibly adapt to a variety of NAND particles and their application scenarios. Furthermore, in the coding process of this application, the core operations are the CPM matrix multiplication operation and the ME matrix inverse matrix multiplication operation. The calculation logic is relatively small, so it can be guaranteed that when data is input for each shot, there is data output for each shot. , Can realize the high-bandwidth and low-delay coding process.
  • the number of values 1 in each row of the multilateral matrix is greater than 1, and is an odd number; and, the number of values 1 in each column of the multilateral matrix is greater than 1, and is an odd number. In this way, it is possible to avoid the appearance of small columns such as column weight 1 or column weight 2, so as to ensure that the error-floor of error correction is sufficiently low.
  • the polygonal matrices on the diagonal in the last M2 column of the lower triangular matrix are the same.
  • the logic of the multiplication operation can be reused when performing the multiplication operation of the code. That is to say, when the code rate is changed, after the row and/or column mask of the LDPC mother matrix, the lower triangle structure of the parity part still exists, so the coding logic of the LDPC mother code can be reused, which can be realized It supports encoding of different code rates, so that it can flexibly adapt to a variety of NAND particles and their application scenarios.
  • a low-density parity-check code LDPC encoder including: a first register for buffering first data; a calculator for encoding the first data according to an LDPC check matrix to obtain the encoded The second data; the first selector, used to output the second data; where the LDPC check matrix includes a check digit part, the check digit part is the lower triangular matrix, and the sub-matrix above the diagonal of the lower triangular matrix is zero Matrix; the sub-matrix located on the diagonal and below the diagonal in the first M1 column of the lower triangular matrix is a cyclic permutation matrix CPM; the sub-matrix located on the diagonal in the last M2 column of the lower triangular matrix is a multilateral matrix, and The sub-matrix below the diagonal is the zero matrix.
  • the parity part of the LDPC provided in this application is to be used for data encoding
  • the data product operation can be performed through the CPM and the ME matrix. Due to the low complexity of the CPM and ME matrix, low-complexity calculations can be realized when the product calculation of data encoding is performed, so that the data encoding characteristics of high bandwidth and low delay can be achieved.
  • the introduction of the ME matrix can also avoid the appearance of columns with small column weights such as column weight 1 or column weight 2, so as to ensure that the error-floor of error correction is sufficiently low.
  • the CPM on the diagonal in the first M1 column of the lower triangular matrix is the identity matrix.
  • the identity matrix means that the value on the diagonal of the matrix is 1, and the other values are 0.
  • the identity matrix can make CPM participate in matrix multiplication operation, the operation complexity is low, so as to achieve the characteristics of high bandwidth and low delay.
  • the LDPC check matrix also includes an information bit part;
  • the calculator includes: a second selector, a first multiplier, a second register, and a second multiplier; and the second selector is used to combine the first The first data output by a register is output to the first multiplier; the first multiplier is used to obtain the first intermediate variable according to the information bit part and the first data; output the intermediate variable to the second register; the second register, also Used to return the first intermediate variable to the second selector; the first multiplier is also used to obtain the first check digit according to the first intermediate variable output by the second selector and the CPM of the first M1 column of the lower triangular matrix And the second intermediate variable and output to the second register; the second register is also used to output the first check digit to the first selector so that the first selector outputs the first check digit; the second multiplier is used to According to the second intermediate variable output by the second register and the inverse matrix of the polygon matrix of the last M2 column of the lower triangular matrix, the second
  • the first M1 column (multiple CPM matrices) in the check digit part has low complexity involved in the multiplication operation, it can also be implemented recursively with low-complexity CPM matrix multiplication Matrix inversion; at the same time, the introduction of the multilateral (ME) matrix in the last M2 column can avoid the appearance of columns with small column weights such as column weight 1 or column weight 2, so as to ensure that the error-floor of error correction is sufficiently low.
  • ME multilateral
  • the first register is also used to output the first data to the first selector; the first selector is used to output the first data; the second data includes the first data and the first check bit And the second check digit.
  • the information bit part includes multiple rows, and the check digit includes multiple columns;
  • the encoder also includes an interface register, a third selector, and a state machine;
  • the interface register is used to store the LDPC check matrix The number of rows and columns involved in the encoding operation;
  • the third selector is used to determine the rows and/or columns in the LDPC check matrix that do not participate in the encoding operation according to the number of rows and columns;
  • the state machine is used to determine the rows and/or columns that do not participate in the encoding operation according to the number of rows and columns;
  • the first indication information is used to indicate the rows that do not participate in the encoding operation;
  • the second indication information is used to indicate not The column participating in the encoding operation;
  • the first multiplier is used to set the values of the rows not participating in the encoding operation to 0 when obtaining the second intermediate variable and the
  • the LDPC mother code encoding can be reused Logic:
  • the code rate of the row/column after being masked changes, so it can support encoding of different code rates, so that it can flexibly adapt to a variety of NAND particles and their application scenarios.
  • the core operations are the CPM matrix multiplication operation and the ME matrix inverse matrix multiplication operation.
  • the calculation logic is relatively small, so it can be guaranteed that when data is input for each shot, there is data output for each shot. , Can realize the high-bandwidth and low-delay coding process.
  • the number of values 1 in each row of the multilateral matrix is greater than 1, and is an odd number; and, the number of values 1 in each column of the multilateral matrix is greater than 1, and is an odd number. In this way, it is possible to avoid the appearance of small columns such as column weight 1 or column weight 2, so as to ensure that the error-floor of error correction is sufficiently low.
  • the polygonal matrices on the diagonal in the last M2 column of the lower triangular matrix are the same.
  • the logic of the multiplication operation can be reused when performing the multiplication operation of the code. That is to say, when the code rate is changed, after the row and/or column mask of the LDPC mother matrix, the lower triangle structure of the parity part still exists, so the coding logic of the LDPC mother code can be reused, which can be realized It supports encoding of different code rates, so that it can flexibly adapt to a variety of NAND particles and their application scenarios.
  • a low-density parity-check code LDPC decoding method including: acquiring first data; decoding the first data according to an LDPC check matrix, and outputting decoded second data; wherein, LDPC
  • the check matrix includes a check digit part, the check digit part is a lower triangular matrix, and the sub-matrix above the diagonal of the lower triangular matrix is a zero matrix; the first M1 column of the lower triangular matrix is located on the diagonal and the diagonal
  • the sub-matrix below is the cyclic permutation matrix CPM; the sub-matrix on the diagonal in the last M2 column of the lower triangular matrix is a multilateral matrix, and the sub-matrix below the diagonal is a zero matrix.
  • the CPMs located on the diagonal in the first M1 column are all identity matrices.
  • a low-density parity-check code LDPC decoder which includes: a first register for buffering first data; a calculator for decoding the first data according to the LDPC check matrix to obtain the translation The second data after the code; the first selector is used to output the second data; among them, the LDPC check matrix includes a check digit part, the check digit part is the lower triangular matrix, and the sub-matrix above the diagonal of the lower triangular matrix It is a zero matrix; the sub-matrix located on the diagonal and below the diagonal in the first M1 column of the lower triangular matrix is the cyclic permutation matrix CPM; the sub-matrix located on the diagonal in the last M2 column of the lower triangular matrix is a multilateral matrix , And the sub-matrix below the diagonal is a zero matrix.
  • the CPMs located on the diagonal in the first M1 column are all identity matrices.
  • a communication device in a fifth aspect, includes the encoder described in the second aspect and any possible design of the second aspect, and any possible design in the fourth aspect and the fourth aspect.
  • the decoder and memory described above are used to store data encoded by the encoder.
  • a communication system in a sixth aspect, includes the communication device as described in the fifth aspect and a server; the server is used for the communication device to send data to be encoded, or the server is used for receiving the decoded data sent by the communication device The data.
  • a communication device in a seventh aspect, includes an encoder, a processor, a modulator, and a transceiver as described in the second aspect and any possible design of the second aspect; the processor is used to execute a computer program or Instruction; modulator, used to convert the digital signal corresponding to the data encoded by the encoder into analog signal; transceiver, used to send analog signal.
  • a communication device in an eighth aspect, includes a decoder, a processor, and a demodulator as described in the fourth aspect and any one of the possible designs of the fourth aspect; the processor is used to execute a computer program Or instructions; transceiver, used to receive analog signals; demodulator, used to convert analog signals into digital signals, so that the decoder can decode the digital signals.
  • a communication system in a ninth aspect, includes the communication device according to the seventh aspect and the communication device according to the eighth aspect.
  • a computer-readable storage medium including a program or instruction.
  • the program or instruction is executed by a processor, such as the first aspect and any one of the possible designs of the first aspect, or the third aspect
  • the method described in any one of the possible designs of the aspect and the third aspect is executed.
  • a computer program product is provided.
  • an electronic device can execute any possible design such as the first aspect and the first aspect, or the third aspect and the third aspect Any of the possible designs described in the method.
  • FIG. 1 is a schematic diagram of the internal hierarchical structure of a NAND particle provided by an embodiment of the application;
  • FIG. 2 is a schematic structural diagram of a check matrix provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the architecture of a storage application provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a network architecture provided by an embodiment of the application.
  • FIG. 5 is a schematic flowchart of an LDPC encoding method provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of an LDPC check matrix provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a variable code rate of an LDPC check matrix provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a variable code rate of an LDPC check matrix provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of a variable code rate of an LDPC check matrix provided by an embodiment of the application.
  • FIG. 10 is a schematic diagram of a data encoding process provided by an embodiment of this application.
  • FIG. 11 is a schematic structural diagram of an LDPC encoder provided by an embodiment of the application.
  • FIG. 12 is a schematic flowchart of an LDPC decoding method provided by an embodiment of this application.
  • FIG. 13 is a schematic structural diagram of an LDPC decoder provided by an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of a communication device provided by an embodiment of this application.
  • NAND A storage medium, which can be called NAND particles, and is widely used in consumer audio and video electronic devices, mobile phones, data centers, servers, and cloud platforms.
  • NAND particles A storage medium, which can be called NAND particles, and is widely used in consumer audio and video electronic devices, mobile phones, data centers, servers, and cloud platforms.
  • 3D TLC Triple-Level Cell
  • eMMC Trinary-Level Cell
  • multiple channels are usually designed to improve read and write performance through multiple channels concurrency.
  • Figure 1 (a) there will be several die under one channel, one die will have 2 or 4 planes (plane), and one plane contains multiple blocks (block); Inside the block, as shown in (b) in Figure 1, a block contains several layers.
  • Each layer contains several WLs (word lines), and one WL contains 3 pages (page), which are the upper page, middle page and lower page, all of which are the same Three bits in the same position on the page share one cell on the WL.
  • the basic unit of read operation is page
  • the basic unit of write operation is page or WL
  • the basic unit of erase operation is block.
  • each ECC codeword contains a certain length of user data (information bits) And ECC check information (check digit).
  • the size of the check information depends on the size of the redundant space on the page, which is specifically related to the ECC code length and the page size, and each ECC codeword has a certain error correction capability.
  • the check matrix includes an information bit part and a check bit part.
  • the information bit portion includes multiple rows and multiple columns, and the check bit portion includes multiple rows and multiple columns.
  • an operation can be performed based on the data to be encoded and the information bit part to obtain the encoded part of the data, and then the operation can be performed based on the part of the data and the check bit part to obtain another part of the encoded data.
  • Code rate The ratio of the information bit length of the ECC codeword to the total length of the ECC codeword.
  • the embodiments of this application can be used for all devices that use NAND as a storage medium, such as CF cards, eMMC, UFS, SSDs, and Flash arrays.
  • FIG. 3 is a storage application architecture 30 shown in this application.
  • the storage application architecture 30 may include a host, a controller, and a memory.
  • the controller and the memory can be in the same device, or they can be separate devices.
  • the controller can be a NAND controller, and the memory can be a NAND memory.
  • NAND memory includes particles that use NAND as a storage medium.
  • the host can pass non-volatile memory protocol (non-volatile memory express, NVMe), serial SCSI (serial attached SCSI, SAS), high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), eMMC, UFS, etc.
  • Various interfaces are connected to the front end of the NAND controller.
  • the back end of the NAND controller can be connected to the NAND memory through an open NAND flash interface (ONFI) or a toggle interface.
  • ONFI open NAND flash interface
  • the host can read, write and erase data in the NAND memory through the NAND controller.
  • the data can be compiled and decoded through ECC in the NAND controller to ensure that the data read from the NAND memory is correct.
  • the NAND controller may include an interface for communicating with the host, an encoder, a processor, and an interface for communicating with the NAND memory. It should be noted that the storage application architecture 30 in FIG. 3 only shows some sub-modules related to the encoder, and the NAND controller may also include other sub-modules.
  • the NAND controller may also include a decoder for reading data from the NAND memory to the host.
  • FIG. 4 is another network architecture 40 shown in this application.
  • the network architecture 40 may include a data sending end and a data receiving end.
  • the transmitting end may include an encoder, a processor, a modulator, and a transceiver.
  • the receiving end may include a decoder, a processor, a demodulator, and a transceiver.
  • the transmitting end may first encode the data to be sent through the encoder, and then the modulator may modulate the encoded data, and send the modulated data through the transceiver.
  • the receiving end receives data through the transceiver, it demodulates the received data through the demodulator, sends the received data to the decoder for decoding, and stores the decoded data in the memory.
  • This application in order to solve the problem of large calculation delay and large calculation complexity of LDPC encoding.
  • This application can improve the encoder, so that when the encoder encodes data, the LDPC check matrix designed in this application can realize data encoding with low complexity operations, thereby achieving the characteristics of high bandwidth and low delay.
  • the encoder improved in the present application may be the encoder of the controller in the architecture 30 of the storage application, or the encoder of the transmitter in the network architecture 40.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present embodiment, unless otherwise specified, “plurality” means two or more.
  • the embodiment of the present application provides an LDPC encoding method, as shown in FIG. 5, which is applied to a communication device, and the communication device may be a NAND controller in a storage application architecture 30 or a sending end in a network architecture 40.
  • the method can be executed by the encoder in the NAND controller or the encoder in the sending end.
  • the method includes:
  • the communication device acquires first data.
  • the encoder in the NAND controller can receive the first data sent by the host through one of multiple interfaces such as NVMe, SAS, PCIe, eMMC, and UFS.
  • the data is the data to be encoded.
  • the first data may be generated by the processor in the transmitting end itself, or may be received by the transceiver of the transmitting end from other devices.
  • the processor at the sending end may send the generated or received first data to the encoder at the sending end.
  • the communication device encodes the first data according to the LDPC check matrix, and outputs the second data obtained after encoding.
  • a new type of LDPC check matrix is proposed, which improves the structure of the check bit part of the LDPC check matrix.
  • the LDPC check matrix includes a check digit part, the check digit part is a lower triangular matrix, and the sub-matrix above the diagonal of the lower triangular matrix is a zero matrix; the first M1 column of the lower triangular matrix is located on the diagonal The sub-matrix below the line and the diagonal is a cyclic permutation matrix (CPM); the sub-matrix on the diagonal in the last M2 column of the lower triangular matrix is a multi-edge (ME) matrix, and The sub-matrix below the diagonal is the zero matrix.
  • the LDPC check matrix also includes an information bit part.
  • the CPMs on the diagonal in the first M1 column of the lower triangular matrix are all identity matrices.
  • the information bit part and the check bit part of the LDPC check matrix are shown in FIG. 6.
  • the information bit part and the check bit part can be collectively referred to as QC-LDPC (quasi cyslic-LDPC).
  • QC-LDPC can be divided into multiple rows by row and multiple columns by column. Multiple rows and multiple columns form multiple sub-matrices.
  • the QC value of each sub-matrix can be Q, that is, each sub-matrix can be a Q*Q matrix.
  • the check digit part is a lower triangular matrix, that is, the sub-matrix above the diagonal of the lower triangular matrix is a zero matrix.
  • the code length of the QC-LDPC is NQ bits, and the length of the information bit part is (NM)Q bits,
  • the length of the parity part is MQ bits.
  • Each row corresponds to a row number, and each column corresponds to a column number.
  • the information bit part can have no special structural constraints.
  • the sub-matrices located on the diagonal and below the diagonal are CPM, that is, the CPM occupies a total of M rows and the first M1 column of the check digit part.
  • the CPM located on the diagonal in the first M1 column of the lower triangular matrix may specifically be an identity matrix.
  • the sub-matrix on the diagonal in the last M2 column of the lower triangular matrix is the ME matrix.
  • the ME matrix can be understood as located on the diagonal between the last M2 column and the last M2 row of the check digit part, and the last M2 column
  • the sub-matrix below the diagonal of the M2 row after the sum is a zero matrix.
  • M1+M2 M.
  • each row or column includes at most one 1 and the rest are all 0s.
  • the identity matrix means that the value on the diagonal of the matrix is 1, and the other values are 0.
  • the number of values 1 in each row is greater than 1, and is an odd number; and, the number of values 1 in each column is greater than 1, and is an odd number.
  • the number of 1s in each row or column is 3, 5, or 7, etc.
  • check digit part provided in this application may be a lower triangular matrix, or a lower triangular matrix after row-column transformation.
  • the parity part of the LDPC provided in this application is to be used for data encoding
  • the data product operation can be performed through the CPM and the ME matrix. Due to the low complexity of the CPM and ME matrix, in addition to ensuring the low error-floor of error correction, low-complexity calculations can be achieved when performing data encoding product operations, so as to achieve high-bandwidth and low-latency data encoding. characteristic.
  • variable code rate can also be realized by masking rows or columns.
  • the following three code rate variable modes are exemplarily shown.
  • the LDPC before the variable code rate can be called the mother code.
  • the code rate of the mother code can be calculated as: 1-M/N.
  • the variable bit rate can be achieved through certain columns in the mask information bit part.
  • the masked column can be an optional column or some columns selected according to certain rules. As shown in FIG. 7, for example, the masked column may include the column in FIG. 7 whose column number is N-M. In this case, the length of the parity bit part remains unchanged and continues to be M. The length of the information bit part becomes shorter than the length before the mask, and the value of N becomes smaller accordingly. Therefore, according to the calculation method of the code rate, the code is changed The code rate after the rate is lower than the code rate of the mother code, that is, the code rate drops.
  • the row number of the masked row is the same as the column number of the masked column (ensure the intersection of the masked row and column
  • the sub-matrix at is on the diagonal of the first M1 column).
  • at least one ME matrix needs to be retained.
  • the column number of the masked column is column 3
  • the row number of the masked LDPC is row 3.
  • the length of the information bit part does not change, the length of the parity bit part becomes shorter, then the value of N becomes smaller, and the value of M becomes smaller. Since the value of M is less than N, according to the code rate In the calculation method, the code rate after changing the code rate is greater than the code rate of the mother code, that is, the code rate is increased.
  • the row number of the masked row is row 2.
  • the number of columns M of the parity part is equal to the number of rows M of LDPC. Therefore, the length of the information bit part becomes longer, the length of the parity part becomes shorter, and the value of M becomes smaller accordingly.
  • the value of N does not change. Therefore, according to the calculation method of the code rate, the code rate after changing the code rate is greater than the code rate of the mother code, that is, the code rate is increased.
  • variable rate in this application is not limited to the above three methods, and other methods may also be used.
  • the other method may be any combination of the above three methods of variable rate.
  • step 502 may specifically include:
  • the communication device determines the row and column size of the LDPC when performing data encoding.
  • the NAND controller needs to support multiple code rates (specifications) to achieve Bandwidth requirements and delay requirements for different particles. Therefore, the NAND controller can determine the row and column size of the LDPC during data encoding according to the code rate corresponding to the NAND particle, that is, determine the size of M and N to realize the variable code rate.
  • the communication device obtains the first intermediate variable according to the information bit part and the first data, and outputs the first data at the same time.
  • the encoder can determine the rows and/or columns that need to be masked according to the sizes of M and N determined by the NAND controller, or the rows and/or columns that do not participate in the encoding operation (the rows and/or columns that are masked)
  • the value of (or column) is set to 0 for calculation to obtain a code rate suitable for NAND particles.
  • the masked row and/or column does not participate in the data encoding operation, that is, it does not participate in the operation of steps 5022-5024.
  • the masked row and/or column in the mother code can be determined according to the size of M and N and according to a preset rule.
  • the line to be masked may be multiple lines starting from a predetermined line, or multiple lines calculated according to a certain rule starting from a predetermined line.
  • the method of determining the masked column can be similar to that of the row.
  • the data received by the NAND controller can be input to the encoder for encoding operation in separate beats.
  • the first data may be the input data of one beat.
  • the encoder may first perform a product operation on the LDPC information bit part after the masked row and/or column and the first data.
  • each si represents a vector of length Q, and i is an integer of 1, 2, 3...M.
  • s i is an intermediate variable obtained by multiplying the ith row of the information bit part with the first data. If there is a masked row in the information bit, the masked row does not participate in the operation of s, or the value of the masked row is set to 0 for operation. At the same time, the first data is output to the NAND memory.
  • the communication device obtains the first check digit and the second intermediate variable according to the first intermediate variable and the CPM of the first M1 column of the lower triangular matrix, and outputs the first check digit.
  • the first intermediate variable can be calculated with the CPM of the first M1 column of the lower triangular matrix to obtain the first check digit and the second intermediate variable.
  • the first check digit can be divided into beats. Output.
  • the first beat can output s 1 to the NAND memory.
  • s 1 is multiplied with the first column of the first M1 column of the lower triangular matrix.
  • the second beat outputs the s 2 after the first update to the NAND memory.
  • the s 2 after the first update is multiplied with the second column of the first M1 column of the lower triangular matrix.
  • the result of the operation is recorded as the operation result 2.
  • the third beat outputs the s 3 after the second update to the NAND memory.
  • the s 3 after the second update is multiplied with the third column of the first M1 column of the lower triangular matrix.
  • the result of the operation is recorded as the operation result 3.
  • the M1-1th beat outputs the updated s M1-1 after the M1-2th time to the NAND memory, and at the same time the M1-2th beat
  • the s M1-1 after the second update is multiplied with the M1-1 column of the previous M1 column.
  • the result of the operation is recorded as the operation result M1-1, and the operation result M1-1 is added to the s i after the M1-2 update
  • i M1, M1+1,...,M.
  • S M1 i.e. after the first update of the M1-2, respectively, the accumulated s M1 + 1, ..., s M M1-1 calculation result, obtained after the first M1-1 s M1 update, s M1 + 1, ..., s M ;
  • the M1th beat can output the M1-1th updated s M1 to the NAND memory.
  • the result of the operation is recorded as the operation result M1
  • the operation result M1 is added to the s i after the M1-1th update.
  • i M1+1, M1+2,...,M. S M1 i.e. after the first update M1-1 + 1, respectively, the accumulated s M1 + 2, ..., s M calculation result M1, M1 S obtained after the first update M1 + 1, s M1 + 2, ..., s M.
  • the front lower triangular matrix M1 column in a first operation to take a shot of a product corresponding to M, the front mask M1 column if the column, the column is not involved in computing the mask, or mask the column
  • the value is set to 0 for operation.
  • the second encoded data output step 5023 i.e. the first parity bit comprises a first Sign s output from a first output of the second beat update s 2, the output of the third beat S 3 after the second update , ..., s M1-1 after the M1-2 update output in the M1-1th beat, and s M1 after the M1-1 update output in the M1 beat.
  • the second intermediate variable is s M1+1 , s M1+2 ,..., s M after the M 1st update.
  • the communication device obtains and outputs a second check digit according to the second intermediate variable and the inverse matrix of the ME matrix in the last M2 column of the lower triangular matrix.
  • each column in the last M2 column has an ME matrix
  • the s M1+1 , s M1+2 ,..., s M. after the M1th update in step 5023 are respectively compared with those of the M2 ME matrices in the last M2 column.
  • S M1 M1 after the first update +2 is multiplied by the inverse matrix of the ME matrix in the second column of the last M2 column, and the result of the second beat operation is obtained and output; and so on, until the s M after the M1 update is updated with the M2 in the last M2 column
  • the inverse matrix of the ME matrix of the column is multiplied to obtain and output the operation result of the M2-th beat.
  • the values of the ME matrix in the masked column are all set to 0 and then the operation is performed, or the ME matrix in the masked column does not participate in the operation.
  • the second check digit includes the M2 operation results output by the M2 beat in step 5024.
  • the second data obtained after encoding includes the unencoded first data, the first check bit and the second check bit.
  • the M2 ME matrices included in the last M2 column are all the same. In this way, when the multiplication operation in step 5024 is performed, the logic of the multiplication operation can be multiplexed.
  • the CPM matrix in the check digit part has a low complexity for participating in the multiplication operation
  • the matrix inversion can also be realized by recursive multiplication of the CPM matrix with low complexity; at the same time, the calibration
  • the introduction of the ME matrix in the checking part can avoid the appearance of columns with small column weights such as column weight 1 or column weight 2, so as to ensure that the error-floor of error correction is sufficiently low.
  • the check digit part is a lower triangular structure, the check digit part after the mask is still a lower triangular structure. If the ME matrix is the same, the ME matrix structure still exists.
  • the encoding logic of the LDPC mother code can be reused; at the same time, the code rate after the row/column is masked changes, so it can realize the encoding of different code rates, so that it can flexibly adapt to a variety of NAND particles and their application scenarios.
  • the core operations are the CPM matrix multiplication operation and the ME matrix inverse matrix multiplication operation.
  • the calculation logic is relatively small, so it can be guaranteed that when data is input for each shot, there is data output for each shot. , Can realize the high-bandwidth and low-delay coding process.
  • the present application can provide an encoder correspondingly, and the hardware design of the encoder can be used to implement the foregoing encoding process.
  • the present application provides an LDPC encoder.
  • the LCPC encoder 11 may include a first register (REG) A, a calculator B, and a first selector (MUX) C;
  • the first register A can be used to buffer the first data; that is, the first register A can be used to receive the first data input to the encoder 11 every beat;
  • Calculator B is used to encode the first data according to the LDPC check matrix to obtain the encoded second data; the calculator B can be specifically used to perform the process of step 502;
  • the first selector C is used to output the second data. That is, the first selector C is used to output the encoded data.
  • the encoder 11 may also include an interface register D, a third selector E, and a state machine F;
  • the interface register D can be used to store the number of rows M and the number of columns N participating in the encoding operation in the LDPC check matrix;
  • the third selector E is used to determine the rows and/or columns in the LDPC check matrix that do not participate in the encoding operation according to the number of rows M and the number of columns N; the third selector E determines the rows and/or columns that do not participate in the encoding according to M and N Or columns can be determined according to preset rules.
  • the state machine F is used to indicate the state of each component in the encoder 11. It includes instructions for sending instructions to calculator B based on rows and/or columns that do not participate in the encoding operation.
  • the instruction information is used to indicate the rows and/or columns that do not participate in the encoding operation (or rows and/or columns that do not participate in the encoding operation during the operation). And/or the value of the column is set to 0).
  • the calculator B When the calculator B receives the instruction information sent by the state machine F, it can perform specific calculations of data encoding according to the instruction information.
  • the calculator B includes a second selector G, a first multiplier H, a second register I, and a second multiplier J;
  • the second selector G is used to output the first data output by the first register to the first multiplier H;
  • the first multiplier H is used to obtain the first intermediate variable according to the information bit portion stored in the first multiplier H and the first data received from the second selector G; output the first intermediate variable to the second register I;
  • the second register is also used to return the first intermediate variable to the second selector G;
  • the second selector G is also used to output the first intermediate variable to the first multiplier H;
  • the first multiplier H is also used to multiply the first intermediate variable and the CPM of the first M1 column of the lower triangular matrix stored in the first multiplier H to obtain the first check digit and the second intermediate variable, and output the first Check bit and the second intermediate variable to the second register I;
  • the second register I is also used to output the first check digit to the first selector C, so that the first selector C outputs the first check digit; the second register I is also used to output the second intermediate variable to the second Multiplier J;
  • the second multiplier J is used to obtain the second check digit and output it to the first selector C according to the second intermediate variable output by the second register I and the inverse matrix of the ME matrix in the last M2 column of the lower triangular matrix, so that the A selector C outputs the second parity bit.
  • the first register A can also output the first data to the first selector C while inputting the first data to the calculator B; the first selector C is also used to output the first data.
  • the second data output by the first selector includes the first data, the first check bit, and the second check bit.
  • the state machine F when used to send instruction information to the calculator B, indicating the rows and/or columns that do not participate in the encoding operation, its specific implementation can be: the state machine F is used to send the first multiplier H to the first multiplier H. Indication information, sending second indication information to the second multiplier J; the first indication information is used to indicate rows that do not participate in the encoding operation; the second indication information is used to indicate columns that do not participate in the encoding operation.
  • the first multiplier H is also used to set the values of rows not participating in the encoding operation to 0 for operation when obtaining the second intermediate variable and the first parity bit;
  • the second multiplier J is also used to set the values of the columns not participating in the encoding operation to 0 for operation when obtaining the second parity bit.
  • the LDPC mother matrix can be solidified in the encoding engine.
  • the encoding engine can obtain the matrix size from the interface register, and thus the mother matrix can be obtained according to the row and column size. In this way, there is no need for a separate random access memory (RAM) space to store the coding matrix, which saves storage space.
  • the improvement of the encoder in this application enables the encoder to support multiple code rates through a simple row and column mask, and the encoder delay is only 1 cycle, that is, the data to be encoded starts from the first one of the encoder per beat. Received by the register, after calculation by the calculator, the result of the operation can output the encoded data for each beat through the first selector. This can ensure high encoding bandwidth.
  • the embodiment of the present application may also provide a low-density parity-check code LDPC decoding method. As shown in FIG. 12, the method includes:
  • the LDPC check matrix includes a check digit part, the check digit part is a lower triangular matrix, and the sub-matrix above the diagonal of the lower triangular matrix is a zero matrix; the first M1 column of the lower triangular matrix is located on the diagonal and the diagonal
  • the sub-matrix below the line is the cyclic permutation matrix CPM; the sub-matrix on the diagonal in the last M2 column of the lower triangular matrix is the ME matrix, and the sub-matrix below the diagonal is the zero matrix.
  • CPM cyclic permutation matrix
  • ME matrix the sub-matrix below the diagonal
  • the CPM on the diagonal in the first M1 column of the lower triangular matrix is the identity matrix.
  • an embodiment of the present application may also provide a low-density parity-check code LDPC decoder 13, including: a first register 130 for buffering first data; a calculator 131 , Used to decode the first data according to the LDPC check matrix to obtain the decoded second data; the first selector 132, used to output the second data; wherein, the LDPC check matrix includes a check bit part, The check digit part is the lower triangular matrix, and the sub-matrix above the diagonal of the lower triangular matrix is the zero matrix; the sub-matrices located on the diagonal and below the diagonal in the first M1 column of the lower triangular matrix are the cyclic permutation matrix CPM; The sub-matrix on the diagonal in the last M2 column of the triangular matrix is the ME matrix, and the sub-matrix below the diagonal is the zero matrix.
  • LDPC check matrix includes a check bit part, The check digit part is the lower triangular matrix, and the sub-matrix above the diagonal
  • the CPM on the diagonal in the first M1 column of the lower triangular matrix is the identity matrix.
  • An embodiment of the present application further provides a communication device 14.
  • the communication device includes an encoder, a decoder, and a memory as described in the foregoing embodiment, and the memory is used to store data encoded by the encoder.
  • the communication device may be, for example, a device combined with a controller and a memory in the architecture corresponding to FIG. 3, and the controller includes an encoder and a decoder.
  • An embodiment of the present application also provides a communication system.
  • the communication system includes a communication device as shown in FIG. 14 and a server; the server is used for the communication device to send data to be encoded, or the server is used for receiving the decoded data sent by the communication device.
  • the data may be the host in the architecture shown in FIG. 3.
  • An embodiment of the present application also provides a communication device.
  • the communication device includes an encoder as shown in FIG. 11, and further includes a processor, a modulator, and a transceiver; the processor is used to execute computer programs or instructions; the modulator is used to encode The digital signal corresponding to the data encoded by the converter is converted into an analog signal; the transceiver is used to send the analog signal.
  • the communication device may be the sending end of data, corresponding to the sending end in FIG. 4.
  • the sending end may be, for example, a terminal device or a network device.
  • An embodiment of the present application further provides a communication device.
  • the communication device includes the decoder as shown in FIG. 13, and further includes a processor, a transceiver, and a demodulator; the processor is used to execute computer programs or instructions; the transceiver, Used to receive analog signals; demodulator, used to convert analog signals into digital signals, so that the decoder can decode the digital signals.
  • the communication device can be the receiving end of data, corresponding to the receiving end in FIG. 4.
  • the receiving end may be, for example, a terminal device or a network device.
  • An embodiment of the present application also provides a communication system.
  • the communication system includes a sending end as shown in FIG. 4 and a receiving end as shown in FIG. 4.
  • An embodiment of the present application also provides a computer-readable storage medium, including a program or instruction.
  • the program or instruction is executed by a processor, the method corresponding to FIG. 5 and/or FIG. 10 and/or FIG. 12 is executed. .
  • the embodiment of the present application also provides a computer program product, which when the computer program product runs on a computer, causes the electronic device to execute the method corresponding to FIG. 5 and/or FIG. 10 and/or FIG. 12.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be divided. It can be combined or integrated into another device, or some features can be omitted or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate parts may or may not be physically separate.
  • the parts displayed as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed to multiple different places. . Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium.
  • the technical solutions of the embodiments of the present application are essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product, and the software product is stored in a storage medium. It includes several instructions to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read only memory (read only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes.

Abstract

本申请实施例提供一种低密度奇偶校验码编码方法和编码器，涉及芯片技术领域，能够解决采用LDPC编码计算时延大，计算复杂度大的问题。其方法为：根据LDPC校验矩阵对第一数据进行编码，并输出编码后得到的第二数据；其中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及对角线下方的子矩阵为CPM；下三角矩阵的后M2列中的位于对角线上的子矩阵为多边矩阵，且位于对角线下方的子矩阵为零矩阵。本申请实施例用于在存储应用架构的数据编码或通信架构中数据发送端的数据编码。

Description

低密度奇偶校验码编码方法和编码器 技术领域
本申请涉及芯片技术领域，尤其涉及一种低密度奇偶校验码(low density parity check code，LDPC)编码方法和编码器。
背景技术
NAND是目前市场上最常使用的存储介质之一，通常以CF(compact flash)卡、嵌入式多媒体卡(embedded multi media card，eMMC)、通用闪存存储(universal flash storage，UFS)以及固态硬盘(solid state drive，SSD)、闪存(Flash)阵列的形态存在。数据可靠性、数据读写的带宽和时延是所有NAND器件或模组的核心指标，同时也是对应产品竞争力的关键因素之一。
随着NAND制程工艺的演进、3D芯片堆叠技术的引入以及存储单元(cell)存储比特(bit)数的增加，存储密度越来越高，在读、写和擦等操作中会产生更多错误bit数，需要更强的可靠性保障技术来保证数据的可靠性。为了保证数据的可靠性，LDPC码已经成为业界主流的编码方式。通常，一款NAND控制器需要适配多种型号的NAND颗粒，但是每种颗粒的冗余空间大小以及纠错能力需求各不相同，需要单一编译码器支持多种规格(码率)，同时不管是消费级应用还是企业级的应用，对于读写带宽和时延的要求也是越来越高，这就需要高吞吐率低时延的LDPC码。另一方面，对于企业级应用，变码率方案也是提升NAND颗粒使用寿命的重要手段之一，该技术要求在NAND颗粒不同的生命周期采用不同的码率。其中，每次在编码器需要切换编码矩阵的规格前，重新加载一次编码矩阵以及相关参数，实现多码率规格的支持。但是，校验矩阵没有特定结构，如果采用编码矩阵直接编码，会导致编码的计算时延很大，且通常需要设计多级pipeline才能达到高带宽，计算复杂度大。
发明内容
本申请实施例提供一种LDPC编码方法和编码器，能够解决采用LDPC编码计算时延大，计算复杂度大的问题。
为达到上述目的，本申请实施例采用如下技术方案：
第一方面，提供一种低密度奇偶校验码LDPC编码方法，包括：获取第一数据；根据LDPC校验矩阵对第一数据进行编码，并输出编码后得到的第二数据；其中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及对角线下方的子矩阵为循环置换矩阵CPM；下三角矩阵的后M2列中的位于对角线上的子矩阵为多边(ME)矩阵，且位于对角线下方的子矩阵为零矩阵。本申请提供的校验位部分可以为下三角矩阵，也可以为经过行列变换后的一个下三角矩阵。其中，CPM中，每行或每列最多包括一个1，其余全为0。ME矩阵中，每行中值为1的个数大于1，且为奇数；以及，每列中值为1的个数大于1，且为奇数。例如每行或每列中1的个数为3个、5个或7个等。
由此，通过本申请提供的LDPC的校验位部分，如果要进行数据编码时，可以通 过CPM以及ME矩阵进行数据乘积运算。由于CPM和ME矩阵的复杂度低，进行数据编码的乘积运算时，可以实现低复杂度的运算，从而可以达到高带宽低时延的数据编码特性。同时，ME矩阵的引入，由于ME矩阵中，每行/列中值为1的个数大于1，且为奇数，可以避免列重1或列重2等小列重的列出现，从而保证纠错的error-floor较低。
在一种可能的设计中，下三角矩阵的前M1列中位于对角线上的CPM为单位矩阵。单位矩阵是指该矩阵中对角线上的值为1，其余值均为0。单位矩阵可以使得CPM参与矩阵乘运算时，运算复杂度低，从而达到高带宽低时延的特性。
在一种可能的设计中，LDPC校验矩阵还包括信息位部分；根据LDPC校验矩阵对第一数据进行编码，并输出编码后得到的第二数据包括：根据信息位部分和第一数据，获取第一中间变量，同时输出第一数据；根据第一中间变量和下三角矩阵的前M1列的CPM，获取第一校验位和第二中间变量，并输出第一校验位；根据第二中间变量和下三角矩阵的后M2列的多边矩阵的逆矩阵，获取第二校验位并输出；其中，第二数据包括第一数据、第一校验位和第二校验位。由此，由于本申请提供的LDPC校验矩阵中，校验位部分中的前M1列(多个CPM矩阵)参与乘法运算的复杂度较低，还可以以低复杂度的CPM矩阵乘递归实现矩阵求逆；同时，后M2列中多边(ME)矩阵的引入，可以避免列重1或列重2等小列重的列出现，从而可以保证纠错的error-floor足够低。
在一种可能的设计中，根据LDPC校验矩阵对第一数据进行编码，输出编码后的第二数据还包括：在根据信息位部分和第一数据获取第一中间变量之前，根据配置的行数和列数确定LDPC校验矩阵中不参与编码运算的行和/或列；在获取第一中间变量、第二中间变量、第一校验位以及第二校验位的过程中，将不参与编码运算的行和/或列的值置为0进行运算。本申请可以对LDPC的行或列进行mask，由于校验位部分为下三角结构，mask后校验位部分剩余部分依然为下三角结构，ME矩阵结构依然存在，因此可以复用LDPC母码的编码逻辑；同时行/列被mask后的码率发生变化，因此可以实现支持不同码率的编码，从而可以灵活适配多种NAND颗粒以其应用场景。再者，本申请的编码流程中，其核心运算为CPM矩阵乘运算和ME矩阵的逆矩阵乘运算，其计算逻辑复杂度较小，因此可以保证每拍数据输入时，每拍都有数据输出，可以实现高带宽低时延的编码流程。
在一种可能的设计中，多边矩阵的每行中值为1的个数大于1，且为奇数；以及，多边矩阵的每列中值为1的个数大于1，且为奇数。这样可以避免列重1或列重2等小列重的列出现，从而可以保证纠错的error-floor足够低。
在一种可能的设计中，下三角矩阵的后M2列中的位于对角线上的多边矩阵相同。这样，在进行编码的乘法运算时，乘法运算的逻辑可以复用。也就是说，在进行变码率时，可以对LDPC母矩阵进行行和/或列的mask后，校验位部分的下三角结构依然存在，因此可以复用LDPC母码的编码逻辑，可以实现支持不同码率的编码，从而可以灵活适配多种NAND颗粒以其应用场景。
第二方面，提供一种低密度奇偶校验码LDPC编码器，包括：第一寄存器，用于缓存第一数据；计算器，用于根据LDPC校验矩阵对第一数据进行编码，得到编码后 的第二数据；第一选择器，用于输出第二数据；其中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及对角线下方的子矩阵为循环置换矩阵CPM；下三角矩阵的后M2列中的位于对角线上的子矩阵为多边矩阵，且位于对角线下方的子矩阵为零矩阵。
由此，通过本申请提供的LDPC的校验位部分，如果要进行数据编码时，可以通过CPM以及ME矩阵进行数据乘积运算。由于CPM和ME矩阵的复杂度低，进行数据编码的乘积运算时，可以实现低复杂度的运算，从而可以达到高带宽低时延的数据编码特性。ME矩阵的引入，还可以避免列重1或列重2等小列重的列出现，从而可以保证纠错的error-floor足够低。
在一种可能的设计中，下三角矩阵的前M1列中位于对角线上的CPM为单位矩阵。单位矩阵是指该矩阵中对角线上的值为1，其余值均为0。单位矩阵可以使得CPM参与矩阵乘运算时，运算复杂度低，从而达到高带宽低时延的特性。
在一种可能的设计中，LDPC校验矩阵还包括信息位部分；计算器包括：第二选择器、第一乘法器、第二寄存器以及第二乘法器；第二选择器，用于将第一寄存器输出的第一数据输出至第一乘法器；第一乘法器，用于根据信息位部分和第一数据，获取第一中间变量；将中间变量输出至第二寄存器；第二寄存器，还用于将第一中间变量返回至第二选择器；第一乘法器，还用于根据第二选择器输出的第一中间变量以及下三角矩阵的前M1列的CPM，获取第一校验位和第二中间变量并输出至第二寄存器；第二寄存器，还用于输出第一校验位至第一选择器，使第一选择器输出第一校验位；第二乘法器，用于根据第二寄存器输出的第二中间变量和下三角矩阵的后M2列的多边矩阵的逆矩阵，获取第二校验位输出至第一选择器，使第一选择器输出第二校验位。由此，由于本申请提供的LDPC校验矩阵中，校验位部分中的前M1列(多个CPM矩阵)参与乘法运算的复杂度较低，还可以以低复杂度的CPM矩阵乘递归实现矩阵求逆；同时，后M2列中多边(ME)矩阵的引入，可以避免列重1或列重2等小列重的列出现，从而可以保证纠错的error-floor足够低。
在一种可能的设计中，第一寄存器，还用于输出第一数据至第一选择器；第一选择器，用于输出第一数据；第二数据包括第一数据、第一校验位以及第二校验位。
在一种可能的设计中，信息位部分包括多个行，校验位包括多个列；编码器还包括接口寄存器、第三选择器以及状态机；接口寄存器，用于存储LDPC校验矩阵中参与编码运算的行数和列数；第三选择器，用于根据行数和列数确定LDPC校验矩阵中不参与编码运算的行和/或列；状态机，用于根据不参与编码运算的行和/或列向第一乘法器发送第一指示信息，向第二乘法器发送第二指示信息；第一指示信息用于指示不参与编码运算的行；第二指示信息用于指示不参与编码运算的列；第一乘法器，用于在获取第二中间变量和第一校验位时，将不参与编码运算的行的值均置为0进行运算；第二乘法器，用于在获取第二校验位时，将不参与编码运算的列的值均置为0进行运算。本申请在对LDPC的行或列进行mask时，由于校验位部分为下三角结构，mask后校验位部分依然为下三角结构，ME矩阵结构依然存在，因此可以复用LDPC母码的编码逻辑；同时行/列被mask后的码率发生变化，因此可以实现支持不同码率的编 码，从而可以灵活适配多种NAND颗粒以其应用场景。再者，本申请的编码流程中，其核心运算为CPM矩阵乘运算和ME矩阵的逆矩阵乘运算，其计算逻辑复杂度较小，因此可以保证每拍数据输入时，每拍都有数据输出，可以实现高带宽低时延的编码流程。
在一种可能的设计中，多边矩阵的每行中值为1的个数大于1，且为奇数；以及，多边矩阵的每列中值为1的个数大于1，且为奇数。这样可以避免列重1或列重2等小列重的列出现，从而可以保证纠错的error-floor足够低。
在一种可能的设计中，下三角矩阵的后M2列中的位于对角线上的多边矩阵相同。这样，在进行编码的乘法运算时，乘法运算的逻辑可以复用。也就是说，在进行变码率时，可以对LDPC母矩阵进行行和/或列的mask后，校验位部分的下三角结构依然存在，因此可以复用LDPC母码的编码逻辑，可以实现支持不同码率的编码，从而可以灵活适配多种NAND颗粒以其应用场景。
第三方面，提供一种低密度奇偶校验码LDPC译码方法，包括：获取第一数据；根据LDPC校验矩阵对第一数据进行译码，输出译码后的第二数据；其中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及所述对角线下方的子矩阵为循环置换矩阵CPM；下三角矩阵的后M2列中的位于对角线上的子矩阵为多边矩阵，且位于对角线下方的子矩阵为零矩阵。与编码过程类似的，通过本申请提供的LDPC校验矩阵，在进行数据译码时，可以通过CPM以及ME矩阵进行数据运算。由于CPM和ME矩阵的复杂度低，进行数据译码运算时，其计算复杂度低，可以达到高带宽低时延的数据译码特性。
在一种可能的设计中，位于前M1列中对角线上的CPM均为单位矩阵。
第四方面，提供一种低密度奇偶检验码LDPC译码器，包括：第一寄存器，用于缓存第一数据；计算器，用于根据LDPC校验矩阵对第一数据进行译码，得到译码后的第二数据；第一选择器，用于输出第二数据；其中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及对角线下方的子矩阵为循环置换矩阵CPM；下三角矩阵的后M2列中的位于对角线上的子矩阵为多边矩阵，且位于对角线下方的子矩阵为零矩阵。与编码过程类似的，通过本申请提供的LDPC校验矩阵，在进行数据译码时，可以通过CPM以及ME矩阵进行数据运算。由于CPM和ME矩阵的复杂度低，进行数据译码运算时，其计算复杂度低，可以达到高带宽低时延的数据译码特性。
在一种可能的设计中，位于前M1列中对角线上的CPM均为单位矩阵。
第五方面，提供一种通信装置，通信装置包括如第二方面以及第二方面的任一种可能的设计所述的编码器、如第四方面以及第四方面的任一种可能的设计所述的译码器以及存储器，存储器用于存储所述编码器编码后的数据。
第六方面，提供一种通信系统，通信系统包括如第五方面所述的通信装置以及服务器；服务器，用于通信装置发送待编码的数据，或服务器，用于接收通信装置发送的译码后的数据。
第七方面，提供一种通信装置，通信装置包括如第二方面以及第二方面的任一种 可能的设计所述的编码器、处理器、调制器以及收发器；处理器用于执行计算机程序或指令；调制器，用于将编码器编码后的数据对应的数字信号转换为模拟信号；收发器，用于发送模拟信号。
第八方面，提供一种通信装置，通信装置包括如第四方面以及第四方面的任一种可能的设计所述的译码器、处理器以及解调器；处理器，用于执行计算机程序或指令；收发器，用于接收模拟信号；解调器，用于将模拟信号转换为数字信号，以便译码器对数字信号进行译码。
第九方面，提供一种通信系统，通信系统包括如第七方面所述的通信装置和如第八方面所述的通信装置。
第十方面，提供一种计算器可读存储介质，包括程序或指令，当所述程序或指令被处理器运行时，如第一方面以及第一方面的任一种可能的设计、或第三方面以及第三方面的任一种可能的设计所述的方法被执行。
第十一方面，提供一种计算机程序产品，当计算机程序产品在计算机上运行时，使得电子设备执行如第一方面以及第一方面的任一种可能的设计、或第三方面以及第三方面的任一种可能的设计所述的方法。
附图说明
图1为本申请实施例提供的一种NAND颗粒的内部层次结构示意图；
图2为本申请实施例提供的一种校验矩阵的结构示意图；
图3为本申请实施例提供的一种存储应用的架构示意图；
图4为本申请实施例提供的一种网络架构示意图；
图5为本申请实施例提供的一种LDPC编码方法流程示意图；
图6为本申请实施例提供的一种LDPC校验矩阵的结构示意图；
图7为本申请实施例提供的一种LDPC校验矩阵变码率的示意图；
图8为本申请实施例提供的一种LDPC校验矩阵变码率的示意图；
图9为本申请实施例提供的一种LDPC校验矩阵变码率的示意图；
图10为本申请实施例提供的一种数据编码的流程示意图；
图11为本申请实施例提供的一种LDPC编码器的结构示意图；
图12为本申请实施例提供的一种LDPC译码方法的流程示意图；
图13为本申请实施例提供的一种LDPC译码器的结构示意图；
图14为本申请实施例提供的一种通信装置的结构示意图。
具体实施方式
为了便于理解，示例的给出了部分与本申请实施例相关概念的说明以供参考。如下所示：
NAND：一种存储介质，可以称为NAND颗粒，在消费类音视频电子器件、手机、数据中心、服务器以及云平台中都有着广泛的使用。以3D TLC(Trinary-Level Cell)的存储结构为例，NAND颗粒内部层次结构可以如图1所示。在eMMC、UFS、SSD等应用中通常会设计多个通道(channel)，通过多个channel并发来提升读写性能。一般而言，如图1中的(a)所示，一个channel下会存在若干个die，一个die会存在2个或4个平面(plane)，而一个plane有包含多个块(block)；在block内部，如图1 中的(b)所示，一个block包含若干个层(layer)。每个layer包含若干个WL(word line，字线)，一个WL中包含3个页(page)，为上页(upper page)、中页(middle page)和下页(lower page)，其中同一WL上3个page相同位置的bit共享一个cell。一般而言，读操作的基本单元为page，写操作的基本单元为page或WL，而擦除操作的基本单元为block。
如图1中的(c)所示，每个page上的数据会被划分若干个纠错码(Error Correction Code，ECC)码字，每个ECC码字包含一定长度的用户数据(信息位)和ECC校验信息(校验位)。其中，校验信息的大小取决于page上冗余空间的大小，具体与ECC码长和page大小相关，每个ECC码字会有一定的纠错能力。
校验矩阵：如图2所示，通常，校验矩阵包括信息位部分和校验位部分。信息位部分包括多行和多列，校验位部分包括多行和多列。在进行数据编码时，可以根据待编码的数据和信息位部分进行运算，得到编码后的部分数据，再根据该部分数据和校验位部分进行运算，得到编码后的另一部分数据。
码率：ECC码字的信息位长度在ECC码字总长度中所占的比例。
本申请实施例可以用于所有应用NAND作为存储介质的器件，例如CF卡、eMMC、UFS、SSD以及Flash阵列等。
图3为本申请示出的一种存储应用的架构30，该存储应用的架构30可以包括主机、控制器以及存储器。控制器和存储器可以在同一个设备中，也可以分别为独立的设备。该控制器可以为NAND控制器，存储器可以为NAND存储器。NAND存储器中包括应用NAND作为存储介质的颗粒。主机可以通过非易失性内存协议(non-volatile memory express，NVMe)、串行SCSI(serial attached SCSI，SAS)、高速串行计算机扩展总线标准(peripheral component interconnect express，PCIe)、eMMC以及UFS等多种接口与NAND控制器的前端连接。NAND控制器的后端可以通过开放式NAND快闪存储器接口(open nAND flash interface，ONFI)或Toggle接口与NAND存储器连接。主机可以通过NAND控制器对NAND存储器中的数据进行读、写和擦等操作。其中，可以在NAND控制器中通过ECC对数据进行编译码操作，保证从NAND存储器中读出的数据是正确的。
其中，NAND控制器可以包括与主机通信的接口、编码器、处理器以及与NAND存储器通信的接口。需要说明的是，图3的存储应用的架构30中只示出了与编码器相关的部分子模块，NAND控制器还可以包括其他子模块。
相应的，NAND控制器中还可以包括译码器，用于对主机从NAND存储器中读取的数据。
图4为本申请示出的另一种网络架构40，该网络架构40可以包括数据的发送端和数据的接收端。发送端可以包括编码器、处理器、调制器以及收发器。接收端可以包括译码器、处理器、解调器以及收发器。发送端可以先通过编码器对待发送的数据进行编码，之后调制器可以对编码后的数据进行调制，通过收发器发送调制后的数据。接收端可以通过收发器接收到数据时，通过解调器解调接收到的数据，将接收到的数据再发送给译码器进行译码，将译码后的数据存储在存储器中。
本申请实施例中，为了解决LDPC编码计算时延大，计算复杂度大的问题。本申 请可以对编码器进行改进，使得该编码器在对数据编码时，可以通过本申请设计的LDPC校验矩阵实现低复杂度运算的数据编码，从而可以达到高带宽低时延的特性。本申请改进的编码器可以是存储应用的架构30中的控制器的编码器，也可以是网络架构40中发送端的编码器。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请实施例的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，在本申请实施例的描述中，“多个”是指两个或多于两个。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例提供一种LDPC编码方法，如图5所示，应用于通信装置，该通信装置可以为存储应用的架构30中的NAND控制器，或网络架构40中的发送端。具体可以由NAND控制器中的编码器或发送端中的编码器执行该方法。该方法包括：
501、通信装置获取第一数据。
在一些实施例中，若通信装置为NAND控制器，NAND控制器中的编码器可以通过NVMe、SAS、PCIe、eMMC以及UFS等多种接口中的一个接口接收主机发送的第一数据，第一数据为待编码的数据。
在一些实施例中，若通信装置为发送端，第一数据可以是发送端中的处理器自身生成的，也可以是发送端的收发器从其他设备接收到的。发送端中的处理器可以将生成的或接收到的第一数据发送给发送端的编码器。
502、通信装置根据LDPC校验矩阵对第一数据进行编码，并输出编码后得到的第二数据。
本申请实施例中，提出一种新型的LDPC校验矩阵，对LDPC校验矩阵的校验位部分的结构进行了改进。
在一些实施例中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及对角线下方的子矩阵为循环置换矩阵(cyclic permutation matrix，CPM)；下三角矩阵的后M2列中的位于对角线上的子矩阵为多边(multi-edge，ME)矩阵，且位于对角线下方的子矩阵为零矩阵。LDPC校验矩阵还包括信息位部分。
在一些实施例中，下三角矩阵的前M1列中位于对角线上的CPM均为单位矩阵。
示例性的，如图6所示，LDPC校验矩阵的信息位部分和校验位部分在图6中已示出。信息位部分和校验位部分可以统称为QC-LDPC(quasi cyslic-LDPC，准循环LDPC)。QC-LDPC按行可以分为多行，按列可以分为多列，多行和多列构成多个子矩阵。每个子矩阵的QC值可以为Q，即每个子矩阵可以为Q*Q的矩阵。其中，校验位部分为下三角矩阵，也就是下三角矩阵对角线上方的子矩阵为零矩阵。
若QC-LDPC的行数为M，列数为N，且校验位部分的列数为M，则该QC-LDPC 的码长为NQ bits，信息位部分的长度为(N-M)Q bits，校验位部分的长度为MQ bits。每一行对应一个行号，每一列对应一个列号。信息位部分可以无特殊结构约束。校验位部分的下三角矩阵的前M1列中位于对角线以及对角线下方的子矩阵为CPM，即CPM共占用M行和校验位部分的前M1列。其中，下三角矩阵的前M1列中位于对角线上的CPM具体可以为单位矩阵。下三角矩阵的后M2列中的位于对角线上的子矩阵为ME矩阵，ME矩阵即则可以理解为位于校验位部分的后M2列和后M2行的对角线上，后M2列和后M2行的对角线下方的子矩阵为零矩阵。其中，M1+M2＝M。
其中，CPM中，每行或每列最多包括一个1，其余全为0。单位矩阵是指该矩阵中对角线上的值为1，其余值均为0。ME矩阵中，每行中值为1的个数大于1，且为奇数；以及，每列中值为1的个数大于1，且为奇数。例如每行或每列中1的个数为3个、5个或7个等。
需要说明的是，本申请提供的校验位部分可以为下三角矩阵，也可以为经过行列变换后的一个下三角矩阵。
由此，通过本申请提供的LDPC的校验位部分，如果要进行数据编码时，可以通过CPM以及ME矩阵进行数据乘积运算。由于CPM和ME矩阵的复杂度低，进行数据编码的乘积运算时，除了保证纠错的error-floor较低以外，还可以实现低复杂度的运算，从而可以达到高带宽低时延的数据编码特性。
在本申请提供的LDPC结构下，还可以通过对行或列进行标记(mask)实现变码率。本申请实施例中，示例性的示出以下三种变码率方式。其中，可以将变码率之前的LDPC称为母码。母码的码率的计算方式可以为：1-M/N。
1)可以通过mask信息位部分中的某些列来实现变码率。被mask的列可以是任选的列，也可以是按照一定的规则选择的某些列。如图7所示，例如被mask的列可以包括图7中的列的列号为N-M。这种情形下，校验位部分的长度不变，继续为M，信息位部分的长度相对mask之前的长度变短，那么N值也相应变小，因此，根据码率的计算方式，变码率后的码率小于母码的码率，即码率下降了。
2)可以通过mask校验位部分中的某些列，同时mask LDPC中的某些行，被mask的行的行号与被mask的列的列号相同(保证被mask的行和列的交汇处的子矩阵在前M1列的对角线上)。但是，需要保留至少一个ME矩阵。如图8所示，例如被mask的列的列号为列3，被mask的LDPC的行号为行3。这种情况下，信息位部分的长度不变，校验位部分的长度变短，那么N的值相应变小，M的值也相应变小，由于M的值小于N，因此，根据码率的计算方式，变码率后的码率大于母码的码率，即码率升高了。
3)可以通过mask LDPC中的某些行，但是需要保留至少一个ME矩阵。如图9所示，例如被mask的行的行号为行2。这种情形下，由于LDPC中，校验位部分的列数M等于LDPC的行数M，因此，信息位部分的长度变长，校验位部分的长度变短，M的值相应变小，N的值不变，因此，根据码率的计算方式，变码率后的码率大于母码的码率，即码率升高了。
需要说明的是，本申请变码率的方式不限于上述三种，还可以为其他的方式，例如其他方式可以为上述三种变码率方式的任意组合。
在了解了利用本申请提供的LDPC实现编码率的原理的基础上，本申请对步骤502中进行数据编码的编码流程进行进一步说明。如图10所示，步骤502具体可以包括：
5021、通信装置确定进行数据编码时的LDPC的行列大小。
由于待存储数据的存储器的NAND颗粒的型号有多种，每种颗粒的冗余空间大小以及纠错能力的需求各不相同，因此，NAND控制器需要支持多种码率(规格)，以实现对不同颗粒的带宽需求和时延需求。因此，NAND控制器可以根据NAND颗粒对应的码率确定进行数据编码时LDPC的行和列的大小，即确定M和N的大小，以实现变码率。
5022、通信装置根据信息位部分和第一数据，获取第一中间变量，同时输出第一数据。
在一些实施例中，编码器可以根据NAND控制器确定的M和N的大小确定需要mask的行和/或列，或者，将不参与编码运算的行和/或列(被mask的行和/或列)的值置为0进行运算，以得到适应NAND颗粒的码率，被mask的行和/或列不参与数据编码的运算，即不参与步骤5022～5024的运算。
在一些实施例中，可以根据M和N的大小并按照预设的规则确定母码中被mask的行和/或列。例如被mask的行可以是从预定的某一行开始的多个行，或者从与预定的某一行开始按照一定的规律计算的多个行。被mask的列的确定方式可以与行类似。
这样，在确定了被mask的行和/或列时，也就确定了母码中参与数据编码运算的行和列。
对于NAND控制器接收到的数据可以分拍输入到编码器中进行编码运算。第一数据可以为输入的一拍数据。编码运算时，编码器可以先将被mask行和/或列后的LDPC的信息位部分和第一数据进行乘积运算。该乘积运算是指将信息位部分的每一行分别与第一数据进行乘积运算，得到第一中间变量。若被mask行和/或列后，信息位部分的行数为M，那么第一中间变量记为s时，s＝(s 1、s 2、s 3、…、s M)。其中，每个s i代表长度为Q的矢量，i为1、2、3……M的整数。s i为将信息位部分的第i行分别与第一数据进行乘积运算得到的中间变量。信息位部分若有被mask的行，被mask的行不参与s的运算，或者将被mask的行的值置为0进行运算。同时输出第一数据给NAND存储器。
5023、通信装置根据第一中间变量和下三角矩阵的前M1列的CPM，获取第一校验位和第二中间变量，并输出第一校验位。
待第一数据输出完成后，接下来将第一中间变量可以和下三角矩阵的前M1列的CPM进行运算，运算得到第一校验位和第二中间变量，第一校验位可以分拍输出。
具体的，第一拍可以输出s 1给NAND存储器，同时将s 1与下三角矩阵的前M1列的第一列进行乘积运算，运算结果记为运算结果1，将运算结果1累加在s i上，此时i＝2、3、…、M。即在s 2、s 3、…、s M上分别累加运算结果1，得到第一次更新后的s 2、s 3、…、s M；
第二拍输出第一次更新后的s 2给NAND存储器，同时将第一次更新后的s 2与下三角矩阵的前M1列的第二列进行乘积运算，运算结果记为运算结果2，将运算结果2累加在第一次更新后的s i上，此时i＝3、4、…、M。即在第一次更新后的s 3、s 4、…、 s M上分别累加运算结果2，得到第二次更新后的s 3、s 4、…、s M；
第三拍输出第二次更新后的s 3给NAND存储器，同时将第二次更新后的s 3与下三角矩阵的前M1列的第三列进行乘积运算，运算结果记为运算结果3，将运算结果3累加在第二次更新后的s i上，此时i＝4、5、…、M。即在第二次更新后的s 4、s 5、…、s M上分别累加运算结果3，得到第三次更新后的s 4、s 5、…、s M；
按照输出第一拍、第二拍和第三拍时对应的乘积运算的计算方式，第M1-1拍输出第M1-2次更新后的s M1-1给NAND存储器，同时将第M1-2次更新后的s M1-1与前M1列的第M1-1列进行乘积运算，运算结果记为运算结果M1-1，将运算结果M1-1累加在第M1-2次更新后的s i上，此时i＝M1、M1+1、…、M。即在第M1-2次更新后的s M1、s M1+1、…、s M上分别累加运算结果M1-1，得到第M1-1次更新后的s M1、s M1+1、…、s M；
当下三角矩阵的前M1列进行乘积运算到第M1列时，则第M1拍可以输出第M1-1次更新后的s M1给NAND存储器。同时，将第M1-1次更新后的s M1与前M1列的第M1列进行乘积运算，运算结果记为运算结果M1，将运算结果M1累加在第M1-1次更新后的s i上，此时i＝M1+1、M1+2、…、M。即在第M1-1次更新后的s M1+1、s M1+2、…、s M上分别累加运算结果M1，得到第M1次更新后的s M1+1、s M1+2、…、s M。
其中，下三角矩阵的前M1列中第一拍到第M 1拍对应的乘积运算中，前M1列中若有被mask的列，被mask的列不参与运算，或者将被mask的列的值置为0进行运算。
也就是说，步骤5023输出的编码后的数据，也就是第一校验位包括第一拍输出的s 1、第二拍输出的第一次更新后的s 2、第三拍输出的第二次更新后的s 3、…、第M1-1拍输出的第M1-2次更新后的s M1-1，以及第M1拍输出的第M1-1次更新后的s M1。第二中间变量为第M 1次更新后的s M1+1、s M1+2、…、s M。
5024、通信装置根据第二中间变量和下三角矩阵的后M2列的ME矩阵的逆矩阵，获取第二校验位并输出。
具体的，后M2列中每一列有一个ME矩阵，将步骤5023中第M1次更新后的s M1+1、s M1+2、…、s M.分别与后M2列中M2个ME矩阵的逆矩阵相乘，得到M2个运算结果，该运算结果也是分拍输出。
即，将第M 1次更新后的s M1+1与后M2列中第一列的ME矩阵的逆矩阵相乘，得到第一拍的运算结果并输出；将第M1次更新后的s M1+2与后M2列中第二列的ME矩阵的逆矩阵相乘，得到第二拍的运算结果并输出；以此类推，直到将第M1次更新后的s M与后M2列中第M2列的ME矩阵的逆矩阵相乘，得到第M2拍的运算结果并输出。其中，后M2列中若有被mask的列，被mask的列中的ME矩阵的值均置为0后进行运算，或者被mask的列中的ME矩阵不参与运算。
因此，第二校验位包括步骤5024中的M2拍输出的M2个运算结果。
那么，编码后得到的第二数据包括未经编码的第一数据、第一校验位和第二校验位。
在一些实施例中，后M2列包括的M2个ME矩阵均相同，这样，在进行步骤5024中的乘法运算时，乘法运算的逻辑可以复用。
由此，由于本申请提供的LDPC校验矩阵中，校验位部分中的CPM矩阵参与乘法运算的复杂度较低，还可以以低复杂度的CPM矩阵乘递归实现矩阵求逆；同时，校验位部分中ME矩阵的引入，可以避免列重1或列重2等小列重的列出现，从而可以保证纠错的error-floor足够低。同时，本申请在对LDPC的行或列进行mask时，由于校验位部分为下三角结构，mask后校验位部分依然为下三角结构，ME矩阵如果都相同时，ME矩阵结构依然存在，因此可以复用LDPC母码的编码逻辑；同时行/列被mask后的码率发生变化，因此可以实现支持不同码率的编码，从而可以灵活适配多种NAND颗粒以其应用场景。再者，本申请的编码流程中，其核心运算为CPM矩阵乘运算和ME矩阵的逆矩阵乘运算，其计算逻辑复杂度较小，因此可以保证每拍数据输入时，每拍都有数据输出，可以实现高带宽低时延的编码流程。
通过上述编码流程的介绍，本申请可以相应的提供一种编码器，该编码器中的硬件设计可以用于实现上述编码流程。
因此，本申请提供一种LDPC编码器，如图11所示，该LCPC编码器11可以包括第一寄存器(REG)A，计算器B以及第一选择器(MUX)C；
其中，第一寄存器A，可以用于缓存第一数据；即第一寄存器A可以用于接收每拍输入到编码器11的第一数据；
计算器B，用于根据LDPC校验矩阵对第一数据进行编码，得到编码后的第二数据；计算器B具体可以用于执行步骤502的流程；
第一选择器C，用于输出第二数据。即第一选择器C用于输出编码后的数据。
此外，编码器11还可以包括接口寄存器(interface register)D、第三选择器E以及状态机F；
其中，接口寄存器D，可以用于存储LDPC校验矩阵中参与编码运算的行数M和列数N；
第三选择器E，用于根据行数M和列数N确定LDPC校验矩阵中不参与编码运算的行和/或列；第三选择器E根据M和N确定不参与编码的行和/或列，可以是按照预设规则确定的。
状态机F，用于指示编码器11中的各个部件的状态。包括用于根据不参与编码运算的行和/或列向计算器B发送指示信息，该指示信息用于指示不参与编码运算的行和/或列(或在运算时将不参与编码运算的行和/或列的值置为0)。
计算器B在接收到了状态机F发送的指示信息时，可以根据指示信息进行数据编码的具体运算。
在一些实施例中，计算器B包括第二选择器G、第一乘法器H、第二寄存器I以及第二乘法器J；
具体的，第二选择器G，用于将第一寄存器输出的第一数据输出至第一乘法器H；
第一乘法器H，用于根据第一乘法器H中存储的信息位部分和从第二选择器G接收到的第一数据，获取第一中间变量；将第一中间变量输出至第二寄存器I；
第二寄存器，还用于将第一中间变量返回至第二选择器G；
第二选择器G，还用于输出第一中间变量给第一乘法器H；
第一乘法器H，还用于根据第一中间变量和第一乘法器H中存储的下三角矩阵的 前M1列的CPM相乘，得到第一校验位和第二中间变量，输出第一校验位和第二中间变量至第二寄存器I；
第二寄存器I，还用于输出第一校验位至第一选择器C，使第一选择器C输出第一校验位；第二寄存器I，还用于输出第二中间变量至第二乘法器J；
第二乘法器J，用于根据第二寄存器I输出的第二中间变量和下三角矩阵的后M2列的ME矩阵的逆矩阵，获取第二校验位输出至第一选择器C，使第一选择器C输出第二校验位。
其中，第一寄存器A在向计算器B输入第一数据的同时，还可以向第一选择器C输出第一数据；第一选择器C，还用于输出该第一数据。
由此，第一选择器输出的第二数据包括第一数据、第一校验位和第二校验位。
其中，状态机F在用于向计算器B发送指示信息，指示不参与编码运算的行和/或列时，其具体实现可以是：状态机F，用于向第一乘法器H发送第一指示信息，向第二乘法器J发送第二指示信息；第一指示信息用于指示不参与编码运算的行；第二指示信息用于指示不参与编码运算的列。
因此，第一乘法器H，还用于在获取第二中间变量和第一校验位时，将不参与编码运算的行的值均置为0进行运算；
第二乘法器J，还用于在获取第二校验位时，将不参与编码运算的列的值均置为0进行运算。
编码器11中各部件内部的具体运算可以参见上述方法实施例，此处不再赘述。
由此，本申请提供的编码器结构下，LDPC母矩阵可以固化在编码引擎中，对于变码率应用，编码引擎可以从接口寄存器获取到矩阵的行列大小，由此可以根据行列大小得到母矩阵中被mask的行列信息，这样，不需要单独的随机存取存储器(random access memory，RAM)空间存储编码矩阵，节省了存储空间。同时，本申请对编码器的改进，可以使得编码器通过简单的行列mask就可支持多种码率，且编码器时延只有1个cycle，即每拍待编码的数据从编码器的第一寄存器接收到，经过计算器运算，运算结果就可通过第一选择器输出每拍编码后的数据。这样可以保证高编码带宽。
与编码方法类似的，本申请实施例还可以提供一种低密度奇偶检验码LDPC译码方法，如图12所示，该方法包括：
120、获取第一数据。
121、根据LDPC校验矩阵对第一数据进行译码，输出译码后的第二数据。
其中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及对角线下方的子矩阵为循环置换矩阵CPM；下三角矩阵的后M2列中的位于对角线上的子矩阵为ME矩阵，且位于对角线下方的子矩阵为零矩阵。与编码过程类似的额，通过本申请提供的LDPC校验矩阵，在进行数据译码时，可以通过CPM以及ME矩阵进行数据运算。由于CPM和ME矩阵的复杂度低，进行数据译码运算时，其计算复杂度低，可以达到高带宽低时延的数据译码特性。
在一种可能的设计中，下三角矩阵的前M1列中位于对角线上的CPM为单位矩阵。
与译码方法对应的，如图13所示，本申请实施例还可以提供一种低密度奇偶检验 码LDPC译码器13，包括：第一寄存器130，用于缓存第一数据；计算器131，用于根据LDPC校验矩阵对第一数据进行译码，得到译码后的第二数据；第一选择器132，用于输出第二数据；其中，LDPC校验矩阵包括校验位部分，校验位部分为下三角矩阵，下三角矩阵对角线上方的子矩阵为零矩阵；下三角矩阵的前M1列中位于对角线及对角线下方的子矩阵为循环置换矩阵CPM；下三角矩阵的后M2列中的位于对角线上的子矩阵为ME矩阵，且对角线下方的子矩阵为零矩阵。与编码过程类似的额，通过本申请提供的LDPC校验矩阵，在进行数据译码时，可以通过CPM以及ME矩阵进行数据运算。由于CPM和ME矩阵的复杂度低，进行数据译码运算时，其计算复杂度低，可以达到高带宽低时延的数据译码特性。
在一种可能的设计中，下三角矩阵的前M1列中位于对角线上的CPM为单位矩阵。
本申请实施例还提供一种通信装置14，如图14所示，通信装置包括如上述实施例中所述的编码器、译码器以及存储器，存储器用于存储所述编码器编码后的数据。该通信装置例如可以为图3对应的架构中的控制器和存储器组合后的装置，该控制器中包括编码器和译码器。
本申请实施例还提供一种通信系统，通信系统包括如图14所述的通信装置以及服务器；服务器，用于通信装置发送待编码的数据，或服务器，用于接收通信装置发送的译码后的数据。该服务器可以为图3示出的架构中的主机。
本申请实施例还提供一种通信装置，通信装置包括如图11所示的编码器，还包括处理器、调制器以及收发器；处理器用于执行计算机程序或指令；调制器，用于将编码器编码后的数据对应的数字信号转换为模拟信号；收发器，用于发送模拟信号。即该通信装置可以为数据的发送端，对应图4中的发送端。该发送端例如可以为终端设备或网络设备等。
本申请实施例还提供一种通信装置，通信装置包括如图13所述的译码器，还包括处理器、收发器以及解调器；处理器，用于执行计算机程序或指令；收发器，用于接收模拟信号；解调器，用于将模拟信号转换为数字信号，以便译码器对数字信号进行译码。即该通信装置可以为数据的接收端，对应图4中的接收端。该接收端例如可以为终端设备或网络设备等。
本申请实施例还提供一种通信系统，通信系统包括如图4所示的发送端和如图4所示的接收端。
本申请实施例还提供一种计算器可读存储介质，包括程序或指令，当所述程序或指令被处理器运行时，如图5和/或图10和/或图12对应的方法被执行。
本申请实施例还提供一种计算机程序产品，当计算机程序产品在计算机上运行时，使得电子设备执行如图5和/或图10和/或图12对应的方法。
通过以上实施方式的描述，所属领域的技术人员可以了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块 或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种低密度奇偶校验码LDPC编码方法，其特征在于，包括：
    获取第一数据；
    根据LDPC校验矩阵对所述第一数据进行编码，并输出编码后得到的第二数据；
    其中，所述LDPC校验矩阵包括校验位部分，所述校验位部分为下三角矩阵，所述下三角矩阵对角线上方的子矩阵为零矩阵；所述下三角矩阵的前M1列中位于所述对角线及所述对角线下方的子矩阵为循环置换矩阵CPM；所述下三角矩阵的后M2列中的位于所述对角线上的子矩阵为多边矩阵，且位于所述对角线下方的子矩阵为零矩阵。
  2. 根据权利要求1所述的方法，其特征在于，所述下三角矩阵的前M1列中位于所述对角线上的CPM为单位矩阵。
  3. 根据权利要求1或2所述的方法，其特征在于，所述LDPC校验矩阵还包括信息位部分；所述根据所述LDPC校验矩阵对所述第一数据进行编码，并输出编码后得到的第二数据包括：
    根据所述信息位部分和所述第一数据，获取第一中间变量，同时输出所述第一数据；
    根据所述第一中间变量和所述下三角矩阵的前M1列的CPM，获取第一校验位和第二中间变量，并输出所述第一校验位；
    根据所述第二中间变量和所述下三角矩阵的后M2列的多边矩阵的逆矩阵，获取第二校验位并输出；
    其中，所述第二数据包括所述第一数据、所述第一校验位和所述第二校验位。
  4. 根据权利要求3所述的方法，其特征在于，所述根据所述LDPC校验矩阵对所述第一数据进行编码，输出编码后的第二数据还包括：
    在根据所述信息位部分和所述第一数据获取所述第一中间变量之前，根据配置的行数和列数确定所述LDPC校验矩阵中不参与编码运算的行和/或列；
    在获取所述第一中间变量、所述第二中间变量、所述第一校验位以及所述第二校验位的过程中，将所述不参与编码运算的行和/或列的值置为0进行运算。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述多边矩阵的每行中值为1的个数大于1，且为奇数；以及，所述多边矩阵的每列中值为1的个数大于1，且为奇数。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述下三角矩阵的后M2列中的位于所述对角线上的多边矩阵相同。
  7. 一种低密度奇偶校验码LDPC编码器，其特征在于，包括：
    第一寄存器，用于缓存第一数据；
    计算器，用于根据LDPC校验矩阵对所述第一数据进行编码，得到编码后的第二数据；
    第一选择器，用于输出所述第二数据；
    其中，所述LDPC校验矩阵包括校验位部分，所述校验位部分为下三角矩阵，所述下三角矩阵对角线上方的子矩阵为零矩阵；所述下三角矩阵的前M1列中位于所述 对角线及所述对角线下方的子矩阵为循环置换矩阵CPM；所述下三角矩阵的后M2列中的位于所述对角线上的子矩阵为多边矩阵，且位于所述对角线下方的子矩阵为零矩阵。
  8. 根据权利要求7所述的编码器，其特征在于，所述下三角矩阵的前M1列中位于所述对角线上的CPM均为单位矩阵。
  9. 根据权利要求7或8所述的编码器，其特征在于，所述LDPC校验矩阵还包括信息位部分；所述计算器包括：第二选择器、第一乘法器、第二寄存器以及第二乘法器；
    所述第二选择器，用于将所述第一寄存器输出的所述第一数据输出至所述第一乘法器；
    所述第一乘法器，用于根据所述信息位部分和所述第一数据，获取第一中间变量；将所述中间变量输出至所述第二寄存器；
    所述第二寄存器，还用于将所述第一中间变量返回至所述第二选择器；
    所述第一乘法器，还用于根据所述第二选择器输出的所述第一中间变量以及所述下三角矩阵的前M1列的CPM，获取第一校验位和第二中间变量并输出至所述第二寄存器；
    所述第二寄存器，还用于输出所述第一校验位至所述第一选择器，使所述第一选择器输出所述第一校验位；
    所述第二乘法器，用于根据第二寄存器输出的所述第二中间变量和所述下三角矩阵的后M2列的多边矩阵的逆矩阵，获取第二校验位输出至所述第一选择器，使所述第一选择器输出所述第二校验位。
  10. 根据权利要求9所述的编码器，其特征在于，
    所述第一寄存器，还用于输出所述第一数据至所述第一选择器；
    所述第一选择器，用于输出所述第一数据；
    所述第二数据包括所述第一数据、所述第一校验位以及所述第二校验位。
  11. 根据权利要求10所述的编码器，其特征在于，所述信息位部分包括多个行，所述校验位包括多个列；所述编码器还包括接口寄存器、第三选择器以及状态机；
    所述接口寄存器，用于存储所述LDPC校验矩阵中参与编码运算的行数和列数；
    所述第三选择器，用于根据所述行数和列数确定所述LDPC校验矩阵中不参与编码运算的行和/或列；
    所述状态机，用于根据所述不参与编码运算的行和/或列向所述第一乘法器发送第一指示信息，向所述第二乘法器发送第二指示信息；所述第一指示信息用于指示不参与编码运算的行；所述第二指示信息用于指示不参与编码运算的列；
    所述第一乘法器，用于在获取所述第二中间变量和所述第一校验位时，将所述不参与编码运算的行的值均置为0进行运算；
    所述第二乘法器，用于在获取所述第二校验位时，将所述不参与编码运算的列的值均置为0进行运算。
  12. 根据权利要求7-11任一项所述的编码器，其特征在于，
    所述多边矩阵的每行中值为1的个数大于1，且为奇数；以及，所述多边矩阵的 每列中值为1的个数大于1，且为奇数。
  13. 根据权利要求7-12任一项所述的编码器，其特征在于，所述下三角矩阵的后M2列中的位于所述对角线上的多边矩阵相同。
  14. 一种低密度奇偶校验码LDPC译码方法，其特征在于，包括：
    获取第一数据；
    根据LDPC校验矩阵对所述第一数据进行译码，并输出译码后得到的第二数据；
    其中，所述LDPC校验矩阵包括校验位部分，所述校验位部分为下三角矩阵，所述下三角矩阵对角线上方的子矩阵为零矩阵；所述下三角矩阵的前M1列中位于所述对角线及所述对角线下方的子矩阵为循环置换矩阵CPM；所述下三角矩阵的后M2列中的位于所述对角线上的子矩阵为多边矩阵，且位于所述对角线下方的子矩阵为零矩阵。
  15. 根据权利要求14所述的方法，其特征在于，所述下三角矩阵的前M1列中位于所述对角线上的CPM均为单位矩阵。
  16. 一种低密度奇偶校验码LDPC译码器，其特征在于，包括：
    第一寄存器，用于缓存第一数据；
    计算器，用于根据LDPC校验矩阵对所述第一数据进行译码，得到译码后的第二数据；
    第一选择器，用于输出所述第二数据；
    其中，所述LDPC校验矩阵包括校验位部分，所述校验位部分为下三角矩阵，所述下三角矩阵对角线上方的子矩阵为零矩阵；所述下三角矩阵的前M1列中位于所述对角线及所述对角线下方的子矩阵为循环置换矩阵CPM；所述下三角矩阵的后M2列中的位于所述对角线上的子矩阵为多边矩阵，且位于所述对角线下方的子矩阵为零矩阵。
  17. 根据权利要求16所述的译码器，其特征在于，所述下三角矩阵的前M1列中位于所述对角线上的CPM均为单位矩阵。
  18. 一种通信装置，其特征在于，所述通信装置包括如权利要求7-13任一项所述的编码器、如权利要求16或17所述的译码器以及存储器，所述存储器用于存储所述编码器编码后的数据。
  19. 一种通信系统，其特征在于，所述通信系统包括如权利要求18所述的通信装置以及服务器；所述服务器，用于向所述通信装置发送待编码的数据，或所述服务器，用于接收所述通信装置发送的译码后的数据。
  20. 一种通信装置，其特征在于，所述通信装置包括如权利要求7-13任一项所述的编码器、处理器、调制器以及收发器；
    所述处理器用于执行计算机程序或指令；
    所述调制器，用于将所述编码器编码后的数据对应的数字信号转换为模拟信号；
    所述收发器，用于发送所述模拟信号。
  21. 一种通信装置，其特征在于，所述通信装置包括如权利要求16或17所述的译码器、收发器、处理器以及解调器；
    所述处理器，用于执行计算机程序或指令；
    所述收发器，用于接收模拟信号；
    所述解调器，用于将所述模拟信号转换为数字信号，以便所述译码器对所述数字信号进行译码。
  22. 一种通信系统，其特征在于，所述通信系统包括如权利要求20所述的通信装置和如权利要求21所述的通信装置。
  23. 一种计算器可读存储介质，包括程序或指令，其特征在于，当所述程序或指令被处理器运行时，如权利要求1至6中任一项、或权利要求14或15所述的方法被执行。
  24. 一种计算机程序产品，其特征在于，当计算机程序产品在计算机上运行时，使得电子设备执行如权利要求1至6中任一项、或权利要求14或15所述的方法。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101321043A (zh) * 2007-06-08 2008-12-10 大唐移动通信设备有限公司 低密度校验码编码的译码方法及译码装置
US20090204868A1 (en) * 2008-02-12 2009-08-13 Samsung Electronics Co. Ltd. Method and apparatus for signal transmission/reception in a communication system using an harq scheme
CN102055485A (zh) * 2010-12-24 2011-05-11 中国人民解放军理工大学 准循环低密度奇偶校验码及其修正和线性编码方法
CN108988871A (zh) * 2017-05-31 2018-12-11 电信科学技术研究院 一种编码方法及装置、计算机存储介质

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9154261B2 (en) * 2013-01-16 2015-10-06 Broadcom Corporation Low density parity check (LDPC) coding in communication systems
KR102429754B1 (ko) * 2014-11-20 2022-08-09 한국전자통신연구원 주파수 변환 장치 및 그것을 포함하는 rf 송신기
AU2018216547B2 (en) * 2017-02-06 2020-04-30 Lg Electronics Inc. LDPC code transmission method using row-orthogonal structure, and device therefor
CN109150196A (zh) * 2017-06-27 2019-01-04 华为技术有限公司 信息处理的方法、装置和通信设备
CN108712174B9 (zh) * 2017-06-27 2019-08-30 华为技术有限公司 信息处理的方法、装置和通信设备
CN110011755B (zh) * 2018-01-05 2021-10-19 中兴通讯股份有限公司 一种ldpc编码的方法、装置及数据发送的方法、装置
CN112204888A (zh) * 2018-05-22 2021-01-08 华为技术有限公司 具有高效编码和良好误码平层特性的一类qc-ldpc码
CN109379086B (zh) * 2018-10-11 2021-06-08 西安电子科技大学 低复杂度的码率兼容的5g ldpc编码方法和编码器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101321043A (zh) * 2007-06-08 2008-12-10 大唐移动通信设备有限公司 低密度校验码编码的译码方法及译码装置
US20090204868A1 (en) * 2008-02-12 2009-08-13 Samsung Electronics Co. Ltd. Method and apparatus for signal transmission/reception in a communication system using an harq scheme
CN102055485A (zh) * 2010-12-24 2011-05-11 中国人民解放军理工大学 准循环低密度奇偶校验码及其修正和线性编码方法
CN108988871A (zh) * 2017-05-31 2018-12-11 电信科学技术研究院 一种编码方法及装置、计算机存储介质

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