WO2021139361A1

WO2021139361A1 - Schottky diode and manufacturing method therefor

Info

Publication number: WO2021139361A1
Application number: PCT/CN2020/125413
Authority: WO
Inventors: 程凯
Original assignee: 苏州晶湛半导体有限公司
Priority date: 2020-01-10
Filing date: 2020-10-30
Publication date: 2021-07-15
Also published as: CN113130666A; US20220416092A1

Abstract

A Schottky diode and a manufacturing method therefor. The Schottky diode (100) comprises a nitride channel layer (1); a nitride barrier layer (2) formed on the nitride channel layer (1); a nitride cap layer (3) formed on the nitride barrier layer (2) and comprising an activated region (31) and a non-activated region (32); a passivation layer (4) formed on the nitride cap layer (3) and comprising a first groove which penetrates through the passivation layer (4) and exposes the nitride cap layer (3), the first groove corresponding to the activated region (31); a dielectric layer (5) located on the passivation layer (4) and the inner wall of the first groove, a second groove being defined by the dielectric layer (5), and the dielectric layer (5) comprising a third groove which penetrates through the dielectric layer (5) and exposes part of the activated region (31) on the nitride cap layer (3); and an anode layer (6) formed in the second groove and the third groove and in contact with the activated region (31).

Description

Schottky diode and manufacturing method thereof

Related cross references

This application is filed based on a Chinese patent application with an application number of 2020100264931 and an application date of January 10, 2020, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by reference into this application.

Technical field

This application relates to the field of semiconductor technology, and in particular to a Schottky diode and a manufacturing method thereof.

Background technique

Based on the advantages of high switching frequency and reduced forward voltage, Schottky diodes are widely used, and can gradually replace the application of silicon in high-power semiconductor devices. Generally, the anode layer of the Schottky diode is directly formed on the heterostructure layer, so that the leakage characteristic of the heterostructure layer in a high temperature environment is relatively large.

Summary of the invention

This application provides a Schottky diode and a manufacturing method thereof to solve the deficiencies in the related art.

According to a first aspect of the embodiments of the present application, there is provided a Schottky diode, including:

Nitride channel layer;

A nitride barrier layer formed on the nitride channel layer;

A nitride cap layer, the nitride cap layer is formed on the nitride barrier layer, and the nitride cap layer includes an active region and an inactive region;

A passivation layer, the passivation layer is formed on the nitride cap, the passivation layer includes a first groove, the first groove penetrates the passivation layer and exposes the nitride cap Layer, the first groove corresponds to the activation area;

The dielectric layer is located on the passivation layer and on the inner wall of the first groove, and the dielectric layer surrounds a second groove, the dielectric layer includes a third groove, and the first groove Three grooves penetrate through the dielectric layer and expose part of the active region on the nitride cap layer; and

An anode layer, the anode layer is formed in the second groove and the third groove, and the anode layer is in contact with the active region.

Optionally, the nitride cap layer includes a fourth groove formed in the active region, the fourth groove penetrates the nitride cap layer and exposes a part of the nitride barrier layer, and The fourth groove communicates with the third groove;

The anode layer includes a first anode layer and a second anode layer, the first anode layer is formed in the second groove, and the second anode layer is formed in the third groove and the fourth anode layer. In the groove and in contact with the nitride barrier layer.

Optionally, it also includes:

The fifth groove and the sixth groove, the fifth groove and the sixth groove are respectively located on both sides of the anode layer, the fifth groove and the sixth groove both penetrate through the The dielectric layer, the passivation layer, and the nitride capping layer to the nitride barrier layer; and

A cathode layer, the cathode layer is formed in the fifth groove and the sixth groove, and is in contact with the nitride barrier layer.

Optionally, a barrier layer is provided between the nitride barrier layer and the nitride cap layer.

Optionally, the active region is a P-type nitride cap layer.

Optionally, the nitride capping layer includes a nitride capping layer doped with magnesium.

Optionally, the doping concentration of magnesium is between 1E16cm3-5E20/cm3.

Optionally, the nitride channel layer includes a gallium nitride channel layer, and the nitride barrier layer includes an aluminum gallium nitride barrier layer.

Optionally, it also includes:

The seventh groove is formed on at least one side of the third groove and is connected or disconnected from the second groove; wherein, the seventh groove penetrates the dielectric layer to the nitride cap Layer, and/or the seventh groove penetrates the dielectric layer and partially enters or penetrates the nitride cap layer; the anode layer is formed in the seventh groove.

According to a second aspect of the embodiments of the present application, there is provided a method for manufacturing a Schottky diode, including:

Forming a nitride channel layer;

Forming a nitride barrier layer on the nitride channel layer;

Forming a nitride cap layer on the nitride barrier layer;

Forming a passivation layer on the nitride capping layer;

Forming a first groove, the first groove penetrating the passivation layer to expose the nitride cap layer;

Forming a dielectric layer, the dielectric layer is located on the passivation layer and on the inner wall of the first groove, and the dielectric layer forms a second groove;

The structure to be processed in which the second groove is formed is annealed to form an active region on the nitride cap layer corresponding to the first groove, and is covered by the nitride cap layer. The area covered by the passivation layer forms the inactive area;

Forming a third groove on the structure to be processed, the third groove penetrating the dielectric layer to expose a part of the active area on the nitride cap;

An anode layer is formed in the second groove and the third groove, and the anode layer is in contact with the active region.

Optionally, it also includes:

Forming a fourth groove, the fourth groove penetrates the nitride cap to expose the nitride barrier layer, and the fourth groove communicates with the third groove;

The forming an anode layer in the second groove and the third groove includes:

Forming a second anode layer in the third groove and the fourth groove and in contact with the nitride barrier layer;

A first anode layer is formed in the second groove.

Optionally, it also includes:

A fifth groove and a sixth groove are formed, the anode layer is located between the fifth groove and the sixth groove, and both the fifth groove and the sixth groove pass through the A dielectric layer, the passivation layer, and the nitride cap to the nitride barrier layer;

A cathode layer is formed in the fifth groove and the sixth groove.

Optionally, it also includes:

A seventh groove is formed on at least one side of the third groove, and is connected or disconnected from the second groove; wherein, the seventh groove penetrates the dielectric layer to the nitride cap layer , And/or the seventh groove penetrates the dielectric layer and partially penetrates or penetrates the nitride cap layer;

A first anode layer is formed in the seventh groove.

The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

In this application, a Schottky contact is formed between the anode layer and the nitride cap layer, which can effectively avoid direct contact between the anode layer and the heterostructure layer including the nitride channel layer and the nitride barrier layer, and can balance the Schottky The diode has a contradiction between the forward turn-on voltage and the reverse leakage characteristics, and can suppress the leakage characteristics of the heterostructure layer in a high-temperature environment. Further, since the anode layer is in contact with the active region on the nitride cap layer, and the concentration of holes in the active region is relatively high, it is beneficial to improve the performance of the device. In addition, by providing a barrier layer, it is possible to utilize the barrier layer’s non-decomposability characteristics at high temperatures during the subsequent high-temperature growth of other epitaxial layers, so that the groove does not penetrate the barrier layer, so that the depth of the groove will not be lower than the barrier layer. In turn, the etching depth of the groove is precisely controlled.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the application.

Description of the drawings

The drawings herein are incorporated into the specification and constitute a part of the specification, show embodiments that conform to the application, and are used together with the specification to explain the principle of the application.

Fig. 1 is a schematic diagram showing the structure of a Schottky diode according to an exemplary embodiment.

Fig. 2 is a schematic diagram showing the structure of another Schottky diode according to an exemplary embodiment.

Fig. 3 is a schematic diagram showing the structure of still another Schottky diode according to an exemplary embodiment.

Fig. 4 is a flow chart showing a manufacturing process of a Schottky diode according to an exemplary embodiment.

Fig. 5 is a manufacturing flow chart showing another Schottky diode according to an exemplary embodiment.

Fig. 6 is a manufacturing flow chart showing yet another Schottky diode according to an exemplary embodiment.

Fig. 7 is a schematic diagram showing the structure of still another Schottky diode according to an exemplary embodiment.

Fig. 8 is a manufacturing flow chart of still another Schottky diode according to an exemplary embodiment.

Detailed ways

The exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the application as detailed in the appended claims.

The terms used in this application are only for the purpose of describing specific embodiments, and are not intended to limit the application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determination".

Fig. 1 is a schematic diagram showing the structure of a Schottky diode 100 according to an exemplary embodiment. As shown in FIG. 1, the Schottky diode 100 may include a nitride channel layer 1, a nitride barrier layer 2, a nitride cap layer 3, a passivation layer 4 and a dielectric layer 5. Wherein, the nitride barrier layer 2 is formed on the nitride channel layer 1. The nitride channel layer 1 can be made of one or more of GaN and AlN, and the nitride barrier layer 2 can be made of AlN. It is made of one or more materials among GaN, AlGaN, and InN, which is not limited in this application. Further, a nitride cap layer 3 may be formed on the nitride barrier layer 2, and the nitride cap layer 3 may include an active region 31 and an inactive region 32. The passivation layer 4 is formed on the nitride cap 3, the passivation layer 4 has passivation and protection, can reduce the surface state of the nitride cap 3, effectively reduce the current collapse effect, wherein the passivation layer 4 can be One or a combination of silicon nitride, silicon aluminum nitrogen, and silicon dioxide. The passivation layer 4 may be formed on the nitride layer 3 by a deposition process, and the process of depositing the passivation layer 4 may be PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), LPCVD (Low Pressure Chemical Vapor) Deposition, low pressure chemical vapor deposition), ALD (Atomic Layer Deposition, atomic layer deposition) and MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition) one or a combination of several processes.

The passivation layer 4 may include a first groove that penetrates the passivation layer 4 and exposes a part of the nitride cap layer 3, and the first groove is disposed corresponding to the active region 31, and the dielectric layer 5 may be formed On the passivation layer 4 and the inner wall of the first groove, the dielectric layer 5 can reduce the gate leakage and enable the Schottky diode 100 to have a higher voltage withstand value. The dielectric layer 5 may include one or a combination of aluminum nitride dielectric layer, silicon nitride dielectric layer, aluminum oxide dielectric layer, aluminum oxynitride dielectric layer, and silicon dioxide dielectric layer, which is not limited in this application.

Since the dielectric layer 5 contacts the inner wall of the first groove, the dielectric layer 5 can form a second groove. Further, the dielectric layer 5 may further include a third groove, which penetrates the dielectric layer 5 and exposes a part of the active region 31 on the nitride cap layer 3. Thus, a space recessed inward can be formed by the first groove, the second groove, and the third groove, and a part of the active region 31 of the nitride cap layer 3 can be exposed by the third groove. Wherein, the Schottky diode 100 may further include an anode layer 6 and a cathode layer 9. The anode layer 6 is formed in the second groove and the third groove, and because the third groove exposes the nitride layer 3 Therefore, the anode layer 6 can form Schottky contact with the active region 31. Wherein, the anode layer 6 may use a metal with a higher work function to realize Schottky metal, for example, the anode layer 6 of Ni, Au or Pt metal may be used to form Schottky contact with the heterostructure layer.

It can be seen from the above embodiment that the Schottky contact between the anode layer 6 and the nitride layer 3 can effectively avoid the anode layer 6 and the heterostructure layer including the nitride channel layer 1 and the nitride barrier layer 2 Direct contact can balance the contradiction between the forward turn-on voltage and the reverse leakage characteristics of the Schottky diode 100, and can effectively suppress the leakage characteristics of the heterostructure layer in a high temperature environment. Further, since the anode layer 6 is in contact with the active region 31 of the nitride cap layer 3, and the active region 31 has a higher hole concentration, it is beneficial to improve the performance of the device.

In this embodiment, the nitride capping layer 3 may include a P-type nitride capping layer, for example, a P-type nitride capping layer formed by doping with magnesium. Alternatively, the nitride run between 1E16 / cm ^³ -5E20 / cm ³ may be a GaN based layer 3 of the P-type doping magnesium nitride obtained risk layer, wherein the doping concentration of magnesium may be located . Further, the active region 31 can be formed by annealing the nitride layer 3. In an embodiment, the process steps may include sequentially stacking and forming a nitride channel layer 1, a nitride barrier layer 2, a nitride cap layer 3, and a passivation layer 4, and then forming a through passivation on the passivation layer 4. Layer 4 to the first groove of nitride layer 3, and then put the structure after forming the first groove in a hydrogen-free atmosphere for annealing, for example, it can be annealed in nitrogen, nitric oxide, air, or nitrogen and oxygen. Annealing in the mixed gas of the first groove region, since the nitride layer 3 corresponding to the first groove area is not blocked by the passivation layer 4, hydrogen atoms overflow and magnesium atoms are activated, thereby forming an active region 31, which is blocked by the passivation layer 4. Since there is no channel for hydrogen atoms to overflow, the nitride layer 3 in the area blocked by the passivation layer 4 still maintains a semi-insulating state, thereby forming an inactive area 32.

In an embodiment, as shown in FIG. 2, the nitride cap layer 3 may further include a fourth groove formed in the active region 31, the fourth groove penetrates the nitride cap layer 3 and exposes the nitride barrier layer 2. And the fourth groove communicates with the third groove, so that the anode layer 6 can further contact the nitride barrier layer 2 through the fourth groove. Specifically, the anode layer 6 may include a first anode layer 61 and a second anode layer 62. As shown in FIG. 2, the first anode layer 61 may be formed in the second groove and formed in the second groove. The first anode layer 61 inside may cooperate with the active region 31 to form a Schottky contact; the second anode layer 62 may be formed in the third groove and the fourth groove, and formed in the third groove and the fourth groove. The second anode layer 62 in the groove forms an ohmic contact with the heterostructure layer including the nitride channel layer 1 and the nitride barrier layer 2. Optionally, as shown in FIG. 2, the side walls of the third groove and the fourth groove may be flush.

It should be noted that the first groove, the third groove, and the fourth groove in the foregoing embodiment may be formed by an etching process, and the second groove may be formed by sputtering the medium along the surface of the passivation layer 4. The layer 5 is formed along the sidewall of the first groove. Moreover, since the third groove is formed through the bottom surface of the second groove, the width of the third groove is less than or equal to the width of the second groove.

In one embodiment, as shown in FIG. 7, it may further include a seventh groove formed in the dielectric layer. The seventh groove is located on at least one side of the third groove and penetrates through the dielectric layer 5 to the nitride cap layer. 3 active area 31, and the seventh groove communicates with the second groove. As shown in the embodiment shown in FIG. 7, the anode layer 6 may include a first anode layer 61 and a second anode layer 62. The first anode layer 61 may be formed in the second groove and the seventh groove, and is formed in the second groove. The first anode layer 61 in the second groove and the seventh groove may cooperate with the active region 31 to form a Schottky contact; the second anode layer 62 may be formed in the third groove and the fourth groove, and is formed in The second anode layer 62 in the third groove and the fourth groove forms an ohmic contact with the heterostructure layer including the nitride channel layer 1 and the nitride barrier layer 2. In another embodiment, the seventh groove penetrates the dielectric layer 5 and partially enters or penetrates the active region 31 of the nitride cap layer 3, so that the first anode layer formed in the second groove and the seventh groove 61 forms a Schottky contact or an ohmic contact.

In each of the foregoing embodiments, the Schottky diode 100 may further include a fifth groove, a sixth groove, and a cathode layer 9, and the anode layer 6 is located between the fifth groove and the sixth groove. The groove and the sixth groove penetrate through the dielectric layer 5, the passivation layer 4, and the nitride layer 3 to the nitride barrier layer 2 in sequence. The cathode layer 9 is formed in the fifth groove and the sixth groove and is combined with nitrogen. An ohmic contact is formed between the barrier layers 2.

As shown in FIG. 3, the Schottky diode 100 may further include a barrier layer 10 located between the nitride barrier layer 2 and the nitride cap layer 3. The barrier layer 10 may be used to limit the depth of etching. . The barrier layer 10 may include an aluminum gallium nitride layer. By providing the barrier layer 10, the depth of the fourth groove can be accurately controlled.

Wherein, the fifth groove and the sixth groove may be formed by an etching process, and the cathode layer 9 may be formed into the fifth groove and the sixth groove by a deposition process. Wherein, the deposition process includes one or a combination of PECVD, LPCVD, ALD, and MOCVD. The cathode layer 9 may include one or more metal materials among Ti, Al, Ni, and Au.

Based on the above technical solution, the present application also provides a method for manufacturing a Schottky diode. For related parts, please refer to the product introduction above. As shown in Figure 4, the manufacturing method may include the following steps:

In step 501, a nitride channel layer 1 is formed.

Step 502, forming a nitride barrier layer 2 on the nitride channel layer 1.

Step 503, forming a nitride dummy layer 3 on the nitride barrier layer 2.

Step 504, forming a passivation layer 4 on the nitride capping layer 3.

In step 505, a first groove 41 is formed, and the first groove 41 penetrates the passivation layer 4 to expose the nitride cap layer 3.

In this embodiment, as shown in FIG. 5, a nitride channel layer 1, a nitride barrier layer 2, a nitride cap layer 3, and a passivation layer 4 can be sequentially stacked on the base substrate, and further can be formed by The etching process forms a first groove 41 on the passivation layer 4, and the first groove 41 penetrates the passivation layer 4 and exposes a part of the nitride cap layer 3. Wherein, a nitride buffer layer (not shown in the figure) can also be formed between the nitride channel layer 1 and the nitride barrier layer 2, or nitrogen can also be formed under the nitride layer 3 as shown in FIG. A compound nucleation layer (not shown in the figure), or a barrier layer may be formed between the nitride barrier layer 2 and the nitride cap layer 3, which is not limited in this application.

Step 506, forming a dielectric layer 5, the dielectric layer 5 is located on the passivation layer 4 and the inner wall of the first groove 41, and the dielectric layer 5 forms a second groove 51.

Step 507: Anneal the structure to be processed in which the second groove is formed to form an active region 31 on the nitride cap layer 3 corresponding to the first groove, and in the nitride cap layer 3 The area on the layer 3 covered by the passivation layer 4 forms an inactive area 32.

In this embodiment, as shown in FIG. 5, based on the structure obtained in step 505, a dielectric layer 5 may be further formed on the passivation layer 4 by a deposition process, and the dielectric layer 5 is in contact with the passivation layer 4, and the dielectric The layer 5 may be in contact with the inner wall of the first groove 41 so that the second groove 51 may be formed around.

Further, a predetermined area on the nitride cap layer 3 can be doped with magnesium element. Alternatively, it may be performed based on magnesium-doped GaN, wherein the doping concentration of magnesium may be located 1E16 / cm ³ -5E20 / cm ^3. Then, the structure to be processed with the second groove 51 doped with magnesium can be placed in a hydrogen-free atmosphere for annealing, such as nitrogen, nitric oxide, air, or a mixed gas of nitrogen and oxygen. During annealing, since the nitride cap 3 corresponding to the region of the first groove 41 is not blocked by the passivation layer 4, hydrogen atoms overflow and magnesium atoms are activated, so that the preset area is activated to obtain a P-type nitride cap. That is, the active area 31 is obtained, and the area covered by the passivation layer 4 has no channels for hydrogen atoms to overflow, so the nitride layer 3 in the area blocked by the passivation layer 4 still maintains a semi-insulating state, thereby forming an inactive area 32, In 5, the active area 31 and the inactive area 32 are distinguished by a dotted line marked on the nitride cap layer 3.

In step 508, a third groove 52 is formed on the structure to be processed, and the third groove 52 penetrates the dielectric layer 5 to expose a part of the active region 31 of the nitride cap layer 3.

In step 509, an anode layer 6 is formed in the second groove 51 and the third groove 52, and the anode layer 6 is partially in contact with the active region 31.

In this embodiment, on the structure to be processed after annealing, a third groove 52 may be formed through an etching process, and the third groove 52 penetrates the dielectric layer 5 and exposes a part of the active region 31. Further, an anode layer 6 may be deposited in the third groove 52 and the second groove 51, and the anode layer 6 is partially in contact with the active region 31 and forms Schottky contact with the nitride barrier layer 2.

In another embodiment, as shown in FIG. 6, in the embodiment shown in FIG. 6, forming the third groove 52 and the steps before forming the third groove 52 are the same as the embodiment shown in FIG. 5. Moreover, in the embodiment shown in FIG. 6, a fourth groove 33 may be formed corresponding to the third groove 52, and the fourth groove 33 penetrates the active region 31 to the nitride barrier layer 2 to expose the nitride potential. A part of the barrier layer 2, the anode layer 6 may be deposited in the second groove 51, the third groove 52, and the fourth groove 33, and the anode layer 6 formed in the second groove 51 may cooperate with the active region 31 A Schottky contact is formed; the anode layer 6 formed in the third groove 52 and the fourth groove 33 forms an ohmic contact with the heterostructure layer including the nitride channel layer 1 and the nitride barrier layer 2.

In one embodiment, as shown in FIG. 8, in the embodiment shown in FIG. 8, the third groove 52 is formed and the steps before the third groove 52 are formed are the same as the embodiment shown in FIG. 5. Moreover, in the embodiment shown in FIG. 8, a seventh groove 53 may also be formed on at least one side of the third groove 52, and the seventh groove 53 is in communication with the second groove 51, and the seventh groove 53 penetrates the dielectric layer 5 to the nitride layer 3, and the anode layer 6 can be deposited in the second groove 51, the third groove 52, the fourth groove 33 and the seventh groove 53, and is formed in the second groove The anode layer 6 in the seventh groove 51 and the seventh groove 53 can cooperate with the active region 31 to form a Schottky contact; the anode layer 6 formed in the third groove 52 and the fourth groove 33 and contains the nitride channel The heterostructure layer of layer 1 and nitride barrier layer 2 forms an ohmic contact. In another embodiment, the seventh groove 53 may penetrate the dielectric layer 5 and partially enter or penetrate the active region 31 of the nitride cap layer 3, so that the anode layer formed in the second groove 51 and the seventh groove 53 6 Form Schottky contact or ohmic contact.

Based on the embodiment shown in FIG. 5, FIG. 6 and FIG. 8, the above-mentioned manufacturing process may further include forming a fifth groove 7 and a sixth groove 8, and the anode layer 6 is located in the fifth groove 7 and the sixth groove 8. In between, the fifth groove 7 and the sixth groove 8 penetrate the dielectric layer 5, the passivation layer 4, and the nitride layer 3 to the nitride barrier layer 2 in sequence. Furthermore, as shown in FIG. 5 and FIG. 6, a cathode layer 9 may be formed in the fifth groove 7 and the sixth groove 8, and the cathode layer 9 is in contact with the nitride barrier layer 2 to form an ohmic contact.

It should be noted that in the embodiments shown in FIGS. 5 and 6, the cathode layer 9 is formed in the fifth groove 7 and the sixth groove 8, and then the second groove 51 and the third groove are formed. The anode layer 6 deposited by 52 and the fourth groove 33 is taken as an example for illustration. In fact, in some other embodiments, the anode layer 6 may be deposited in the second groove 51, the third groove 52, and the fourth groove 33 first, and then in the fifth groove 7 and the sixth groove 8. The cathode layer 9 is formed inside, and the application does not limit the deposition sequence of the anode layer 6 and the cathode layer 9.

After considering the specification and practicing the disclosure disclosed herein, those skilled in the art will easily think of other embodiments of the present application. This application is intended to cover any variations, uses, or adaptive changes of this application. These variations, uses, or adaptive changes follow the general principles of this application and include common knowledge or customary technical means in the technical field that are not disclosed in this application. . The description and the embodiments are only regarded as exemplary, and the true scope and spirit of the application are pointed out by the following claims.

It should be understood that the present application is not limited to the precise structure that has been described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the application is only limited by the appended claims.

Claims

A Schottky diode, including:

Nitride channel layer;

A nitride barrier layer formed on the nitride channel layer;

A nitride cap layer formed on the nitride barrier layer, the nitride cap layer including an active area and an inactive area;

The passivation layer is formed on the nitride cap layer, the passivation layer includes a first groove, the first groove penetrates the passivation layer and exposes the nitride cap layer, the first The groove corresponds to the activation area;

The dielectric layer is located on the passivation layer and on the inner wall of the first groove, and the dielectric layer encloses a second groove, the dielectric layer further includes a third groove, the third groove Penetrate through the dielectric layer and expose a portion of the active region on the nitride cap layer; and

An anode layer is formed in the second groove and the third groove, and the anode layer is in contact with the active region.
The Schottky diode according to claim 1, wherein the nitride cap layer includes a fourth groove formed in the active region, and the fourth groove penetrates the nitride cap layer and exposes the A part of a nitride barrier layer, and the fourth groove communicates with the third groove;

The anode layer includes a first anode layer and a second anode layer, the first anode layer is formed in the second groove, and the second anode layer is formed in the third groove and the fourth anode layer. In the groove and in contact with the nitride barrier layer.
The Schottky diode according to claim 1, wherein the width of the third groove is smaller than that of the second groove.
The Schottky diode according to claim 1, further comprising:

The fifth groove and the sixth groove, the fifth groove and the sixth groove are respectively located on both sides of the anode layer, and the fifth groove and the sixth groove both penetrate sequentially The dielectric layer, the passivation layer, and the nitride cap to the nitride barrier layer; and

A cathode layer is formed in the fifth groove and the sixth groove and is in contact with the nitride barrier layer.
The Schottky diode according to claim 1, wherein a barrier layer is provided between the nitride barrier layer and the nitride cap layer.
The Schottky diode of claim 1, wherein the active region is a P-type nitride cap layer.
The Schottky diode according to claim 6, wherein the P-type nitride capping layer is doped with magnesium element.
The Schottky diode of claim 7, wherein the doping concentration of the magnesium element located 1E16 / cm 3 -5E20 / cm 3.
The Schottky diode of claim 1, wherein the nitride channel layer includes a gallium nitride channel layer, and the nitride barrier layer includes a gallium aluminum nitride barrier layer.
The Schottky diode according to claim 1, further comprising:

A seventh groove is formed on at least one side of the third groove, and is connected or disconnected from the second groove; wherein, the seventh groove penetrates the dielectric layer to the nitride cap layer , And/or the seventh groove penetrates the dielectric layer and partially penetrates or penetrates the nitride cap layer;

The anode layer is formed in the seventh groove.
A method for manufacturing a Schottky diode includes:

Forming a nitride channel layer;

Forming a nitride barrier layer on the nitride channel layer;

Forming a nitride cap layer on the nitride barrier layer;

Forming a passivation layer on the nitride capping layer;

Forming a first groove, the first groove penetrating the passivation layer to expose the nitride cap layer;

Forming a dielectric layer, the dielectric layer is located on the passivation layer and on the inner wall of the first groove, and the dielectric layer forms a second groove;

The structure to be processed in which the second groove is formed is annealed to form an active region on the nitride cap layer corresponding to the first groove, and is covered by the nitride cap layer. The area covered by the passivation layer forms an inactive area;

Forming a third groove on the structure to be processed, the third groove penetrating the dielectric layer to expose a part of the active region on the nitride cap layer;

An anode layer is formed in the second groove and the third groove, and the anode layer is in contact with the active region.
The manufacturing method according to claim 11, further comprising:

Forming a fourth groove, the fourth groove penetrates the nitride cap to expose the nitride barrier layer, and the fourth groove communicates with the third groove;

Forming an anode layer in the second groove and the third groove includes:

Forming a second anode layer in the third groove and the fourth groove and in contact with the nitride barrier layer;

A first anode layer is formed in the second groove.
The manufacturing method according to claim 11, further comprising:

A fifth groove and a sixth groove are formed, the anode layer is located between the fifth groove and the sixth groove, and both the fifth groove and the sixth groove pass through the A dielectric layer, the passivation layer, and the nitride cap to the nitride barrier layer;

A cathode layer is formed in the fifth groove and the sixth groove.
The manufacturing method according to claim 11, further comprising:

A seventh groove is formed on at least one side of the third groove, and is connected or disconnected with the second groove; wherein, the seventh groove penetrates the dielectric layer to the nitride cap layer , And/or the seventh groove penetrates the dielectric layer and partially penetrates or penetrates the nitride cap layer;

A first anode layer is formed in the seventh groove.