WO2021136099A1 - 数据传输方法、装置、设备及存储介质 - Google Patents

数据传输方法、装置、设备及存储介质 Download PDF

Info

Publication number
WO2021136099A1
WO2021136099A1 PCT/CN2020/139522 CN2020139522W WO2021136099A1 WO 2021136099 A1 WO2021136099 A1 WO 2021136099A1 CN 2020139522 W CN2020139522 W CN 2020139522W WO 2021136099 A1 WO2021136099 A1 WO 2021136099A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory access
direct memory
data
address
instruction
Prior art date
Application number
PCT/CN2020/139522
Other languages
English (en)
French (fr)
Inventor
杨子
刘永钦
梅超
Original Assignee
京信网络系统股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京信网络系统股份有限公司 filed Critical 京信网络系统股份有限公司
Publication of WO2021136099A1 publication Critical patent/WO2021136099A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • This application relates to the field of computer technology, in particular to a data transmission method, device, equipment and storage medium.
  • PCIe is a high-speed serial computer expansion bus standard.
  • a typical PCIe bus architecture includes an upper computer, a lower computer (English: endpoint), a main memory (English: main memory), a root component (English: root complex), and a switch (English: switch).
  • the technical problem to be solved by this application is to solve the problems of long data transmission time delay and low data transmission efficiency between the existing upper computer and the lower computer.
  • embodiments of the present application provide a data transmission method, device, device, and storage medium.
  • a data transmission method for use in a lower computer of a PCIe bus architecture.
  • the PCIe bus architecture includes an upper computer, a main memory, and the lower computer.
  • the data transmission method includes:
  • a first direct memory access instruction is generated, where the first direct memory access instruction is used to indicate a source address and a first target address, and the source address indicates that the first data is in the lower position.
  • the storage address in the computer, the first target address is the address of the first storage space in the main memory, and the first storage space is preset for storing the upper computer and the lower computer to communicate with each other through direct memory access operations
  • the first direct memory access operation is executed according to the first direct memory access instruction; wherein, the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and according to the The first target address transfers the first data to the first storage space.
  • a data transmission device for use in a lower computer of a PCIe bus architecture.
  • the PCIe bus architecture includes an upper computer, a main memory, and the lower computer.
  • the data transmission device includes:
  • the first generation module is configured to generate a first direct memory access instruction when transmitting the first data to the host computer, where the first direct memory access instruction is used to indicate a source address and a first target address, and the source address is The storage address of the first data in the lower computer, the first target address is the address of the first storage space in the main memory, and the first storage space is preset for storing the upper computer and the lower computer Storage space of data passed to each other through direct memory access operations;
  • the first execution module is configured to execute a first direct memory access operation according to the first direct memory access instruction; wherein, the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and according to The first target address transfers the first data to the first storage space.
  • a computer device including a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the data transmission method as described in any one of the above-mentioned first aspects is implemented.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the data transmission method according to any one of the above-mentioned first aspects is realized.
  • the lower computer of the PCIe bus architecture When the lower computer of the PCIe bus architecture transmits the first data to the upper computer, it can generate the first direct memory access instruction, and execute the first direct memory access operation according to the first direct memory access instruction, so as to pass the first direct memory access
  • the operation transfers the first data from the lower computer to the first storage space of the main memory, where the first storage space is a preset storage space for storing the data transferred between the upper computer and the lower computer through direct memory access operations , Because the first storage space in the main memory for storing the data transferred between the upper computer and the lower computer through the direct memory access operation is preset, therefore, in the process of transferring the first data from the lower computer to the upper computer, it is In the process of uplink data transmission, there is no need for the upper computer to obtain the address of the storage space in the main memory that can store the data transmitted by the lower computer by means of system calls.
  • the lower computer can obtain the address of the first storage space in advance. Therefore, in the process of uplink data transmission, there is no need for the upper computer to send the address to the lower computer. In this way, the upper computer can be simplified in the process of uplink data transmission.
  • the interaction process with the lower computer can reduce the delay of uplink data transmission and improve the efficiency of uplink data transmission.
  • Figure 1 is a schematic diagram of a typical PCIe bus architecture
  • FIG. 2 is a schematic structural diagram of a lower computer provided by an embodiment of the application.
  • FIG. 3 is a flowchart of a data transmission method provided by an embodiment of the application.
  • FIG. 4 is a flowchart of a data transmission method provided by an embodiment of the application.
  • FIG. 5 is a flowchart of a data transmission method provided by an embodiment of this application.
  • FIG. 6 is a flowchart of a data transmission method provided by an embodiment of this application.
  • FIG. 7 is a block diagram of a data transmission device provided by an embodiment of this application.
  • FIG. 8 is a block diagram of another data transmission device provided by an embodiment of the application.
  • PCIe (English: peripheral component interconnect express) is a high-speed serial computer expansion bus standard.
  • FIG. 1 shows a schematic diagram of a typical PCIe bus architecture.
  • the PCIe bus architecture may include an upper computer 00, a lower computer 01, a main memory 03, a root component 04, and a switch 05.
  • the upper computer 00, the main memory 03, and the switch 05 are all connected to the root assembly 04, and the lower computer 01 is connected to the switch 05.
  • the upper computer 00 can store data in the main memory 03 through a multi-level cache mechanism.
  • the upper computer 00 can access the main memory 03 through the root component 04; at the same time, the lower computer 01 can access the main memory 03 through the switch 05 and the root component 04.
  • the upper computer 00 in the PCIe bus architecture can be a CPU (English: central processing unit; Chinese: central processing unit), and the lower computer 01 can also be called a terminal (English: PCIe endpoint), which can be an FPGA ( English: Field Programmable Gate Array) chip.
  • data transmission can be performed between the upper computer and the lower computer in the PCIe architecture.
  • the data transmission between the upper computer and the lower computer in the PCIe architecture can include uplink data transmission and downlink data transmission.
  • the uplink data transmission refers to the lower computer transmitting data to the upper computer.
  • the data is transferred from the storage space of the lower computer to the main memory
  • the downlink data transmission refers to the upper computer transmitting the data to the lower computer.
  • the data is transferred from the main memory to the storage space of the lower machine.
  • the upper computer In the process of uplink data transmission, the upper computer needs to obtain the address of the storage space in the main memory that can store the data transmitted by the lower computer (hereinafter referred to as the first address) by means of a system call, and then the upper computer can trigger the lower computer Perform the uplink data transmission process, and send the first address to the lower computer during the triggering process. After the lower computer receives the first address, it can transfer the data stored in the lower computer to the main memory corresponding to the first address In the storage space.
  • the first address the address of the storage space in the main memory that can store the data transmitted by the lower computer
  • the upper computer In the process of downlink data transmission, the upper computer needs to obtain the address of the storage space (hereinafter referred to as the second address) in the main memory where the data to be transmitted is stored in the main memory by means of a system call, and then the upper computer can use the second address Send to the lower computer. After receiving the second address, the lower computer can obtain the data to be transmitted from the storage space of the main memory corresponding to the second address, and store the data to be transmitted to the lower computer In the storage space.
  • the second address the address of the storage space
  • the upper computer needs to send address information (the first address and second address mentioned above) to the lower computer.
  • address information the first address and second address mentioned above
  • the interaction process between the upper computer and the lower computer is relatively cumbersome, which results in a longer data transmission delay, which in turn affects the data transmission efficiency.
  • the embodiments of the present application provide a data transmission method, which can simplify the interaction process between the upper computer and the lower computer in the data transmission process, reduce the data transmission delay, and improve the data transmission efficiency.
  • the lower computer may include a main controller (English: main controller) and a control status adapter (English: control and status) adaptor), PCIe HIP component, user data interface adapter (English: user logic dataadaptor), buffer monitoring component (English: buffer monitor), upstream data buffer (English: uplink buffer), downstream data buffer (English: downlink buffer), PCIe HIP data interface adapter (English: PCIe HIP dataadaptor) and driver.
  • main controller English: main controller
  • control status adapter English: control and status
  • PCIe HIP component PCIe HIP component
  • user data interface adapter English: user logic dataadaptor
  • buffer monitoring component English: buffer monitor
  • upstream data buffer English: uplink buffer
  • downstream data buffer English: downlink buffer
  • PCIe HIP data interface adapter English: PCIe HIP dataadaptor
  • the main controller is used to provide processing and control functions.
  • the main controller can control the lower computer and the upper computer for data interaction.
  • the control state adapter is used to adapt the data interaction between the main controller and PCIe HIP components.
  • PCIe HIP components usually cannot directly analyze the data generated by the main controller.
  • the main controller usually cannot directly analyze the data generated by the PCIe HIP components. Therefore, in order to realize the main controller and PCIe For data interaction between HIP components, the embodiment of this application can set a control state adapter, which can adapt the data generated by the PCIe HIP component, so that the host controller can parse the data generated by the PCIe HIP component through the adaptation
  • the control state adapter can also adapt the data generated by the main controller, so that the PCIe HIP component can parse the data generated by the main controller through the adaptation.
  • the adaptation between the main controller and the control state adapter does not change with the change of the lower computer platform. Therefore, when the technical solutions provided by the embodiments of this application are implemented on different lower computer platforms (for example, Xilinx or Intel When deploying on ), the adaptation between the main controller and the control state adapter does not need to be modified.
  • the PCIe HIP component can perform data interaction between the lower computer and the upper computer under the control of the main controller.
  • the user data interface adapter is the buffer interface of the lower computer. It can receive the data generated by the application layer and store it in the upstream data buffer. At the same time, the user data interface adapter can also transfer the data stored in the downstream data buffer to the application layer. .
  • the upstream data buffer is used to store data generated by the application layer.
  • the lower computer can transmit the data stored in the upstream data buffer to the upper computer (that is, the main memory).
  • Downlink data buffer is used to store the data sent by the host computer.
  • the buffer monitoring component can monitor the status of the upstream data buffer and the downstream data buffer.
  • the PCIe HIP data interface adapter is used to adapt the data interaction between the PCIe HIP component, the upstream data buffer and the downstream data buffer to provide a data transmission channel between the PCIe HIP component, the upstream data buffer and the downstream data buffer.
  • FIG. 3 shows a flow chart of a data transmission method provided by an embodiment of the present application.
  • the data transmission method can be applied to a lower computer of the PCIe bus architecture. As shown in FIG. 3, the data transmission The method can include the following steps:
  • Step 101 When transmitting the first data to the upper computer, the lower computer generates a first direct memory access instruction.
  • the lower computer may generate the first direct memory access instruction.
  • the first direct memory access instruction can indicate the source address and the first target address.
  • the so-called source address refers to the storage address of the first data in the lower computer, that is, the source address refers to the upstream of the lower computer.
  • the address at which the first data is stored in the data cache, the so-called first target address is the address of the first storage space in the main memory, where the first storage space is preset for storing the upper computer and the lower computer through the direct memory Access operation (English: direct memory access; abbreviation: DMA) is the storage space of data that is transferred to each other.
  • Direct memory access operation refers to the technology of directly transferring data from one storage space to another storage space without using the CPU.
  • the so-called address segment includes the start address of the storage space and the offset size of the storage space.
  • the buffer monitoring element in the lower computer can monitor the upstream data buffer of the lower computer.
  • the buffer monitoring element can report to The main controller sends uplink data buffer status information, the uplink data buffer status information is used to indicate that data is stored in the uplink data buffer, and after the main controller receives the uplink data buffer status information, it can generate the above-mentioned first direct memory access instruction .
  • Step 102 The lower computer executes the first direct memory access operation according to the first direct memory access instruction.
  • the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and transferring the first data to the first storage space of the main memory according to the first target address.
  • the main controller may generate the above-mentioned first direct memory access instruction. After generating the first direct memory access instruction, the main controller may access the first direct memory access instruction.
  • the instruction is passed to the control state adapter, and the control state adapter can convert the first direct memory access instruction into the first PCIe HIP control instruction.
  • the first PCIe HIP control instruction is an instruction that can be directly parsed by the PCIe HIP component, and then the control state adapter
  • the first PCIe HIP control instruction may be transferred to the PCIe HIP component, and the PCIe HIP component may execute the first direct memory access operation described above according to the first PCIe HIP control instruction.
  • the lower computer of the PCIe bus architecture when the lower computer of the PCIe bus architecture transmits the first data to the upper computer, it can generate the first direct memory access instruction and execute it according to the first direct memory access instruction.
  • the first direct memory access operation is to transfer the first data from the lower computer to the first storage space of the main memory through the first direct memory access operation, where the first storage space is preset for storing the upper computer The storage space of the data transferred to each other through direct memory access operation with the lower computer.
  • the transmission of the uplink data in the embodiment of this application may not be triggered by the upper computer, but can be triggered by the lower computer. Start independently, which can improve the flexibility of uplink data transmission and further reduce the delay of uplink data transmission.
  • the data transmission method provided in the embodiment of the present application may further include the following steps:
  • Step 201 The lower computer receives the first data generated by the application layer through the user data interface adapter, and stores the first data in the uplink data buffer.
  • Step 202 The lower computer monitors the upstream data buffer through the buffer monitoring element, obtains the storage address of the first data in the upstream data buffer through monitoring, uses the storage address of the first data in the upstream data buffer as the source address, and sets The source address is passed to the main controller.
  • step 201 and step 202 the main controller can obtain the source address, and then the main controller can generate the above-mentioned first direct memory access instruction according to the source address.
  • the data transmission method provided by the embodiment of the present application may further include the following steps:
  • Step 301 The lower computer receives the data downlink indication information sent by the upper computer.
  • the data transmission between the upper computer and the lower computer may include uplink data transmission and downlink data transmission.
  • step 301 to step 303 the embodiment of the present application will describe the process of downlink data transmission.
  • the upper computer can store the second data (data to be transmitted downstream) in the first storage space of the main memory, and then the upper computer can generate data downlink indication information and indicate the data downlink The information is sent to the lower computer.
  • the data downlink indication information is used to trigger the lower computer to perform downlink data transmission.
  • the data downlink indication information may be a second bar address write command.
  • the PCIe HIP component in the lower computer can receive the second bar address transmitted by the upper computer. bar address write instruction, and transfer the second bar address write instruction to the control state adapter, the control state adapter can convert the second bar address write instruction into the second main controller control information, wherein the second main control The controller control information can be directly parsed by the main controller, and then the control state adapter can transfer the second main controller control information to the main controller. In this way, the lower computer realizes the reception of the data downlink indication information.
  • Step 302 The lower computer generates a second direct memory access instruction according to the instruction of the data downlink instruction information.
  • the second direct memory access instruction is used to indicate the first target address mentioned above.
  • the main controller may generate the second direct memory access instruction after receiving the control information of the second main controller.
  • Step 303 The lower computer executes the second direct memory access operation according to the second direct memory access instruction.
  • the second direct memory access operation includes obtaining second data from the first storage space and storing the second data in a lower computer.
  • the second direct memory access operation can store the second data To the downstream data buffer of the lower computer.
  • the main controller may generate the above-mentioned second direct memory access instruction. After generating the second direct memory access instruction, the main controller may access the second direct memory access instruction.
  • the instruction is transferred to the control state adapter, and the control state adapter can convert the second direct memory access instruction into a second PCIe HIP control instruction.
  • the second PCIe HIP control instruction is an instruction that can be directly parsed by the PCIe HIP component, and then the control state
  • the adapter may transfer the second PCIe HIP control instruction to the PCIe HIP component, and the PCIe HIP component may execute the second direct memory access operation according to the second PCIe HIP control instruction.
  • the lower computer of the PCIe architecture can receive the data downlink instruction information transmitted by the upper computer, and generate the second direct memory access instruction according to the instruction of the data downlink instruction information, and then, Perform a second direct memory access operation according to the second direct memory access instruction to transfer the second data from the first storage space of the main memory to the lower computer through the second direct memory access operation, wherein the first storage space It is the pre-set storage space for storing the data transferred between the upper computer and the lower computer through the direct memory access operation, because the main memory is preset to store the data that the upper computer and the lower computer pass through each other through the direct memory access operation.
  • the first storage space therefore, in the process of the upper computer transferring the second data to the lower computer, that is, in the process of downlink data transmission, there is no need for the upper computer to obtain the storage requirements in the main memory by means of system calls.
  • the address of the storage space of the data to be transmitted (that is, the second data) is set. Since the first storage space is preset, the lower computer can obtain the address of the first storage space in advance. Therefore, the downstream data is being processed.
  • the interaction process between the upper computer and the lower computer during the downlink data transmission process can be simplified, thereby reducing the delay of the downlink data transmission. Improve the efficiency of downlink data transmission.
  • the data transmission method provided by the embodiment of the present application may further include the following steps:
  • Step 401 After the first direct memory access operation or the second direct memory access operation is executed, the lower computer generates an execution completion message.
  • the PCIe HIP component since the PCIe HIP component performs the first direct memory access operation and the second direct memory access operation, the first direct memory access operation or the second direct memory access operation After the operation is executed, the PCIe HIP component can generate an execution completion instruction, and transfer the execution completion instruction to the control state adapter, and the control state adapter can convert the execution completion instruction into the third main controller control information, where the The third main controller control information can be directly parsed by the main controller. Then, the control state adapter can transfer the third main controller control information to the main controller, and the main controller can be based on the third main controller. The control information generates intermediate execution completion information, and transfers the intermediate execution completion information to the control state adapter.
  • the control state adapter can convert the intermediate execution completion information into execution completion information, where the execution completion information is a PCIe HIP component. Directly parsed information, and then the control state adapter can transfer the execution completion information to the PCIe HIP component, so that the lower computer completes the execution completion information generation process.
  • Step 402 The lower computer transmits the execution completion information to the second storage space in the main memory according to the second target address.
  • the second target address is an address of a second storage space
  • the second storage space is a preset storage space for storing execution completion information transmitted by a lower computer.
  • the second target address here may also be an address segment. It can include the start address of the storage space and the offset size of the storage space.
  • the PCIe HIP component may transfer the execution completion information to the second storage space according to the second target address.
  • the upper computer may check the second storage space when needed, to determine whether the uplink data transmission or the downlink data transmission is completed according to the execution completion information in the second storage space.
  • the upper computer when the upper computer needs to perform downlink data transmission, it can check the second storage space to determine whether the lower computer still has the unfinished first direct memory access operation or the second direct memory access operation. When there is an uncompleted first direct memory access operation or second direct memory access operation, the upper computer can perform downlink data transmission, thereby avoiding the occurrence of the lower computer performing two direct memory access operations at the same time, and then avoiding system abnormalities .
  • the upper computer when the upper computer needs to use the data transmitted by the lower computer, it can check the second storage space to determine whether the lower computer has performed the first direct memory access operation. When it is determined that the lower computer has performed the first direct memory access During operation, it indicates that the lower computer has completely transmitted the data to the main memory. At this time, the upper computer can use the data transmitted by the lower computer normally.
  • the second storage space can be checked to determine whether the lower computer has completed the second direct memory access operation.
  • it indicates that the data in the first storage space has been completely transferred to the lower computer.
  • the first storage space can be released, and at the same time, the upper computer can store the data in the first storage space. in.
  • the host computer may be a multi-core CPU.
  • a CPU may be used to monitor the second storage space in real time. At this time, the host computer can not only view the second storage space when needed. The storage space is available, but the second storage space can be viewed in real time.
  • the data transmission method provided in the embodiments of the present application may further include the following steps:
  • the lower computer receives the first target address and the second target address transmitted by the upper computer.
  • the PCIe HIP component in the lower computer may receive the first bar address write instruction transmitted by the upper computer, and transmit the first bar address write instruction to the control state adapter, where: The first bar address write instruction carries the first target address and the second target address. Then, the control state adapter can convert the first bar address write instruction into the first main controller control information, and the first main controller control information is The main controller can directly parse the information, and then, the control state adapter can transfer the first main controller control information to the main controller, and the first main controller control information carries the first target address and the second target address. In this way, the lower computer realizes the reception of the first target address and the second target address transmitted by the upper computer.
  • the first target address and the second target address are sent by the host computer after the first storage space and the second storage space are set, and the first storage space and the second storage space are the host computer in the lower position It is set after the driver of the machine is loaded.
  • the data transmission method provided in the embodiments of this application can be applied to a PCIe bus architecture deployed in a 5G base station (for example, a 5G indoor base station).
  • a 5G base station for example, a 5G indoor base station.
  • the upper computer can be a CPU
  • the lower computer can be FPGA
  • the CPU can use its own general computing power to process the L2 and L3 protocols
  • the FPGA can use its own parallel processing power to process the L1 protocol.
  • service data or operation and maintenance management data (abbreviated as OAM) can be transmitted between the upper computer and the lower computer.
  • OAM operation and maintenance management data
  • FIG. 7 shows a block diagram of a data transmission device 700 provided by an embodiment of the present application.
  • the data transmission device 700 may be configured in the above-mentioned lower computer.
  • the data transmission device 700 may include: a first generation module 701 and a first execution module 702.
  • the first generating module 701 is configured to generate a first direct memory access instruction when transmitting the first data to the upper computer, where the first direct memory access instruction is used to indicate the source address and the first target address, and the source address Is the storage address of the first data in the lower computer, the first target address is the address of the first storage space in the main memory, and the first storage space is preset for storing the upper computer and the lower computer.
  • the first execution module 702 is configured to execute a first direct memory access operation according to the first direct memory access instruction; wherein, the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, And transfer the first data to the first storage space according to the first target address.
  • the first generation module 701 is specifically configured to generate the first direct memory access instruction through the main controller.
  • the first execution module 702 is specifically configured to: pass the first direct memory access instruction to the control state adapter through the main controller; access the first direct memory through the control state adapter The instruction is converted into the first PCIe HIP control instruction; the first PCIe HIP control instruction is transferred to the PCIe HIP component through the control state adapter; the first direct memory access operation is executed according to the first PCIe HIP control instruction through the PCIe HIP component .
  • an embodiment of the present application also provides another data transmission device 800.
  • the data transmission device 800 may optionally include a data transmission device 800.
  • the first receiving module 703 is configured to receive data downlink indication information sent by the upper computer.
  • the second generating module 704 is configured to generate a second direct memory access instruction according to the indication of the data downlink indication information, and the second direct memory access instruction is used to indicate the first target address.
  • the second execution module 705 is configured to execute a second direct memory access operation according to the second direct memory access instruction; wherein, the second direct memory access operation includes obtaining second data from the first storage space, and storing the The second data is stored in the lower computer.
  • the sending module 706 is configured to generate execution completion information after the first direct memory access operation or the second direct memory access operation is completed, and transmit the execution completion information to the main memory in the main memory according to the second target address.
  • the second storage space wherein the second target address is the address of the second storage space, and the second storage space is a preset storage space for storing the execution completed information delivered by the lower computer.
  • the second receiving module 707 is configured to receive the first target address and the second target address transmitted by the host computer; wherein, the first target address and the second target address are when the host computer is in the first storage After the space and the second storage space are set, the first storage space and the second storage space are set by the upper computer after the driver of the lower computer is loaded.
  • the second receiving module 707 is specifically configured to: receive the first bar address write instruction delivered by the host computer through the PCIe HIP component, and transmit the first bar address write instruction to the control state adapter, and the first bar address write instruction
  • the bar address write instruction carries the first target address and the second target address
  • the first bar address write instruction is converted into the first main controller control information by the control state adapter, and the first main controller control information is converted And transferred to the main controller, the first main controller control information carries the first target address and the second target address.
  • the third receiving module 708 is configured to receive the first data generated by the application layer through the user data interface adapter, and store the first data in the uplink data buffer.
  • the monitoring module 709 is configured to monitor the upstream data buffer through the buffer monitoring element, obtain the storage address of the first data in the upstream data buffer through monitoring, and store the first data in the upstream data buffer The address is used as the source address, and the source address is passed to the main controller.
  • the first receiving module 703 is specifically configured to: receive the second bar address write instruction transmitted by the host computer through the PCIe HIP component, and transmit the second bar address write instruction to the control state adapter; and pass the control state
  • the adapter converts the second bar address writing instruction into the second main controller control information, and transmits the second main controller control information to the main controller.
  • the second generating module 704 is specifically configured to generate the second direct memory access instruction through the main controller.
  • the second execution module 705 is specifically configured to: transfer the second direct memory access instruction to the control state adapter through the main controller; and convert the second direct memory access instruction into a second PCIe HIP through the control state adapter Control instruction; the second PCIe HIP control instruction is transferred to the PCIe HIP component through the control state adapter; the second direct memory access operation is executed according to the second PCIe HIP control instruction through the PCIe HIP component.
  • the sending module 706 is specifically used to: generate an execution completion instruction through the PCIe HIP component, and transfer the execution completion instruction to the control state adapter; and convert the execution completion instruction to the third main controller control through the control state adapter Information, and transfer the third main controller control information to the main controller; through the main controller, generate intermediate execution completion information according to the third main controller control information, and transmit the intermediate execution completion information to the control State adapter; through the control state adapter, the intermediate execution completion information is converted into the execution completion information, and the execution completion information is transferred to the PCIe HIP component; the execution completion information is transmitted by the PCIe HIP component according to the second target address To the second storage space.
  • the device for determining the CPU utilization rate provided by the embodiment of the present application can implement the foregoing method embodiment, and its implementation principles and technical effects are similar, and details are not described herein again.
  • Each module in the above-mentioned determining data transmission device can be implemented in whole or in part by software, hardware, and a combination thereof.
  • the above-mentioned modules may be embedded in the form of hardware or independent of the processor in the computer equipment, or may be stored in the memory of the computer equipment in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules.
  • a computer device in an embodiment of the present application, includes a memory and a processor, and a computer program is stored in the memory.
  • the processor executes the computer program, the following steps are implemented:
  • a first direct memory access instruction is generated, where the first direct memory access instruction is used to indicate the source address and the first target address, and the source address is the first data in the lower computer.
  • the first target address is the address of the first storage space in the main memory, and the first storage space is preset for storing the transfer between the upper computer and the lower computer through direct memory access operations Data storage space; execute a first direct memory access operation according to the first direct memory access instruction; wherein, the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and according to the first direct memory access A target address transfers the first data to the first storage space.
  • the processor further implements the following steps when executing the computer program: receiving the data downlink indication information sent by the upper computer; generating a second direct memory access instruction according to the indication of the data downlink indication information, the second The direct memory access instruction is used to indicate the first target address; execute a second direct memory access operation according to the second direct memory access instruction; wherein, the second direct memory access operation includes obtaining second data from the first storage space , And store the second data in the lower computer.
  • the processor further implements the following steps when executing the computer program: after the first direct memory access operation or the second direct memory access operation is completed, an execution completion message is generated, and according to the second target The address transfers the execution completion information to the second storage space in the main memory; wherein, the second target address is the address of the second storage space, and the second storage space is preset for storing the transfer of the lower computer The storage space of the completed information.
  • the processor further implements the following steps when executing the computer program: receiving the first target address and the second target address transmitted by the host computer; wherein, the first target address and the second target address The address is sent by the host computer after setting the first storage space and the second storage space, and the first storage space and the second storage space are set by the host computer after the driver of the lower computer is loaded. of.
  • the lower computer includes a main controller, a control state adapter, and a PCIe HIP component.
  • the processor also implements the following steps when executing a computer program: receiving the first bar from the upper computer through the PCIe HIP component Address write instruction, and transfer the first bar address write instruction to the control state adapter, the first bar address write instruction carries the first target address and the second target address; the first bar address is transferred through the control state adapter
  • the address write instruction is converted into the first main controller control information, and the first main controller control information is transferred to the main controller, and the first main controller control information carries the first target address and the second target address .
  • the processor further implements the following step when executing the computer program: the main controller generates the first direct memory access instruction.
  • the lower computer also includes a user data interface adapter, an uplink data buffer, and a buffer monitoring element.
  • the processor also implements the following steps when executing the computer program: receiving the user data interface adapter generated by the application layer First data, and store the first data in the uplink data buffer; monitor the uplink data buffer by the buffer monitoring element, obtain the storage address of the first data in the uplink data buffer through monitoring, and then The storage address of a data in the upstream data buffer is used as the source address, and the source address is transferred to the main controller.
  • the processor further implements the following steps when executing the computer program: the first direct memory access instruction is transmitted to the control state adapter through the main controller; the first direct memory access instruction is transmitted to the control state adapter through the control state adapter; The memory access instruction is converted into the first PCIe HIP control instruction; the first PCIe HIP control instruction is transferred to the PCIe HIP component through the control state adapter; the PCIe HIP component executes the first direct instruction according to the first PCIe HIP control instruction Memory access operation.
  • the lower computer includes a main controller, a control state adapter, and a PCIe HIP component.
  • the processor also implements the following steps when executing a computer program: receiving the second bar from the upper computer through the PCIe HIP component Address write instruction, and transfer the second bar address write instruction to the control state adapter; convert the second bar address write instruction into the second main controller control information through the control state adapter, and transfer the second main control The controller control information is transferred to the main controller.
  • the processor when the processor executes the computer program, the following steps are further implemented: generating the second direct memory access instruction through the main controller.
  • the second direct memory access instruction is transmitted to the control state adapter through the main controller; the second direct memory access instruction is transmitted to the control state adapter through the control state adapter;
  • the memory access instruction is converted into a second PCIe HIP control instruction; the second PCIe HIP control instruction is transferred to the PCIe HIP component through the control state adapter; the second PCIe HIP control instruction is executed by the PCIe HIP component according to the second PCIe HIP control instruction.
  • the lower computer includes a main controller, a control state adapter, and a PCIe HIP component.
  • the processor also implements the following steps when executing a computer program: the PCIe HIP component generates an execution completion instruction, and executes it.
  • the completion instruction is transmitted to the control state adapter; the execution completion instruction is converted into the third main controller control information through the control state adapter, and the third main controller control information is transmitted to the main controller; through the main control The device generates intermediate execution completion information according to the third main controller control information, and transmits the intermediate execution completion information to the control state adapter; the intermediate execution completion information is converted into the execution completion information through the control state adapter, and The execution completion information is transferred to the PCIe HIP component; the execution completion information is transferred to the second storage space through the PCIe HIP component according to the second target address.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:
  • a first direct memory access instruction is generated, where the first direct memory access instruction is used to indicate the source address and the first target address, and the source address is the first data in the lower computer.
  • the first target address is the address of the first storage space in the main memory, and the first storage space is preset for storing the transfer between the upper computer and the lower computer through direct memory access operations Data storage space; execute a first direct memory access operation according to the first direct memory access instruction; wherein, the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and according to the first direct memory access A target address transfers the first data to the first storage space.
  • the following steps are also implemented: receiving the data downlink indication information sent by the upper computer; generating a second direct memory access instruction according to the indication of the data downlink indication information, the first A second direct memory access instruction is used to indicate the first target address; a second direct memory access operation is performed according to the second direct memory access instruction; wherein, the second direct memory access operation includes obtaining a second direct memory access operation from the first storage space Data, and store the second data in the lower computer.
  • the following steps are also implemented: after the first direct memory access operation or the second direct memory access operation is completed, the execution completion information is generated, and the execution completion information is generated according to the second direct memory access operation.
  • the target address transfers the execution completion information to the second storage space in the main memory; wherein, the second target address is the address of the second storage space, and the second storage space is preset for storing the lower computer The storage space of the transmitted execution completed information.
  • the following steps are also implemented: receiving the first target address and the second target address transmitted by the host computer; wherein, the first target address and the second target address
  • the target address is sent by the upper computer after setting the first storage space and the second storage space.
  • the first storage space and the second storage space are the upper computer after the driver of the lower computer is loaded. Set.
  • the lower computer includes a main controller, a control state adapter, and PCIe HIP components.
  • the following steps are also implemented: receiving the first transfer from the upper computer through the PCIe HIP component. bar address write command, and transfer the first bar address write command to the control state adapter, the first bar address write command carries the first target address and the second target address; the first bar address write command carries the first target address and the second target address; The bar address write instruction is converted into the first main controller control information, and the first main controller control information is transferred to the main controller.
  • the first main controller control information carries the first target address and the second target address.
  • the main controller when the computer program is executed by the processor, the following steps are further implemented: the main controller generates the first direct memory access instruction.
  • the lower computer also includes a user data interface adapter, an upstream data buffer, and a buffer monitoring element.
  • the following steps are also implemented: receiving the data generated by the application layer through the user data interface adapter The first data, and store the first data in the uplink data buffer; monitor the uplink data buffer by the buffer monitoring element, obtain the storage address of the first data in the uplink data buffer by monitoring, and then The storage address of the first data in the upstream data buffer is used as the source address, and the source address is transferred to the main controller.
  • the first direct memory access instruction is transmitted to the control state adapter through the main controller; the first direct memory access instruction is transmitted to the control state adapter through the control state adapter;
  • the direct memory access command is converted into the first PCIe HIP control command; the first PCIe HIP control command is transferred to the PCIe HIP component through the control state adapter; the PCIe HIP component executes the first PCIe HIP control command according to the first PCIe HIP control command.
  • Direct memory access operation is further implemented: the first direct memory access instruction is transmitted to the control state adapter through the main controller; the first direct memory access instruction is transmitted to the control state adapter through the control state adapter;
  • the direct memory access command is converted into the first PCIe HIP control command; the first PCIe HIP control command is transferred to the PCIe HIP component through the control state adapter; the PCIe HIP component executes the first PCIe HIP control command according to the first PCIe HIP control command.
  • the lower computer includes a main controller, a control state adapter, and a PCIe HIP component.
  • the following steps are also implemented: receiving the second pass from the upper computer through the PCIe HIP component. bar address write instruction, and transfer the second bar address write instruction to the control state adapter; through the control state adapter, the second bar address write instruction is converted into the second master controller control information, and the second master The controller control information is transferred to the main controller.
  • the main controller when the computer program is executed by the processor, the following steps are further implemented: the main controller generates the second direct memory access instruction.
  • the second direct memory access instruction is transmitted to the control state adapter through the main controller; the second direct memory access instruction is transmitted to the control state adapter through the control state adapter;
  • the direct memory access command is converted into a second PCIe HIP control command; the second PCIe HIP control command is transferred to the PCIe HIP component through the control state adapter; the second PCIe HIP control command is executed by the PCIe HIP component according to the second PCIe HIP control command Direct memory access operation.
  • the lower-level computer includes a main controller, a control state adapter, and PCIe HIP components.
  • the PCIe HIP component when the computer program is executed by the processor, the following steps are also implemented: the PCIe HIP component generates an execution completion instruction, and the The execution completion instruction is transferred to the control state adapter; the execution completion instruction is converted into the third main controller control information through the control state adapter, and the third main controller control information is transmitted to the main controller;
  • the controller generates intermediate execution completion information according to the third main controller control information, and transmits the intermediate execution completion information to the control state adapter; converts the intermediate execution completion information into the execution completion information through the control state adapter, and
  • the execution completion information is transferred to the PCIe HIP component; the execution completion information is transferred to the second storage space through the PCIe HIP component according to the second target address.
  • the data transmission method provided in this application is applied to the lower computer of the PCIe bus architecture.
  • direct memory access is used to simplify the interaction process between the upper computer and the lower computer and reduce the uplink data transmission.
  • the time delay, improve the efficiency of uplink data transmission, has strong industrial applicability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

一种数据传输方法、装置、设备及存储介质，该方法包括：在向上位机传递第一数据时，下位机生成第一直接内存访问指令（101），其中，第一直接内存访问指令用于指示源地址和第一目标地址，第一目标地址为主内存中的第一存储空间的地址，第一存储空间为预先设置的用于存储上位机和下位机通过直接内存访问操作相互传递的数据的存储空间；下位机根据第一直接内存访问指令执行第一直接内存访问操作（102）；其中，第一直接内存访问操作包括从源地址对应的存储空间中获取第一数据，并根据第一目标地址将第一数据传递至第一存储空间。该方法能够在一定程度上提高上位机和下位机之间数据传输的效率，降低数据传输时延。

Description

数据传输方法、装置、设备及存储介质
本申请要求于2019年12月30日提交中国专利局、申请号为201911399205.0、发明名称为“数据传输方法、装置、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别是涉及一种数据传输方法、装置、设备及存储介质。
背景技术
PCIe是一种高速串行计算机扩展总线标准。典型的PCIe总线架构包括上位机、下位机(英文：endpoint)、主内存(英文：main memory)、根组件(英文：root complex)以及交换器(英文：switch)等。
其中，上位机和下位机之间可以进行数据传输，当前，如何提高上位机和下位机之间数据传输的效率，降低其数据传输时延已经成为了一个亟待解决的问题。
发明内容
(一)要解决的技术问题
本申请要解决的技术问题是解决现有的上位机和下位机之间数据传输的时延较长、数据传输的效率低的问题。
(二)技术方案
为了解决上述技术问题，本申请实施例提供了一种数据传输方法、装置、设备及存储介质。
第一方面，提供了一种数据传输方法，用于PCIe总线架构的下位机中，该PCIe总线架构包括上位机、主内存和该下位机，该数据传输方法包括：
在向该上位机传递第一数据时，生成第一直接内存访问指令，其中，该第一直接内存访问指令用于指示源地址和第一目标地址，该源地址为该第一数据在该下位机中的存储地址，该第一目标地址为该主内存中的第一存储空间的地址，该第一存储空间为预先设置的用于存储该上位机和该下位机通过直接内存访问操作相互传递的数据的存储空间；根据该第一直接内存访问指令执行第一直接内存访问操作；其中，该第一直接内存访问操作包括从该源地址对应的存储空间中获取该第一数据，并根据该第一目标地址将该第一数据传递至该第一存储空间。
第二方面，提供了一种数据传输装置，用于PCIe总线架构的下位机中，该PCIe总线架构包括上位机、主内存和该下位机，该数据传输装置包括：
第一生成模块，用于在向该上位机传递第一数据时，生成第一直接内存访问指令，其中，该第一直接内存访问指令用于指示源地址和第一目标地址，该源地址为该第一数据在该下位机中的存储地址，该第一目标地址为该主内存中的第一存储空间的地址，该第一存储空间为预先设置的用于存储该上位机和该下位机通过直接内存访问操作相互传递的数据的存储空间；
第一执行模块，用于根据该第一直接内存访问指令执行第一直接内存访问操作；其中，该第一直接内存访问操作包括从该源地址对应的存储空间中获取该第一数据，并根据该第一目标地址将该第一数据传递至该第一存储空间。
第三方面，提供了一种计算机设备，包括存储器和处理器，该存储器存储有计算机程序，该计算机程序被该处理器执行时实现如上述第一方面任一所述的数据传输方法。
第四方面，提供了一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现如上述第一方面任一所述的数据传输方法。
(三)有益效果
本申请实施例提供的上述技术方案与现有技术相比具有如下优点：
PCIe总线架构的下位机在向上位机传递第一数据时，可以生成第一直接内存访问指令，并根据该第一直接内存访问指令执行第一直接内存访问操作，以通过该第一直接内存访问操作将第一数据从下位机传递至主内存的第一存储空间中，其中，该第一存储空间为预先设置的用于存储上位机和下位机通过直接内存访问操作相互传递的数据的存储空间，由于预先设置了主内存中用于存储上位机和下位机通过直接内存访问操作相互传递的数据的第一存储空间，因此，在下位机向上位机传递第一数据的过程中，也即是，在进行上行数据传输的过程中，就不需要上位机通过系统调用的方式获取主内存中能够存储下位机所传输的数据的存储空间的地址了，由于预先设置了第一存储空间，因此，下位机可以预先获取到该第一存储空间的地址，故而，在进行上行数据传输的过程中，也不需要上位机向下位机发送该地址了，这样，就可以简化上行数据传输过程中上位机和下位机之间的交互流程，从而可以减小上行数据传输的时延，提高上行数据传输的效率。
附图说明
图1为一种典型的PCIe总线架构的示意图；
图2为本申请实施例提供的一种下位机的结构示意图；
图3为本申请实施例提供的一种数据传输方法的流程图；
图4为本申请实施例提供的一种数据传输方法的流程图；
图5为本申请实施例提供的一种数据传输方法的流程图；
图6为本申请实施例提供的一种数据传输方法的流程图；
图7为本申请实施例提供的一种数据传输装置的框图；
图8为本申请实施例提供的另一种数据传输装置的框图。
具体实施方式
PCIe(英文：peripheral component interconnect express)是一种高速串行计算机扩展总线标准。
请参考图1，其示出了一种典型的PCIe总线架构的示意图，如图1所示，PCIe总线架构可以包括上位机00、下位机01、主内存03、根组件04以及交换器05。其中，上位机00、主内存03以及交换器05均与根组件04连接，下位机01与交换器05连接。上位机00可以通过多级缓存机制将数据存放于主内存03之中，上位00可以通过根组件04访问主内存03；同时，下位机01可以通过交换器05以及根组件04访问主内存03。
实际应用中，PCIe总线架构中的上位机00可以为CPU(英文：central processing unit；中文：中央处理器)，下位机01也可以被称为终端(英文：PCIe endpoint)，其可以为FPGA(英文：Field Programmable Gate Array)芯片。
通常情况下，PCIe架构中的上位机和下位机之间可以进行数据传输，其中，PCIe架构中上位机和下位机之间的数据传输可以包括上行数据传输和下行数据传输。其中，上行数据传输指的是下位机将数据传输至上位机中，在上行数据传输中，数据由下位机的存储空间转移至主内存中，下行数据传输指的是上位机将数据传输至下位机中，在下行数据传输中，数据由主内存转移至下位机的存储空间中。
在上行数据传输的过程中，上位机需要通过系统调用的方式获取主内存中能够存储下位机所传输的数据的存储空间的地址(以下简称为第一地址)，而后，上位机可以触发下位机执行上行数据的传输过程，并在触发的过程中向下位机发送该第一地址，下位机接收到该第一地址之后，可以将下位机中存储的数据转移至该第一地址对应的主内存的存储空间中。
在下行数据传输的过程中，上位机需要通过系统调用的方式获取主内存中存储需要进行传输的数据的存储空间的地址(以下简称为第二地址)，而后，上位机可以将该第二地址发送至下位机中，下位机接收到该第二地址之后，可以从该第二地址对应的主内存的存储空间中获取该需要进行传输的数据，并将该需要进行传输的数据存储至下位机的存储空间中。
根据以上说明可知，在上行数据和下行数据的传输过程中，上位机都需要向下位机发送地址信息(上文所述的第一地址和第二地址)，这导致在上行数据和下行数据的传输过程中，上位机和下位机之间的交互流程较为繁琐，因而，导致数据传输的时延较长，继而影响数据的传输效率。
有鉴于此，本申请实施例提供了一种数据传输方法，该数据传输方法可以简化数据传输过程中上位机和下位机之间的交互流程，减小数据传输时延，提高数 据传输效率。
下面，本申请将以下位机为FPGA为例，对下位机的结构进行简要说明，请参考图2，该下位机可以包括主控制器(英文：main controller)、控制状态适配器(英文：controland status adaptor)、PCIe HIP元件、用户数据接口适配器(英文：user logic dataadaptor)、缓存监控元件(英文：buffer monitor)、上行数据缓存(英文：uplink buffer)、下行数据缓存(英文：downlink buffer)、PCIe HIP数据接口适配器(英文：PCIe HIP dataadaptor)和驱动。
其中，主控制器用于提供处理及控制功能，例如，主控制器可以控制下位机与上位机进行数据交互等。
控制状态适配器用于对主控制器和PCIe HIP元件之间的数据交互进行适配。在许多情况下，PCIe HIP元件通常并不能直接对主控制器产生的数据进行解析，同时，主控制器通常也不能直接对PCIe HIP元件产生的数据进行解析，因此，为了实现主控制器和PCIe HIP元件之间的数据交互，本申请实施例可以设置控制状态适配器，该控制状态适配器可以对PCIe HIP元件产生的数据进行适配，以通过适配使主控制器能够解析PCIe HIP元件产生的数据，此外，该控制状态适配器还可以对主控制器产生的数据进行适配，以通过适配使PCIe HIP元件能够解析主控制器产生的数据。
需要指出的是，主控制器和控制状态适配器之间的适配不随着下位机平台的变化而变化，因此，当本申请实施例提供的技术方案在不同的下位机平台(例如，Xilinx或者Intel)上部署时，主控制器和控制状态适配器之间的适配不需要进行修改。
PCIe HIP元件可以在主控制器的控制下执行下位机与上位机之间的数据交互。
用户数据接口适配器是下位机的缓存接口，其可以接收应用层产生的数据，并将其存储于上行数据缓存中，同时，用户数据接口适配器还可以将下行数据缓存中存储的数据传递至应用层。
上行数据缓存用于存储应用层产生的数据，在数据传输的过程中，下位机可以将上行数据缓存中存储的数据传输至上位机(也即是主内存中)中。下行数据缓存用于存储上位机发送的数据。
缓存监控元件可以对上行数据缓存和下行数据缓存的状态进行监控。
PCIe HIP数据接口适配器用于对PCIe HIP元件、上行数据缓存以及下行数据缓存之间的数据交互进行适配，以提供PCIe HIP元件、上行数据缓存以及下行数据缓存之间的数据传输通道。
请参考图3，其示出了本申请实施例提供的一种数据传输方法的流程图，其中，该数据传输方法可以应用于PCIe总线架构的下位机中，如图3所示，该数据传输方法可以包括如下步骤：
步骤101、在向上位机传递第一数据时，下位机生成第一直接内存访问指令。
在上行数据传输的过程中，也即是，在向上位机传递第一数据的过程中，下位机可以生成第一直接内存访问指令。其中，该第一直接内存访问指令可以指示源地址和第一目标地址，所谓源地址指的是第一数据在下位机中的存储地址，也即是，该源地址指的是下位机的上行数据缓存中存储该第一数据的地址，所谓第一目标地址为主内存中的第一存储空间的地址，其中，该第一存储空间为预先设置的用于存储上位机和下位机通过直接内存访问操作(英文：direct memory access；简称：DMA)相互传递的数据的存储空间，直接内存访问操作指的是不通过CPU直接将数据从一个存储空间传递到另外一个存储空间的技术。
需要指出的是，这里的源地址以及第一目标地址均为地址段，所谓地址段包括存储空间的起始地址以及存储空间的偏移大小。
在本申请的可选的实施例中，下位机中的缓存监控元件可以对下位机的上行数据缓存进行监控，当缓存监控元件监控到上行数据缓存中存储入数据时，该缓存监控元件可以向主控制器发送上行数据缓存状态信息，该上行数据缓存状态信息用于指示上行数据缓存中存入数据，主控制器接收到该上行数据缓存状态信息之后，即可生成上述第一直接内存访问指令。
步骤102、下位机根据第一直接内存访问指令执行第一直接内存访问操作。
其中，第一直接内存访问操作包括从源地址对应的存储空间中获取第一数据，并根据第一目标地址将第一数据传递至主内存的第一存储空间。
如上所述，在本申请的可选的实施例中，主控制器可以生成上述第一直接内存访问指令，在生成该第一直接内存访问指令之后，主控制器可以将该第一直接内存访问指令传递至控制状态适配器，控制状态适配器可以将该第一直接内存访问指令转换为第一PCIe HIP控制指令，该第一PCIe HIP控制指令为PCIe HIP元件能够直接解析的指令，而后，控制状态适配器可以将该第一PCIe HIP控制指令传递至PCIe HIP元件，该PCIe HIP元件可以根据该第一PCIe HIP控制指令执行上文所述的第一直接内存访问操作。
综上所述，本申请实施例提供的数据传输方法，PCIe总线架构的下位机在向上位机传递第一数据时，可以生成第一直接内存访问指令，并根据该第一直接内存访问指令执行第一直接内存访问操作，以通过该第一直接内存访问操作将第一数据从下位机传递至主内存的第一存储空间中，其中，该第一存储空间为预先设置的用于存储上位机和下位机通过直接内存访问操作相互传递的数据的存储空间，由于预先设置了主内存中用于存储上位机和下位机通过直接内存访问操作相互传递的数据的第一存储空间，因此，在下位机向上位机传递第一数据的过程中，也即是，在进行上行数据传输的过程中，就不需要上位机通过系统调用的方式获取主内存中能够存储下位机所传输的数据的存储空间的地址了，由于预先设置了第一存储空间，因此，下位机可以预先获取到该第一存储空间的地址，故而，在 进行上行数据传输的过程中，也不需要上位机向下位机发送该地址了，这样，就可以简化上行数据传输过程中上位机和下位机之间的交互流程，从而可以减小上行数据传输的时延，提高上行数据传输的效率。
此外，由于本申请实施例中，在上行数据的传输过程中，上位机不需要向下位机发送地址，因此，本申请实施例中上行数据的传输可以不由上位机进行触发，而可以由下位机自主进行启动，这样可以提高上行数据传输的灵活性，进一步减小上行数据传输的时延。
请参考图4，在上文所述实施例的基础上，本申请实施例提供的数据传输方法还可以包括以下步骤：
步骤201、下位机通过用户数据接口适配器接收应用层产生的该第一数据，并将该第一数据存储至上行数据缓存中。
步骤202、下位机通过缓存监控元件对上行数据缓存进行监控，通过监控得到第一数据在该上行数据缓存中的存储地址，将第一数据在上行数据缓存中的存储地址作为源地址，并将该源地址传递至主控制器。
通过步骤201和步骤202的技术过程，主控制器可以获取到该源地址，继而，主控制器就可以根据该源地址生成上述第一直接内存访问指令。
请参考图5，在上文所述实施例的基础上，本申请实施例提供的数据传输方法还可以包括以下步骤：
步骤301、下位机接收上位机发送的数据下行指示信息。
如上文所述，上位机和下位机之间的数据传输可以包括上行数据传输和下行数据传输，在步骤301至步骤303中，本申请实施例将对下行数据传输的过程进行说明。
在下行数据传输的过程中，上位机可以将第二数据(待下行传输的数据)存储至主内存的第一存储空间中，而后，上位机可以生成数据下行指示信息，并将该数据下行指示信息发送至下位机中。该数据下行指示信息用于触发下位机进行下行数据传输。
在本申请的一个可选的实施例中，该数据下行指示信息可以为第二bar地址写指令，在下行数据传输的过程中，下位机中的PCIe HIP元件可以接收上位机传递的该第二bar地址写指令，并将该第二bar地址写指令传递至控制状态适配器，该控制状态适配器可以将该第二bar地址写指令转换为第二主控制器控制信息，其中，该第二主控制器控制信息为主控制器能够直接解析的信息，而后，控制状态适配器可以将该第二主控制器控制信息传递至主控制器。这样，下位机就实现了对数据下行指示信息的接收。
步骤302、下位机根据数据下行指示信息的指示生成第二直接内存访问指令。
其中，该第二直接内存访问指令用于指示上文所述的第一目标地址。
在本申请的一个可选的实施例中，主控制器在接收到该第二主控制器控制信 息之后，即可生成该第二直接内存访问指令。
步骤303、下位机根据第二直接内存访问指令执行第二直接内存访问操作。
其中，该第二直接内存访问操作包括从第一存储空间中获取第二数据，并将该第二数据存储至下位机中，可选的，该第二直接内存访问操作可以将第二数据存储至下位机的下行数据缓存中。
如上所述，在本申请的可选的实施例中，主控制器可以生成上述第二直接内存访问指令，在生成该第二直接内存访问指令之后，主控制器可以将该第二直接内存访问指令传递至控制状态适配器，该控制状态适配器可以将该第二直接内存访问指令转换为第二PCIe HIP控制指令，该第二PCIe HIP控制指令为PCIe HIP元件能够直接解析的指令，而后，控制状态适配器可以将该第二PCIe HIP控制指令传递至PCIe HIP元件，该PCIe HIP元件可以根据该第二PCIe HIP控制指令执行第二直接内存访问操作。
综上所述，本申请实施例提供的数据传输方法，PCIe架构的下位机可以接收上位机传输的数据下行指示信息，并根据该数据下行指示信息的指示生成第二直接内存访问指令，而后，根据该第二直接内存访问指令执行第二直接内存访问操作，以通过该第二直接内存访问操作将第二数据从主内存的第一存储空间传递至下位机中，其中，该第一存储空间为预先设置的用于存储上位机和下位机通过直接内存访问操作相互传递的数据的存储空间，由于预先设置了主内存中用于存储上位机和下位机通过直接内存访问操作相互传递的数据的第一存储空间，因此，在上位机向下位机传递第二数据的过程中，也即是，在进行下行数据传输的过程中，就不需要上位机通过系统调用的方式获取主内存中存储需要进行传输的数据(也即是第二数据)的存储空间的地址了，由于预先设置了第一存储空间，因此，下位机可以预先获取到该第一存储空间的地址，故而，在进行下行数据传输的过程中，也不需要上位机向下位机发送该地址了，这样，就可以简化下行数据传输过程中上位机和下位机之间的交互流程，从而可以减小下行数据传输的时延，提高下行数据传输的效率。
请参考图6，在上文所述实施例的基础上，本申请实施例提供的数据传输方法还可以包括以下步骤：
步骤401、在第一直接内存访问操作或者第二直接内存访问操作执行完毕后，下位机生成执行完毕信息。
可选的，在本申请的一个实施例中，由于是由PCIe HIP元件执行第一直接内存访问操作以及第二直接内存访问操作的，因此，在第一直接内存访问操作或者第二直接内存访问操作执行完毕后，该PCIe HIP元件可以生成执行完毕指令，并将该执行完毕指令传递至控制状态适配器，该控制状态适配器可以将该执行完毕指令转换为第三主控制器控制信息，其中，该第三主控制器控制信息为主控制器能够直接解析的信息，而后，控制状态适配器可以将该第三主控制器控制信息传 递至主控制器，该主控制器可以根据该第三主控制器控制信息生成中间执行完毕信息，并将该中间执行完毕信息传递至该控制状态适配器，该控制状态适配器可以将该中间执行完毕信息转换为执行完毕信息，其中，该执行完毕信息为PCIe HIP元件可以直接解析的信息，接着，该控制状态适配器可以将该执行完毕信息传递至PCIe HIP元件中，这样，下位机就完成了执行完毕信息的生成过程。
步骤402、下位机根据第二目标地址将执行完毕信息传递至主内存中的第二存储空间。
其中，该第二目标地址为第二存储空间的地址，该第二存储空间为预先设置的用于存储下位机传递的执行完毕信息的存储空间，这里的第二目标地址也可以为地址段，其可以包括存储空间的起始地址以及存储空间的偏移大小。
在控制状态适配器将该执行完毕信息传递至PCIe HIP元件之后，该PCIe HIP元件可以根据该第二目标地址将该执行完毕信息传递至该第二存储空间。
上位机可以在需要时查看该第二存储空间，以通过第二存储空间中的执行完毕信息确定上行数据传输或者下行数据传输是否完成。
例如，上位机在需要进行下行数据传输时，可以查看该第二存储空间，以确定下位机是否还有未执行完成的第一直接内存访问操作或者第二直接内存访问操作，当确定下位机不存在未执行完成的第一直接内存访问操作或者第二直接内存访问操作时，上位机可以进行下行数据传输，从而避免下位机同时执行两个直接内存访问操作的情况的发生，继而可以避免系统异常。
又例如，上位机在需要使用下位机传输的数据时，可以查看该第二存储空间，以确定下位机是否已经执行完毕第一直接内存访问操作，当确定下位机已经执行完毕第一直接内存访问操作时，说明下位机已经将数据完整地传输至主内存中，此时，上位机可以正常地使用下位机传输的数据。
再例如，当上位机需要在主内存的第一存储空间中存储数据时，可以查看该第二存储空间，以确定下位机是否已经执行完毕第二直接内存访问操作，当确定下位机已经执行完毕第二直接内存访问操作时，说明第一存储空间中的数据已经完整地传递至下位机中，此时，可以释放该第一存储空间，同时，上位机可以将数据存储至该第一存储空间中。
在本申请的一个实施例中，该上位机可以为多核CPU，在这种情况下，可以采用一个CPU实时监控第二存储空间，此时，上位机就可以不仅仅在需要时查看该第二存储空间了，而是可以实时地查看该第二存储空间。
在上文所述实施例的基础上，本申请实施例提供的数据传输方法还可以包括以下步骤：
下位机接收上位机传递的该第一目标地址和该第二目标地址。
可选的，在本申请的一个实施例中，下位机中的PCIe HIP元件可以接收上位机传递的第一bar地址写指令，并将该第一bar地址写指令传递至控制状态适配器， 其中，该第一bar地址写指令携带第一目标地址和第二目标地址，接着，控制状态适配器可以将第一bar地址写指令转换为第一主控制器控制信息，该第一主控制器控制信息为主控制器可以直接解析的信息，而后，控制状态适配器可以将第一主控制器控制信息传递至主控制器，该第一主控制器控制信息携带第一目标地址和第二目标地址。这样，下位机就实现了对上位机传递的该第一目标地址和该第二目标地址的接收。
其中，该第一目标地址和该第二目标地址是上位机在对第一存储空间和第二存储空间进行设置后发送的，该第一存储空间和该第二存储空间是上位机在对下位机的驱动加载完毕后设置的。
需要指的是，本申请实施例提供的数据传输方法可以应用于部署于5G基站(例如，5G室内基站)中的PCIe总线架构中，在5G基站中，上位机可以为CPU，下位机可以为FPGA，该CPU可以利用自身的通用计算能力处理L2和L3协议，FPGA可以利用自身的并行处理能力处理L1协议。
在5G基站中，上位机和下位机之间可以传输业务数据或者操作维护管理数据(简称：OAM)。
请参考图7，其示出了本申请实施例提供的一种数据传输装置700的框图，该数据传输装置700可以配置于上文所述的下位机中。如图7所示，该数据传输装置700可以包括：第一生成模块701和第一执行模块702。
该第一生成模块701，用于在向上位机传递第一数据时，生成第一直接内存访问指令，其中，该第一直接内存访问指令用于指示源地址和第一目标地址，该源地址为该第一数据在该下位机中的存储地址，该第一目标地址为该主内存中的第一存储空间的地址，该第一存储空间为预先设置的用于存储该上位机和该下位机通过直接内存访问操作相互传递的数据的存储空间。
该第一执行模块702，用于根据该第一直接内存访问指令执行第一直接内存访问操作；其中，该第一直接内存访问操作包括从该源地址对应的存储空间中获取该第一数据，并根据该第一目标地址将该第一数据传递至该第一存储空间。
在本申请的一个实施例中，该第一生成模块701，具体用于：通过主控制器生成该第一直接内存访问指令。
在本申请的一个实施例中，该第一执行模块702，具体用于：通过主控制器将该第一直接内存访问指令传递至控制状态适配器；通过该控制状态适配器将该第一直接内存访问指令转换为第一PCIe HIP控制指令；通过该控制状态适配器将该第一PCIe HIP控制指令传递至PCIe HIP元件；通过该PCIe HIP元件根据该第一PCIe HIP控制指令执行该第一直接内存访问操作。
请参考图8，本申请实施例还提供了另外一种数据传输装置800，该数据传输装置800除了包括数据传输装置700包括的各模块外，可选的，该数据传输装置800还可以包括第一接收模块703、第二生成模块704、第二执行模块705、发送 模块706、第二接收模块707、第三接收模块708和监控模块709。
该第一接收模块703，用于接收该上位机发送的数据下行指示信息。
该第二生成模块704，用于根据该数据下行指示信息的指示生成第二直接内存访问指令，该第二直接内存访问指令用于指示该第一目标地址。
该第二执行模块705，用于根据该第二直接内存访问指令执行第二直接内存访问操作；其中，该第二直接内存访问操作包括从该第一存储空间中获取第二数据，并将该第二数据存储至该下位机中。
该发送模块706，用于在该第一直接内存访问操作或者该第二直接内存访问操作执行完毕后，生成执行完毕信息，并根据第二目标地址将该执行完毕信息传递至该主内存中的第二存储空间；其中，该第二目标地址为该第二存储空间的地址，该第二存储空间为预先设置的用于存储该下位机传递的执行完毕信息的存储空间。
该第二接收模块707，用于接收该上位机传递的该第一目标地址和该第二目标地址；其中，该第一目标地址和该第二目标地址是该上位机在对该第一存储空间和该第二存储空间进行设置后发送的，该第一存储空间和该第二存储空间是该上位机在对该下位机的驱动加载完毕后设置的。
其中，该第二接收模块707，具体用于：通过该PCIe HIP元件接收该上位机传递的第一bar地址写指令，并将该第一bar地址写指令传递至该控制状态适配器，该第一bar地址写指令携带该第一目标地址和该第二目标地址；通过该控制状态适配器将该第一bar地址写指令转换为第一主控制器控制信息，并将该第一主控制器控制信息传递至该主控制器，该第一主控制器控制信息携带该第一目标地址和该第二目标地址。
该第三接收模块708，用于通过该用户数据接口适配器接收应用层产生的该第一数据，并将该第一数据存储至该上行数据缓存。
该监控模块709，用于通过该缓存监控元件对该上行数据缓存进行监控，通过监控得到该第一数据在该上行数据缓存中的存储地址，将该第一数据在该上行数据缓存中的存储地址作为该源地址，并将该源地址传递至该主控制器。
其中，该第一接收模块703，具体用于：通过PCIe HIP元件接收该上位机传递的第二bar地址写指令，并将该第二bar地址写指令传递至该控制状态适配器；通过该控制状态适配器将该第二bar地址写指令转换为第二主控制器控制信息，并将该第二主控制器控制信息传递至该主控制器。
该第二生成模块704，具体用于通过该主控制器生成该第二直接内存访问指令。
该第二执行模块705，具体用于：通过该主控制器将该第二直接内存访问指令传递至该控制状态适配器；通过该控制状态适配器将该第二直接内存访问指令转换为第二PCIe HIP控制指令；通过该控制状态适配器将该第二PCIe HIP控制指令 传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第二PCIe HIP控制指令执行该第二直接内存访问操作。
该发送模块706，具体用于：通过该PCIe HIP元件生成执行完毕指令，并将该执行完毕指令传递至该控制状态适配器；通过该控制状态适配器将该执行完毕指令转换为第三主控制器控制信息，并将该第三主控制器控制信息传递至该主控制器；通过该主控制器根据该第三主控制器控制信息生成中间执行完毕信息，并将该中间执行完毕信息传递至该控制状态适配器；通过该控制状态适配器将该中间执行完毕信息转换为该执行完毕信息，并将该执行完毕信息传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第二目标地址将该执行完毕信息传递至该第二存储空间。
本申请实施例提供的确定CPU利用率的装置，可以实现上述方法实施例，其实现原理和技术效果类似，在此不再赘述。
关于确定数据传输装置的具体限定可以参见上文中对于确定数据传输方法的限定，在此不再赘述。上述确定数据传输装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器中，也可以以软件形式存储于计算机设备中的存储器中，以便于处理器调用执行以上各个模块对应的操作。
在本申请的一个实施例中，提供了一种计算机设备，该计算机设备包括存储器和处理器，存储器中存储有计算机程序，该处理器执行计算机程序时实现以下步骤：
在向上位机传递第一数据时，生成第一直接内存访问指令，其中，该第一直接内存访问指令用于指示源地址和第一目标地址，该源地址为该第一数据在该下位机中的存储地址，该第一目标地址为该主内存中的第一存储空间的地址，该第一存储空间为预先设置的用于存储该上位机和该下位机通过直接内存访问操作相互传递的数据的存储空间；根据该第一直接内存访问指令执行第一直接内存访问操作；其中，该第一直接内存访问操作包括从该源地址对应的存储空间中获取该第一数据，并根据该第一目标地址将该第一数据传递至该第一存储空间。
在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：接收该上位机发送的数据下行指示信息；根据该数据下行指示信息的指示生成第二直接内存访问指令，该第二直接内存访问指令用于指示该第一目标地址；根据该第二直接内存访问指令执行第二直接内存访问操作；其中，该第二直接内存访问操作包括从该第一存储空间中获取第二数据，并将该第二数据存储至该下位机中。
在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：在该第一直接内存访问操作或者该第二直接内存访问操作执行完毕后，生成执行完毕信息，并根据第二目标地址将该执行完毕信息传递至该主内存中的第二存储空间；其中，该第二目标地址为该第二存储空间的地址，该第二存储空间为预先设置的 用于存储该下位机传递的执行完毕信息的存储空间。
在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：接收该上位机传递的该第一目标地址和该第二目标地址；其中，该第一目标地址和该第二目标地址是该上位机在对该第一存储空间和该第二存储空间进行设置后发送的，该第一存储空间和该第二存储空间是该上位机在对该下位机的驱动加载完毕后设置的。
该下位机包括主控制器、控制状态适配器以及PCIe HIP元件，在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该PCIe HIP元件接收该上位机传递的第一bar地址写指令，并将该第一bar地址写指令传递至该控制状态适配器，该第一bar地址写指令携带该第一目标地址和该第二目标地址；通过该控制状态适配器将该第一bar地址写指令转换为第一主控制器控制信息，并将该第一主控制器控制信息传递至该主控制器，该第一主控制器控制信息携带该第一目标地址和该第二目标地址。
在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该主控制器生成该第一直接内存访问指令。
该下位机还包括用户数据接口适配器、上行数据缓存和缓存监控元件，在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该用户数据接口适配器接收应用层产生的该第一数据，并将该第一数据存储至该上行数据缓存；通过该缓存监控元件对该上行数据缓存进行监控，通过监控得到该第一数据在该上行数据缓存中的存储地址，将该第一数据在该上行数据缓存中的存储地址作为该源地址，并将该源地址传递至该主控制器。
在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该主控制器将该第一直接内存访问指令传递至该控制状态适配器；通过该控制状态适配器将该第一直接内存访问指令转换为第一PCIe HIP控制指令；通过该控制状态适配器将该第一PCIe HIP控制指令传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第一PCIe HIP控制指令执行该第一直接内存访问操作。
该下位机包括主控制器、控制状态适配器以及PCIe HIP元件，在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该PCIe HIP元件接收该上位机传递的第二bar地址写指令，并将该第二bar地址写指令传递至该控制状态适配器；通过该控制状态适配器将该第二bar地址写指令转换为第二主控制器控制信息，并将该第二主控制器控制信息传递至该主控制器。
在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该主控制器生成该第二直接内存访问指令。
在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该主控制器将该第二直接内存访问指令传递至该控制状态适配器；通过该控制状态适配器将该第二直接内存访问指令转换为第二PCIe HIP控制指令；通过该控制 状态适配器将该第二PCIe HIP控制指令传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第二PCIe HIP控制指令执行该第二直接内存访问操作。
该下位机包括主控制器、控制状态适配器以及PCIe HIP元件，在本申请的一个实施例中，处理器执行计算机程序时还实现以下步骤：通过该PCIe HIP元件生成执行完毕指令，并将该执行完毕指令传递至该控制状态适配器；通过该控制状态适配器将该执行完毕指令转换为第三主控制器控制信息，并将该第三主控制器控制信息传递至该主控制器；通过该主控制器根据该第三主控制器控制信息生成中间执行完毕信息，并将该中间执行完毕信息传递至该控制状态适配器；通过该控制状态适配器将该中间执行完毕信息转换为该执行完毕信息，并将该执行完毕信息传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第二目标地址将该执行完毕信息传递至该第二存储空间。
本申请实施例提供的计算机设备，其实现原理和技术效果与上述方法实施例类似，在此不再赘述。
在本申请的一个实施例中，提供了一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现以下步骤：
在向上位机传递第一数据时，生成第一直接内存访问指令，其中，该第一直接内存访问指令用于指示源地址和第一目标地址，该源地址为该第一数据在该下位机中的存储地址，该第一目标地址为该主内存中的第一存储空间的地址，该第一存储空间为预先设置的用于存储该上位机和该下位机通过直接内存访问操作相互传递的数据的存储空间；根据该第一直接内存访问指令执行第一直接内存访问操作；其中，该第一直接内存访问操作包括从该源地址对应的存储空间中获取该第一数据，并根据该第一目标地址将该第一数据传递至该第一存储空间。
在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：接收该上位机发送的数据下行指示信息；根据该数据下行指示信息的指示生成第二直接内存访问指令，该第二直接内存访问指令用于指示该第一目标地址；根据该第二直接内存访问指令执行第二直接内存访问操作；其中，该第二直接内存访问操作包括从该第一存储空间中获取第二数据，并将该第二数据存储至该下位机中。
在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：在该第一直接内存访问操作或者该第二直接内存访问操作执行完毕后，生成执行完毕信息，并根据第二目标地址将该执行完毕信息传递至该主内存中的第二存储空间；其中，该第二目标地址为该第二存储空间的地址，该第二存储空间为预先设置的用于存储该下位机传递的执行完毕信息的存储空间。
在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：接收该上位机传递的该第一目标地址和该第二目标地址；其中，该第一目标地址和该第二目标地址是该上位机在对该第一存储空间和该第二存储空间进行设置后发送的，该第一存储空间和该第二存储空间是该上位机在对该下位机的驱动加载完 毕后设置的。
该下位机包括主控制器、控制状态适配器以及PCIe HIP元件，在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该PCIe HIP元件接收该上位机传递的第一bar地址写指令，并将该第一bar地址写指令传递至该控制状态适配器，该第一bar地址写指令携带该第一目标地址和该第二目标地址；通过该控制状态适配器将该第一bar地址写指令转换为第一主控制器控制信息，并将该第一主控制器控制信息传递至该主控制器，该第一主控制器控制信息携带该第一目标地址和该第二目标地址。
在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该主控制器生成该第一直接内存访问指令。
该下位机还包括用户数据接口适配器、上行数据缓存和缓存监控元件，在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该用户数据接口适配器接收应用层产生的该第一数据，并将该第一数据存储至该上行数据缓存；通过该缓存监控元件对该上行数据缓存进行监控，通过监控得到该第一数据在该上行数据缓存中的存储地址，将该第一数据在该上行数据缓存中的存储地址作为该源地址，并将该源地址传递至该主控制器。
在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该主控制器将该第一直接内存访问指令传递至该控制状态适配器；通过该控制状态适配器将该第一直接内存访问指令转换为第一PCIe HIP控制指令；通过该控制状态适配器将该第一PCIe HIP控制指令传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第一PCIe HIP控制指令执行该第一直接内存访问操作。
该下位机包括主控制器、控制状态适配器以及PCIe HIP元件，在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该PCIe HIP元件接收该上位机传递的第二bar地址写指令，并将该第二bar地址写指令传递至该控制状态适配器；通过该控制状态适配器将该第二bar地址写指令转换为第二主控制器控制信息，并将该第二主控制器控制信息传递至该主控制器。
在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该主控制器生成该第二直接内存访问指令。
在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该主控制器将该第二直接内存访问指令传递至该控制状态适配器；通过该控制状态适配器将该第二直接内存访问指令转换为第二PCIe HIP控制指令；通过该控制状态适配器将该第二PCIe HIP控制指令传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第二PCIe HIP控制指令执行该第二直接内存访问操作。
该下位机包括主控制器、控制状态适配器以及PCIe HIP元件，在本申请的一个实施例中，计算机程序被处理器执行时还实现以下步骤：通过该PCIe HIP元件生成执行完毕指令，并将该执行完毕指令传递至该控制状态适配器；通过该控制 状态适配器将该执行完毕指令转换为第三主控制器控制信息，并将该第三主控制器控制信息传递至该主控制器；通过该主控制器根据该第三主控制器控制信息生成中间执行完毕信息，并将该中间执行完毕信息传递至该控制状态适配器；通过该控制状态适配器将该中间执行完毕信息转换为该执行完毕信息，并将该执行完毕信息传递至该PCIe HIP元件；通过该PCIe HIP元件根据该第二目标地址将该执行完毕信息传递至该第二存储空间。
本实施例提供的计算机可读存储介质，其实现原理和技术效果与上述方法实施例类似，在此不再赘述。
工业实用性
本申请提供的数据传输方法，应用于在PCIe总线架构的下位机中，在上行数据传输的过程中，通过直接内存访问操作来简化上位机和下位机之间的交互流程，减小上行数据传输的时延，提高上行数据传输的效率，具有很强的工业实用性。

Claims (15)

  1. 一种数据传输方法，其特征在于，用于PCIe总线架构的下位机中，所述PCIe总线架构包括上位机、主内存和所述下位机，所述数据传输方法包括：
    在向所述上位机传递第一数据时，生成第一直接内存访问指令，其中，所述第一直接内存访问指令用于指示源地址和第一目标地址，所述源地址为所述第一数据在所述下位机中的存储地址，所述第一目标地址为所述主内存中的第一存储空间的地址，所述第一存储空间为预先设置的用于存储所述上位机和所述下位机通过直接内存访问操作相互传递的数据的存储空间；
    根据所述第一直接内存访问指令执行第一直接内存访问操作；
    其中，所述第一直接内存访问操作包括从所述源地址对应的存储空间中获取所述第一数据，并根据所述第一目标地址将所述第一数据传递至所述第一存储空间。
  2. 根据权利要求1所述的数据传输方法，其特征在于，所述数据传输方法还包括：
    接收所述上位机发送的数据下行指示信息；
    根据所述数据下行指示信息的指示生成第二直接内存访问指令，所述第二直接内存访问指令用于指示所述第一目标地址；
    根据所述第二直接内存访问指令执行第二直接内存访问操作；
    其中，所述第二直接内存访问操作包括从所述第一存储空间中获取第二数据，并将所述第二数据存储至所述下位机中。
  3. 根据权利要求2所述的数据传输方法，其特征在于，所述数据传输方法还包括：
    在所述第一直接内存访问操作或者所述第二直接内存访问操作执行完毕后，生成执行完毕信息，并根据第二目标地址将所述执行完毕信息传递至所述主内存中的第二存储空间；
    其中，所述第二目标地址为所述第二存储空间的地址，所述第二存储空间为预先设置的用于存储所述下位机传递的执行完毕信息的存储空间。
  4. 根据权利要求3所述的数据传输方法，其特征在于，所述生成第一直接内存访问指令之前，所述数据传输方法还包括：
    接收所述上位机传递的所述第一目标地址和所述第二目标地址；
    其中，所述第一目标地址和所述第二目标地址是所述上位机在对所述第一存储空间和所述第二存储空间进行设置后发送的，所述第一存储空间和所述第二存储空间是所述上位机在对所述下位机的驱动加载完毕后设置的。
  5. 根据权利要求4所述的数据传输方法，其特征在于，所述下位机包括主控制器、控制状态适配器以及PCIe HIP元件，所述接收所述上位机传递的所述第一 目标地址和所述第二目标地址，包括：
    通过所述PCIe HIP元件接收所述上位机传递的第一bar地址写指令，并将所述第一bar地址写指令传递至所述控制状态适配器，所述第一bar地址写指令携带所述第一目标地址和所述第二目标地址；
    通过所述控制状态适配器将所述第一bar地址写指令转换为第一主控制器控制信息，并将所述第一主控制器控制信息传递至所述主控制器，所述第一主控制器控制信息携带所述第一目标地址和所述第二目标地址。
  6. 根据权利要求5所述的数据传输方法，其特征在于，所述生成第一直接内存访问指令，包括：
    通过所述主控制器生成所述第一直接内存访问指令。
  7. 根据权利要求6所述的数据传输方法，其特征在于，所述下位机还包括用户数据接口适配器、上行数据缓存和缓存监控元件；所述通过所述主控制器生成所述第一直接内存访问指令之前，所述数据传输方法还包括：
    通过所述用户数据接口适配器接收应用层产生的所述第一数据，并将所述第一数据存储至所述上行数据缓存；
    通过所述缓存监控元件对所述上行数据缓存进行监控，通过监控得到所述第一数据在所述上行数据缓存中的存储地址，将所述第一数据在所述上行数据缓存中的存储地址作为所述源地址，并将所述源地址传递至所述主控制器。
  8. 根据权利要求6所述的数据传输方法，其特征在于，所述根据所述第一直接内存访问指令执行第一直接内存访问操作，包括：
    通过所述主控制器将所述第一直接内存访问指令传递至所述控制状态适配器；
    通过所述控制状态适配器将所述第一直接内存访问指令转换为第一PCIe HIP控制指令；
    通过所述控制状态适配器将所述第一PCIe HIP控制指令传递至所述PCIe HIP元件；
    通过所述PCIe HIP元件根据所述第一PCIe HIP控制指令执行所述第一直接内存访问操作。
  9. 根据权利要求2所述的数据传输方法，其特征在于，所述下位机包括主控制器、控制状态适配器以及PCIe HIP元件，所述接收所述上位机发送的数据下行指示信息，包括：
    通过所述PCIe HIP元件接收所述上位机传递的第二bar地址写指令，并将所述第二bar地址写指令传递至所述控制状态适配器；
    通过所述控制状态适配器将所述第二bar地址写指令转换为第二主控制器控制信息，并将所述第二主控制器控制信息传递至所述主控制器。
  10. 根据权利要求9所述的数据传输方法，其特征在于，所述根据所述数据 下行指示信息的指示生成第二直接内存访问指令，包括：
    通过所述主控制器生成所述第二直接内存访问指令。
  11. 根据权利要求10所述的数据传输方法，其特征在于，所述根据所述第二直接内存访问指令执行第二直接内存访问操作，包括：
    通过所述主控制器将所述第二直接内存访问指令传递至所述控制状态适配器；
    通过所述控制状态适配器将所述第二直接内存访问指令转换为第二PCIe HIP控制指令；
    通过所述控制状态适配器将所述第二PCIe HIP控制指令传递至所述PCIe HIP元件；
    通过所述PCIe HIP元件根据所述第二PCIe HIP控制指令执行所述第二直接内存访问操作。
  12. 根据权利要求3所述的数据传输方法，其特征在于，所述下位机包括主控制器、控制状态适配器以及PCIe HIP元件，所述生成执行完毕信息，并根据第二目标地址将所述执行完毕信息传递至所述主内存中的第二存储空间，包括：
    通过所述PCIe HIP元件生成执行完毕指令，并将所述执行完毕指令传递至所述控制状态适配器；
    通过所述控制状态适配器将所述执行完毕指令转换为第三主控制器控制信息，并将所述第三主控制器控制信息传递至所述主控制器；
    通过所述主控制器根据所述第三主控制器控制信息生成中间执行完毕信息，并将所述中间执行完毕信息传递至所述控制状态适配器；
    通过所述控制状态适配器将所述中间执行完毕信息转换为所述执行完毕信息，并将所述执行完毕信息传递至所述PCIe HIP元件；
    通过所述PCIe HIP元件根据所述第二目标地址将所述执行完毕信息传递至所述第二存储空间。
  13. 一种数据传输装置，其特征在于，用于PCIe总线架构的下位机中，所述PCIe总线架构包括上位机、主内存和所述下位机，所述数据传输装置包括：
    第一生成模块，用于在向所述上位机传递第一数据时，生成第一直接内存访问指令，其中，所述第一直接内存访问指令用于指示源地址和第一目标地址，所述源地址为所述第一数据在所述下位机中的存储地址，所述第一目标地址为所述主内存中的第一存储空间的地址，所述第一存储空间为预先设置的用于存储所述上位机和所述下位机通过直接内存访问操作相互传递的数据的存储空间；
    第一执行模块，用于根据所述第一直接内存访问指令执行第一直接内存访问操作；
    其中，所述第一直接内存访问操作包括从所述源地址对应的存储空间中获取所述第一数据，并根据所述第一目标地址将所述第一数据传递至所述第一存储空 间。
  14. 一种计算机设备，其特征在于，包括存储器和处理器，所述存储器存储有计算机程序，所述计算机程序被所述处理器执行时实现如权利要求1至12任一所述的数据传输方法。
  15. 一种计算机可读存储介质，其特征在于，其上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至12任一所述的数据传输方法。
PCT/CN2020/139522 2019-12-30 2020-12-25 数据传输方法、装置、设备及存储介质 WO2021136099A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911399205.0 2019-12-30
CN201911399205.0A CN111177054B (zh) 2019-12-30 2019-12-30 数据传输方法、装置、设备及存储介质

Publications (1)

Publication Number Publication Date
WO2021136099A1 true WO2021136099A1 (zh) 2021-07-08

Family

ID=70623585

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/139522 WO2021136099A1 (zh) 2019-12-30 2020-12-25 数据传输方法、装置、设备及存储介质

Country Status (2)

Country Link
CN (1) CN111177054B (zh)
WO (1) WO2021136099A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111177054B (zh) * 2019-12-30 2021-09-03 京信网络系统股份有限公司 数据传输方法、装置、设备及存储介质
CN112765057B (zh) * 2020-12-30 2024-04-30 京信网络系统股份有限公司 数据传输方法、pcie系统、设备及存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080189720A1 (en) * 2006-10-17 2008-08-07 Moertl Daniel F Apparatus and Method for Communicating with a Network Adapter Using a Queue Data Structure and Cached Address Translations
CN102968395A (zh) * 2012-11-28 2013-03-13 中国人民解放军国防科学技术大学 用于微处理器的内存拷贝加速方法及装置
CN103885900A (zh) * 2012-12-20 2014-06-25 北京华为数字技术有限公司 数据访问处理方法、PCIe设备和用户设备
CN104246742A (zh) * 2012-01-17 2014-12-24 英特尔公司 用于远程客户端访问存储设备的命令验证的技术
CN108334470A (zh) * 2018-01-10 2018-07-27 西安万像电子科技有限公司 数据处理方法、装置和系统
CN111177054A (zh) * 2019-12-30 2020-05-19 京信通信系统（中国）有限公司 数据传输方法、装置、设备及存储介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107291629B (zh) * 2016-04-12 2020-12-25 华为技术有限公司 一种用于访问内存的方法和装置
CN108804356A (zh) * 2017-04-26 2018-11-13 上海寒武纪信息科技有限公司 数据传输装置及方法
CN109491587B (zh) * 2017-09-11 2021-03-23 华为技术有限公司 数据访问的方法及装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080189720A1 (en) * 2006-10-17 2008-08-07 Moertl Daniel F Apparatus and Method for Communicating with a Network Adapter Using a Queue Data Structure and Cached Address Translations
CN104246742A (zh) * 2012-01-17 2014-12-24 英特尔公司 用于远程客户端访问存储设备的命令验证的技术
CN102968395A (zh) * 2012-11-28 2013-03-13 中国人民解放军国防科学技术大学 用于微处理器的内存拷贝加速方法及装置
CN103885900A (zh) * 2012-12-20 2014-06-25 北京华为数字技术有限公司 数据访问处理方法、PCIe设备和用户设备
CN108334470A (zh) * 2018-01-10 2018-07-27 西安万像电子科技有限公司 数据处理方法、装置和系统
CN111177054A (zh) * 2019-12-30 2020-05-19 京信通信系统（中国）有限公司 数据传输方法、装置、设备及存储介质

Also Published As

Publication number Publication date
CN111177054A (zh) 2020-05-19
CN111177054B (zh) 2021-09-03

Similar Documents

Publication Publication Date Title
US11176068B2 (en) Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link
CN106951388B (zh) 一种基于PCIe的DMA数据传输方法及系统
WO2021136099A1 (zh) 数据传输方法、装置、设备及存储介质
CN108107827B (zh) 一种基于zynq平台软核的srio控制方法
CN108132897B (zh) 一种基于zynq平台软核的srio控制器
EP3722938B1 (en) Nof based reading control method, device and system
US10990549B2 (en) Methods and devices for extending USB 3.0—compliant communication over an extension medium
WO2016019725A1 (zh) 一种软件升级管理方法、设备、系统及计算机存储介质
US20230080588A1 (en) Mqtt protocol simulation method and simulation device
KR20200125389A (ko) 저장 장치에서 가속 커널들의 상태 모니터링 방법 및 이를 사용하는 저장 장치
WO2024113704A1 (zh) 一种pcie数据传输方法及相关装置
KR20210033889A (ko) 메시지 터널링을 위한 시스템 및 방법
CN107517167B (zh) 一种数据传输控制方法、装置及SoC芯片
US9882737B2 (en) Network system
CN103842979B (zh) 用于执行等时数据缓冲的系统和方法
US20210160320A1 (en) Data transmission and network interface controller
CN110687854B (zh) 一种pa总线控制器以及一种pa总线控制系统
US8904062B2 (en) Network control model driver
JP2022553741A (ja) サービス品質測定方法及び装置並びにユーザプレーン機能
CN107066360A (zh) 一种信息传输方法及服务器
JP2019176366A (ja) 情報処理装置、情報処理方法、及びプログラム
JP6542513B2 (ja) Ｕｓｂ転送装置、ｕｓｂ転送システムおよびｕｓｂ転送方法
US20110055421A1 (en) Information processing apparatus, method for controlling information processing apparatus, and program
CN116560826A (zh) 内存管理方法，系统以及相关装置
CN117155878A (zh) 一种基于PCIe交换机的反压控制方法及相关设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20909289

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20909289

Country of ref document: EP

Kind code of ref document: A1