WO2021134510A1 - 一种复合型双波长led芯片及其制作方法 - Google Patents

一种复合型双波长led芯片及其制作方法 Download PDF

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WO2021134510A1
WO2021134510A1 PCT/CN2019/130611 CN2019130611W WO2021134510A1 WO 2021134510 A1 WO2021134510 A1 WO 2021134510A1 CN 2019130611 W CN2019130611 W CN 2019130611W WO 2021134510 A1 WO2021134510 A1 WO 2021134510A1
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layer
gallium nitride
nitride layer
semiconductor layer
doped gallium
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PCT/CN2019/130611
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English (en)
French (fr)
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黄嘉宏
杨顺贵
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重庆康佳光电技术研究院有限公司
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Priority to CN201980003482.7A priority Critical patent/CN111149223A/zh
Priority to PCT/CN2019/130611 priority patent/WO2021134510A1/zh
Publication of WO2021134510A1 publication Critical patent/WO2021134510A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the invention relates to the technical field of miniaturized light-emitting diode self-luminous display devices, in particular to a composite dual-wavelength LED chip and a manufacturing method thereof.
  • the existing Light Emitting Diode includes several n-type contact layers, two active layers and several p-type contact layers.
  • the n-type contact layer, the active layer and the p-type contact layer are superimposed on each other
  • the two active layers are quantum wells with different optical wavelength bands
  • a p-type contact layer or an n-type contact layer is shared between the two active layers.
  • the LED device can control the luminous intensity of two quantum wells of different light wavebands by controlling the magnitude of the current and voltage applied to each electrode, and has the characteristics of simple device circuit, long life, and high photoelectric conversion efficiency.
  • there may be a driving voltage difference which results in uneven emission brightness of the two wavelengths.
  • the technical problem to be solved by the present invention is to provide a composite dual-wavelength LED chip and a manufacturing method thereof in view of the above-mentioned defects of the prior art, aiming to solve the situation that the LED device in the prior art encounters a dual-wavelength emission common electrode. At this time, there may be a difference in the driving voltage, resulting in the problem of uneven emission brightness of the two wavelengths.
  • a composite dual-wavelength LED chip including: a substrate, a first buffer layer on the first side of the substrate, a first semiconductor layer on the side of the first buffer layer away from the substrate, and The first light-emitting layer on the side of the first semiconductor layer facing away from the first buffer layer, the second semiconductor layer on the side of the first light-emitting layer facing away from the first semiconductor layer, and the second semiconductor layer on the side facing away from the first light-emitting layer
  • the second buffer layer on one side, the third semiconductor layer on the side of the second buffer layer away from the second semiconductor layer, and the second light-emitting layer on the side of the third semiconductor layer away from the second buffer layer, are located at the
  • the second light-emitting layer is a fourth semiconductor layer on the side facing away from the third semiconductor layer; the first semiconductor layer and the fourth semiconductor layer are both first-type semiconductor layers, and the second semiconductor layer and the third semiconductor layer are both The second type of semiconductor layer.
  • the substrate is a sapphire substrate.
  • the first buffer layer is a first undoped gallium nitride layer; the second buffer layer is a second undoped gallium nitride layer.
  • the first light-emitting layer is a blue light quantum well layer; the second light-emitting layer is a green light quantum well layer.
  • the first semiconductor layer is a first P-doped gallium nitride layer
  • the fourth semiconductor layer is a second P-doped gallium nitride layer
  • the second semiconductor layer is a first N-doped nitrogen A gallium sulfide layer
  • the third semiconductor layer is a second N-doped gallium nitride layer.
  • the first semiconductor layer is a first N-doped gallium nitride layer
  • the fourth semiconductor layer is a second N-doped gallium nitride layer
  • the second semiconductor layer is a first P-doped nitrogen A gallium sulfide layer
  • the third semiconductor layer is a second P-doped gallium nitride layer.
  • first P-type electrode the side of the first P-doped gallium nitride layer facing away from the substrate is provided with a first P-type electrode
  • first N-doped gallium nitride layer facing away from the substrate is provided with a first N electrode.
  • a second P-type electrode is provided on the side of the second P-doped gallium nitride layer away from the substrate
  • a second N-type electrode is provided on the side of the second N-doped gallium nitride layer away from the substrate.
  • Type electrode is provided.
  • the present invention also provides a method for manufacturing a composite dual-wavelength LED chip, which includes:
  • a third semiconductor layer is grown on the side of the second buffer layer away from the second semiconductor layer;
  • a fourth semiconductor layer is grown on the side of the second light-emitting layer away from the third semiconductor layer;
  • first semiconductor layer and the fourth semiconductor layer are both first-type semiconductor layers
  • second and third semiconductor layers are both second-type semiconductor layers
  • the manufacturing method of the composite dual-wavelength LED chip specifically includes:
  • a blue quantum well layer is grown on the side of the first P-doped gallium nitride layer away from the first undoped gallium nitride layer;
  • a first P-type electrode is formed on the first P-doped gallium nitride layer, a first N-type electrode is formed on the first N-doped gallium nitride layer, and a first P-type electrode is formed on the second P-doped gallium nitride layer.
  • a second P-type electrode is formed on the gallium layer, and a second N-type electrode is formed on the second N-doped gallium nitride layer.
  • the manufacturing method of the composite dual-wavelength LED chip specifically includes:
  • a first P-type electrode is formed on the first P-doped gallium nitride layer, a first N-type electrode is formed on the first N-doped gallium nitride layer, and a first P-type electrode is formed on the second P-doped gallium nitride layer.
  • a second P-type electrode is formed on the gallium layer, and a second N-type electrode is formed on the second N-doped gallium nitride layer.
  • a composite dual-wavelength LED chip and a manufacturing method thereof provided by the present invention include: a substrate, a first buffer layer located on a first side of the substrate, and a first buffer layer located on a side of the first buffer layer away from the substrate
  • the first semiconductor layer, the first light-emitting layer located on the side of the first semiconductor layer away from the first buffer layer, the second semiconductor layer located on the side of the first light-emitting layer away from the first semiconductor layer, is located at the second semiconductor layer
  • the second light-emitting layer is a fourth semiconductor layer located on the side of the second light-emitting layer away from the third semiconductor layer; the first semiconductor layer and the fourth semiconductor layer are both first-type semiconductor layers, and the second semiconductor layer Both and the third semiconductor layer are the second type semiconductor layer.
  • the present invention does not require a common electrode, so that the light-emitting layers can be controlled independently, and mixed light emission can be realized; there will be no difference in driving voltage, and therefore, the emission of two wavelengths will not be caused.
  • the brightness is uneven.
  • Fig. 1 is a schematic structural diagram of a preferred embodiment of a composite dual-wavelength LED chip in the present invention.
  • Fig. 2 is a schematic structural diagram of another preferred embodiment of the composite dual-wavelength LED chip of the present invention.
  • Fig. 3 is a schematic structural view of the first embodiment of the electrode used in the composite dual-wavelength LED chip of the present invention.
  • Fig. 4 is a schematic structural diagram of a second embodiment of electrodes used in the composite dual-wavelength LED chip of the present invention.
  • Fig. 5 is a schematic structural view of a third embodiment of electrodes used in the composite dual-wavelength LED chip of the present invention.
  • Fig. 6 is a flowchart of a preferred embodiment of a method for manufacturing a composite dual-wavelength LED chip in the present invention.
  • Mini/Micro LED displays have good stability, longevity, and operating temperature advantages. At the same time, they inherit the advantages of LED low power consumption, color saturation, fast response speed, and strong contrast, and have great application prospects.
  • the present invention uses an epitaxial structure to grow dual MQWs to emit dual wavelengths of blue and green light, and adopts a PNP design in the chip design, so that blue and green light can be independently controlled or mixed to emit light.
  • a composite dual-wavelength LED chip provided by the present invention includes: a substrate 10, a first buffer layer 20 located on a first side of the substrate 10, and a first buffer layer 20 located away from the first buffer layer 20
  • the first semiconductor layer 30 on the side of the substrate 10, the first light-emitting layer 40 on the side of the first semiconductor layer 30 away from the first buffer layer 20, and the first light-emitting layer 40 on the side away from the first semiconductor layer 30
  • the semiconductor layer 70 is the second light emitting layer 80 on the side of the third semiconductor layer 70 away from the second buffer layer 60, and the fourth semiconductor layer 90 on the side of the second light emitting layer 80 away from the third semiconductor layer 70.
  • the composite dual-wavelength LED chip includes: a substrate 10, a first buffer layer 20, a second buffer layer 60, a first semiconductor layer 30, a second semiconductor layer 50, a third semiconductor layer 70, and a fourth semiconductor layer 90.
  • a total of 9 layers of the first light-emitting layer 40 and the second light-emitting layer 80, and in accordance with the substrate 10, the first buffer layer 20, the first semiconductor layer 30, the first light-emitting layer 40, the second semiconductor layer 50, the second The buffer layer 60, the third semiconductor layer 70, the second light emitting layer 80, and the fourth semiconductor layer 90 are arranged in this order.
  • the first semiconductor layer 30 and the fourth semiconductor layer 90 are both first type semiconductor layers
  • the second semiconductor layer 50 and the third semiconductor layer 70 are both second type semiconductor layers.
  • the first buffer layer 20 is located on the substrate 10
  • the first semiconductor layer 30 is located on the first buffer layer 20
  • the first light-emitting layer 40 is located on the first semiconductor layer 30
  • the second semiconductor layer 50 is located on the first light-emitting layer 40
  • the second buffer layer 60 is located on the second semiconductor layer 50
  • the third semiconductor layer 70 is located on the second buffer layer 60
  • the second light-emitting layer 80 is located on the third semiconductor layer 70
  • the fourth semiconductor layer 90 is located on the second light-emitting layer 80.
  • the first semiconductor layer 30 and the fourth semiconductor layer 90 belong to the same type of semiconductor layer
  • the second semiconductor layer 50 and the third semiconductor layer 70 belong to the same type of semiconductor layer.
  • the present invention does not require a common electrode, so that the light-emitting layers can be controlled independently, and mixed light emission can be realized; there will be no difference in driving voltage, and therefore, the emission of two wavelengths will not be caused.
  • the brightness is uneven.
  • the substrate is a sapphire substrate.
  • the epitaxial layers of GaN-based materials and devices are mainly grown on sapphire substrates; sapphire substrates have many advantages: firstly, the production technology of sapphire substrates is mature and the device quality is good; secondly, sapphire has good stability and can be used In the process of high temperature growth; finally, sapphire has high mechanical strength and is easy to handle and clean.
  • the first buffer layer is a first undoped gallium nitride layer; the second buffer layer is a second undoped gallium nitride layer.
  • the first light-emitting layer is a blue light quantum well layer (MQW for blue layer); the second light-emitting layer is a green light quantum well layer (MQW for green layer).
  • the blue light quantum well layer is a multi-quantum well in the blue light band, and the green light quantum well layer is a multi-quantum well in the green light band.
  • the first type semiconductor layer is a P-doped gallium nitride layer; the second type semiconductor layer is an N-doped gallium nitride layer. Further, the first semiconductor layer is a first P-doped gallium nitride layer, the fourth semiconductor layer is a second P-doped gallium nitride layer; the second semiconductor layer is a first N-doped nitrogen A gallium sulfide layer, and the third semiconductor layer is a second N-doped gallium nitride layer. Specifically, in this embodiment, referring to FIG.
  • the composite dual-wavelength LED chips are sequentially arranged in the following order: sapphire substrate 11, first undoped gallium nitride layer 21, first P-doped nitrogen
  • the gallium oxide layer 31 the blue light quantum well layer 41, the first N-doped gallium nitride layer 51, the second undoped gallium nitride layer 61, the second N-doped gallium nitride layer 71, the green light quantum well layer 81,
  • the second P-doped gallium nitride layer 91 is a P-type doped GaN film
  • the N-doped gallium nitride layer is an N-type doped GaN film.
  • the first P-type electrode 101 is provided on the side of the first P-doped gallium nitride layer 31 facing away from the substrate, and the first N-doped gallium nitride layer 51 is facing away from the substrate.
  • a first N-type electrode 102 is provided on one side of the bottom, a second P-type electrode 104 is provided on the side of the second P-doped gallium nitride layer 91 away from the substrate, and the second N-doped gallium nitride
  • a second N-type electrode 103 is provided on the side of the layer 71 facing away from the substrate.
  • a first P-type electrode 101 (first P-type electrode 101) is formed on the first P-doped gallium nitride layer 31 through a chip process flow, including a series of processes such as glue coating, exposure, development, and etching.
  • PAD which is a green light P-type electrode
  • a first N-type electrode 102 (first N-PAD) is made on the first N-doped gallium nitride layer 51, which is a green light N-type electrode
  • the second N-doped gallium nitride layer 71 is provided with a second N-type electrode 103 (second N-PAD), which is a blue N-type electrode
  • a second N-type electrode 103 (second N-PAD) is provided on the second P-doped gallium nitride layer 91.
  • the two P-type electrodes 104 (the second P-PAD), which are blue P-type electrodes, form the final chip.
  • the first type semiconductor layer is an N-doped gallium nitride layer; the second type semiconductor layer is a P-doped gallium nitride layer. Further, the first semiconductor layer is a first N-doped gallium nitride layer, the fourth semiconductor layer is a second N-doped gallium nitride layer; the second semiconductor layer is a first P-doped nitrogen A gallium sulfide layer, and the third semiconductor layer is a second P-doped gallium nitride layer.
  • the composite dual-wavelength LED chips are sequentially arranged in the following order: a sapphire substrate, a first undoped gallium nitride layer, a first N-doped gallium nitride layer, a blue quantum well Layer, a first P-doped gallium nitride layer, a second undoped gallium nitride layer, a second P-doped gallium nitride layer, a green light quantum well layer, and a second N-doped gallium nitride layer.
  • the P-doped gallium nitride layer is a P-type doped GaN film
  • the N-doped gallium nitride layer is an N-type doped GaN film.
  • first P-type electrode the side of the first P-doped gallium nitride layer facing away from the substrate is provided with a first P-type electrode
  • first N-doped gallium nitride layer facing away from the substrate is provided with a first N electrode.
  • a second P-type electrode is provided on the side of the second P-doped gallium nitride layer away from the substrate
  • a second N-type electrode is provided on the side of the second N-doped gallium nitride layer away from the substrate.
  • Type electrode is provided.
  • the present invention uses a chip process flow, including a series of processes such as glue coating, exposure, development, and etching, to form a first N-type electrode (first N-PAD) on the first N-doped gallium nitride layer , which is the green light N-type electrode; the first P-type electrode (first P-PAD) is made on the first P-doped gallium nitride layer, which is the green light P-type electrode; in the second P-doped gallium nitride layer A second P-type electrode (second P-PAD) is provided on the hetero gallium nitride layer, which is a blue P-type electrode; a second N-type electrode (second P-PAD) is made on the second N-doped gallium nitride layer N-PAD), which is the blue N-type electrode, which forms the final chip.
  • first N-PAD first N-type electrode
  • first P-PAD is made on the first P-doped gallium n
  • the first P-type electrode 101, the second P-type electrode 104, the first N-type electrode 102, and the second N-type electrode 103 They are located at the four corners of the LED chip.
  • the four electrodes are set to be on the same level; of course, they can also be set to not be on the same level according to the requirements of the carrier board.
  • the electrode is in the shape of a cylinder, as shown in Figure 3; or in the shape of a cube, as shown in Figure 4; or in the shape of a rectangular parallelepiped, as shown in Figure 5.
  • the present invention also provides a method for manufacturing a composite dual-wavelength LED chip, including:
  • first semiconductor layer and the fourth semiconductor layer are both first-type semiconductor layers
  • second and third semiconductor layers are both second-type semiconductor layers
  • the first embodiment is specifically as follows:
  • a blue quantum well layer is grown on the side of the first P-doped gallium nitride layer away from the first undoped gallium nitride layer;
  • a first P-type electrode is formed on the first P-doped gallium nitride layer, a first N-type electrode is formed on the first N-doped gallium nitride layer, and a first P-type electrode is formed on the second P-doped gallium nitride layer.
  • a second P-type electrode is formed on the gallium layer, and a second N-type electrode is formed on the second N-doped gallium nitride layer.
  • the second embodiment is specifically:
  • a first P-type electrode is formed on the first P-doped gallium nitride layer, a first N-type electrode is formed on the first N-doped gallium nitride layer, and a first P-type electrode is formed on the second P-doped gallium nitride layer.
  • a second P-type electrode is formed on the gallium layer, and a second N-type electrode is formed on the second N-doped gallium nitride layer.
  • a composite dual-wavelength LED chip and a manufacturing method thereof disclosed in the present invention include: a substrate, a first buffer layer located on the first side of the substrate, and a first buffer layer located away from the substrate.
  • the first semiconductor layer on the bottom side, the first light-emitting layer on the side of the first semiconductor layer away from the first buffer layer, and the second semiconductor layer on the side of the first light-emitting layer away from the first semiconductor layer are located The second buffer layer on the side of the second semiconductor layer facing away from the first light-emitting layer, the third semiconductor layer on the side of the second buffer layer facing away from the second semiconductor layer, and the third semiconductor layer on the side facing away from the second buffer layer.
  • the second light-emitting layer on the side of the second light-emitting layer is located on the fourth semiconductor layer on the side of the second light-emitting layer away from the third semiconductor layer; the first semiconductor layer and the fourth semiconductor layer are both first-type semiconductor layers, Both the second semiconductor layer and the third semiconductor layer are second-type semiconductor layers.

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Abstract

一种复合型双波长LED芯片及其制作方法，包括：依次设置的衬底（10），第一缓冲层（20），第一半导体层（30），第一发光层（40），第二半导体层（50），第二缓冲层（60），第三半导体层（70），第二发光层（80），第四半导体层（90）；所述第一半导体层（30）和第四半导体层（90）均为第一类型半导体层，所述第二半导体层（50）和第三半导体层（70）均为第二类型半导体层。通过设置两个发光层和四个半导体层，不需要共用电极，使得发光层可以独立被控制，也可以实现混合发光；不会存在驱动电压差，因此，不会导致两种波长的发射亮度不均匀。

Description

一种复合型双波长LED芯片及其制作方法 技术领域
本发明涉及微型化发光二级管自发光显示装置技术领域，尤其涉及的是一种复合型双波长LED芯片及其制作方法。
背景技术
现有的发光二极管(Light Emitting Diode，LED)，包括若干个n型接触层、两个有源层和若干个p型接触层，n型接触层、有源层和p型接触层为相互叠加结构，两个有源层为不同光波段的量子阱，且两个有源层之间共用一p型接触层或一n型接触层。该LED器件可以通过控制各个电极所加的电流、电压的大小，控制两种不同光波段的量子阱的发光强度，且具有器件电路简单，寿命长，光电转化效率高的特点。然而，当该LED器件遇到双波长发射共用电极的情况时，可能存在驱动电压差，从而导致两种波长的发射亮度不均匀。
因此，现有技术存在缺陷，有待改进与发展。
发明内容
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种复合型双波长LED芯片及其制作方法，旨在解决现有技术中的LED器件遇到双波长发射共用电极的情况时，可能存在驱动电压差，从而导致两种波长的发射亮度不均匀的问题。
本发明解决技术问题所采用的技术方案如下：
一种复合型双波长LED芯片，其中，包括：衬底，位于所述衬底第一侧的第一缓冲层，位于所述第一缓冲层背离衬底一侧的第一半导体层，位于所述第一半导体层背离第一缓冲层一侧的第一发光层，位于所述第一发光层背离第一半导体层一侧的第二半导体层，位于所述第二半导体层背离第一发光层一侧的第二缓冲层，位于所述第二缓冲层背离第二半导体层一侧的第三半导体层，位于所述第三半导体层背离第二缓冲层一侧的第二发光层，位于所述第二发光层背离第三半导体层一侧的第四半导体层；所述第一半导体层和第四半导体层均为第一类型半 导体层，所述第二半导体层和第三半导体层均为第二类型半导体层。
进一步地，所述衬底为蓝宝石衬底。
进一步地，所述第一缓冲层为第一未掺杂氮化镓层；所述第二缓冲层为第二未掺杂氮化镓层。
进一步地，所述第一发光层为蓝光量子阱层；所述第二发光层为绿光量子阱层。
进一步地，所述第一半导体层为第一P掺杂氮化镓层，所述第四半导体层为第二P掺杂氮化镓层；所述第二半导体层为第一N掺杂氮化镓层，所述第三半导体层为第二N掺杂氮化镓层。
进一步地，所述第一半导体层为第一N掺杂氮化镓层，所述第四半导体层为第二N掺杂氮化镓层；所述第二半导体层为第一P掺杂氮化镓层，所述第三半导体层为第二P掺杂氮化镓层。
进一步地，所述第一P掺杂氮化镓层背离衬底的一侧设置有第一P型电极，所述第一N掺杂氮化镓层背离衬底的一侧设置有第一N型电极，所述第二P掺杂氮化镓层背离衬底的一侧设置有第二P型电极，所述第二N掺杂氮化镓层背离衬底的一侧设置有第二N型电极。
本发明还提供了一种复合型双波长LED芯片的制作方法，其中，包括：
在衬底上表面生长出第一缓冲层；
在所述第一缓冲层背离衬底的一侧生长出第一半导体层；
在所述第一半导体层背离第一缓冲层一侧生长出第一发光层；
在所述第一发光层背离第一半导体层一侧生长出第二半导体层；
在所述第二半导体层背离第一发光层一侧生长出第二缓冲层；
在所述第二缓冲层背离第二半导体层一侧生长出第三半导体层；
在所述第三半导体层背离第二缓冲层一侧生长出第二发光层；
在所述第二发光层背离第三半导体层一侧生长出第四半导体层；
其中，所述第一半导体层和第四半导体层均为第一类型半导体层，所述第二半导体层和第三半导体层均为第二类型半导体层。
进一步地，所述复合型双波长LED芯片的制作方法具体包括：
在蓝宝石衬底上表面生长出第一未掺杂氮化镓层；
在所述第一未掺杂氮化镓层背离蓝宝石衬底的一侧生长出第一P掺杂氮化镓层；
在所述第一P掺杂氮化镓层背离第一未掺杂氮化镓层一侧生长出蓝光量子阱层；
在所述蓝光量子阱层背离第一P掺杂氮化镓层一侧生长出第一N掺杂氮化镓层；
在所述第一N掺杂氮化镓层背离绿光量子阱层一侧生长出第二未掺杂氮化镓层；
在所述第二未掺杂氮化镓层背离第一N掺杂氮化镓层一侧生长出第二N掺杂氮化镓层；
在所述第二N掺杂氮化镓层背离第二未掺杂氮化镓层一侧生长出绿光量子阱层；
在所述绿光量子阱层背离第二N掺杂氮化镓层一侧生长出第二P掺杂氮化镓层；
在所述第一P掺杂氮化镓层上形成第一P型电极，在所述第一N掺杂氮化镓层上形成第一N型电极，在所述第二P掺杂氮化镓层上形成第二P型电极，在所述第二N掺杂氮化镓层上形成第二N型电极。
进一步地，所述复合型双波长LED芯片的制作方法具体包括：
在蓝宝石衬底上表面生长出第一未掺杂氮化镓层；
在所述第一未掺杂氮化镓层背离蓝宝石衬底的一侧生长出第一N掺杂氮化镓层；
在所述第一N掺杂氮化镓层背离第一未掺杂氮化镓层一侧生长出蓝光量子阱层；
在所述蓝光量子阱层背离第一N掺杂氮化镓层一侧生长出第一P掺杂氮化镓层；
在所述第一P掺杂氮化镓层背离绿光量子阱层一侧生长出第二未掺杂氮化镓层；
在所述第二未掺杂氮化镓层背离第一P掺杂氮化镓层一侧生长出第二P掺杂氮化镓层；
在所述第二P掺杂氮化镓层背离第二未掺杂氮化镓层一侧生长出绿光量子阱层；
在所述绿光量子阱层背离第二P掺杂氮化镓层一侧生长出第二N掺杂氮化镓层；
在所述第一P掺杂氮化镓层上形成第一P型电极，在所述第一N掺杂氮化镓层上形成第一N型电极，在所述第二P掺杂氮化镓层上形成第二P型电极，在所述第二N掺杂氮化镓层上形成第二N型电极。
本发明所提供的一种复合型双波长LED芯片及其制作方法，包括：衬底，位于所述衬底第一侧的第一缓冲层，位于所述第一缓冲层背离衬底一侧的第一半导体层，位于所述第一半导体层背离第一缓冲层一侧的第一发光层，位于所述第一发光层背离第一半导体层一侧的第二半导体层，位于所述第二半导体层背离第一发光层一侧的第二缓冲层，位于所述第二缓冲层背离第二半导体层一侧的第三半导体层，位于所述第三半导体层背离第二缓冲层一侧的第二发光层，位于所述第二发光层背离第三半导体层一侧的第四半导体层；所述第一半导体层和第四半导体层均为第一类型半导体层，所述第二半导体层和第三半导体层均为第二类型半导体层。本发明通过设置两个发光层和四个半导体层，不需要共用电极，使得发光层可以独立被控制，也可以实现混合发光；不会存在驱动电压差，因此，不会导致两种波长的发射亮度不均匀。
附图说明
图1是本发明中复合型双波长LED芯片的较佳实施例的结构示意图。
图2是本发明中复合型双波长LED芯片的另一较佳实施例的结构示意图。
图3是本发明中复合型双波长LED芯片中所用电极的第一实施例的结构示意图。
图4是本发明中复合型双波长LED芯片中所用电极的第二实施例的结构示意图。
图5是本发明中复合型双波长LED芯片中所用电极的第三实施例的结构示意图。
图6是本发明中复合型双波长LED芯片的制作方法较佳实施例的流程图。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
Mini/Micro LED显示器具有良好的稳定性、寿命，以及运行温度上的优势，同时也继承了LED低功耗、色彩饱和度、反应速度快、对比度强等优点，具有极大的应用前景。
由于u-LED三原色激发成白光有别于传统的蓝光+YAG荧光粉，且如果像素要提高，chip size越小越有利于像素的提升与空间的利用。因此，本发明利用一种磊晶结构生长双MQW发出蓝光和绿光双波长，并在chip设计上采用PNP的设计，使得蓝光和绿光可以独立被控制或是混合发光。
请参阅图1，本发明所提供的一种复合型双波长LED芯片，包括：衬底10，位于所述衬底10第一侧的第一缓冲层20，位于所述第一缓冲层20背离衬底10一侧的第一半导体层30，位于所述第一半导体层30背离第一缓冲层20一侧的第一发光层40，位于所述第一发光层40背离第一半导体层30一侧的第二半导体层50，位于所述第二半导体层50背离第一发光层40一侧的第二缓冲层60，位于所述第二缓冲层60背离第二半导体层50一侧的第三半导体层70，位于所述第三半导体层70背离第二缓冲层60一侧的第二发光层80，位于所述第二发光层80背离第三半导体层70一侧的第四半导体层90。即，所述复合型双波长LED芯片包括：衬底10，第一缓冲层20、第二缓冲层60、第一半导体层30、第二半导体层50、第三半导体层70、第四半导体层90、第一发光层40以及第二发光层80共9层，并且，按照衬底10、第一缓冲层20、第一半导体层30、第一发光层40、第二半导体层50、第二缓冲层60、第三半导体层70、第二发光层80、第四半导体层90的顺序依次设置。其中，所述第一半导体层30和第四半导体层90均为第一类型半导体层，所述第二半导体层50和第三半导体层70均为第二类型半导体层。
也就是说，所述第一缓冲层20位于衬底10上，所述第一半导体层30位于所述第一缓冲层20上，所述第一发光层40位于所述第一半导体层30上，所述第二半导体层50位于所述第一发光层40上，所述第二缓冲层60位于所述第二 半导体层50上，所述第三半导体层70位于所述第二缓冲层60上，所述第二发光层80位于所述第三半导体层70上，所述第四半导体层90位于所述第二发光层80上。所述第一半导体层30和所述第四半导体层90属于同一类型的半导体层，所述第二半导体层50和所述第三半导体层70属于同一类型的半导体层。
本发明通过设置两个发光层和四个半导体层，不需要共用电极，使得发光层可以独立被控制，也可以实现混合发光；不会存在驱动电压差，因此，不会导致两种波长的发射亮度不均匀。
在本发明较佳实施例中，所述衬底为蓝宝石衬底(sapphire)。GaN基材料和器件的外延层主要生长在蓝宝石衬底上；蓝宝石衬底有许多的优点:首先，蓝宝石衬底的生产技术成熟、器件质量较好；其次，蓝宝石的稳定性很好，能够运用在高温生长过程中；最后，蓝宝石的机械强度高，易于处理和清洗。
进一步地，所述第一缓冲层为第一未掺杂氮化镓层；所述第二缓冲层为第二未掺杂氮化镓层。
进一步地，所述第一发光层为蓝光量子阱层(MQW for blue层)；所述第二发光层为绿光量子阱层(MQW for green层)。蓝光量子阱层即为蓝光波段的多量子阱，绿光量子阱层即为绿光波段的多量子阱。
在本发明的第一具体实施例中，所述第一类型半导体层为P掺杂氮化镓层；所述第二类型半导体层为N掺杂氮化镓层。进一步地，所述第一半导体层为第一P掺杂氮化镓层，所述第四半导体层为第二P掺杂氮化镓层；所述第二半导体层为第一N掺杂氮化镓层，所述第三半导体层为第二N掺杂氮化镓层。具体的，在本实施例中，请参阅图2，所述复合型双波长LED芯片按照以下顺序依次设置：蓝宝石衬底11、第一未掺杂氮化镓层21、第一P掺杂氮化镓层31、蓝光量子阱层41、第一N掺杂氮化镓层51、第二未掺杂氮化镓层61、第二N掺杂氮化镓层71、绿光量子阱层81、第二P掺杂氮化镓层91。其中，P掺杂氮化镓层即为P型掺杂的GaN薄膜；N掺杂氮化镓层即为N型掺杂的GaN薄膜。
进一步地，请继续参阅图2，所述第一P掺杂氮化镓层31背离衬底的一侧设置有第一P型电极101，所述第一N掺杂氮化镓层51背离衬底的一侧设置有第一N型电极102，所述第二P掺杂氮化镓层91背离衬底的一侧设置有第二P型电极104，所述第二N掺杂氮化镓层71背离衬底的一侧设置有第二N型电极 103。具体的，本发明通过芯片工艺流程，包括：涂胶、曝光、显影、蚀刻等一系列工艺，在第一P掺杂氮化镓层31上做出第一P型电极101(第一P-PAD)，即为绿光的P型电极；在第一N掺杂氮化镓层51上做出第一N型电极102(第一N-PAD)，即为绿光的N型电极；在第二N掺杂氮化镓层71上设置有第二N型电极103(第二N-PAD)，即为蓝光的N型电极；在第二P掺杂氮化镓层91上做出第二P型电极104(第二P-PAD)，即为蓝光的P型电极，形成最终的芯片。
在本发明的第二具体实施例中，所述第一类型半导体层为N掺杂氮化镓层；所述第二类型半导体层为P掺杂氮化镓层。进一步地，所述第一半导体层为第一N掺杂氮化镓层，所述第四半导体层为第二N掺杂氮化镓层；所述第二半导体层为第一P掺杂氮化镓层，所述第三半导体层为第二P掺杂氮化镓层。具体的，在本实施例中，所述复合型双波长LED芯片按照以下顺序依次设置：蓝宝石衬底、第一未掺杂氮化镓层、第一N掺杂氮化镓层、蓝光量子阱层、第一P掺杂氮化镓层、第二未掺杂氮化镓层、第二P掺杂氮化镓层、绿光量子阱层、第二N掺杂氮化镓层。其中，P掺杂氮化镓层即为P型掺杂的GaN薄膜；N掺杂氮化镓层即为N型掺杂的GaN薄膜。
进一步地，所述第一P掺杂氮化镓层背离衬底的一侧设置有第一P型电极，所述第一N掺杂氮化镓层背离衬底的一侧设置有第一N型电极，所述第二P掺杂氮化镓层背离衬底的一侧设置有第二P型电极，所述第二N掺杂氮化镓层背离衬底的一侧设置有第二N型电极。具体的，本发明通过芯片工艺流程，包括：涂胶、曝光、显影、蚀刻等一系列工艺，在第一N掺杂氮化镓层上做出第一N型电极(第一N-PAD)，即为绿光的N型电极；在第一P掺杂氮化镓层上做出第一P型电极(第一P-PAD)，即为绿光的P型电极；在第二P掺杂氮化镓层上设置有第二P型电极(第二P-PAD)，即为蓝光的P型电极；在第二N掺杂氮化镓层上做出第二N型电极(第二N-PAD)，即为蓝光的N型电极，形成最终的芯片。
在本发明进一步较佳实施例中，请参阅图3、图4和图5，所述第一P型电极101、第二P型电极104、第一N型电极102和第二N型电极103分别位于LED芯片的四角。优选的，将4个电极设置为处于同一水平面上；当然的，也 可以按照载板需求，设置为不处于同一水平面上。其中，电极呈圆柱体型，如图3所示；或者呈正方体型，如图4所示；或者呈长方体型，如图5所示。
请参阅图6，本发明还提供了一种复合型双波长LED芯片的制作方法，包括：
S100、在衬底上表面生长出第一缓冲层；
S200、在所述第一缓冲层背离衬底的一侧生长出第一半导体层；
S300、在所述第一半导体层背离第一缓冲层一侧生长出第一发光层；
S400、在所述第一发光层背离第一半导体层一侧生长出第二半导体层；
S500、在所述第二半导体层背离第一发光层一侧生长出第二缓冲层；
S600、在所述第二缓冲层背离第二半导体层一侧生长出第三半导体层；
S700、在所述第三半导体层背离第二缓冲层一侧生长出第二发光层；
S800、在所述第二发光层背离第三半导体层一侧生长出第四半导体层；
其中，所述第一半导体层和第四半导体层均为第一类型半导体层，所述第二半导体层和第三半导体层均为第二类型半导体层。
本发明复合型双波长LED芯片的制作方法中，第一个实施例具体为：
在蓝宝石衬底上表面生长出第一未掺杂氮化镓层；
在所述第一未掺杂氮化镓层背离蓝宝石衬底的一侧生长出第一P掺杂氮化镓层；
在所述第一P掺杂氮化镓层背离第一未掺杂氮化镓层一侧生长出蓝光量子阱层；
在所述蓝光量子阱层背离第一P掺杂氮化镓层一侧生长出第一N掺杂氮化镓层；
在所述第一N掺杂氮化镓层背离绿光量子阱层一侧生长出第二未掺杂氮化镓层；
在所述第二未掺杂氮化镓层背离第一N掺杂氮化镓层一侧生长出第二N掺杂氮化镓层；
在所述第二N掺杂氮化镓层背离第二未掺杂氮化镓层一侧生长出绿光量子阱层；
在所述绿光量子阱层背离第二N掺杂氮化镓层一侧生长出第二P掺杂氮化 镓层；
在所述第一P掺杂氮化镓层上形成第一P型电极，在所述第一N掺杂氮化镓层上形成第一N型电极，在所述第二P掺杂氮化镓层上形成第二P型电极，在所述第二N掺杂氮化镓层上形成第二N型电极。
本发明复合型双波长LED芯片的制作方法中，第二个实施例具体为：
在蓝宝石衬底上表面生长出第一未掺杂氮化镓层；
在所述第一未掺杂氮化镓层背离蓝宝石衬底的一侧生长出第一N掺杂氮化镓层；
在所述第一N掺杂氮化镓层背离第一未掺杂氮化镓层一侧生长出蓝光量子阱层；
在所述蓝光量子阱层背离第一N掺杂氮化镓层一侧生长出第一P掺杂氮化镓层；
在所述第一P掺杂氮化镓层背离绿光量子阱层一侧生长出第二未掺杂氮化镓层；
在所述第二未掺杂氮化镓层背离第一P掺杂氮化镓层一侧生长出第二P掺杂氮化镓层；
在所述第二P掺杂氮化镓层背离第二未掺杂氮化镓层一侧生长出绿光量子阱层；
在所述绿光量子阱层背离第二P掺杂氮化镓层一侧生长出第二N掺杂氮化镓层；
在所述第一P掺杂氮化镓层上形成第一P型电极，在所述第一N掺杂氮化镓层上形成第一N型电极，在所述第二P掺杂氮化镓层上形成第二P型电极，在所述第二N掺杂氮化镓层上形成第二N型电极。
综上所述，本发明公开的一种复合型双波长LED芯片及其制作方法，包括：衬底，位于所述衬底第一侧的第一缓冲层，位于所述第一缓冲层背离衬底一侧的第一半导体层，位于所述第一半导体层背离第一缓冲层一侧的第一发光层，位于所述第一发光层背离第一半导体层一侧的第二半导体层，位于所述第二半导体层背离第一发光层一侧的第二缓冲层，位于所述第二缓冲层背离第二半导体层一侧的第三半导体层，位于所述第三半导体层背离第二缓冲层一侧的第二发光层，位 于所述第二发光层背离第三半导体层一侧的第四半导体层；所述第一半导体层和第四半导体层均为第一类型半导体层，所述第二半导体层和第三半导体层均为第二类型半导体层。本发明通过设置两个发光层和四个半导体层，不需要共用电极，使得发光层可以独立被控制，也可以实现混合发光；不会存在驱动电压差，因此，不会导致两种波长的发射亮度不均匀。
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (10)

  1. 一种复合型双波长LED芯片，其特征在于，包括：衬底，位于所述衬底第一侧的第一缓冲层，位于所述第一缓冲层背离衬底一侧的第一半导体层，位于所述第一半导体层背离第一缓冲层一侧的第一发光层，位于所述第一发光层背离第一半导体层一侧的第二半导体层，位于所述第二半导体层背离第一发光层一侧的第二缓冲层，位于所述第二缓冲层背离第二半导体层一侧的第三半导体层，位于所述第三半导体层背离第二缓冲层一侧的第二发光层，位于所述第二发光层背离第三半导体层一侧的第四半导体层；所述第一半导体层和第四半导体层均为第一类型半导体层，所述第二半导体层和第三半导体层均为第二类型半导体层。
  2. 根据权利要求1所述的复合型双波长LED芯片，其特征在于，所述衬底为蓝宝石衬底。
  3. 根据权利要求1所述的复合型双波长LED芯片，其特征在于，所述第一缓冲层为第一未掺杂氮化镓层；所述第二缓冲层为第二未掺杂氮化镓层。
  4. 根据权利要求1所述的复合型双波长LED芯片，其特征在于，所述第一发光层为蓝光量子阱层；所述第二发光层为绿光量子阱层。
  5. 根据权利要求4所述的复合型双波长LED芯片，其特征在于，所述第一半导体层为第一P掺杂氮化镓层，所述第四半导体层为第二P掺杂氮化镓层；所述第二半导体层为第一N掺杂氮化镓层，所述第三半导体层为第二N掺杂氮化镓层。
  6. 根据权利要求4所述的复合型双波长LED芯片，其特征在于，所述第一半导体层为第一N掺杂氮化镓层，所述第四半导体层为第二N掺杂氮化镓层；所述第二半导体层为第一P掺杂氮化镓层，所述第三半导体层为第二P掺杂氮化镓层。
  7. 根据权利要求5或6所述的复合型双波长LED芯片，其特征在于，所述第一P掺杂氮化镓层背离衬底的一侧设置有第一P型电极，所述第一N掺杂氮化镓层背离衬底的一侧设置有第一N型电极，所述第二P掺杂氮化镓层背离衬底的一侧设置有第二P型电极，所述第二N掺杂氮化镓层背离衬底的一侧设置有第二N型电极。
  8. 一种复合型双波长LED芯片的制作方法，其特征在于，包括：
    在衬底上表面生长出第一缓冲层；
    在所述第一缓冲层背离衬底的一侧生长出第一半导体层；
    在所述第一半导体层背离第一缓冲层一侧生长出第一发光层；
    在所述第一发光层背离第一半导体层一侧生长出第二半导体层；
    在所述第二半导体层背离第一发光层一侧生长出第二缓冲层；
    在所述第二缓冲层背离第二半导体层一侧生长出第三半导体层；
    在所述第三半导体层背离第二缓冲层一侧生长出第二发光层；
    在所述第二发光层背离第三半导体层一侧生长出第四半导体层；
    其中，所述第一半导体层和第四半导体层均为第一类型半导体层，所述第二半导体层和第三半导体层均为第二类型半导体层。
  9. 根据权利要求8所述的复合型双波长LED芯片的制作方法，其特征在于，所述复合型双波长LED芯片的制作方法具体包括：
    在蓝宝石衬底上表面生长出第一未掺杂氮化镓层；
    在所述第一未掺杂氮化镓层背离蓝宝石衬底的一侧生长出第一P掺杂氮化镓层；
    在所述第一P掺杂氮化镓层背离第一未掺杂氮化镓层一侧生长出蓝光量子阱层；
    在所述蓝光量子阱层背离第一P掺杂氮化镓层一侧生长出第一N掺杂氮化镓层；
    在所述第一N掺杂氮化镓层背离绿光量子阱层一侧生长出第二未掺杂氮化镓层；
    在所述第二未掺杂氮化镓层背离第一N掺杂氮化镓层一侧生长出第二N掺杂氮化镓层；
    在所述第二N掺杂氮化镓层背离第二未掺杂氮化镓层一侧生长出绿光量子阱层；
    在所述绿光量子阱层背离第二N掺杂氮化镓层一侧生长出第二P掺杂氮化镓层；
    在所述第一P掺杂氮化镓层上形成第一P型电极，在所述第一N掺杂氮化镓层上形成第一N型电极，在所述第二P掺杂氮化镓层上形成第二P型电极，在所述第二N掺杂氮化镓层上形成第二N型电极。
  10. 根据权利要求8所述的复合型双波长LED芯片的制作方法，其特征在于，所述复合型双波长LED芯片的制作方法具体包括：
    在蓝宝石衬底上表面生长出第一未掺杂氮化镓层；
    在所述第一未掺杂氮化镓层背离蓝宝石衬底的一侧生长出第一N掺杂氮化镓层；
    在所述第一N掺杂氮化镓层背离第一未掺杂氮化镓层一侧生长出蓝光量子阱层；
    在所述蓝光量子阱层背离第一N掺杂氮化镓层一侧生长出第一P掺杂氮化镓层；
    在所述第一P掺杂氮化镓层背离绿光量子阱层一侧生长出第二未掺杂氮化镓层；
    在所述第二未掺杂氮化镓层背离第一P掺杂氮化镓层一侧生长出第二P掺杂氮化镓层；
    在所述第二P掺杂氮化镓层背离第二未掺杂氮化镓层一侧生长出绿光量子阱层；
    在所述绿光量子阱层背离第二P掺杂氮化镓层一侧生长出第二N掺杂氮化镓层；
    在所述第一P掺杂氮化镓层上形成第一P型电极，在所述第一N掺杂氮化镓层上形成第一N型电极，在所述第二P掺杂氮化镓层上形成第二P型电极，在所述第二N掺杂氮化镓层上形成第二N型电极。
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