WO2021132184A1 - センサ装置 - Google Patents

センサ装置 Download PDF

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Publication number
WO2021132184A1
WO2021132184A1 PCT/JP2020/047751 JP2020047751W WO2021132184A1 WO 2021132184 A1 WO2021132184 A1 WO 2021132184A1 JP 2020047751 W JP2020047751 W JP 2020047751W WO 2021132184 A1 WO2021132184 A1 WO 2021132184A1
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Prior art keywords
pixel
sensor device
sensor
sensor element
substrate
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PCT/JP2020/047751
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English (en)
French (fr)
Japanese (ja)
Inventor
貴博 若林
健一 田口
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2021567454A priority Critical patent/JPWO2021132184A1/ja
Priority to CN202080078029.5A priority patent/CN114679913A/zh
Priority to US17/784,289 priority patent/US20220381617A1/en
Priority to EP20906812.1A priority patent/EP4084075A4/de
Publication of WO2021132184A1 publication Critical patent/WO2021132184A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14665—Imagers using a photoconductor layer
    • H01L27/14669—Infrared imagers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/06—Arrangements for eliminating effects of disturbing radiation; Arrangements for compensating changes in sensitivity
    • G01J5/061—Arrangements for eliminating effects of disturbing radiation; Arrangements for compensating changes in sensitivity by controlling the temperature of the apparatus or parts thereof, e.g. using cooling means or thermostats
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/024—Arrangements for cooling, heating, ventilating or temperature compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/52—Elements optimising image sensor operation, e.g. for electromagnetic interference [EMI] protection or temperature control by heat transfer or cooling elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J2005/0077—Imaging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/06—Arrangements for eliminating effects of disturbing radiation; Arrangements for compensating changes in sensitivity
    • G01J5/061—Arrangements for eliminating effects of disturbing radiation; Arrangements for compensating changes in sensitivity by controlling the temperature of the apparatus or parts thereof, e.g. using cooling means or thermostats
    • G01J2005/062—Peltier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/13—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the heat-exchanging means at the junction

Definitions

  • This disclosure relates to a sensor device.
  • An airtight sealing package containing a Perche element is known as a means for cooling a sensor element such as a solid-state image sensor (see, for example, Patent Document 1).
  • a sensor device includes a Perche element, a sensor element thermally connected to the cooling surface of the Perche element, and a window member provided facing the light receiving surface of the sensor element and made of borosilicate glass. Be prepared.
  • FIG. 1 It is a bottom view which shows the structural example of the sensor device which concerns on modification 3 of embodiment of this disclosure. It is a figure which shows the substrate structure of the sensor element of another example which concerns on embodiment of this disclosure. It is a figure which shows the substrate structure of the sensor element of another example which concerns on embodiment of this disclosure. It is a figure which shows the circuit structure example of the laminated substrate of the sensor element of another example which concerns on embodiment of this disclosure. It is a figure which shows the equivalent circuit of the pixel of the sensor element of another example which concerns on embodiment of this disclosure. It is a top view of the pixel array area which shows the pixel arrangement of the charge emission pixel which concerns on modification 4. FIG.
  • An airtight sealing package containing a Perche element is known as a means for cooling a sensor element such as a solid-state image sensor.
  • sapphire glass is used as a window member that transmits the detected light to the inside.
  • the sapphire glass has a wavelength region in which the absorption rate increases, the incident light is absorbed by the sapphire glass, so that there is a problem that the detection sensitivity is lowered.
  • FIG. 1 is a diagram showing a schematic configuration of a sensor element 10 according to an embodiment of the present disclosure.
  • the sensor element 10 of FIG. 1 has a pixel array region 103 in which pixels 102 are two-dimensionally arranged in a matrix on a semiconductor substrate 112 using, for example, single crystal silicon (Si) as a semiconductor, and a peripheral circuit region 161 around the pixel array region 103 ( (See FIG. 4).
  • the peripheral circuit region 161 includes a vertical drive circuit 104, a column signal processing circuit 105, a horizontal drive circuit 106, an output circuit 107, a control circuit 108, and the like.
  • the pixel 102 includes a photoelectric conversion unit made of a semiconductor thin film and a plurality of pixel transistors.
  • the plurality of pixel transistors are composed of, for example, three MOS transistors: a reset transistor, an amplification transistor, and a selection transistor.
  • the control circuit 108 receives an input clock and data for instructing an operation mode and the like, and outputs data such as internal information of the sensor element 10. That is, the control circuit 108 generates a clock signal or a control signal that serves as a reference for the operation of the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do.
  • control circuit 108 outputs the generated clock signal and control signal to the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, and the like.
  • the vertical drive circuit 104 is composed of, for example, a shift register, selects a predetermined pixel drive wiring 110, supplies a pulse for driving the pixel 102 to the selected pixel drive wiring 110, and drives the pixel 102 in units of rows. To do.
  • the vertical drive circuit 104 sequentially selectively scans each pixel 102 of the pixel array area 103 in the vertical direction in units of rows. Then, the vertical drive circuit 104 supplies the column signal processing circuit 105 with a pixel signal based on the signal charge generated according to the amount of light received by the photoelectric conversion unit of each pixel 102 through the vertical signal line 109.
  • the column signal processing circuit 105 is arranged for each column of the pixel 102, and performs signal processing such as noise removal for each column of the signal output from the pixel 102 for one row.
  • the column signal processing circuit 105 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion for removing fixed pattern noise peculiar to pixels.
  • the horizontal drive circuit 106 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, each of the column signal processing circuits 105 is sequentially selected, and a pixel signal is output from each of the column signal processing circuits 105 as a horizontal signal line. Output to 111.
  • the output circuit 107 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 105 through the horizontal signal line 111 and outputs the signals.
  • the output circuit 107 may, for example, only buffer, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.
  • the input / output terminal 113 exchanges signals with the outside.
  • the sensor element 10 configured as described above is a CMOS image sensor called a column AD method in which a column signal processing circuit 105 that performs CDS processing and AD conversion processing is arranged for each column.
  • FIG. 2 is a diagram showing a pixel circuit of each pixel of the sensor element 10 according to the embodiment of the present disclosure.
  • Each pixel 102 has a photoelectric conversion unit 121, a capacitive element 122, a reset transistor 123, an amplification transistor 124, and a selection transistor 125.
  • the photoelectric conversion unit 121 is made of a semiconductor thin film using a compound semiconductor such as InGaAs, and generates an electric charge (signal charge) according to the amount of received light.
  • a predetermined bias electric Va is applied to the photoelectric conversion unit 121.
  • the capacitive element 122 accumulates the electric charge generated by the photoelectric conversion unit 121.
  • the capacitance element 122 can be configured to include at least one of, for example, a pn junction capacitance, a MOS capacitance, or a wiring capacitance.
  • the reset transistor 123 When the reset transistor 123 is turned on by the reset signal RST, the electric charge accumulated in the capacitive element 122 is discharged to the source (ground) to reset the potential of the capacitive element 122.
  • the amplification transistor 124 outputs a pixel signal corresponding to the storage potential of the capacitive element 122. That is, the amplification transistor 124 constitutes a load MOS (not shown) as a constant current source connected via the vertical signal line 109 and a source follower circuit.
  • a pixel signal indicating the level corresponding to the electric charge stored in the capacitive element 122 is output from the amplification transistor 124 to the column signal processing circuit 105 (see FIG. 1) via the selection transistor 125.
  • the selection transistor 125 is turned on when the pixel 102 is selected by the selection signal SEL, and outputs the pixel signal of the pixel 102 to the column signal processing circuit 105 via the vertical signal line 109.
  • Each signal line through which the transfer signal TRX, the selection signal SEL, and the reset signal RST are transmitted corresponds to the pixel drive wiring 110 of FIG.
  • FIG. 3 is a cross-sectional view showing the structure of the pixel 102 according to the embodiment of the present disclosure. Although details will be described later, in FIG. 3, each pixel 102 in the pixel array region 103 is divided into a normal pixel 102A and a charge emission pixel 102B depending on the difference in control of the reset transistor 123.
  • the charge emission pixel 102B is arranged on the outermost side of the pixel array region 103 (see FIG. 1).
  • the readout circuit of the capacitive element 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 of each pixel 102 described with reference to FIG. 2 is formed for each pixel 102 on the semiconductor substrate 112 made of a single crystal material such as single crystal silicon. Has been done.
  • the reference numerals of the capacitive element 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 formed on the semiconductor substrate 112 are omitted.
  • An N-type semiconductor thin film 141 serving as a photoelectric conversion unit 121 is formed on the entire surface of the pixel array region 103 on the upper side of the semiconductor substrate 112 on the light incident side.
  • As the N-type semiconductor thin film 141 InGaP, InAlP, InGaAs, InAlAs, and further compound semiconductors having a chalcopyrite structure are used.
  • a compound semiconductor having a chalcopyrite structure is a material that can obtain a high light absorption coefficient and high sensitivity over a wide wavelength range, and is preferably used as an N-type semiconductor thin film 141 for photoelectric conversion.
  • Such a compound semiconductor having a chalcopyrite structure is composed of elements around Group IV elements such as Cu, Al, Ga, In, S, and Se, and is composed of CuGaInS-based mixed crystals, CuAlGaInS-based mixed crystals, and CuAlGaInSse-based. Examples include mixed crystals.
  • the material of the N-type semiconductor thin film 141 in addition to the compound semiconductor described above, amorphous silicon, germanium (Ge), quantum dot photoelectric conversion film, organic photoelectric conversion film and the like can also be used. In the present disclosure, it is assumed that an InGaAs compound semiconductor is used as the N-type semiconductor thin film 141.
  • a high-concentration P-type layer 142 constituting a pixel electrode is formed for each pixel 102 on the lower side of the N-type semiconductor thin film 141 on the semiconductor substrate 112 side. Then, between the high-concentration P-type layers 142 formed for each pixel 102, an N-type layer 143 as a pixel separation region for separating each pixel 102 is formed of, for example, a compound semiconductor such as InP. ..
  • the N-type layer 143 has a role of preventing a dark current as well as a function as a pixel separation region.
  • an N-type layer 144 having a higher concentration than that of the N-type semiconductor thin film 141 is formed by using a compound semiconductor such as InP used as a pixel separation region. Has been done.
  • This high-concentration N-type layer 144 functions as a barrier layer that prevents the backflow of electric charges generated by the N-type semiconductor thin film 141.
  • compound semiconductors such as InP, InGaAs, and InAlAs can be used.
  • An antireflection film 145 is formed on the high-concentration N-type layer 144 as a barrier layer.
  • the material of the antireflection film 145 includes, for example, silicon nitride (SiN), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), and oxidation. Titanium (TiO 2 ) or the like can be used.
  • Either one of the high-concentration N-type layer 144 and the antireflection film 145 also functions as an upper upper electrode among the electrodes sandwiching the N-type semiconductor thin film 141 on the upper and lower sides, and the high-concentration N-type as the upper electrode.
  • a predetermined voltage Va is applied to the layer 144 or the antireflection film 145.
  • a color filter 146 and an on-chip lens 147 are further formed on the antireflection film 145.
  • the color filter 146 is a filter that transmits light (wavelength light) of either R (red), G (green), or B (blue), and is arranged in a so-called bayer array in the pixel array region 103, for example. ing.
  • a passivation layer 151 and an insulating layer 152 are formed under the high-concentration P-type layer 142 constituting the pixel electrode and the N-type layer 143 as the pixel separation region.
  • the connection electrodes 153A and 153B and the bump electrode 154 are formed so as to penetrate the passivation layer 151 and the insulating layer 152.
  • connection electrodes 153A and 153B and the bump electrode 154 electrically connect the high-concentration P-type layer 142 constituting the pixel electrode and the capacitance element 122 for accumulating electric charges.
  • the normal pixel 102A and the charge emission pixel 102B are configured as described above and have the same pixel structure. However, the control method of the reset transistor 123 is different between the normal pixel 102A and the charge emission pixel 102B.
  • the reset transistor 123 is turned on and off based on the reset signal RST according to the charge generation period (light receiving period) by the photoelectric conversion unit 121, the reset period of the potential of the capacitance element 122 before the start of light receiving, and the like. ..
  • the reset transistor 123 is always controlled to be ON.
  • FIG. 4 is a plan view of the pixel array region 103 showing the pixel arrangement of the charge emitting pixels 102B.
  • the pixel array region 103 is arranged inside the peripheral circuit region 161 in which the vertical drive circuit 104, the column signal processing circuit 105, and the like are formed.
  • the outermost rows and columns of the pixel array region 103 are the charge emission regions 162, and the charge emission pixels 102B are arranged therein.
  • the charge emission region 162 may be composed of a plurality of rows and a plurality of columns including at least one row and one column on the outermost side of the rectangular pixel array region 103.
  • the pixels 102 located in the outermost columns and rows of each side of the rectangular pixel array region 103 are from the processed portion interface (processed portion end face) of the photoelectric conversion unit 121 which is a compound semiconductor. Dark current is likely to be generated due to the influence.
  • the readout circuit formed on the semiconductor substrate 112 is a source follower type circuit
  • the potential difference between the pixels becomes smaller as the electric charge accumulates, so that the dark current component affects the adjacent pixels one after another due to blooming. Will affect.
  • the pixels 102 located in the outermost columns and rows of each side of the rectangular pixel array region 103 are the charge emission pixels 102B controlled so that the reset transistor 123 is always on.
  • FIG. 5 is a diagram showing a schematic cross-sectional configuration of the sensor element 10 according to the embodiment of the present disclosure.
  • the sensor element 10 is applied to an infrared sensor or the like using a compound semiconductor material such as a group III-V semiconductor.
  • the sensor element 10 has, for example, a photoelectric conversion function for light having a wavelength in the visible region (for example, 380 nm or more and less than 780 nm) to the short infrared region (for example, 780 nm or more and less than 2500 nm).
  • the sensor element 10 is provided with, for example, a plurality of light receiving unit regions (pixels 102) arranged two-dimensionally.
  • FIG. 5 shows a cross-sectional configuration of a portion corresponding to the three pixels 102.
  • the sensor element 10 has a laminated structure of an element substrate 180 and a circuit board 190.
  • One surface of the element substrate 180 is a light incident surface (light incident surface S1), and the surface opposite to the light incident surface S1 (the other surface) is a bonding surface (joining surface S2) with the circuit board 190.
  • the element substrate 180 has a wiring layer 180W including the first electrode 181, a semiconductor layer 180S, a second electrode 185, and a passivation film 186 in this order from a position close to the circuit board 190.
  • the facing surface and end surface (side surface) of the semiconductor layer 180S with the wiring layer 180W are covered with an insulating film 187.
  • the circuit board 190 has a wiring layer 192W in contact with the junction surface S2 of the element substrate 180 and a support substrate 191 facing the element substrate 180 with the wiring layer 192W in between.
  • An element region R1 which is an effective pixel region is provided in the central portion of the element substrate 180, and the semiconductor layer 180S is arranged in this element region R1.
  • the region provided with the semiconductor layer 180S is the device region R1.
  • a peripheral region R2 surrounding the element region R1 is provided outside the element region R1.
  • An embedded layer 188 is provided together with an insulating film 187 in the peripheral region R2 of the element substrate 180.
  • light is incident on the semiconductor layer 180S from the light incident surface S1 of the element substrate 180 via the passivation film 186, the second electrode 185, and the second contact layer 184.
  • the signal charge photoelectrically converted by the semiconductor layer 180S moves through the wiring layer 180W and is read out by the circuit board 190.
  • the configuration of each part will be described.
  • the wiring layer 180W is provided over the element region R1 and the peripheral region R2, and has a joint surface S2 with the circuit board 190.
  • the joint surface S2 of the element substrate 180 is provided in the element region R1 and the peripheral region R2.
  • the joint surface S2 of the element region R1 and the joint surface S2 of the peripheral region R2 form the same plane. There is.
  • the joint surface S2 of the peripheral region R2 is formed by providing the embedded layer 188.
  • the wiring layer 180W has, for example, the first electrode 181 and the contact electrodes 189EAA and 189EB in the interlayer insulating films 189A and 189B.
  • an interlayer insulating film 189B is arranged on the circuit board 190 side
  • an interlayer insulating film 189A is arranged on the first contact layer 182 side
  • these interlayer insulating films 189A and 189B are laminated and provided.
  • the interlayer insulating films 189A and 189B are made of, for example, an inorganic insulating material.
  • the inorganic insulating material include silicon nitride, aluminum oxide, silicon oxide (SiO 2 ) and hafnium oxide.
  • the interlayer insulating films 189A and 189B may be made of the same inorganic insulating material.
  • the first electrode 181 is an electrode (anode) to which a voltage for reading a signal charge (holes or electrons, hereinafter for convenience, the signal charge is described as a hole) generated in the photoelectric conversion layer 183 is supplied. It is provided for each pixel 102 in the element region R1.
  • the first electrode 181 provided in the wiring layer 180W is in contact with the semiconductor layer 180S (more specifically, the first contact layer 182 described later) via the connection holes of the interlayer insulating film 189A and the insulating film 187.
  • the adjacent first electrodes 181 are electrically separated by an interlayer insulating film 189B.
  • the first electrode 181 contains, for example, any simple substance of titanium, tungsten, titanium nitride (TiN), platinum, gold), germanium, palladium, zinc, nickel and aluminum, or at least one of them. It is composed of alloy.
  • the first electrode 181 may be a single film of such a constituent material, or may be a laminated film in which two or more kinds are combined.
  • the first electrode 181 is composed of a laminated film of titanium and tungsten.
  • the contact electrode 189EA is for electrically connecting the first electrode 181 and the circuit board 190, and is provided for each pixel 102 in the element region R1.
  • the adjacent contact electrodes 189EA are electrically separated by an interlayer insulating film 189B.
  • the contact electrode 189EB is for electrically connecting the second electrode 185 and the wiring of the circuit board 190 (wiring 192CB described later), and is arranged in the peripheral region R2.
  • the contact electrode 189EB is formed in the same process as the contact electrode 189EA, for example.
  • the contact electrodes 189EA and 189EB are composed of, for example, a copper (Cu) pad and are exposed on the joint surface S2.
  • the semiconductor layer 180S includes, for example, a first contact layer 182, a photoelectric conversion layer 183, and a second contact layer 184 from a position close to the wiring layer 180W.
  • the first contact layer 182, the photoelectric conversion layer 183, and the second contact layer 184 have the same planar shape as each other, and their end faces are arranged at the same positions in a plan view.
  • the first contact layer 182 is provided in common to all the pixels 102, for example, and is arranged between the insulating film 187 and the photoelectric conversion layer 183.
  • the first contact layer 182 is for electrically separating adjacent pixels 102, and the first contact layer 182 is provided with, for example, a plurality of diffusion regions 182A.
  • the first contact layer 182 By using a compound semiconductor material having a bandgap larger than the bandgap of the compound semiconductor material constituting the photoelectric conversion layer 183 for the first contact layer 182, it is possible to suppress a dark current.
  • a compound semiconductor material having a bandgap larger than the bandgap of the compound semiconductor material constituting the photoelectric conversion layer 183 for the first contact layer 182 for example, an N-type InP can be used.
  • the diffusion regions 182A provided in the first contact layer 182 are arranged apart from each other.
  • the diffusion region 182A is arranged for each pixel 102, and the first electrode 181 is connected to each diffusion region 182A.
  • the diffusion region 182A is for reading out the signal charge generated in the photoelectric conversion layer 183 for each pixel 102, and contains, for example, a p-type impurity.
  • a p-type impurity examples include Zn and the like.
  • a pn junction interface is formed between the diffusion region 182A and the first contact layer 182 other than the diffusion region 182A, and the adjacent pixels 102 are electrically separated.
  • the diffusion region 182A is provided, for example, in the thickness direction of the first contact layer 182, and is also provided in a part of the photoelectric conversion layer 183 in the thickness direction.
  • the photoelectric conversion layer 183 between the first electrode 181 and the second electrode 185, more specifically, between the first contact layer 182 and the second contact layer 184, is common to, for example, all pixels 102. It is provided.
  • the photoelectric conversion layer 183 absorbs light having a predetermined wavelength to generate a signal charge, and is made of a compound semiconductor material such as an i-type III-V group semiconductor, for example.
  • a compound semiconductor material such as an i-type III-V group semiconductor
  • Examples of the compound semiconductor material constituting the photoelectric conversion layer 183 include InGaAs, InAsSb, InAs, InSb, and HgCdTe.
  • the photoelectric conversion layer 183 may be formed by Ge.
  • photoelectric conversion of light having a wavelength in the visible region to the short infrared region is performed.
  • the second contact layer 184 is provided in common to all the pixels 102, for example.
  • the second contact layer 184 is provided between the photoelectric conversion layer 183 and the second electrode 185, and is in contact with them.
  • the second contact layer 184 is a region where the electric charge discharged from the second electrode 185 moves, and is composed of, for example, a compound semiconductor containing N-type impurities.
  • a compound semiconductor containing N-type impurities for example, an N-type InP can be used.
  • the second electrode 185 is provided, for example, as an electrode common to each pixel 102, on the second contact layer 184 (on the light incident side) so as to be in contact with the second contact layer 184.
  • the second electrode 185 is for discharging a charge that is not used as a signal charge among the charges generated in the photoelectric conversion layer 183 (cathode).
  • the second electrode 185 is made of a conductive film capable of transmitting incident light such as infrared rays.
  • ITO Indium Tin Oxide
  • ITOO In 2 O 3- TIO 2
  • the passivation film 186 covers the second electrode 185 from the light incident surface S1 side.
  • the passivation film 186 may have an antireflection function.
  • silicon nitride, aluminum oxide, silicon oxide, tantalum oxide and the like can be used.
  • the insulating film 187 is provided between the first contact layer 182 and the wiring layer 180W, and the end face of the first contact layer 182, the end face of the photoelectric conversion layer 183, the end face of the second contact layer 184, and the second electrode 185. Cover the end face. Further, the insulating film 187 is in contact with the passivation film 186 in the peripheral region R2.
  • the insulating film 187 is composed of, for example, an oxide such as silicon oxide (SiO x ) or aluminum oxide.
  • the insulating film 187 may be formed by a laminated structure composed of a plurality of films.
  • the insulating film 187 may be made of a silicon (Si) -based insulating material such as silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), silicon nitride and silicon carbide (SiC).
  • Si silicon oxynitride
  • SiOC carbon-containing silicon oxide
  • SiC silicon carbide
  • the embedded layer 188 is for filling a step between the temporary substrate and the semiconductor layer 180S (not shown) in the manufacturing process of the sensor element 10. Although the details will be described later, in the present embodiment, since the embedded layer 188 is formed, it is possible to suppress the occurrence of defects in the manufacturing process due to the step between the semiconductor layer 180S and the temporary substrate.
  • the embedded layer 188 of the peripheral region R2 is provided between the wiring layer 180W and the passivation film 186, and has a thickness equal to or greater than the thickness of the semiconductor layer 180S, for example.
  • the embedded layer 188 is provided so as to surround the semiconductor layer 180S, a region around the semiconductor layer 180S (peripheral region R2) is formed.
  • the joint surface S2 with the circuit board 190 can be provided in the peripheral region R2. If the joint surface S2 is formed in the peripheral region R2, the thickness of the embedded layer 188 may be reduced, but the embedded layer 188 covers the semiconductor layer 180S in the thickness direction, and the entire end surface of the semiconductor layer 180S is buried. It is preferably covered with an inclusion layer 188.
  • the surface of the embedded layer 188 on the joint surface S2 side is flattened, and in the peripheral region R2, the wiring layer 180W is provided on the surface of the flattened embedded layer 188.
  • an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, carbon-containing silicon oxide and silicon carbide can be used.
  • the embedded layer 188 is provided with a through electrode 188V.
  • the through electrode 188V is for connecting the second electrode 185 and the wiring of the circuit board 190 (wiring 192CB described later), and a part of the through electrode 188V is provided on the passivation film 186.
  • One of the through electrodes 188V penetrates the passivation film 186 from above the passivation film 186 and is connected to the second electrode 185.
  • the other of the through electrodes 188V is connected to the contact electrode 189EB from above the passivation film 186 through the passivation film 186, the insulating film 187, the embedded layer 188 and the interlayer insulating film 189A.
  • the support board 191 of the circuit board 190 is for supporting the wiring layer 192W, and is made of, for example, silicon (Si).
  • the wiring layer 192W has, for example, contact electrodes 192EA and 192EB, a pixel circuit 192CA, wiring 192CB, and a pad electrode 192P in the interlayer insulating film 192A.
  • the interlayer insulating film 192A is made of, for example, an inorganic insulating material.
  • this inorganic insulating material include silicon nitride, aluminum oxide, silicon oxide and hafnium oxide.
  • the contact electrode 192EA is for electrically connecting the first electrode 181 and the pixel circuit 192CA, and is in contact with the contact electrode 189EA at the joint surface S2 of the element substrate 180.
  • the adjacent contact electrodes 192EA are electrically separated by an interlayer insulating film 192A.
  • the contact electrode 192EB is for electrically connecting the second electrode 185 and the wiring 192CB of the circuit board 190, and is in contact with the contact electrode 189EB at the joint surface S2 of the element substrate 180.
  • the contact electrode 192EB is formed in the same process as the contact electrode 192EA, for example.
  • the through electrode 188V may be connected to the wiring 192CB without providing the contact electrodes 189EB and 192EB.
  • the contact electrodes 192EA and 192EB are composed of, for example, copper pads, and are exposed on the surface of the circuit board 190 facing the element board 180.
  • a CuCu bond is formed between the contact electrode 189EA and the contact electrode 192EA, and between the contact electrode 189EB and the contact electrode 192EB, for example.
  • the pixel circuit 192CA is provided for each pixel 102 and is connected to the contact electrode 192EA. This pixel circuit 192CA constitutes the ROIC.
  • the wiring 192CB connected to the contact electrode 192EB is connected to, for example, a predetermined potential.
  • one of the electric charges (for example, holes) generated in the photoelectric conversion layer 183 is read from the first electrode 181 to the pixel circuit 192CA via the contact electrodes 189EA and 192EA.
  • the other side (for example, electrons) of the electric charge generated in the photoelectric conversion layer 183 is discharged from the second electrode 185 to a predetermined potential via the through electrode 188V and the contact electrodes 189EB and 192EB. ..
  • the pad electrode 192P is for making an electrical connection with the outside.
  • the sensor element 10 is provided with a hole H that penetrates the element substrate 180 and reaches the pad electrode 192P, and is electrically connected to the outside through the hole H.
  • the connection is made, for example, by a method such as wire bonding or bumping.
  • FIG. 6 is a cross-sectional view showing a configuration example of the sensor device 1 according to the embodiment of the present disclosure
  • FIG. 7 is a bottom view showing a configuration example of the sensor device 1 according to the embodiment of the present disclosure.
  • the sensor device 1 is a sensor device having a package structure in which the inside is airtightly sealed, and the light transmitted through the window member 60 is received by the internal sensor element 10.
  • the side where the window member 60 is provided in the sensor device 1 is defined as upward for convenience, and indicates the vertical direction.
  • the sensor device 1 includes a sensor element 10, a perche element 20, a relay board 30, a package board 40, a plurality of pin terminals 50, a window member 60, and a support member. 70 and.
  • the plurality of pin terminals 50 are examples of external terminals.
  • the sensor element 10 has an effective pixel region 11 on a light receiving surface 10a which is a main surface (upper surface in the figure).
  • a plurality of the above-mentioned pixels 102 that convert the received light into an electric signal are formed.
  • the sensor element 10 according to the embodiment is a SWIR (Short Wave InfraRed) image sensor such as an InGaAs image sensor. That is, the sensor element 10 according to the embodiment has pixels that convert light including a shortwave infrared region (for example, light having a wavelength of 400 nm to 2500 nm) into an electric signal.
  • SWIR Short Wave InfraRed
  • the perche element 20 has a cooling substrate 21, a columnar portion 22, and a heat radiating substrate 23, and the cooling substrate 21, the columnar portion 22, and the heat radiating substrate 23 are laminated in this order from the top.
  • FIG. 8 is a top view showing a configuration example of the cooling substrate 21 of the Perche element 20 according to the embodiment of the present disclosure.
  • the cooling substrate 21 is formed of a copper thin film or the like, and a metal layer ML1 having a predetermined pattern is formed on a surface facing the columnar portion 22 (lower surface in FIG. 6). Note that FIG. 8 shows the arrangement of the metal layer ML1 when viewed from above for easy understanding.
  • FIG. 9 is a top view showing a configuration example of the heat radiating substrate 23 of the Pelche element 20 according to the embodiment of the present disclosure.
  • the heat radiating substrate 23 is formed of a copper thin film or the like, and a metal layer ML2 having a predetermined pattern is formed on a surface facing the columnar portion 22 (upper surface in FIG. 6). Further, a pair of electrodes 24 are provided at a predetermined portion of the metal layer ML2 on the heat radiating substrate 23.
  • FIG. 10 is a top view showing a configuration example of the perche element 20 according to the embodiment of the present disclosure.
  • the metal layer ML1 of the cooling substrate 21 and the metal layer ML2 of the heat radiating substrate 23 are aligned, and the columnar portion 22 is arranged at a portion where both the metal layer ML1 and the metal layer ML2 are arranged. To do.
  • a one-stroke electric circuit formed by the metal layer ML1, the metal layer ML2, and the columnar portion 22 is formed between one electrode 24 and the other electrode 24 inside the Pelche element 20.
  • the columnar portion 22 has a columnar P-type thermoelectric semiconductor and a columnar N-type thermoelectric semiconductor. One end of each of the P-type thermoelectric semiconductor and the N-type thermoelectric semiconductor is connected to the metal layer ML1 and the other end is connected to the metal layer ML2.
  • the P-type thermoelectric semiconductor and the N-type thermoelectric semiconductor of the columnar portion 22 are alternately connected in series via the metal layer ML1 and the metal layer ML2.
  • the cooling substrate 21 absorbs heat from the cooling surface 21a (see FIG. 6) and is cooled, and the heat radiating substrate 23 is cooled. The heat absorbed by the substrate 21 is radiated from the heat radiating surface 23a (see FIG. 6).
  • the cooling surface 21a is a surface opposite to the surface of the cooling substrate 21 to which the columnar portions 22 are joined (that is, the surface on which the metal layer ML1 is arranged).
  • the heat radiating surface 23a is a surface opposite to the surface of the heat radiating substrate 23 to which the columnar portions 22 are joined (that is, the surface on which the metal layer ML2 is arranged).
  • the relay board 30 is arranged between the cooling surface 21a of the Pelche element 20 and the sensor element 10.
  • the sensor element 10 is bonded to the front surface 31 of the relay board 30 via an adhesive (not shown), and the cooling surface 21a of the Pelche element 20 is bonded to the back surface 32 of the relay board 30 with an adhesive (not shown). It is joined via such as.
  • the sensor element 10 is thermally connected to the cooling surface 21a of the Pelche element 20 via the relay board 30.
  • the relay board 30 has a wiring layer (not shown) on the surface or inside, and the wiring layer relays the electrical connection between the sensor element 10 and the package board 40.
  • the wiring layer of the relay board 30 and the sensor element 10 are electrically connected by a bonding wire 33.
  • the wiring layer of the relay board 30 and the bonding pad (not shown) provided in the stepped portion 41b of the package board 40 are electrically connected by the bonding wire 34.
  • the relay board 30 can relay the electrical connection between the sensor element 10 and the package board 40.
  • the relay board 30 is, for example, an interposer board made of ceramic.
  • the relay board 30 is not limited to the ceramic board, and may be a resin printed circuit board or the like.
  • the package substrate 40 is made of a ceramic having high thermal conductivity such as alumina (Al 2 O 3 ), aluminum nitride (AlN), and silicon nitride (Si 3 N 4). Accommodates the relay board 30.
  • alumina Al 2 O 3
  • AlN aluminum nitride
  • Si 3 N 4 silicon nitride
  • the package substrate 40 is a multilayer substrate made of ceramic such as alumina, for example, a PGA (Pin Grid Array) substrate. As shown in FIG. 6, the package substrate 40 has a first surface (for example, an upper surface 42) and a second surface (for example, a bottom surface 43) located on the opposite side of the first surface.
  • a first surface for example, an upper surface 42
  • a second surface for example, a bottom surface 43
  • a plurality of wirings are provided in multiple layers inside the package substrate 40 located between the upper surface 42 and the bottom surface 43. These wirings are connected to a plurality of terminals (for example, pin terminals 50) provided on the bottom surface 43 of the package substrate 40.
  • the package substrate 40 has a substantially rectangular parallelepiped shape, and a recess 41 is formed on the upper surface 42. Then, the perche element 20, the relay board 30, and the sensor element 10 are laminated in this order from the bottom on the bottom surface 41a of the recess 41.
  • the recess 41 is provided with a step portion 41b at a position higher than the bottom surface 41a. Then, the bonding pad provided on the step portion 41b and the wiring layer of the corresponding relay board 30 are electrically connected by the bonding wire 34.
  • the bonding pad provided on the step portion 41b is electrically connected to the pin terminal 50 provided on the bottom surface 43 of the package substrate 40 via a wiring layer (not shown) formed on the surface or inside of the package substrate 40.
  • Ru the package board 40 has a function of a relay board that relays the electrical connection between the relay board 30 and the pin terminal 50.
  • the bonding pad on the step portion 41b By forming the bonding pad on the step portion 41b in this way, the distance between the bonding pad and the relay board 30 can be shortened. As a result, the length of the bonding wire 34 can be shortened, so that the wiring resistance between the package substrate 40 and the relay substrate 30 can be reduced.
  • the electrical characteristics of the sensor device 1 can be improved.
  • the bottom surface 43 and the plurality of side surfaces 44 of the package substrate 40 are substantially flat. As shown in FIG. 7, a plurality of pin terminals 50 are arranged side by side in a matrix on the bottom surface 43 of the package substrate 40, and a flat bottom heat dissipation area is provided in a region where the plurality of pin terminals 50 are not arranged. 43a is provided.
  • flat side heat dissipation areas 44a are provided on the plurality of side surfaces 44 of the package substrate 40, respectively.
  • the pin terminal 50 is made of a conductive material (for example, metal) and has a substantially cylindrical shape. Then, one end of the pin terminal 50 is electrically and mechanically connected to the wiring layer exposed from the bottom surface 43 of the package substrate 40, and the pin terminal 50 extends downward from the bottom surface 43.
  • a conductive material for example, metal
  • the power supply from the external device to the electrode 24 of the Pelche element 20 is performed via the terminal 45 provided on the bottom surface 41a of the recess 41 in the package substrate 40 and the bonding wire 25 connected to the terminal 45.
  • the window member 60 is provided so as to face the light receiving surface 10a (that is, the effective pixel region 11) of the sensor element 10, and is made of borosilicate glass, which is a translucent material. In the sensor device 1 according to the embodiment, the light transmitted through the window member 60 is received in the effective pixel region 11 of the sensor element 10.
  • the support member 70 is arranged between the sensor element 10 and the window member 60 to support the window member 60.
  • the support member 70 has an opening 71 and a frame portion 72.
  • the opening 71 is formed so as to face the light receiving surface 10a (that is, the effective pixel region 11) of the sensor element 10 and allows incident light to pass therethrough.
  • the frame portion 72 has a frame shape, is arranged so as to surround the opening 71, and supports the window member 60.
  • the window member 60 is supported by the support member 70 by being attached to the support member 70 so as to cover the opening 71.
  • the window member 60 and the support member 70 are joined without a gap by using low melting point glass or the like.
  • the support member 70 is joined to the upper surface 42 of the package substrate 40 so as to cover the recess 41 of the package substrate 40.
  • the support member 70 and the package substrate 40 are joined without a gap by using an existing method.
  • the window member 60 and the support member 70 are joined without gaps, and the support member 70 and the package substrate 40 are joined without gaps. Therefore, in the sensor device 1, the inside of the recess 41 of the package substrate 40 is formed. It can be hermetically sealed.
  • the support member 70 can be made of various materials such as a metal material and a ceramic material.
  • the detection sensitivity of the sensor device 1 can be improved by forming the window member 60 with borosilicate glass.
  • FIG. 11 is a diagram showing the wavelength dependence of the transmittance of the window members 60 of Examples and Reference Examples.
  • the transmittance of the window member 60 made of borosilicate glass is shown as an example, and the transmittance of the window member 60 made of sapphire glass is shown as a reference example.
  • the transmittance shows a stable high value in the same visible region and the short wave infrared region.
  • the window member 60 by configuring the window member 60 with borosilicate glass showing a stable high value in the entire visible region and the shortwave infrared region, the sensor element 10 in the entire visible region and the shortwave infrared region 10 The amount of light received can be increased.
  • the detection sensitivity of the sensor device 1 can be improved.
  • the window member 60 by forming the window member 60 with borosilicate glass having crystal isotropic property, it is possible to suppress that the optical characteristics (for example, transmittance) are influenced in the axial direction of the crystal. Therefore, according to the embodiment, it is possible to realize the sensor device 1 having a small variation in optical characteristics.
  • the thermal shock characteristics of the sensor device 1 can be improved by forming the window member 60 with borosilicate glass having a small coefficient of thermal expansion and high toughness.
  • the processing cost of the sensor device 1 can be reduced by configuring the window member 60 with borosilicate glass, which is relatively easy to process.
  • the sensor device 1 is provided with a support member 70 having an opening 71 and a frame portion 72 and supporting the window member 60.
  • a support member 70 having an opening 71 and a frame portion 72 and supporting the window member 60.
  • the reliability of the sensor device 1 can be improved.
  • the frame portion 72 may be arranged outside the effective pixel area 11 in a plan view, and the area of the opening 71 may be larger than the area of the effective pixel area 11.
  • the opening angle of the opening 71 with respect to the effective pixel region 11 is preferably 30 ° or more.
  • the light from the detection target of the sensor device 1 can be guided to the effective pixel region 11 without being blocked by the support member 70. Therefore, according to the embodiment, the detection target can be stably detected.
  • the window member 60 may be arranged so as to cover the opening 71. That is, in the embodiment, it is preferable that the area of the window member 60 is larger than the area of the opening 71. As a result, the margin portion between the window member 60 and the support member 70 can be increased, so that it is possible to suppress the formation of a gap between the window member 60 and the support member 70.
  • the inside of the recess 41 of the package substrate 40 can be stably and airtightly sealed.
  • the window member 60 according to the embodiment is not limited to the case where the window member 60 is arranged so as to cover the opening 71, and the window member 60 having a size substantially equal to that of the opening 71 may be arranged so as to be fitted into the opening 71. Good.
  • the sensor element 10 that generates high heat during operation such as the SWIR image sensor is used because the sensor element 10 is thermally connected to the cooling surface 21a of the Pelche element 20, the sensor element 10 is used. Can be operated stably.
  • the cooling surface 21a of the perche element 20 is larger than the surface in the direction opposite to the light receiving surface 10a of the sensor element 10. That is, in a plan view, the cooling surface 21a of the Pelche element 20 may be larger than the sensor element 10.
  • the entire sensor element 10 can be uniformly cooled by the Pelche element 20, so that the sensor element 10 can be operated more stably.
  • FIG. 12 is a cross-sectional view showing a configuration example of the sensor device 1 according to the first modification of the embodiment of the present disclosure.
  • the recess 41 can be made smaller by making the cooling surface 21a of the Pelche element 20 smaller than the sensor element 10, so that the sensor device 1 can be miniaturized.
  • the bottom surface 41a of the recess 41 in the package substrate 40 may be thermally connected to the heat dissipation surface 23a of the perche element 20.
  • the heat generated by the sensor element 10 can be efficiently dissipated to the outside through the Perche element 20 and the package substrate 40.
  • the perche element 20 and the sensor element 10 are hermetically sealed in a low humidity state, dew condensation occurs on the cooling surface 21a when the cooling surface 21a of the perche element 20 is cooled. Can be suppressed.
  • the sensor element 10 of the sensor device 1 can have a large number of pixels by forming the package substrate 40 with ceramic. The reason for this will be described below.
  • FIG. 13 is a cross-sectional view showing a configuration example of the sensor device 1 according to the second modification of the embodiment of the present disclosure, and shows the sensor device 1 composed of the metal package substrate 90.
  • the sensor element 10 the perche element 20, and the relay board 30 are housed in the recess 91 of the metal package board 90.
  • a plurality of columnar pin terminals 95 are provided on the bottom surface 91a of the recess 91.
  • an insulating sealing member 96 is provided between the pin terminal 95 and the package substrate 90.
  • one end of the pin terminal 95 projects downward from the bottom surface 93 of the package substrate 90, and the other end of the pin terminal 95 is electrically connected to the relay board 30 by the bonding wire 34 in the recess 91.
  • the package substrate 90 is made of a conductive metal material, it is necessary to secure the insulation of each pin terminal 95 with the seal member 96. That is, in the example of FIG. 13, since a space for providing the seal member 96 is required, it is difficult to reduce the distance between the adjacent pin terminals 95. Therefore, the plurality of pin terminals 95 are connected to the package substrate 90 at a high density. It is difficult to place in.
  • the package substrate 40 is made of an insulating ceramic, it is not necessary to separately provide a member for ensuring the insulating property. Therefore, in the example of FIG. 6, by making the package substrate 40 made of ceramic, the distance between the adjacent pin terminals 50 can be shortened.
  • the wiring layer can be provided three-dimensionally inside the package substrate 40, even if a large number of pin terminals 50 are arranged on the bottom surface 43, all the pin terminals 50 can be provided. Can be wired individually.
  • the sensor element 10 of the sensor device 1 can have a large number of pixels.
  • the detection sensitivity of the sensor device 1 can be improved by making the window member 60 made of borosilicate glass. Can be done.
  • the plurality of pin terminals 50 and the Pelche element 20 are provided at different positions in a plan view.
  • a heat radiating device (not shown) can be directly attached to the position corresponding to the Perche element 20 on the bottom surface 43 (that is, directly below the Perche element 20).
  • the heat transferred from the heat radiating surface 23a of the Pelche element 20 to the bottom surface 43 of the package substrate 40 can be radiated by the heat radiating device without being hindered by the pin terminals 50. Therefore, according to the embodiment, the heat dissipation of the sensor device 1 can be improved.
  • the bottom heat dissipation area 43a which is wider and flatter than the Perche element 20, is provided at a position corresponding to the Perche element 20 on the bottom surface 43 of the package substrate 40.
  • a heat radiating device having a larger area than the Pelche element 20 can be provided in the bottom heat radiating area 43a, so that the heat radiating property of the sensor device 1 can be further improved.
  • the heat radiating device can be arranged so as to protrude from the package substrate 40, so that the heat radiating property of the sensor device 1 can be further improved.
  • FIG. 14 is a bottom view showing a configuration example of the sensor device 1 according to the third modification of the embodiment of the present disclosure.
  • the heat dissipation area 43a can be removed from the perche element 20.
  • the heat can be dissipated by the heat dissipation device without any trouble.
  • a plurality of pin terminals 50 may be provided so as to surround the perche element 20 in a plan view.
  • a large number of pin terminals 50 can be provided on the package substrate 40, so that the heat radiating device can be arranged so as to protrude from the package substrate 40. Therefore, according to the example of FIG. 14, the sensor element 10 of the sensor device 1 can be further increased in number of pixels.
  • a flat side heat dissipation area 44a is provided on the side surface 44 of the package substrate 40.
  • a heat radiating device (not shown) can be provided in the side heat radiating area 44a, so that the heat radiating property of the sensor device 1 can be further improved.
  • the surface area of the bottom heat radiation area 43a and the side heat radiation area 44a can be increased.
  • the heat dissipation can be improved.
  • the thickness of the wiring between the package substrate 40 and the sensor element 10 can be made thicker than the bonding wires 33 and 34, so that the wiring resistance between the package substrate 40 and the sensor element 10 can be reduced. Can be done.
  • the electrical characteristics of the sensor device 1 can be improved. Further, in the embodiment, the sensor device 1 can be made multifunctional by mounting various mounting components (for example, a capacitor, a resistor, etc.) on the relay board 30.
  • various mounting components for example, a capacitor, a resistor, etc.
  • the sensor element 10 may be a SWIR image sensor.
  • the sensor device 1 can perform sensing using light having a wavelength longer than that of visible light.
  • the sensor element 10 according to the embodiment is not limited to the SWIR image sensor.
  • the sensor element 10 according to the embodiment may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor having pixels that convert light in the visible region into an electric signal.
  • CMOS Complementary Metal Oxide Semiconductor
  • CCD Charge Coupled Device
  • the sensor element according to the embodiment is a CMOS image sensor having pixels for converting light in the visible region into an electric signal will be described with reference to FIGS. 15A to 17.
  • the sensor element 10A is a semiconductor package in which a laminated substrate 213, which is formed by laminating a lower substrate 211 and an upper substrate 212, is packaged.
  • An R (red), G (green), or B (blue) color filter (not shown) and an on-chip lens (not shown) are formed on the upper surface of the upper substrate 212. Further, the upper substrate 212 is connected by a cavityless structure via a glass protective substrate (not shown) for protecting the on-chip lens and a glass seal resin (not shown).
  • the upper substrate 212 is formed with a pixel region 221 in which pixel portions for photoelectric conversion are two-dimensionally arranged, and a control circuit 222 for controlling the pixel portions. Further, a logic circuit 223 such as a signal processing circuit for processing a pixel signal output from a pixel portion is formed on the lower substrate 211.
  • only the pixel region 221 may be formed on the upper substrate 212, and the control circuit 222 and the logic circuit 223 may be formed on the lower substrate 211.
  • both the logic circuit 223 or the control circuit 222 and the logic circuit 223 are formed and laminated on the lower substrate 211 different from the upper substrate 212 of the pixel area 221.
  • the size of the sensor element 10A can be reduced as compared with the case where the pixel region 221 and the control circuit 222 and the logic circuit 223 are arranged in the plane direction on one semiconductor substrate.
  • the upper substrate 212 on which at least the pixel region 221 is formed will be referred to as a pixel sensor substrate
  • the lower substrate 211 on which at least the logic circuit 223 is formed will be referred to as a logic substrate.
  • FIG. 16 is a diagram showing a circuit configuration example of the laminated substrate 213 of the sensor element 10A of another example according to the embodiment of the present disclosure.
  • the laminated substrate 213 includes a pixel array unit 233 in which pixels 232 are arranged in a two-dimensional array, a vertical drive circuit 234, a column signal processing circuit 235, a horizontal drive circuit 236, an output circuit 237, a control circuit 238, and an input / output terminal 239. And so on.
  • Pixel 232 includes a photodiode as a photoelectric conversion element and a plurality of pixel transistors. An example of the circuit configuration of the pixel 232 will be described later with reference to FIG.
  • the pixel 232 can also have a shared pixel structure.
  • This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion (floating diffusion region), and one shared other pixel transistor. That is, in the shared pixel, the photodiode and the transfer transistor constituting the plurality of unit pixels are configured by sharing the other pixel transistor.
  • the control circuit 238 receives the input clock and data instructing the operation mode, etc., and outputs data such as internal information of the laminated board 213. That is, the control circuit 238 generates a clock signal or a control signal that serves as a reference for the operation of the vertical drive circuit 234, the column signal processing circuit 235, the horizontal drive circuit 236, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do.
  • control circuit 238 outputs the generated clock signal and control signal to the vertical drive circuit 234, the column signal processing circuit 235, the horizontal drive circuit 236, and the like.
  • the vertical drive circuit 234 is composed of, for example, a shift register, selects a predetermined pixel drive wiring 240, supplies a pulse for driving the pixel 232 to the selected pixel drive wiring 240, and drives the pixel 232 in a row unit. To do.
  • the vertical drive circuit 234 selectively scans each pixel 232 of the pixel array unit 233 in the vertical direction in a row-by-row manner. Then, the vertical drive circuit 234 supplies a pixel signal based on the signal charge generated according to the amount of received light in the photoelectric conversion unit of each pixel 232 to the column signal processing circuit 235 through the vertical signal line 241.
  • the column signal processing circuit 235 is arranged for each column of the pixel 232, and performs signal processing such as noise removal for each pixel string of the signal output from the pixel 232 for one row.
  • the column signal processing circuit 235 performs signal processing such as CDS and AD conversion for removing fixed pattern noise peculiar to pixels.
  • the horizontal drive circuit 236 is composed of, for example, a shift register, selects each of the column signal processing circuits 235 in order by sequentially outputting horizontal scanning pulses, and outputs a pixel signal from each of the column signal processing circuits 235 as a horizontal signal line. Output to 242.
  • the output circuit 237 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 235 through the horizontal signal line 242 and outputs the signals.
  • the output circuit 237 may, for example, only buffer, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.
  • the input / output terminal 239 exchanges signals with the outside.
  • the laminated substrate 213 configured as described above is a CMOS image sensor called a column AD method in which a column signal processing circuit 235 that performs CDS processing and AD conversion processing is arranged for each pixel string.
  • FIG. 17 is a diagram showing an equivalent circuit of pixel 232 of the sensor element 10A of another example according to the embodiment of the present disclosure.
  • the pixel 232 shown in FIG. 17 shows a configuration that realizes an electronic global shutter function.
  • Pixel 232 includes a photodiode 251, a first transfer transistor 252, a memory unit 253, a second transfer transistor 254, an FD 255, a reset transistor 256, an amplification transistor 257, a selection transistor 258, and an emission transistor 259.
  • the photodiode 251 is an example of a photoelectric conversion element, and the FD 255 is a floating diffusion region.
  • the photodiode 251 is a photoelectric conversion unit that generates and stores an electric charge (signal charge) according to the amount of received light.
  • the anode terminal of the photodiode 251 is grounded, and the cathode terminal is connected to the memory unit 253 via the first transfer transistor 252. Further, the cathode terminal of the photodiode 251 is also connected to the discharge transistor 259 for discharging unnecessary electric charges.
  • the memory unit 253 is a charge holding unit that temporarily holds the electric charge until the electric charge is transferred to the FD 255.
  • the second transfer transistor 254 When the second transfer transistor 254 is turned on by the transfer signal TRG, the second transfer transistor 254 reads out the electric charge held in the memory unit 253 and transfers it to the FD 255.
  • the FD 255 is a charge holding unit that holds the electric charge read from the memory unit 253 to read it as a signal.
  • the reset transistor 256 is turned on by the reset signal RST, the electric charge stored in the FD 255 is discharged to the constant voltage source VDD to reset the potential of the FD 255.
  • the amplification transistor 257 outputs a pixel signal corresponding to the potential of the FD 255. That is, the amplification transistor 257 constitutes a load MOS 260 as a constant current source and a source follower circuit.
  • a pixel signal indicating the level corresponding to the electric charge stored in the FD 255 is output from the amplification transistor 257 to the column signal processing circuit 235 (see FIG. 16) via the selection transistor 258.
  • the load MOS 260 is arranged in, for example, the column signal processing circuit 235.
  • the selection transistor 258 is turned on when the pixel 232 is selected by the selection signal SEL, and outputs the pixel signal of the pixel 232 to the column signal processing circuit 235 via the vertical signal line 241.
  • the discharge transistor 259 When the discharge transistor 259 is turned on by the discharge signal OFG, the discharge transistor 259 discharges the unnecessary charge stored in the photodiode 251 to the constant voltage source VDD.
  • the transfer signals TRX and TRG, the reset signal RST, the discharge signal OFG, and the selection signal SEL are supplied from the vertical drive circuit 234 via the pixel drive wiring 240.
  • the operation of pixel 232 will be briefly described. First, before the start of exposure, the high-level emission signal OFG is supplied to the emission transistor 259 to turn on the emission transistor 259, and the electric charge accumulated in the photodiode 251 is discharged to the constant voltage source VDD to all pixels. Photodiode 251 is reset.
  • the first transfer transistor 252 When a predetermined exposure time elapses, the first transfer transistor 252 is turned on by the transfer signal TRX in all the pixels of the pixel array unit 233, and the electric charge accumulated in the photodiode 251 is transferred to the memory unit 253. Will be done.
  • the electric charges held in the memory unit 253 of each pixel 232 are sequentially read out to the column signal processing circuit 235 line by line.
  • the second transfer transistor 254 of the pixel 232 of the read line is turned on by the transfer signal TRG, and the electric charge held in the memory unit 253 is transferred to the FD 255.
  • the exposure time is set to be the same for all the pixels of the pixel array unit 233, and after the exposure is completed, the electric charge is temporarily held in the memory unit 253, and the electric charge is temporarily held from the memory unit 253.
  • a global shutter method operation (imaging) that sequentially reads out charges line by line is possible.
  • the circuit configuration of the pixel 232 is not limited to the configuration shown in FIG. 17, and for example, a circuit configuration that does not have the memory unit 253 and operates by the so-called rolling shutter method can be adopted.
  • FIG. 18 is a plan view of the pixel array region 103 showing the pixel arrangement of the charge emitting pixels according to the modified example 4.
  • an OPB (Optical Black) region for detecting a reference black level is formed as a part of the pixel array region 103.
  • the pixel structure of the modification 4 is a pixel structure when the OPB region is formed as a part of the pixel array region 103.
  • the OPB region 163 when the OPB region 163 is formed as a part of the pixel array region 103, the OPB region 163 is a plurality of rows and a plurality of outermost rows of each side of the rectangular pixel array region 103. Consists of lines. Then, the innermost row and column of the OPB region 163 are set in the charge emission region 162.
  • the area inside the OPB area 163 of the pixel array area 103 is an effective pixel area in which normal pixels 102A (see FIG. 19) that outputs a pixel signal according to the amount of received light are arranged.
  • FIG. 19 is a cross-sectional view showing the structure of the pixel 102 according to the modified example 4 of the embodiment of the present disclosure. As shown in FIG. 19, OPB pixels 102C (102Ca, 102Cb) are arranged in the OPB region 163.
  • a light-shielding film 165 is formed on the upper side of the N-type semiconductor thin film 141, which is the photoelectric conversion unit 121, in place of the color filter 146 and the on-chip lens 147.
  • the light-shielding film 165 is made of a metal material such as tungsten, aluminum or gold.
  • the OPB pixel 102C on the innermost side is the OPB pixel 102Cb for charge release in which the reset transistor 123 is controlled to be always on, as in the above-described embodiment. It has become.
  • the outer two OPB pixels 102C are controlled to read the black level.
  • OPB pixel 102Ca for use.
  • Other configurations in the modified example 4 are the same as those in the above-described embodiment.
  • the pixel array region 103 of the sensor element 10 when the pixel array region 103 of the sensor element 10 is irradiated with high-intensity light, blooming may occur in the normal pixel 102A closest to the OPB region 163.
  • the OPB pixel 102C adjacent to the OPB pixel 102C, that is, the innermost OPB pixel 102C in the OPB region 163 may be affected.
  • the light incident on the normal pixel 102A closest to the OPB region 163 may leak to the adjacent OPB pixel 102C, and blooming may occur in the adjacent OPB pixel 102C.
  • the innermost OPB pixel 102C in the OPB region 163 is used as the OPB pixel 102Cb for charge release, which is controlled so that the reset transistor 123 is always on.
  • the occurrence of blooming can be stopped by the OPB pixel 102Cb for charge release, and the inflow of charge to the OPB pixel 102Ca for reading the black level adjacent to the OPB pixel 102Cb can be prevented. Therefore, according to the modified example 4, deterioration of image quality due to the occurrence of blooming can be suppressed.
  • FIG. 20 is a cross-sectional view showing a configuration example of the sensor device 1 according to the modified example 5 of the embodiment of the present disclosure.
  • the sensor device 1 of the modified example 5 is different from the embodiment in that a connector 98 is provided as an external terminal instead of the pin terminal 50.
  • the connector 98 is provided on the bottom surface 43 at a position different from the position corresponding to the Perche element 20 (that is, directly below the Perche element 20), and is electrically connected to the wiring layer exposed from the bottom surface 43 of the package substrate 40.
  • the connector 98 and an external device are electrically connected, so that the external device inputs power, a control signal, and the like to the sensor device 1, and the electric signal from the sensor element 10 is input. Output to an external device.
  • the sensor device 1 can be easily attached to an external device (not shown) by configuring the external terminal with the connector 98.
  • the external terminal of the sensor device 1 is not limited to the pin terminal 50 and the connector 98, and various external terminals can be adopted.
  • FIG. 21 is a cross-sectional view showing a configuration example of the sensor device 1 according to the modified example 6 of the embodiment of the present disclosure.
  • metal heat dissipation is provided on at least a part of the surface (bottom surface 41a in the present disclosure) of the perche element 20 facing the heat dissipation surface 23a of the package substrate 40. It has a member 46.
  • the heat radiating member 46 is exposed on the bottom surface 41a.
  • an adhesive or the like may be interposed between the heat radiating surface 23a and the bottom surface 41a of the Pelche element 20.
  • the heat radiating member 46 is made of a metal having high thermal conductivity such as copper, aluminum, and tungsten. That is, in the package substrate 40 of the modification 6, at least a part of the heat transfer path from the heat radiation surface 23a of the Pelche element 20 to the bottom heat radiation area 43a is made of a metal having a higher thermal conductivity than ceramic.
  • the heat transfer efficiency from the heat radiating surface 23a of the Pelche element 20 to the bottom heat radiating area 43a can be improved. Therefore, according to the modification 6, the heat dissipation of the sensor device 1 can be improved.
  • the heat radiating member 46 penetrates between the surface (bottom surface 41a) facing the heat radiating surface 23a of the Pelche element 20 and the bottom surface 43 in the package substrate 40. As a result, the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be reduced, so that the heat dissipation of the sensor device 1 can be further improved.
  • the heat radiating member 46 is provided on the entire surface of the package substrate 40 facing the heat radiating surface 23a of the Pelche element 20. As a result, the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be further reduced, so that the heat dissipation of the sensor device 1 can be further improved.
  • FIG. 22 is a cross-sectional view showing a configuration example of the sensor device 1 according to the modified example 7 of the embodiment of the present disclosure.
  • a plurality of via-shaped heat radiating members 46 penetrating between the surface (bottom surface 41a) of the Pelche element 20 facing the heat radiating surface 23a and the bottom surface 43 may be provided on the package substrate 40. .. Also in the example of FIG. 22, since the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be reduced, the heat dissipation of the sensor device 1 can be further improved.
  • the heat radiating member 46 is not necessarily limited to the metal material, and the heat conduction is higher than that of the ceramic constituting the package substrate 40. Any material with a high rate may be used.
  • a ceramic material having a high thermal conductivity or the like may be used as the heat radiating member 46.
  • the heat radiating member 46 is provided so as to be exposed on the surface of the package substrate 40 facing the heat radiating surface 23a of the Pelche element 20 is shown, but this is not necessarily the case.
  • the heat radiating member 46 does not have to be exposed on the surface.
  • the heat radiating member 46 may be arranged so as to be embedded directly under the Pelche element 20. That is, the heat radiating member 46 may be arranged so as to overlap the Pelche element 20 in a plan view. As a result, the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be reduced, so that the heat dissipation of the sensor device 1 can be further improved.
  • the heat radiating member 46 may be arranged at a place other than directly under the Pelche element 20.
  • FIG. 23 is a cross-sectional view showing a configuration example of the sensor device 1 according to the modified example 8 of the embodiment of the present disclosure. As shown in FIG. 23, in the sensor device 1 of the modified example 8, the configuration of the perche element 20 is different from that of the embodiment.
  • the package substrate 40 is integrally formed with the heat radiating substrate 23 of the Pelche element 20. That is, in the modified example 8, the metal layer ML2 shown in FIG. 9 is provided not on the heat dissipation substrate 23 but on the bottom surface 41a of the recess 41 in the package substrate 40, and the metal layer ML2 on the bottom surface 41a has the columnar portion 22 and the cooling substrate 21. Are laminated to form the Pelche element 20.
  • the thermal resistance at the interface between the heat radiating substrate 23 and the package substrate 40 can be reduced. Further, in the modified example 8, since the heat radiating substrate 23 can be omitted, the heat transfer path from the sensor element 10 to the bottom heat radiating area 43a can be shortened.
  • the heat dissipation of the sensor device 1 can be improved.
  • FIG. 24 is a cross-sectional view showing a configuration example of the sensor device 1 according to the modified example 9 of the embodiment of the present disclosure. As shown in FIG. 24, in the sensor device 1 of the modification 9, the configuration of the perche element 20 is different from that of the embodiment and the modification 8.
  • the relay board 30 is integrally formed with the cooling board 21 of the Pelche element 20. That is, in the modified example 9, the metal layer ML1 shown in FIG. 8 is provided not on the cooling substrate 21 but on the back surface 32 of the relay substrate 30, and the relay substrate 30 is further laminated on the laminated heat radiation substrate 23 and the columnar portion 22. , Perche element 20 is configured.
  • the thermal resistance at the interface between the relay board 30 and the cooling board 21 can be reduced. Further, in the modified example 9, since the cooling substrate 21 can be omitted, the heat transfer path from the sensor element 10 to the bottom heat dissipation area 43a can be shortened.
  • the heat dissipation of the sensor device 1 can be improved.
  • FIG. 25 is a cross-sectional view showing a configuration example of the sensor device 1 according to the modified example 10 of the embodiment of the present disclosure. As shown in FIG. 25, the sensor device 1 of the modified example 10 is different from the embodiment in that the relay board 30 is not provided.
  • the sensor element 10 is directly bonded to the cooling surface 21a of the Pelche element 20. Further, the sensor element 10 and the package substrate 40 are directly electrically connected by the bonding wire 33.
  • the relay board 30 can be omitted, the heat transfer path from the sensor element 10 to the bottom heat dissipation area 43a can be shortened. Therefore, according to the modification 10, the heat dissipation of the sensor device 1 can be improved.
  • the sensor device 1 can be made smaller.
  • the sensor device 1 faces the perche element 20, the sensor element 10 (10A) thermally connected to the cooling surface 21a of the perche element 20, and the light receiving surface 10a of the sensor element 10 (10A).
  • a window member 60 provided and made of borosilicate glass is provided.
  • the detection sensitivity of the sensor device 1 can be improved.
  • an effective pixel region 11 for receiving the incident light from the window member 60 is arranged on the light receiving surface 10a of the sensor element 10 (10A).
  • the detection sensitivity of the sensor device 1 can be improved.
  • the sensor device 1 further includes a support member 70 arranged between the sensor element 10 (10A) and the window member 60. Further, the support member 70 has an opening 71 for passing incident light and a frame portion 72 for supporting the window member 60.
  • the frame portion 72 is arranged outside the effective pixel region 11 in a plan view.
  • the area of the opening 71 is larger than the area of the effective pixel area 11.
  • the window member 60 is arranged so as to cover the opening 71.
  • the inside of the recess 41 of the package substrate 40 can be stably and airtightly sealed.
  • the cooling surface 21a of the perche element 20 is larger than the surface of the sensor element 10 (10A) in the direction opposite to the light receiving surface 10a.
  • the entire sensor element 10 (10A) can be uniformly cooled by the Pelche element 20, so that the sensor element 10 (10A) can be operated more stably.
  • the sensor device 1 is further provided with a package substrate 40 which is thermally connected to the heat radiating surface 23a of the perche element 20 and accommodates the perche element 20 and the sensor element 10 (10A).
  • the heat generated by the sensor element 10 (10A) is efficiently dissipated to the outside via the Perche element 20 and the package substrate 40. be able to.
  • the sensor device 1 is arranged between the cooling surface 21a of the Pelche element 20 and the sensor element 10 (10A), and relays the electrical connection between the package substrate 40 and the sensor element 10 (10A).
  • a relay board 30 is further provided.
  • the sensor element 10 is a SWIR image sensor.
  • the sensor device 1 can perform sensing using light having a wavelength longer than visible light.
  • the terminal 45 of the package substrate 40 and the electrode 24 of the Pelche element 20 are electrically connected by the bonding wire 25
  • the terminal 45 and the electrode 24 are connected by the bonding wire 25. It is not limited to the case where it is done.
  • the terminal 45 and the electrode 24 may be electrically connected by a lead wire or the like.
  • the present technology can also have the following configurations.
  • (1) With the Perche element A sensor element that is thermally connected to the cooling surface of the Pelche element, A window member provided facing the light receiving surface of the sensor element and made of borosilicate glass, and a window member.
  • a sensor device equipped with (2) The sensor device according to (1), wherein an effective pixel region that receives incident light from the window member is arranged on a light receiving surface of the sensor element. (3) A support member arranged between the sensor element and the window member is further provided. The sensor device according to (2) above, wherein the support member has an opening through which the incident light passes and a frame portion for supporting the window member. (4) The sensor device according to (3), wherein the frame portion is arranged outside the effective pixel region in a plan view.
  • (6) The sensor device according to any one of (3) to (5) above, wherein the window member is arranged so as to cover the opening.
  • (7) The sensor device according to any one of (1) to (6), wherein the cooling surface of the Pelche element is larger than the surface in the direction opposite to the light receiving surface of the sensor element.
  • (8) The sensor device according to any one of (1) to (7) above, further comprising a package substrate that is thermally connected to the heat radiating surface of the Pelche element and houses the Pelche element and the sensor element.
  • the sensor device according to (8) further comprising a relay board arranged between the cooling surface of the Pelche element and the sensor element and relaying an electrical connection between the package substrate and the sensor element.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
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PCT/JP2020/047751 2019-12-27 2020-12-21 センサ装置 WO2021132184A1 (ja)

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JP2021567454A JPWO2021132184A1 (de) 2019-12-27 2020-12-21
CN202080078029.5A CN114679913A (zh) 2019-12-27 2020-12-21 传感器装置
US17/784,289 US20220381617A1 (en) 2019-12-27 2020-12-21 Sensor device
EP20906812.1A EP4084075A4 (de) 2019-12-27 2020-12-21 Sensorvorrichtung

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JP2019-239632 2019-12-27

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WO2023037787A1 (ja) * 2021-09-09 2023-03-16 富士フイルム株式会社 撮像装置及び撮像装置の制御方法
WO2023112691A1 (ja) * 2021-12-15 2023-06-22 ソニーセミコンダクタソリューションズ株式会社 半導体装置
WO2023227410A1 (fr) * 2022-05-25 2023-11-30 3D Plus Pièce de drainage thermique d'un module électronique 3d
WO2023243402A1 (ja) * 2022-06-15 2023-12-21 ソニーセミコンダクタソリューションズ株式会社 半導体装置及び電子機器
WO2023248346A1 (ja) * 2022-06-21 2023-12-28 ソニーセミコンダクタソリューションズ株式会社 撮像装置

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WO2023248346A1 (ja) * 2022-06-21 2023-12-28 ソニーセミコンダクタソリューションズ株式会社 撮像装置

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EP4084075A4 (de) 2023-02-01
US20220381617A1 (en) 2022-12-01
CN114679913A (zh) 2022-06-28

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