WO2021131847A1 - Signal processing device, amplification device, and replay device - Google Patents

Abstract

A signal processing device according to an embodiment of the present invention is provided with a first generation unit and a second generation unit. The first generation unit generates corrected data by correcting input data on the basis of feedback data. The second generation unit generates the feedback data by correcting output data from a comparator to which pulse signals in accordance with the corrected data are input.

Description

Signal processing equipment, amplification equipment, and playback equipment

This technology relates to signal processing devices, amplification devices, and reproduction devices that can be applied to signal amplification and the like.

Patent Document 1 describes a digital amplifier that amplifies an audio signal. In this digital amplifier, the voltage fluctuation of the power supply line is converted into data via an AD converter (Analog-to-Digital converter). The data of this voltage fluctuation is fed back to the variable attenuator circuit, and the volume level of the audio signal is controlled. By configuring such a feedback circuit, it is possible to suppress deterioration of sound quality due to fluctuations in the power supply line (paragraphs [0016] [0031] [0043] of Patent Document 1 and the like).

Japanese Unexamined Patent Publication No. 2003-273656

As described above, in the method in which the AD converter is included in the feedback circuit, the circuit configuration including the peripheral circuit becomes large, and the power consumption may increase. Therefore, there is a demand for a technology capable of reducing the size of the device and suppressing power consumption.

In view of the above circumstances, an object of the present technology is to provide a signal processing device, an amplification device, and a reproduction device capable of reducing the size of the device and suppressing power consumption.

In order to achieve the above object, the signal processing device according to one embodiment of the present technology includes a first generation unit and a second generation unit.
The first generation unit corrects the input data based on the feedback data and generates the correction data.
The second generation unit corrects the output data of the comparator to which the pulse signal corresponding to the correction data is input to generate the feedback data.

In this signal processing device, correction data is generated by correcting the input data using the feedback data. The pulse signal corresponding to the correction data is input to the comparator, and the output data of the comparator is corrected to generate feedback data. By configuring the feedback circuit using the comparator in this way, it is possible to reduce the size of the device and suppress the power consumption.

The second generation unit may correct the output data so that the shape of the pulse included in the pulse signal is restored.

The second generation unit may correct the slope of the rising or falling edge of the pulse in the output data.

The second generation unit may correct the amplitude of the pulse in the output data.

The second generation unit may correct the output data based on the circuit information about the output circuit that generates the output signal corresponding to the pulse signal.

The output circuit may include a switching amplifier that generates the pulse signal according to the correction data. In this case, the circuit information may include first information which is information about the switching amplifier.

The first information may include shape information of the pulse signal detected by AD conversion. In this case, the second generation unit may correct the output data based on the slope of the rise or fall of the pulse included in the pulse signal calculated from the shape information.

The first information may include information about the element characteristics of the switching amplifier, the dead time set in the switching amplifier, and at least one of the power supplies that drive the switching amplifier.

The output circuit may include a demodulation circuit that demodulates the pulse signal to generate the output signal. In this case, the circuit information may include a second piece of information that is information about the demodulation circuit.

The second information may include information regarding the output signal.

The second generation unit may generate the output data by sampling the signal output from the comparator at a second frequency higher than the first frequency representing the resolution of the pulse signal.

The output data may be binary data in which the pulse signal is binarized. In this case, the second generation unit may correct the level values of a plurality of data points included in the binary data.

The first generation unit may generate the correction data by subtracting the feedback data whose gain has been adjusted at a predetermined ratio from the input data.

The pulse signal may be a pulse width modulation type signal.

The input data may be voice data.

The amplification device according to one embodiment of the present technology includes a first generation unit, a switching amplifier, a comparator, and a second generation unit.
The first generation unit corrects the input data based on the feedback data and generates the correction data.
The switching amplifier generates a pulse signal according to the correction data.
The pulse signal is input to the comparator.
The second generation unit corrects the output data of the comparator to generate the feedback data.

The reproduction device according to one embodiment of the present technology includes a first generation unit, a switching amplifier, a demodulation circuit, a comparator, and a second generation unit.
The first generation unit corrects the voice data based on the feedback data and generates the correction data.
The switching amplifier generates a pulse signal according to the correction data.
The demodulation circuit demodulates the pulse signal to generate an audio signal.
The pulse signal is input to the comparator.
The second generation unit corrects the output data of the comparator to generate the feedback data.

It is a block diagram which shows the structural example of the digital amplifier which concerns on one Embodiment of this technique. It is a schematic diagram which shows an example of the signal of the PWM system. It is a schematic diagram for demonstrating the signal processing in a feedback path. It is a schematic diagram which shows the outline form of the amplification PWM signal and the comparator signal. It is a schematic diagram which shows the outline form of the comparator data and feedback data. It is a schematic diagram which shows an example of the shape information of the amplified PWM signal. It is a block diagram which shows the structural example of the feedback processing part. It is a block diagram which shows the structural example of the digital amplifier given as a comparative example.

Hereinafter, embodiments relating to the present technology will be described with reference to the drawings.

[Digital control amplifier configuration]
FIG. 1 is a block diagram showing a configuration example of a digital amplifier according to an embodiment of the present technology.
The digital amplifier 100 is an amplifier that amplifies and outputs an analog signal corresponding to the input data 1 which is a digital signal. The analog signal output from the digital amplifier 100 is used as an input for a predetermined element or circuit.

In the present embodiment, as an example of the digital amplifier 100, a digital audio amplifier that outputs an amplified audio signal 2 will be described. In this case, the input data 1 input to the digital amplifier 100 is audio data (digital audio source).
For example, by inputting the audio signal 2 output from the digital amplifier 100 to the reproduction device 10 such as headphones or speakers, it is possible to reproduce the audio. In the present embodiment, the digital amplifier 100 corresponds to an amplification device and a reproduction device.

As the method of the digital audio source which is the input data 1, for example, a pulse code modulation (PCM) method is used. That is, it can be said that the input data 1 is a PCM sound source. In the PCM method, for example, an analog waveform of voice is sampled at a predetermined sampling frequency, and the signal strength at each sampling point is quantized with a predetermined number of bits.
In the example shown in FIG. 1, the input data 1 is a PCM sound source of [1Fs, 16 bits]. Here, 1Fs is a sampling frequency, and 1Fs = 1 × Fs = 44.1 kHz. Further, 16 bits is the number of quantization bits in the PCM method.
In addition, the method of input data 1 is not limited, and any sound source format can be used. For example, pulse density modulation (PDM) type audio data or the like may be used as the input data 1.

As shown in FIG. 1, the digital amplifier 100 includes a feedback processing unit 20, a PWM conversion processing unit 21, a switching amplifier 22, a low-pass filter 23, a comparator 24, and a PWM shape correction processing unit 25. Of these, the processes executed by the feedback processing unit 20, the PWM conversion processing unit 21, and the PWM shape correction processing unit 25 are mainly digital processes for processing digital signals (data).

The feedback processing unit 20 executes feedback processing on the input data 1 using the feedback data 7. Specifically, the feedback processing unit 20 corrects the input data 1 based on the feedback data 7 to generate the correction data 3.
As shown in FIG. 1, the feedback data 7 is signal data generated by using the output of the subsequent stage (switching amplifier 22) of the digital amplifier 100. With reference to the feedback data 7, the input data 1 is corrected so that, for example, the waveform of the voice represented by the input data 1 and the waveform of the voice signal 2 match. Further, the corrected input data 1 is output as the corrected data 3.

In this way, in the digital amplifier 100, the feedback processing unit 20 realizes feedback control that controls the input value (target value) and the output value (feedback value) to match. This makes it possible to improve the stability of the audio signal 2 and the like, which is the output of the digital amplifier 100, and eliminate the influence of disturbance.
In the present embodiment, the feedback processing unit 20 corresponds to the first generation unit. Further, the feedback data 7 corresponds to the feedback data.

The PWM conversion processing unit 21 converts the correction data 3 into a PWM signal 4. Here, the PWM signal 4 is a pulse width modulation (PWM) type signal.
For example, the correction data 3 is converted into PWM data, and the PWM signal 4 is generated based on the data.

FIG. 2 is a schematic diagram showing an example of a PWM signal. FIG. 2A is a schematic graph showing an outline of the PWM signal 4 generated by the PWM conversion processing unit 21. The horizontal axis of the graph is time T, and the vertical axis is level. The amplitude level of the PWM signal 4 is represented by, for example, a voltage V.
As shown in FIG. 2A, the PWM signal 4 is a signal including a plurality of pulses and the width W of each pulse is modulated. The cycle T of the PWM signal 4 (for example, the cycle in which the pulse rises) is set to a constant cycle, and the width W of each pulse is modulated in the cycle T. That is, the timing at which each pulse falls is modulated according to the correction data 3.

_{The frequency F 0} of the master clock of the system used to generate the PWM signal 4 is set to, for example, F ₀ = 512 × Fs = 22.5792 MHz. Further, the width W of each pulse is modulated in units of time represented by the reciprocal of the _{frequency F 0.} That is, it can be said that the frequency F ₀ is a frequency representing the resolution of the PWM signal 4. For example, the higher the frequency F ₀ , the shorter the time representing the modulation unit of the PWM signal 4, and the higher the resolution.
The frequency F _{0 of the} master clock is not limited, and for example, the frequency at which the input data 1 can be appropriately converted may be appropriately set within a practical range.
Further, the amplitude of the PWM signal 4 (pulse voltage V ₀ ) is set to a voltage value that can be output by, for example, a system that performs digital processing. Further, the amplitude of each pulse included in the PWM signal 4 is set to be constant.

The switching amplifier 22 is a power amplification element that amplifies the power of the PWM signal 4. For example, the amplitude (voltage) of each pulse of the PWM signal 4 is amplified. Hereinafter, the amplified PWM signal 4 will be referred to as an amplified PWM signal 5.
The switching amplifier 22 has a switching circuit configured by using a semiconductor element or the like. This switching circuit is connected to, for example, a predetermined power supply, and is configured to output an _{amplified voltage VA in the ON state.} Further, the switching circuit is _{configured so that the amplification voltage VA} can be adjusted according to the amplification factor.

FIG. 2B is a schematic graph showing an outline of the amplified PWM signal 5 generated by the switching amplifier 22. FIG. 2B schematically shows an outline of the amplified PWM signal 5 in which the PWM signal 4 shown in FIG. 2A is amplified.
In the switching amplifier 22, the switching circuit is switched ON and OFF by using the pulse of the PWM signal 4 which is the input. As a result, the output of the switching amplifier 22 becomes an amplified PWM signal 5 including a pulse having the same width W as each pulse of the PWM signal 4 and whose amplitude is amplified to the amplified voltage _VA.

In this way, the switching amplifier 22 amplifies the PWM signal 4 according to the correction data 3 and generates the amplified PWM signal 5 according to the correction data 3. Therefore, the amplified PWM signal 5 is a PWM signal. In this embodiment, the amplified PWM signal 5 corresponds to a pulse signal.
In the digital amplifier 100, the amplified PWM signal 5 is a signal converted into an audio signal 2 described later, and is also used as a feedback signal for performing feedback processing.
In the switching amplifier 22, the shape of the pulse may be distorted depending on its characteristics and the like. For example, it is conceivable that the rise and fall of the pulse are inclined. FIG. 2B is a graph emphasizing the distortion of the shape of such a pulse.

By using the switching amplifier 22, for example, the current loss when the switching circuit is OFF is suppressed, and it is possible to configure an amplification device with low power consumption. Further, the switching circuit can be configured by using a semiconductor element, and the element can be miniaturized.
The specific configuration of the switching circuit is not limited. For example, a switching circuit composed of semiconductor elements such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) is used.

The low-pass filter 23 cuts the high frequency component of the amplified PWM signal 5 and demodulates the amplified PWM signal 5 which is a pulse signal. That is, the low-pass filter 23 outputs an analog signal obtained by demodulating the amplified PWM signal 5.
The amplified PWM signal 5 is a signal modulated according to the voice waveform represented by the voice data which is the input data 1. Therefore, the signal obtained by demodulating the amplified PWM signal 5 becomes an analog voice signal 2 representing a voice waveform. In this way, the low-pass filter 23 outputs the audio signal 2 in which the audio data is demodulated. In this embodiment, the low-pass filter 23 corresponds to a demodulation circuit.
As the low-pass filter 23, for example, a passive low-pass filter configured by using a coil element, a capacitor element, a resistance element, or the like is used. Alternatively, an active low-pass filter using an operational amplifier or the like may be used. In addition, the specific configuration of the low-pass filter 23 is not limited, and any low-pass filter configured to be able to demodulate the amplified PWM signal 5 may be used.

In the present embodiment, the switching amplifier 22 and the low-pass filter 23 constitute a signal output unit 30 that generates an audio signal 2 corresponding to the amplified PWM signal 5. The signal output unit 30 is a circuit that generates a signal (audio signal 2) that is the final output of the digital amplifier 100. In this embodiment, the signal output unit 30 corresponds to an output circuit. The audio signal 2 corresponds to an output signal.

The comparator 24 is a comparator that compares an input signal with a predetermined threshold value. As shown in FIG. 1, the amplification PWM signal 5 output from the switching amplifier 22 is input to the comparator 24. Further, the comparator 24 outputs a comparator signal 6 in which the amplified PWM signal 5 is compared with the threshold value.
A reference voltage is set in the comparator 24, for example, as a predetermined threshold value. The reference voltage is appropriately set so that, for example, the rising and falling edges of the pulse of the amplified PWM signal 5 can be appropriately detected.
This reference voltage is compared with the voltage of the amplified PWM signal 5. For example, when the voltage of the amplified PWM signal 5 is higher than the reference voltage, the power supply voltage on the + side is output, and when the voltage of the amplified PWM signal 5 is lower than the reference voltage, the power supply voltage on the-side is output ( See FIGS. 3 and 4 etc.).
Therefore, the signal output from the comparator 24 includes a rectangular pulse corresponding to the pulse of the amplified PWM signal 5, and is represented by 1 (+ side power supply voltage) or 0 (-side power supply voltage) of the output of the comparator 24. It becomes a digital signal.
The shape of the pulse of the signal output from the comparator 24 is different from the shape of the pulse of the amplified PWM signal 5. This point will be described later.

The PWM shape correction processing unit 25 corrects the comparator data to generate feedback data 7.
Here, the comparator data is, for example, a digital signal generated by sampling the comparator signal 6 at a predetermined sampling frequency, and corresponds to the output data of the comparator 24. For example, a digital signal obtained by binarizing the comparator signal 6 to 0 and 1 becomes comparator data (see FIG. 5).

The PWM shape correction processing unit 25 corrects the comparator data so that the shape of the pulse included in the amplified PWM signal 5 is restored. That is, the feedback data 7 in which the shape of the pulse of the amplified PWM signal 5 is restored is generated.
As a result, the feedback processing unit 20 can perform processing equivalent to the feedback processing based on the amplified PWM signal 5.

In this embodiment, the comparator data is corrected based on the circuit information about the signal output unit 30. Here, the circuit information is, for example, information related to the switching amplifier 22 and the low-pass filter 23 constituting the signal output unit 30.
In this way, by correcting the comparator data using the circuit information of the circuit that outputs the audio signal 2 (signal output unit 30), it is possible to generate appropriate feedback data 7 that matches the characteristics of the actual circuit. It will be possible. In the present embodiment, the PWM shape correction processing unit 25 corresponds to the second generation unit.

The circuit information is generated by measuring and analyzing, for example, the operation of the signal output unit 30 and the characteristics of each unit. For example, circuit information is generated in the process of an operation test of the digital amplifier 100, and processing parameters and the like of the PWM shape correction processing unit 25 are set based on the information.
The circuit information includes amplifier information which is information about the switching amplifier 22. The amplifier information is, for example, the characteristics of a switching circuit, information on an amplified signal, or the like. In this embodiment, the amplifier information corresponds to the first information.
Further, the circuit information includes filter information which is information about the low-pass filter 23. The filter information includes, for example, the characteristics of each element constituting the low-pass filter 23, information on the signal to be demodulated, and the like. In this embodiment, the filter information corresponds to the second information.

In FIG. 1, the AD converter 11 and the analysis unit 12 are shown by dotted lines. The AD converter 11 and the analysis unit 12 are blocks that acquire and analyze circuit information necessary for the PWM shape correction processing unit 25. The AD converter 11 and the analysis unit 12 are used only when generating circuit information, and are not mounted on the actual digital amplifier 100. That is, these blocks are used only in the development stage and the manufacturing stage, and do not affect the system size.
The AD converter 11 performs AD conversion (Analog to Digital conversion) of the output of the switching amplifier 22 (amplification PWM signal 5) and the output of the low-pass filter 23 (audio signal 2) to generate digital data of each output.
The analysis unit 12 analyzes, for example, digital data generated by the AD converter 11, measurement data obtained by measuring the characteristics of the switching amplifier 22, and the like.
The PWM shape correction processing unit 25 utilizes the information generated by the AD converter 11 and the analysis unit 12 to provide a feedback signal (amplified PWM signal) including error components such as distortion and noise generated by a switching amplifier or the like from the output of the comparator 24. 5) is restored.
The method of correcting the comparator data based on the circuit information (amplifier information and filter information) will be described in detail later.

In the present embodiment, the feedback processing unit 20, the PWM conversion processing unit 21, the comparator 24, and the PWM shape correction processing unit 25 perform signal processing for generating a signal (PWM signal 4) to be output to the signal output unit 30. The signal processing unit 31 is configured.
The signal processing unit 31 is configured by using an element capable of digital arithmetic processing such as a DSP (Digital Signal Processor). The signal processing unit 31 may be configured as one processing unit on the same substrate, or each block may be configured by using a dedicated IC (Integrated Circuit) or the like. In this embodiment, the signal processing unit 31 corresponds to a signal processing device.

[Basic operation of digital amplifier]
The digital amplifier 100 includes two signal paths, a reproduction path from the input data 1 to the reproduction of the audio signal 2, and a feedback path for performing feedback processing on the reproduction path. Hereinafter, the basic operation of the digital amplifier 100 will be described along each signal path.

First, the reproduction route excluding the feedback route will be described.
The PCM type input data 1 of [1Fs, 16 bits], which is a digital audio source, is input to the feedback processing unit 20. The feedback processing unit 20 performs predetermined signal processing on the input data 1 based on the feedback data 7, and outputs the correction data 3.
The correction data 3 is input to the PWM conversion processing unit 21 and converted into a PWM signal (PWM signal 4). The PWM signal 4 is a signal for driving a switching amplifier 22 that amplifies power as a digital amplifier. In the example shown in FIG. 1, the PWM signal 4 of [512 Fs, 1 bit] is output.
The PWM signal 4 is amplified in the amplitude direction by the switching amplifier 22, and the amplified PWM signal 5 is output. The amplification factor and the like in the switching amplifier 22 are appropriately set.
The amplified PWM signal 5 is transmitted separately in two signal paths, one is input to the low-pass filter 23 and the other is input to the comparator 24. The amplified PWM signal 5 input to the low-pass filter 23 is demodulated by passing through the low-pass filter 23, and is output as an analog audio signal (audio signal 2).
The audio signal 2 is input to the playback device 10 connected to the digital amplifier 100. The audio signal 2 drives a speaker mounted on the playback device 10 to output audio.

Next, the feedback route will be described.
FIG. 3 is a schematic diagram for explaining signal processing in the feedback path. FIG. 3 shows the waveform of the pulse in the signal processing of the feedback path along the same time axis. In practice, each signal processing is performed in turn along the feedback path.
The amplified PWM signal 5 (first stage from the top in the figure) output from the switching amplifier 22 is input to the comparator 24. In the comparator 24, the voltage of the amplified PWM signal 5 is compared, and the comparator signal 6 (second stage from the top in the figure) including the rectangular pulse corresponding to the pulse of the amplified PWM signal 5 is output. The input / output of these comparators 24 (amplified PWM signal 5 and comparator signal 6) are analog voltage signals.
The comparator signal 6 is input to the PWM shape correction processing unit 25, sampled at a predetermined sampling frequency, and converted into comparator data 8 (third stage from the top in the figure). The comparator data 8 is a digital signal represented by the Hi and Low levels of logic in the device.
The PWM shape correction processing unit 25 executes correction processing of the comparator data 8 to generate feedback data 7 (fourth stage from the top in the figure) in which the shape of the pulse of the amplified PWM signal 5 which is a feedback signal is restored. To. The feedback data 7 is a digital signal represented by a predetermined number of bits (16 bits in this case).
The feedback data 7 is input to the feedback processing unit 20 and is used for feedback processing for correcting the input data 1. This makes it possible to output the correction data 3 that can suppress the distortion of the pulse generated by the switching amplifier 22, for example.
In the following, the operation of each part in the feedback path will be specifically described.

[Comparator operation]
FIG. 4 is a schematic diagram showing an outline of the amplified PWM signal 5 and the comparator signal 6. Here, the operation of the comparator 24 that generates the comparator signal 6 from the amplified PWM signal 5 will be described.
In FIG. 4, one pulse included in the amplified PWM signal 5 is shown by a thick solid line, and one pulse that becomes the comparator signal 6 is shown by a thin solid line.
As described above, the amplified PWM signal 5 takes a certain amount of time for the rise and fall of the pulse depending on the characteristics of the switching amplifier 22, and becomes a signal in which both ends of the pulse are inclined (see FIG. 2B). The comparator 24 generates a rectangular pulse in which the time required for rising and falling is shorter than that of the pulse of the amplified PWM signal 5.

A first reference voltage V ₁ and a second reference voltage V ₂ lower than the first reference voltage V ₁ are set in the _{comparator 24 (V 1} > V ₂ ). The first reference voltage V ₁ is a threshold level on the Hi side that is referred to when the output of the comparator 24 is switched to the power supply voltage (Hi level) on the + side. The second reference voltage V ₂ is the threshold level on the Low side that is referred to when the output of the comparator 24 is switched to the power supply voltage (Low level) on the − side. The negative side supply voltage is typically set to GND level.

For example, the pulse of the amplified PWM signal 5 is input, and the voltage of the comparator signal 6 is switched to the Hi level at the timing T _{1 when the voltage of the amplified PWM signal 5 exceeds the first reference voltage V 1.} As a result, the rising edge of the pulse of the amplified PWM signal 5 is detected.
After the timing T ₁ , the voltage of the amplified PWM signal 5 _{rises to the amplified voltage VA} , and then the voltage drops according to the fall of the pulse. At this time, the voltage of the comparator signal 6 is switched to the Low level at the timing T ₂ when the voltage of the amplified PWM signal 5 _{exceeds the second reference voltage V 2.} As a result, the fall of the pulse of the amplified PWM signal 5 is detected.
As a result, the comparator signal 6 including the rectangular pulse corresponding to the pulse of the amplified PWM signal 5 is generated.

The voltage of the amplified PWM signal 5 may fluctuate due to the influence of noise and the like. For example, it is conceivable that the voltage of the amplified PWM signal 5 fluctuates after the _{timing T 1 and temporarily becomes lower than the first reference voltage V 1.} Even in such a case, the output of the comparator 24 is not switched to the Low level unless the voltage of the amplified PWM signal 5 becomes _{lower than the second reference voltage V 2.} This also applies when the pulse of the amplified PWM signal 5 falls.
The first and second reference voltages V ₁ and V ₂ are appropriately set according to, for example, the noise level of the amplified PWM signal 5 so that an unintended oscillation operation or the like does not occur.
As a result, the amplified PWM signal 5 can be appropriately converted into the comparator signal 6, and stable feedback operation is possible.

[Generation of comparator data]
FIG. 5 is a schematic diagram showing an outline of the comparator data 8 and the feedback data 7. _{FIG. 5 schematically shows each data point corresponding to times t 1} to t ₉ and its level value (Lv) in the comparator data 8 and the feedback data 7. Of these, time t ₆ corresponds to _{timing T 1} shown in FIG. These data points are data points that represent the rise of one pulse.
The comparator data 8 is represented by black data points, and the level value is represented by the vertical axis on the left side. The feedback data 7 is represented by gray data points, and the level value is represented by the vertical axis on the right side. The level values represented by the vertical axes on the left and right sides are independent of each other.

First, the process of generating the comparator data 8 from the comparator signal 6 will be described.
Comparator signal 6 input to the PWM shape correction process section 25 is sampled at a predetermined sampling frequency F _1. For example, each data point of the comparator data 8 shown in FIG. 5, is acquired at time intervals represented by the reciprocal of the sampling frequency F _1.
Specifically, when the comparator signal 6 is at the Low level (time t ₁ to t ₅ ), the value of the data point is set to 0 (Low level of the logic circuit). When the comparator signal 6 is at Hi level (time t ₆ to t ₉ ), the value of the data point is set to 1 (Hi level of the logic circuit).
In this way, the comparator data 8 obtained by sampling the comparator signal 6 of the amplified PWM signal 5 becomes binary data obtained by binarizing the amplified PWM signal 5.

The sampling frequency F ₁ is set to a value higher than _{the frequency F 0} of the master clock of the PWM conversion processing unit 21 _{(F 1} > F ₀ ).
As described with reference to FIG. 2A, the frequency F _{0 of the} master clock is a frequency representing the resolution of the PWM signal 4. Therefore, the resolution of the amplified PWM signal 5 in which the PWM signal 4 is amplified is also represented by the _{frequency F 0.}
In this way, the PWM shape correction processing unit 25 samples the comparator signal 6 output from the comparator 24 at a sampling frequency F _{1 higher than the frequency F 0 of the} master clock representing the resolution of the amplified PWM signal 5, and the comparator data. 8 is generated.
In the present embodiment, the frequency F _{0 of the} master clock corresponds to the first frequency, and the sampling frequency F ₁ corresponds to the second frequency.

In the example shown in FIG. 1, the sampling frequency F ₁ of the comparator signal 6 is set to F ₁ = 2048 × Fs = 90.316 MHz. Therefore, the comparator data 8 becomes a digital signal of [2048Fs, 1 bit]. In this way, the comparator signal 6 is sampled at a _{frequency F 1 that is sufficiently higher than the frequency F 0} (512 × Fs) of the master clock, which represents the resolution of the amplified PWM signal.
If the comparator signal 6 is sampled at a low frequency, the resolution of the amplified PWM signal 5 is thinned out and acquired, so that a new error component (distortion or noise) may occur.
On the other hand, in the present embodiment, by _{setting the sampling frequency F 1} to be higher than the resolution of the amplified PWM signal 5 (frequency F ₀ ), it is possible to avoid a situation in which the modulation unit of the amplified PWM signal 5 is thinned out. .. This makes it possible to appropriately acquire the degree of modulation of the amplified PWM signal 5 (PWM signal 4) and convert it into data.
In this way, the PWM shape correction processing unit 25 does not directly correct the comparator signal 6, but once samples at a high sampling frequency F ₁ , and then executes the correction processing.

[Generation of feedback data]
Subsequently, a process of correcting the comparator data 8 to generate the feedback data 7 will be described.
The PWM shape correction processing unit 25 corrects the level values of a plurality of data points included in the binary data which is the comparator data 8. Specifically, a level value represented by a predetermined number of bits is set at each data point of the comparator data 8. The data in which the level value of a predetermined number of bits is set for each data point in this way is generated as the feedback data 7.

Here, for example, a level value expressed in 16 bits is used. In this case, the feedback data 7 becomes a digital signal of [2048Fs, 16 bits]. In the example shown in FIG. 5, the level value of each data point is represented in 7 stages. For example, when the number of data points is large, the level value of each data point is divided into finer levels.
The method of expressing the level value is not limited, and for example, an arbitrary number of bits or the like may be set as the resolution of the level value according to the accuracy of the feedback processing, the processing capacity of the apparatus, or the like.
As described above, it can be said that the process of correcting the level value of the data point is the shape correction process of correcting the shape of the feedback data 7 so as to restore the shape of the pulse of the amplified PWM signal 5.

[Shape correction processing]
The PWM shape correction processing unit 25 corrects the slope of the rise or fall of the pulse in the comparator data 8.
As shown in FIG. 5, since the comparator data 8 is represented by a binary value of Hi level or Low level, the shape of the pulse is rectangular. The level value of each data point is corrected so as to give an inclination to the rising and falling edges of such a rectangular pulse.
This makes it possible to restore a gradient pulse similar to the amplified PWM signal 5 actually output from the switching amplifier 22.

Note that the shape correction process may be performed on both the rising and falling slopes of the pulse, or may be performed on only one of them. For example, it is possible to improve the accuracy of the feedback processing by correcting both inclinations. Further, for example, when correcting one of the inclinations, it is possible to reduce the amount of calculation, improve the operating speed, and reduce the power consumption.

Further, the PWM shape correction processing unit 25 corrects the amplitude of the pulse in the comparator data 8. As described above, in the shape correction process, a level value represented by a predetermined number of bits is set for each data point of the comparator data 8. A level value (amplitude level) representing the pulse amplitude in the feedback data 7 is set within the range of the level value that can be expressed by the predetermined number of bits. This makes it possible to appropriately adjust the pulse height of the feedback data 7.

FIG. 6 is a schematic diagram showing an example of the shape information of the amplified PWM signal 5. The shape information 13 is data generated by AD-converting the amplified PWM signal 5 using the AD converter 11 shown in FIG. In FIG. 6, a schematic graph showing shape information 13 showing the rise of the pulse of the amplified PWM signal 5 is shown by a solid black line.
Hereinafter, as an example of the shape correction process, a process using the shape information 13 of the amplified PWM signal 5 will be described.

The shape information 13 is data detected by AD-converting the actual shape of the amplified PWM signal 5 using the AD converter 11. The sampling frequency of the AD converter 11 is set to a value equal to or higher than the _{sampling frequency F 1} when generating the comparator data 8, for example. For example, when F ₁ = 2048 Fs, the sampling frequency of the AD converter 11 is set to a high frequency such as 2048 Fs or more. This makes it possible to correct the level value of each data point of the comparator data 8 with high accuracy.
The shape information 13 is an example of amplifier information regarding the switching amplifier 22. That is, the amplifier information includes the shape information 13 in which the shape of the amplified PWM signal 5 is detected by AD conversion.

The shape information 13 thus acquired is analyzed by the analysis unit 12. Specifically, the slope of the shape (pulse) of the amplified PWM signal 5 is calculated.
For example, from the shape information 13, data points corresponding to the upper end and the lower end of the rising edge of the pulse are acquired. Then, the slope of the straight line 14 (dotted line in the figure) connecting the data points is calculated as the slope of the rising edge of the pulse. It can be said that the slope of the straight line 14 represents the time until the signal rises from the Low level to the Hi level.
In addition, the analysis unit 12 can also calculate the slope of the fall of the pulse and the like by using the above method.
The inclination value calculated here is stored as a parameter of the shape correction processing in, for example, a memory referred to by the PWM shape correction processing unit 25.

In this method, it is conceivable that error information that is a difference from the ideal waveform (rectangular waveform) such as ringing (voltage fluctuation at the upper end and lower end of the pulse) other than the inclination is missing. However, in the PWM shape correction processing unit 25, since the band is limited by a low-pass filter or the like for data processing, the slope of the straight line 14 described above can be treated as the slope of the pulse.
In addition, the method of calculating the slope of the pulse is not limited.

The PWM shape correction processing unit 25 corrects the comparator data 8 based on the inclination of the rise or fall of the pulse included in the amplified PWM signal 5 calculated from the shape information 13. That is, the PWM shape correction processing unit 25 sets the level value so as to give the comparator data 8 the inclination of the straight line 14, and generates the feedback data 7.
For example, the level value of each data point is set so that the time at which the level value of the data point rises in the feedback data 7 is equal to the time represented by the inclination of the straight line 14.

For example, in FIG. 5, the level values of the data points at _{times t 3} to t _{8 are set to increase in this order.} At this time, the level value of each data point is set according to the inclination of the straight line 14 shown in FIG. 6, and the time from time t _{3 to time t 8} (that is, the rise time of the pulse) is the straight line 14 shown in FIG. It is the same as the rise time represented by the inclination of.
As a result, the slope of the pulse of the feedback data 7 becomes the same slope as the slope of the pulse of the actual amplified PWM signal 5. As a result, the feedback data 7 becomes a digital signal in which the slope of the pulse of the amplified PWM signal 5 is restored.
The pulse amplitude (amplitude level) in the feedback data 7 is set based on, for example, a voltage value representing the pulse amplitude of the amplified PWM signal 5 in the shape information 13 shown in FIG. For example, when the voltage value representing the amplitude is large, the amplitude level is set high, and when the voltage value is small, the amplitude level is set low.
This makes it possible to set the amplitude level according to the amplitude of the actual signal.

_{As described above, in the digital amplifier 100, the comparator data 8 sampled at the sampling frequency F 1} higher than the resolution of the amplified PWM signal 5 which is the feedback signal is corrected by using the analysis result by the analysis unit 12. This makes it possible to restore the pulse, which is an error component of the amplified PWM signal 5 input to the comparator 24, in a stepped manner.

In the above, the shape correction process using the shape information 13 (amplifier information) of the amplified PWM signal 5 has been described. The shape correction process may be executed based on, for example, other amplifier information, filter information, or the like.

The amplifier information includes information regarding the element characteristics of the switching amplifier 22. Here, the element characteristics are, for example, element parameters (on resistance between drain and source, charge capacitance characteristics, switching characteristics, etc.) of an FET or the like mounted on the switching amplifier 22.
For example, the amplitude of the amplified PWM signal 5 may change depending on the on-resistance. In this case, the amplitude level is set according to the on-resistance. Further, the shape of the pulse may be deformed depending on the capacitance component represented by the charge capacitance characteristic. Such a shape change may be corrected. Further, it is conceivable that the slope of the pulse changes depending on the switching characteristics. In this case, the slope of the feedback data 7 is corrected based on the switching characteristics.

Further, the amplifier information includes information on the dead time set in the switching amplifier 22. Here, the dead time is a time set in order to prevent the phenomenon that the high side and the low side are turned on at the same time in the switching amplifier 22. Due to such dead time, the slope of the pulse may change. In this case, the slope of the feedback data 7 is corrected based on the dead time.

Also, the amplifier information includes information about the power supply that drives the switching amplifier. Examples of the information on the power supply include information on the power supply quality such as the noise level and the fluctuation level of the power supply. For example, power supply noise may appear as the waveform of the amplified PWM signal 5. It is also possible to generate feedback data 7 so as to reproduce such a waveform of power supply noise.

The filter information includes information about the audio signal 2 in which the amplified PWM signal 5 is demodulated. For example, using, for example, an AD converter 11, the audio signal 2 which is an analog audio signal for driving the speaker is AD-converted, and the shape information of the audio signal 2 is acquired. Then, the analysis unit 12 analyzes the quality of the audio signal 2. The quality of the audio signal 2 is distortion, noise characteristics, etc. in the analog waveform.
In the shape correction process, the feedback data 7 is generated so that the distortion of the audio signal 2 and the like are corrected. This makes it possible to make corrections according to the characteristics of the low-pass filter 23, and for example, it is possible to output an audio signal 2 or the like that accurately reproduces the audio waveform of the input data 1.

The shape correction process based on the amplifier information and the filter information may be executed independently, or a process in which each correction is combined may be executed.
The feedback data 7 generated by the shape correction process is input to the feedback processing unit and used for the feedback process for the input data 1.
As described above, in the digital amplifier 100, the analog feedback signal (amplified PWM signal 5) including the error component and the like is binarized via the comparator 24. This binarized data (comparator data 8) is corrected according to the characteristics of the switching amplifier 22 and the low-pass filter 23, and feedback data 7 in which error components and the like are restored is generated. This enables high quality feedback processing.

[Feedback processing]
FIG. 7 is a block diagram showing a configuration example of the feedback processing unit 20. FIG. 7 schematically shows a processing block constituting the feedback processing unit 20.
The feedback processing unit 20 includes an upsampling unit 40, a downsampling unit 41, a low-pass filter 42, a gain adjusting unit 43, and an addition processing unit 44. Each part of the feedback processing unit 20 is a functional block that performs digital processing.

The upsampling unit 40 upsamples the input data 1 to increase the sampling rate. The downsampling unit 41 downsamples the feedback data 7 to lower the sampling rate. The outputs of the upsampling unit 40 and the downsampling unit 41 are sampled so as to have the same sampling rate.
The low-pass filter 42 removes noise components included in a band other than the feedback-capable frequency band from the downsampled feedback data 7.
The gain adjusting unit 43 adjusts the gain to adjust the level value of the feedback data 7 at a predetermined ratio. The rate of gain adjustment is appropriately set according to, for example, the amplification factor of the switching amplifier 22.
The addition processing unit 44 subtracts the gain-adjusted feedback data 7 from the upsampled input data 1, and outputs the correction data 3.

In the example shown in FIG. 7, the input data 1 of [1Fs, 16 bits] is input to the upsampling unit 40. This input data 1 is upsampled to the data of [64 Fs, 24 bits].
Further, the feedback data 7 of [2048Fs, 16 bits] is input to the downsampling unit 41. The feedback data 7 is downsampled to the same [64Fs, 24bit] data as the input data 1 after upsampling.
The downsampled feedback data 7 passes through the low-pass filter 42 to remove noise components, is input to the gain adjusting unit 43, and the gain is adjusted at a predetermined ratio.
The addition processing unit 44 subtracts the gain-adjusted feedback data 7 from the upsampled input data 1, and generates the correction data 3.

In this way, the feedback processing unit 20 generates the correction data 3 by subtracting the feedback data 7 whose gain is adjusted at a predetermined ratio from the input data 1.
The feedback data 7 is a signal in which the shape of the pulse of the output signal (amplified PWM signal 5) in the subsequent stage of the digital amplifier 100 is restored as described above. That is, it can be said that the feedback data 7 is a signal in which an error component is added to the component of the ideal output signal.
By applying feedback gain to the feedback data 7 including the output signal and the error component at a predetermined ratio and returning the data to the input data 1, it is possible to generate the correction data 3 capable of suppressing noise.
The configuration of the feedback processing unit 20, the specific content of the feedback processing, and the like are not limited, and any processing that can generate the desired correction data 3 may be executed.

FIG. 8 is a block diagram showing a configuration example of a digital amplifier given as a comparative example. In the digital amplifier 110, the audio signal 2 for driving the speaker is used as the feedback signal, and the pre-low-pass filter 111 and the AD converter 112 are provided in the feedback path.
Further, a feedback processing unit 113, a PWM conversion processing unit 114, a switching amplifier 115, and a low-pass filter 116 are provided in the reproduction path of the digital audio source (input data 1).

An analog signal including error components such as distortion and noise generated by the switching amplifier 115 or the like is input to the pre-low pass filter 111 as an audio signal 2 for driving the speaker. In the pre-low pass filter 111, the pass band is limited so as to remove high frequency switching noise and the like caused by the digital amplifier 110 in order to stably operate the feedback system.
The audio signal 2 whose band is limited by the pre-low pass filter 111 is input to the AD converter 112 and subjected to AD conversion. In the AD converter 112, for example, a process of quantizing into a pulse density modulated signal (PDM signal) of [64 Fs, 1 bit] is executed.
The quantized audio signal 2 (output of the AD converter 112) is input to the feedback processing unit 113 as a digital signal (feedback data) including an error component. In the feedback processing unit 113, signal processing for reducing the error component is performed together with the input data 1.

As described above, when the AD converter 112 is used for the feedback path, power for driving the AD converter 112 is required, which may increase the power consumption. Further, it is necessary to provide a peripheral circuit including an AD converter 112, a pre-low pass filter 111, and the like, which may increase the system size.
Further, the digital amplifier 110 requires an AD converter 112 corresponding to the switching noise of the switching amplifier 115, which increases the design difficulty and the number of parts. Further, in order to bring out the performance of the AD converter 112, it is necessary to tune an external passive component and select a high-performance device, which may increase the development cost.
Further, since the pre-low-pass filter 111 is required as the preprocessing of the input of the AD converter 112, there is a possibility that extra noise components are mixed (distortion of the audio signal 2 etc.) and the delay time of the feedback path is increased. .. As a result, in the configuration including the AD converter 112, the feedback effect may be reduced or the feedback band may be limited.

On the other hand, in the digital amplifier 100 according to the present embodiment, the amplified PWM signal 5 which is a feedback signal is converted into the comparator data 8 via the comparator 24. That is, it can be said that the digital amplifier 100 uses the comparator 24 to perform AD conversion of the feedback signal. In this way, in this configuration, it is possible to configure a feedback path that does not include an AD converter.

In the AD conversion using only the comparator 24, error components such as distortion and noise included in the signal to be acquired as the feedback signal (amplified PWM signal 5) are missing.
Therefore, in the digital amplifier 100, the output of the comparator 24 _{is sampled by the high frequency F 1} , and the shape correction process using the circuit information regarding the switching amplifier 22 and the low-pass filter 23 is executed.
By this shape correction process, data (feedback data 7) including an error component similar to the feedback signal is generated. This makes it possible to construct a feedback system capable of appropriately executing feedback processing on the input data 1 without using the AD converter 112 as shown in FIG.

As described above, in the digital amplifier 100 according to the present embodiment, the correction data 3 obtained by correcting the input data 1 using the feedback data 7 is generated. The amplified PWM signal 5 corresponding to the correction data 3 is input to the comparator 24, and the comparator data 8 which is the output data of the comparator 24 is corrected to generate the feedback data 7. By configuring the feedback circuit using the comparator 24 in this way, it is possible to reduce the size of the device and suppress the power consumption.

Generally, in the digital amplifier 100, a feedback system is adopted in order to improve the performance of the device. With the recent progress in miniaturization of products, low power consumption and miniaturization of device size are expected by adopting digital amplifiers. However, as shown in FIG. 8, when a feedback system including an AD converter 112 is used, the merit of the digital amplifier 100 may not be utilized depending on the construction method thereof.

In the present embodiment, the feedback system is constructed by using the comparator 24 without using the AD converter which is an AD conversion device. As a result, power consumption can be suppressed and the system size can be made compact.
Further, since the AD converter is not used, it is not necessary to provide the necessary pre-low pass filter in front of the AD converter. This makes it possible to prevent the mixing of extra noise components. In addition, since the delay time caused by the pre-low pass filter does not occur, the feedback effect can be expected to be improved as the delay is reduced.

Further, in the present embodiment, an error required in the feedback system from the output of the comparator 24 is utilized by utilizing parameters related to the switching amplifier 22 or the like which is a component of the digital amplifier 100 (such as the gradient of the pulse of the amplified PWM signal 5). Feedback data 7 including the components is generated. This enables highly accurate feedback processing that matches the waveform of the actual amplified PWM signal 5.

The sampling of the comparator signal 6 output from the comparator 24 is executed at a _{frequency F 1} higher than the resolution of the pulse width modulation in the digital amplifier 100. As a result, it is possible to secure a sufficient band for reproducing the error component, and it is possible to bring the feedback data 7 closer to the actual waveform. As a result, it is possible to sufficiently improve the accuracy of the feedback processing.

<Other Embodiments>
The present technology is not limited to the embodiments described above, and various other embodiments can be realized.
In the above, the digital amplifier 100 mainly configured as an audio amplifier has been described. This technology can be applied to any digital control amplifier, inverter, or the like.
For example, a switching amplifier or the like is used when generating a control signal used for motor control. A feedback system using a comparator may be configured by using the output of such a switching amplifier as a feedback signal. Thereby, it is possible to easily realize the feedback processing for the control signal.
In addition to this, by using a feedback system using a comparator, it is also possible to correct a control signal or the like output by inverter control.

It is also possible to combine at least two feature parts among the feature parts related to the present technology described above. That is, the various feature portions described in each embodiment may be arbitrarily combined without distinction between the respective embodiments. Further, the various effects described above are merely examples and are not limited, and other effects may be exhibited.

In the present disclosure, "same", "equal", "orthogonal", etc. are concepts including "substantially the same", "substantially equal", "substantially orthogonal", and the like. For example, a state included in a predetermined range (for example, a range of ± 10%) based on "exactly the same", "exactly equal", "exactly orthogonal", etc. is also included.

The present technology can also adopt the following configurations.
(1) A first generation unit that corrects input data based on feedback data and generates correction data, and
A signal processing device including a second generation unit that corrects the output data of a comparator to which a pulse signal corresponding to the correction data is input and generates the feedback data.
(2) The signal processing device according to (1).
The second generation unit is a signal processing device that corrects the output data so that the shape of the pulse included in the pulse signal is restored.
(3) The signal processing device according to (2).
The second generation unit is a signal processing device that corrects the slope of the rise or fall of the pulse in the output data.
(4) The signal processing device according to (2) or (3).
The second generation unit is a signal processing device that corrects the amplitude of the pulse in the output data.
(5) The signal processing device according to any one of (1) to (4).
The second generation unit is a signal processing device that corrects the output data based on circuit information about an output circuit that generates an output signal corresponding to the pulse signal.
(6) The signal processing device according to (5).
The output circuit includes a switching amplifier that generates the pulse signal according to the correction data.
The circuit information is a signal processing device including first information which is information about the switching amplifier.
(7) The signal processing device according to (6).
The first information includes shape information of the pulse signal detected by AD conversion.
The second generation unit is a signal processing device that corrects the output data based on the inclination of the rise or fall of the pulse included in the pulse signal calculated from the shape information.
(8) The signal processing device according to (6) or (7).
The first information is a signal processing device including information on the element characteristics of the switching amplifier, the dead time set in the switching amplifier, and at least one of the power supplies for driving the switching amplifier.
(9) The signal processing device according to any one of (5) to (8).
The output circuit includes a demodulation circuit that demodulates the pulse signal to generate the output signal.
The circuit information is a signal processing device including a second information which is information about the demodulation circuit.
(10) The signal processing device according to (9).
The second information is a signal processing device including information about the output signal.
(11) The signal processing device according to any one of (1) to (10).
The second generation unit is a signal processing device that generates the output data by sampling the signal output from the comparator at a second frequency higher than the first frequency representing the resolution of the pulse signal.
(12) The signal processing device according to any one of (1) to (11).
The output data is binary data obtained by binarizing the pulse signal.
The second generation unit is a signal processing device that corrects the level values of a plurality of data points included in the binary data.
(13) The signal processing device according to any one of (1) to (12).
The first generation unit is a signal processing device that generates the correction data by subtracting the feedback data whose gain is adjusted at a predetermined ratio from the input data.
(14) The signal processing device according to any one of (1) to (13).
The pulse signal is a signal processing device that is a pulse width modulation type signal.
(15) The signal processing device according to any one of (1) to (14).
The input data is a signal processing device that is voice data.
(16) A first generation unit that corrects the input data based on the feedback data and generates the correction data,
A switching amplifier that generates a pulse signal according to the correction data, and
A comparator to which the pulse signal is input and
An amplification device including a second generation unit that corrects the output data of the comparator and generates the feedback data.
(17) A first generation unit that corrects audio data based on feedback data and generates correction data, and
A switching amplifier that generates a pulse signal according to the correction data, and
A demodulation circuit that demodulates the pulse signal to generate an audio signal,
A comparator to which the pulse signal is input and
A reproduction device including a second generation unit that corrects the output data of the comparator and generates the feedback data.

1 ... Input data 2 ... Audio signal 3 ... Correction data 5 ... Amplified PWM signal 7 ... Feedback data 8 ... Comparator data 13 ... Shape information 20 ... Feedback processing unit 21 ... PWM conversion processing unit 22 ... Switching amplifier 23 ... Low pass filter 24 ... Comparator 25 ... PWM shape correction processing unit 30 ... Signal output unit 31 ... Signal processing unit 100 ... Digital amplifier

Claims (17)

1. The first generator that corrects the input data based on the feedback data and generates the corrected data,
   A signal processing device including a second generation unit that corrects the output data of a comparator to which a pulse signal corresponding to the correction data is input and generates the feedback data.
2. The signal processing device according to claim 1.
   The second generation unit is a signal processing device that corrects the output data so that the shape of the pulse included in the pulse signal is restored.
3. The signal processing device according to claim 2.
   The second generation unit is a signal processing device that corrects the slope of the rise or fall of the pulse in the output data.
4. The signal processing device according to claim 2.
   The second generation unit is a signal processing device that corrects the amplitude of the pulse in the output data.
5. The signal processing device according to claim 1.
   The second generation unit is a signal processing device that corrects the output data based on circuit information about an output circuit that generates an output signal corresponding to the pulse signal.
6. The signal processing device according to claim 5.
   The output circuit includes a switching amplifier that generates the pulse signal according to the correction data.
   The circuit information is a signal processing device including first information which is information about the switching amplifier.
7. The signal processing device according to claim 6.
   The first information includes shape information of the pulse signal detected by AD conversion.
   The second generation unit is a signal processing device that corrects the output data based on the inclination of the rise or fall of the pulse included in the pulse signal calculated from the shape information.
8. The signal processing device according to claim 6.
   The first information is a signal processing device including information on the element characteristics of the switching amplifier, the dead time set in the switching amplifier, and at least one of the power supplies for driving the switching amplifier.
9. The signal processing device according to claim 5.
   The output circuit includes a demodulation circuit that demodulates the pulse signal to generate the output signal.
   The circuit information is a signal processing device including a second information which is information about the demodulation circuit.
10. The signal processing device according to claim 9.
    The second information is a signal processing device including information about the output signal.
11. The signal processing device according to claim 1.
    The second generation unit is a signal processing device that generates the output data by sampling the signal output from the comparator at a second frequency higher than the first frequency representing the resolution of the pulse signal.
12. The signal processing device according to claim 1.
    The output data is binary data obtained by binarizing the pulse signal.
    The second generation unit is a signal processing device that corrects the level values of a plurality of data points included in the binary data.
13. The signal processing device according to claim 1.
    The first generation unit is a signal processing device that generates the correction data by subtracting the feedback data whose gain is adjusted at a predetermined ratio from the input data.
14. The signal processing device according to claim 1.
    The pulse signal is a signal processing device that is a pulse width modulation type signal.
15. The signal processing device according to claim 1.
    The input data is a signal processing device that is voice data.
16. The first generator that corrects the input data based on the feedback data and generates the corrected data,
    A switching amplifier that generates a pulse signal according to the correction data, and
    A comparator to which the pulse signal is input and
    An amplification device including a second generation unit that corrects the output data of the comparator and generates the feedback data.
17. The first generator that corrects the audio data based on the feedback data and generates the corrected data,
    A switching amplifier that generates a pulse signal according to the correction data, and
    A demodulation circuit that demodulates the pulse signal to generate an audio signal,
    A comparator to which the pulse signal is input and
    A reproduction device including a second generation unit that corrects the output data of the comparator and generates the feedback data.

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