WO2021131583A1 - Dispositif de synchronisation et procédé de synchronisation - Google Patents

Dispositif de synchronisation et procédé de synchronisation Download PDF

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Publication number
WO2021131583A1
WO2021131583A1 PCT/JP2020/045105 JP2020045105W WO2021131583A1 WO 2021131583 A1 WO2021131583 A1 WO 2021131583A1 JP 2020045105 W JP2020045105 W JP 2020045105W WO 2021131583 A1 WO2021131583 A1 WO 2021131583A1
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Prior art keywords
counter
count value
master
unit
packet
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PCT/JP2020/045105
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English (en)
Japanese (ja)
Inventor
道人 石井
将斗 近藤
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ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2021567140A priority Critical patent/JPWO2021131583A1/ja
Publication of WO2021131583A1 publication Critical patent/WO2021131583A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00—Details of transducers, loudspeakers or microphones
    • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones

Definitions

  • This disclosure relates to a synchronization device and a synchronization method.
  • TWS Truste Wireless Stereo
  • Bluetooth registered trademark
  • BLE Bluetooth Low Energy
  • time information is transmitted from a playback device such as a smartphone or music player during audio playback, and playback synchronization is realized by synchronizing with this time information.
  • a playback device such as a smartphone or music player during audio playback
  • playback synchronization is realized by synchronizing with this time information.
  • this time information is not included in the packet, it is necessary to realize audio playback synchronization by using a method different from the conventional technology.
  • the present disclosure provides a synchronization device and a synchronization method capable of accurately synchronizing between a master and a slave that perform wireless communication.
  • a synchronization device that synchronizes time series data between a master and a slave by wireless communication.
  • the master A packet generator that generates multiple packets and It has a packet transmission unit that transmits an arbitrary packet in the plurality of packets to the slave at predetermined intervals.
  • the slave A packet receiver that receives the arbitrary packet and A counter that counts the interval of the arbitrary packet based on the reference clock signal is provided.
  • a synchronization device is provided that synchronizes between the master and the plurality of slaves by adjusting the frequency of the reference clock signal based on the count value of the counter.
  • a synchronization device that synchronizes time series data between a master and a plurality of slaves by wireless communication.
  • the master A packet generator that generates multiple packets and It has a packet transmission unit that transmits an arbitrary packet in the plurality of packets to one of the plurality of slaves at a predetermined interval.
  • One of the plurality of slaves A packet receiver that receives the arbitrary packet and A counter that counts the interval of the arbitrary packet based on the reference clock signal is provided.
  • a synchronization device is provided that synchronizes between the master and the plurality of slaves by adjusting the frequency of the reference clock signal based on the count value of the counter.
  • the plurality of packets include information on packet intervals and time-series data. Each time a new packet is received by the packet receiving unit, a latching unit that latches the count value of the counter and a latching unit. An information extraction unit that extracts information on packet intervals included in packets received by the packet reception unit, and an information extraction unit. An ideal count value calculation unit that calculates an ideal count value based on the information regarding the interval of the extracted packets, and an ideal count value calculation unit. A difference calculation unit that calculates the difference between the count value of the counter latched by the latch unit and the ideal count value, and A frequency adjusting unit that adjusts the frequency of the reference clock signal based on the difference may be provided.
  • the frequency adjusting unit lowers the frequency of the reference clock signal and reduces the frequency of the counter latched by the latch unit. If the count value is smaller than the ideal count value, the frequency of the reference clock signal may be increased.
  • the slave It has a control value calculation unit that calculates a control value for adjusting the frequency of the reference clock signal so that the difference becomes equal to or less than a predetermined value based on the time change of the difference.
  • the frequency adjusting unit may adjust the frequency of the reference clock signal based on the control value.
  • the slave A velocity component extraction unit that extracts a velocity component indicating a change value of the difference per unit time, and a velocity component extraction unit. It has an acceleration component extraction unit that extracts an acceleration component indicating a change value of the velocity component per unit time.
  • the control value calculation unit may calculate the control value based on the velocity component and the acceleration component.
  • the slave has a control value adjusting unit that adjusts the variation of the control value within a predetermined range.
  • the frequency adjusting unit may adjust the frequency of the reference clock signal based on the control value adjusted by the control value adjusting unit.
  • the packet transmission unit transmits a packet group including the plurality of packets a plurality of times at predetermined intervals.
  • the counter in the slave measures the interval of each packet included in the packet group, respectively.
  • the slave Among the intervals of each packet included in the packet group, if there is an interval of packets for which the count value cannot be measured, an interpolation unit that interpolates the count value and Among the count values counted by the counter, the exclusion unit for removing the count values that deviate from the permissible range is provided.
  • the difference calculation unit may calculate the difference between the count value obtained by the interpolation by the interpolation unit and the exclusion by the exclusion unit and the ideal count value.
  • the time series data may be data including biometric information or audio data.
  • the packet receiving unit in each of the plurality of slaves may perform wireless communication at a timing different from that of the master and receive the plurality of packets including unique time series data transmitted from the master.
  • the master is an information providing terminal having a storage unit for storing audio data. It is equipped with two slaves that perform wireless communication at different timings from the information providing terminal. Even if one of the two slaves is an earphone that reproduces the audio data for the left ear transmitted from the master, and the other is an earphone that reproduces the audio data for the right ear transmitted from the master. Good.
  • the master A first counter that counts based on the first reference clock signal, A second counter that counts the intervals between a plurality of packets transmitted from the information providing terminal based on the second reference clock signal, and It has a first packet transmission unit that transmits a packet including the count value of the first counter and the count value of the second counter to the slave.
  • the slave A third counter that counts based on the third reference clock signal, A fourth counter that counts the intervals between the plurality of packets transmitted from the information providing terminal based on the fourth reference clock signal, and A second packet transmission unit that transmits a packet containing the count value of the third counter and the count value of the fourth counter to the master.
  • a synchronization device having a frequency adjusting unit for adjusting the frequency of the fourth reference clock signal based on the count value of the second counter transmitted from the master and the count value of the fourth counter. Will be done.
  • a difference calculation unit for calculating the difference between the count value of the second counter and the count value of the fourth counter transmitted from the master is provided.
  • the frequency adjusting unit may adjust the frequency of the fourth reference clock signal based on the difference.
  • the count value of the first counter and the count value of the third counter are adjusted so that they become the same value or the difference becomes the same each time the master and the slave perform packet communication. May be good.
  • the slave An end time information acquisition unit that acquires information on transmission end times included in a plurality of packets transmitted from the information providing terminal, and an end time information acquisition unit.
  • a start time calculation unit that calculates information on the start time of reproduction or processing of time-series data based on the information on the transmission end time.
  • the count value of the third counter, the count value of the fourth counter after adjusting the frequency of the fourth reference clock signal by the frequency adjusting unit, and the frequency of the fourth reference clock signal are adjusted by the frequency adjusting unit.
  • a synchronization unit that synchronizes the time for reproducing or processing the time-series data with the master based on the difference calculated later by the difference calculation unit and the information regarding the start time. You may have.
  • the second packet transmission unit may transmit the count value of the third counter acquired by the count value acquisition unit and the count value of the fourth counter to the master.
  • the time series data is audio data and
  • the fifth counter may count the number of frames of the audio data.
  • the frequency adjusting unit adjusts the frequency of the fourth reference clock signal based on the difference.
  • the synchronization unit may synchronize the time for reproducing or processing the time series data with the master while the master and the slave perform packet communication with the information providing terminal.
  • One of the master and the slave is a first earphone that receives audio data for the left ear from the information providing terminal, and the other is for the right ear at a timing different from that of the first earphone from the information providing terminal. It may be a second earphone that receives the audio data of.
  • Each of the first earphone and the second earphone sends and receives a packet to and from each other, and the own device is the master or the master based on the profile information included in the packet received by each of the first earphone and the second earphone. It may have a master / slave confirmation unit that confirms that it is the slave.
  • the master and the slave may perform packet communication conforming to the Bluetooth (registered trademark) Low Energy standard.
  • it is a synchronization method for synchronizing time series data by wireless communication between a master and a plurality of slaves.
  • the master Generate multiple packets and Arbitrary packets in the plurality of packets are transmitted to one of the plurality of slaves at predetermined intervals.
  • One of the plurality of slaves Receive the arbitrary packet and Based on the reference clock signal, the interval of the arbitrary packet is counted by the counter, and the interval is counted.
  • a synchronization method is provided that synchronizes between the master and the plurality of slaves by adjusting the frequency of the reference clock signal based on the count value of the counter.
  • it is a synchronization method for synchronizing time series data by wireless communication between a master and a slave.
  • the master The counting operation is performed by the first counter based on the first reference clock signal, and the counting operation is performed. Based on the second reference clock signal, the interval between a plurality of packets transmitted from the information providing terminal is counted by the second counter, and the interval is counted. A packet containing the count value of the first counter and the count value of the second counter is transmitted to the slave.
  • the slave The count operation is performed by the third counter based on the third reference clock signal, and the count operation is performed.
  • the interval between the plurality of packets transmitted from the information providing terminal is counted by the fourth counter, and the interval is counted.
  • a packet containing the count value of the third counter and the count value of the fourth counter is transmitted to the master.
  • a synchronization method is provided in which the frequency of the fourth reference clock signal is adjusted based on the count value of the second counter transmitted from the master and the count value of the fourth counter.
  • the figure which shows the data structure of one packet transmitted in the sub-interval of FIG. The block diagram which shows an example of the hardware composition of the master or slave which constitutes a part of the synchronization apparatus by this Embodiment.
  • FIGS. 7 and 8 A detailed flowchart of the clock recovery process in the flowcharts of FIGS. 7 and 8.
  • Conceptual diagram of sound output timing adjustment of left and right earphones The figure which shows the procedure of the sound output timing adjustment of the left and right earphones performed by the slave and the sound output timing deviation confirmation process by the arrow line.
  • the synchronization device synchronizes time series data between the master and the slave by wireless communication.
  • the master transmits a packet containing time-series data to the slave by wireless communication, and the slave performs a process of synchronizing the time-series data included in the received packet with the time-series data of the master.
  • the time series data may be data including biometric information or audio data.
  • the master and the slave synchronize audio data will be mainly described.
  • the master may be an information providing terminal that provides audio data
  • the slave may be an earphone.
  • the master may be either the left or right earphone, and the slave may be the other earphone.
  • FIG. 1 is a diagram showing a schematic configuration of a synchronization device 1 according to the present embodiment.
  • the synchronization device 1 of FIG. 1 includes, for example, an information providing terminal 2 such as a smartphone, a tablet, a mobile phone, or a portable music player, and left and right earphones 3a and 3b that receive audio data from the information providing terminal 2 and output audio. It has.
  • the information providing terminal 2 can be the master M
  • the left and right earphones 3a and 3b can be the slaves S1 and S2.
  • either the left or right earphone 3a can be the master M and the other can be the slave S.
  • BLE Bluetooth Low Energy
  • the master M when the master M is the information providing terminal 2 and the slaves S1 and S2 are the left and right earphones 3a and 3b, according to the BLE standard, the master M sends the earphones 3a and 3b to the audio data for the earphones 3a and 3b. Send only. That is, the audio data for the other earphones 3a and 3b is not transmitted to one earphone 3a and 3b. Since the earphones 3a and 3b communicate wirelessly, the processing for synchronizing the audio data received by the earphones 3a and 3b is performed between the information providing terminal 2 and the earphones 3a and 3b, and each earphone 3a and 3b is used. It is necessary to synchronize the earphones 3a and 3b with each other.
  • the present embodiment has a technical feature in the synchronous processing performed between the master M and the slaves S1 and S2. First, the BLE standard will be described.
  • connection requirements and clock requirements the BLE standard defines synchronous connection (ISO: Isochronous connection) and general data frame connection (ACL: Asynchronous Connection Interval).
  • the master M and the slaves S1 and S2 perform audio data transmission and clock recovery by synchronous connection (ISO), and perform a GATT (Genetic Attribute) profile by general data frame connection (ACL).
  • the counter values are exchanged between the left and right earphones 3a and 3b, and the deviation of the counter is adjusted.
  • FIG. 2 is a diagram showing the timing of packet communication conforming to the BLE standard.
  • FIG. 2 shows an example in which a packet including audio data for reproduction is transmitted from the master M (information providing terminal 2) to the two slaves S1 and S2 (left and right earphones 3a and 3b).
  • each of the plurality of packets is arranged at a predetermined interval.
  • the transmission interval of one packet is called a sub-interval.
  • the slaves S1 and S2 that have received the packet from the master M transmit the packet including the receive (ACK) information to the master M.
  • the transmission period of a packet group including a plurality of packets is called a synchronization delay (synchronization delay period), and the information of this synchronization delay is included in the packet and transmitted from the master M to the slaves S1 and S2.
  • the packet transmission times of the left and right earphones 3a and 3b are different.
  • a packet containing the left audio data is transmitted to the left earphone 3b
  • a packet containing the right audio data is transmitted to the right earphone 3a.
  • packets cannot be transmitted to the left and right earphones 3a and 3b at the same time. Therefore, as shown in FIG. 2, there is a difference in packet transmission time between the left earphone 3b and the right earphone 3a.
  • the Synchronization Delay in the left packet and the right packet, respectively, the end times of the Synchronization Delay are matched by the left and right earphones 3a and 3b.
  • the audio data is started to be played back by the left and right earphones 3a and 3b from the end time of the Synchronization Delay and after the elapse of the Presentation Delay period.
  • FIG. 3 is a diagram showing a data structure of one packet transmitted within the sub-interval of FIG.
  • the data structure of the packet in FIG. 3 conforms to the BLE standard and is called a BLE packet.
  • the BLE packet has a preamble, an access address, a PDU, and a CRC.
  • the preamble does not include data about the audio data, but does include a BLE modulated signal.
  • the access address includes information that identifies a communication partner and information that represents the type of packet.
  • the PDU includes the above-mentioned information on the synchronization delay and packet interval (BLE parameter).
  • CRC is data for error checking.
  • FIG. 4 is a block diagram showing an example of the hardware configuration of the master M or slaves S1 and S2 constituting a part of the synchronization device 1 according to the present embodiment. More specifically, FIG. 4 shows the hardware configuration of the earphones 3a and 3b. As described above, the earphones 3a and 3b of FIG. 4 operate as slaves S1 and S2 when receiving audio data from the information providing terminal 2. Further, when the earphones 3a and 3b perform the synchronization process, they operate as the master M or the slave S.
  • the earphones 3a and 3b of FIG. 4 include a clock generation unit (CRG) 11, a counter unit 12, an RF (Radio Frequency) unit 13, a base band unit 14, a CPU 15, and an audio processing unit (Audio Processor) 16. It has a buffer interface unit (BIF) 17, an audio interface unit (AIF: Audio Interface) 18, an audio output unit (Audio Chip) 19, a speaker 20, and a microphone 21.
  • the RF unit 13 performs a process of receiving and demodulating the radio signal including the packet shown in FIG. Although the description of the internal configuration of the RF unit 13 is omitted, the RF unit 13 receives a radio signal in the 2.4 GHz band and performs demodulation processing in accordance with the BLE standard. In this way, the RF unit 13 functions as a packet receiving unit that receives a plurality of packets transmitted from the master M.
  • the baseband portion 14 has a PHY portion 14a and a LINK portion 14b.
  • the PHY unit 14a converts the signal demodulated by the RF unit 13 into a digital signal.
  • the LINK unit 14b extracts a packet having a specific access address, and calculates an ideal PCD count value (ideal PCD count value) from the packet interval information included in the packet.
  • the PCD count value is a count value of a counter (referred to as a PCD counter 12a) that counts the interval of packets transmitted from the master M, as will be described later.
  • the LINK unit 14b ideally calculates an ideal count value based on the information extraction unit that extracts information on the packet interval included in the received packet and the information on the extracted packet interval. It functions as a count value calculation unit.
  • the LINK unit 14b may receive the PCD count value of the communication partner as the ideal PCD count value.
  • the CPU 15 performs comparison processing (CMP), PCD control processing, SyncDelay detection processing (end time information acquisition unit), and Depacket processing.
  • CMP comparison processing
  • PCD control processing PCD control processing
  • SyncDelay detection processing end time information acquisition unit
  • Depacket processing Depacket processing.
  • the ideal PCD count value calculated by the LINK unit 14b or the PCD count value of the communication partner is compared with the count value of the PCD counter 12a described later in the own device.
  • the difference between the ideal PCD count value and the count value of the PCD counter 12a is detected based on the comparison result in the comparison process, and the frequency of the reference clock signal for operating the PCD counter 12a based on the difference. To control.
  • the contents of the received packet are extracted.
  • the Synchronization Delay included in the received packet is detected.
  • Information such as Synchronization Delay and audio data in the packet is stored in the first RAM 22.
  • the data stored in the first RAM 22 is read by the audio processing unit 16.
  • the CPU 15 functions as a difference calculation unit that calculates the difference between the PCD count value and the ideal count value, and a frequency adjustment unit that adjusts the frequency of the reference clock signal based on the difference.
  • the CPU 15 adjusts the sound output timing and confirms the sound deviation between the left and right earphones 3a and 3b
  • the CPU 15 performs the LR synchronization packet generation process synchronized with the left and right earphones 3a and 3b and the LR communication. Performs playback Delay value generation processing.
  • the audio processing unit 16 has the DSP 16a, reads the information of the packet stored in the first RAM 22, and calculates the presentation delay described above. Further, the audio processing unit 16 has a built-in DMAC 16b that performs DMA transfer of the audio data of the packet stored in the first RAM 22. The DMAC 16b stores the audio data in the second RAM 23.
  • the audio processing unit 16 adjusts the sound output timing and confirms the sound deviation between the left and right earphones 3a and 3b, the audio processing unit 16 performs packet delay processing using the playback delay value generated by the CPU 15 and the playback delay value. Mix processing of the audio data in consideration of.
  • the clock generator 11 includes a crystal oscillator 11a, a 1/2 divider 11b, a PLL circuit (SysPLL) 11c, a 1 / N divider 11d, an unequal divide PCD clock generator 11e, and 1 /. It has a 4-divider 11f.
  • the crystal oscillator 11a outputs, for example, a 32 MHz source oscillation signal.
  • the 1/2 divider 11b outputs a frequency divider signal in which the frequency of the source oscillation signal is reduced to 1/2.
  • the PLL circuit 11c uses the frequency division signal to generate a PLL-controlled clock signal.
  • the frequency of the clock signal is, for example, a signal having a frequency higher than that of the source oscillation signal.
  • the 1 / N frequency divider 11d generates a frequency divider signal in which the frequency of the clock signal is reduced to 1 / N.
  • the unequally divided PCD clock generation unit 11e variably controls the frequency of the clock signal that is the source of the reference clock signal that operates the PCD counter 12a according to the difference between the ideal PCD count value and the count value of the PCD counter 12a. ..
  • the frequency of the clock signal output from the unequally divided PCD clock generation unit 11e is divided by 4 by the quarter divider 11f to generate a reference clock signal.
  • the counter unit 12 has a PCD counter 12a and a frequency division control register 12b.
  • the frequency division control register 12b stores the frequency division control value according to the difference between the ideal PCD count value and the count value of the PCD counter 12a calculated by the CPU 15 described above.
  • the unequal division PCD clock generation unit 11e described above sets the division ratio of the clock signal based on the division control value stored in the division control register 12b.
  • the PCD counter 12a is a 32-bit counter that performs a counting operation in synchronization with the reference clock signal output from the 1/4 divider 11f.
  • the PCD counter 12a counts the interval of packets transmitted from the master M in synchronization with the reference clock signal.
  • the count value of the PCD counter 12a is sent to the CPU 15 as well as to the BIF 17.
  • the BIF 17 has a BIF unit 17a, a comparator (CMP) 17b, a trigger generation unit (Kicker) 17c, a FIFO 17d, and an I2S communication unit 17e.
  • the comparator 17b compares the value according to the reproduction time determined by the Synchronization Delay included in the packet sent from the master M and the Presentation Delay calculated by the audio processing unit 16 with the count value of the PCD counter 12a. .. When the comparator 17b detects a match, the trigger generation unit 17c outputs a trigger signal.
  • the FIFA 17d When the trigger signal is output from the trigger generation unit 17c, the FIFA 17d outputs the audio data stored in the second RAM 23 in order.
  • the audio data output from the FIFO 17d is serially transmitted to the AIF 18 via the I2S communication unit 17e.
  • the AIF18 performs predetermined audio processing on the audio data output from the BIF17, and then transmits the audio data to the audio output unit 19.
  • FIG. 5 is a functional block diagram of software processing performed by the master M and the slaves S1 and S2. More specifically, the upper side of the broken line in FIG. 5 shows the functional blocks of software processing, and the lower side of the broken line shows the constituent blocks of hardware related to software processing.
  • the hardware configuration blocks shown in FIG. 5 are associated with some blocks in the block diagram of FIG.
  • the BLE-PHY counter 14c of FIG. 5 is provided inside the LINK portion 14b of FIG.
  • the PCD counter 12a of FIG. 5 corresponds to the PCD counter 12a inside the counter unit 12 of FIG.
  • the BIF17 of FIG. 5 corresponds to the BIF17 of FIG. Although omitted in FIG. 5, in reality, the AIF 18 and the audio output unit 19 are present between the BIF 17 and the speaker 20, as shown in FIG.
  • the PCD latch portion 17f of FIG. 5 is provided, for example, in the comparator 17b of FIG.
  • the PCD control unit 11g of FIG. 5 is provided in the unequally divided PCD clock generation unit 11e of FIG.
  • the software function block diagram shown in FIG. 5 shows a BLE-PCD counter pair acquisition unit 31, a left / right PCD deviation calculation unit 32, an output PCD calculation unit (synchronization unit) 33, and a Presentation Delay calculation unit (start time calculation unit). 34, an audio decoder 35, an audio frame counter (fifth counter) 36, an audio PCD counter pair acquisition unit (count value acquisition unit) 37, a dropout / wrap-around detection unit 38, and an out-of-tolerance data removal unit. 39, BLE parameter extraction unit 40, ideal PCD value calculation unit 41, PCD difference extraction unit 42, velocity component extraction unit 43, acceleration component extraction unit 44, ideal PCD control value calculation unit 45, and possible PCD. It has a control value calculation unit 46. These software functional blocks are mainly executed by the CPU 15 of FIG.
  • the BLE-PCD counter pair acquisition unit 31 acquires a pair of the count value of the BLE-PHY counter 14c and the count value of the PCD counter 12a of the communication partner (for example, the master M), and also acquires the pair of the count value of the own device (for example, slaves S1 and S2). Acquires a pair of the count value of the BLE-PHY counter 14c and the count value of the PCD counter 12a.
  • the count value of the BLE-PHY counter 14c is periodically calibrated so that the master M and the slaves S1 and S2 have the same count value, or the difference between the count values is the same. Therefore, in the following description, it is assumed that the count values of the BLE-PHY counters 14c on the master side and the slave side are the same or the differences are the same.
  • the left / right PCD deviation calculation unit 32 calculates the difference between the count value of the PCD counter 12a of the master M and the count value of the PCD counter 12a of the slaves S1 and S2.
  • the Presentation Delay calculation unit 34 calculates the Presentation Delay from the Synchronous Delay included in the packet transmitted from the communication partner (for example, the master M).
  • the output PCD calculation unit 33 calculates the count value of the PCD counter 12a corresponding to the playback time of the audio data based on the difference between the count values of the PCD counter 12a calculated by the left and right PCD deviation calculation unit 32 and the Presentation Delay. To do.
  • the audio frame counter 36 counts the number of output audio frames.
  • the audio PCD counter pair acquisition unit 37 acquires the count value of the PCD counter 12a and the count value of the BLE-PHY counter 14c of its own device (for example, slaves S1 and S2) at the timing when the audio frame counter 36 counts up.
  • the count values of the PCD counter 12a and the BLE-PHY counter 14c acquired by the audio PCD counter pair acquisition unit 37 are transmitted to the communication partner (for example, the master M).
  • the omission / wrap-around detection unit 38 interpolates the count value when the PCD counter 12a fails to count the packet interval. Further, when the PCD counter 12a reaches the maximum count value, the count value is recounted from 0. Therefore, the PCD counter 12a detects that the count value is recounted from 0 during the counting process of the PCD counter 12a, and calculates the count value corresponding to the packet interval. To do.
  • the data removal unit 39 out of tolerance improves the reliability of the count value by removing the count value.
  • the BLE parameter extraction unit 40 extracts the BLE parameters included in the received packet.
  • the BLE parameters include, for example, information about parameter intervals.
  • the ideal PCD value calculation unit 41 calculates the ideal PCD count value based on the information regarding the packet interval included in the BLE parameter. More specifically, the ideal PCD value calculation unit 41 latches the packet interval (connection interval) included in the received packet for each access address in the PHY unit 14a, and sets the PCD count value of the master M at that time. Expected value.
  • the PCD difference extraction unit 42 compares the count value of the PCD counter 12a in the own device (for example, slaves S1 and S2) with the value latched by the PCD latch unit 17f with the ideal PCD count value, and extracts the difference. .. Since there is a possibility that the difference extracted by the PCD difference extraction unit 42 contains an abnormal value, the difference is not detected for each time, but the change rate of the difference for a plurality of times is checked to obtain an abnormal difference. Exclude the value.
  • the difference ⁇ PCDdiff is calculated by the following equation (1).
  • ⁇ PCDdiff ⁇ (PCDresultN-PCDresult1)-(PCDreferN-PCDrefer1) ⁇ / N ...
  • FIG. 6 is a diagram showing an example of the relationship between the PCD count value and the ideal PCD count value.
  • the horizontal axis of FIG. 6 is the time, and the vertical axis is the PCD count value.
  • the white circle in FIG. 6 indicates the PCD count value, and the straight line in FIG. 6 indicates the ideal PCD count value.
  • the PCD count value at time t2 is excluded by the non-allowable data exclusion unit.
  • the distance between the straight line and the white circle represents the difference in the PCD count value.
  • the PCD count value includes some error each time a packet is received, a highly reliable difference can be calculated by taking into consideration the measurement results of the PCD count value a plurality of times.
  • the velocity component extraction unit 43 extracts a velocity component indicating a value in which the difference extracted by the PCD difference extraction unit 42 changes in a unit time.
  • the acceleration component extraction unit 44 extracts an acceleration component indicating a value obtained by changing the velocity component extracted by the velocity component extraction unit 43 in a unit time.
  • the ideal PCD control value calculation unit 45 calculates the PCD control value so that the velocity component and the acceleration component approach zero.
  • the PCD control value that is over or under may be calculated by giving a state transition, or the control may be abandoned in some cases, the control value is increased in the initial state, and the control value is increased in other than the initial state.
  • the gain of the PCD control value may be adjusted so as to reduce the rate of change of.
  • the possible PCD control value calculation unit 46 performs a rounding process so that the PCD control value falls within a predetermined range.
  • the PCD control value calculated by the possible PCD control value calculation unit 46 is stored in the frequency division control register 12b of FIG.
  • the unequally divided PCD clock generation unit 11e generates a clock divided by a division ratio according to the PCD control value. Based on this clock, the quarter divider 11f generates a reference clock signal.
  • FIG. 7 is a flowchart showing a processing operation when the master M is an information providing terminal 2 such as a smartphone and the slaves S1 and S2 are earphones 3a and 3b.
  • ICO Isychronous Connection Oriented
  • the master M and the slaves S1 and S2 each acquire the access address included in the packet transmitted from the communication partner (step S2).
  • the communication partner can be specified by the access address. In this case, it is determined whether or not the packet is from a communication partner that performs clock recovery processing described later.
  • step S3 the clock recovery process is started (step S3).
  • the interval between packets transmitted from the information providing terminal 2 functioning as the master M is counted by the PCD counters 12a of the slaves S1 and S2, and the count value of the PCD counter 12a is ideal.
  • a process of controlling the frequency of the reference clock signal for operating the PCD counter 12a is performed so as to match the PCD count value.
  • ACL Asynchronous Connection Less communication is started between the left slaves S1 and S2 (earphones 3a and 3b) and the right slaves S1 and S2 (earphones 3a and 3b) (step S4).
  • ACL communication is to send and receive packets between the left and right earphones 3a and 3b to adjust the timing of the playback time and check the sound deviation.
  • step S5 acquire the access address
  • step S6 acquires the GATT (Genetic Attribute) profile included in the received packet
  • step S7 based on the acquired GATT, it is determined whether the master M or the slaves S1 and S2 (step S7).
  • step S8 clock recovery processing is performed (step S8).
  • the clock recovery process of step S8 the PCD count values sent from the master M earphones 3a and 3b are acquired by the slave S1 and S2 earphones 3a and 3b, and the difference from the PCD count values of the slaves S1 and S2. Is calculated, and the frequency of the reference clock signal for operating the PCD counters 12a of the slaves S1 and S2 is adjusted so that the difference becomes small.
  • the clock recovery process performed after pairing is performed only by the slaves S1 and S2.
  • FIG. 8 is a flowchart showing a processing operation when one of the master M and the slave S is the left earphone 3b and the other is the right earphone 3a.
  • ACL communication is started (step S11).
  • the access address is acquired (step S12).
  • the GATT profile is acquired (step S13).
  • the processing of FIG. 8 is performed between the left and right earphones 3a and 3b.
  • information This is performed for the purpose of synchronizing the left and right earphones 3a and 3b while receiving the audio data from the providing terminal 2.
  • FIG. 9 is a detailed flowchart of the clock recovery process in the flowcharts of FIGS. 7 and 8.
  • the flowchart of FIG. 9 shows the clock recovery process performed by the slaves S1 and S2 (earphones 3a and 3b).
  • step S21 it is determined whether or not to change the frequency of the reference clock signal that operates the PCD counter 12a (step S21).
  • step S21 when the master M is the information providing terminal 2 and the slaves S1 and S2 are the earphones 3a and 3b, it is determined that the frequency of the reference clock signal is changed.
  • the reference point (reference time) for clock recovery is determined (step S22).
  • the time when a specific packet is received is used as a reference point.
  • the count value (PCD count value) of the PCD counter 12a in the slaves S1 and S2 is read (step S23).
  • the difference between the count value of the PCD counter 12a and the ideal PCD count value calculated based on the packet interval is calculated (step S24).
  • step S24 when the left and right earphones 3a and 3b that receive the audio data from the information providing terminal 2 perform the synchronization process, one earphone 3a and 3b is set as the master M, and the PCD transmitted from the master M is used. The difference between the count value and the PCD count value of the slave S is calculated.
  • step S25 the frequency of the reference clock signal for operating the PCD counter 12a is adjusted based on the calculated difference.
  • the count value of the PCD counter 12a and the count value of the BLE-PHY counter 14c are paired and transmitted to the master M (step S26).
  • step S27 it is determined whether or not to adjust the phase of the count value of the PCD counter 12a (step S27).
  • the master M is the information providing terminal 2
  • the phase adjustment is not performed, so the process of FIG. 8 is terminated.
  • the sound output timing with the left earphone 3b and the right earphone 3a it is determined that the phase adjustment is performed.
  • step S28 When it is determined that the phase of the count value of the PCD counter 12a is adjusted, the pair of the count value of the PCD counter 12a and the count value of the BLE-PHY counter 14c transmitted from the master M (one earphone 3a, 3b) is used. Acquire (step S28).
  • step S29 the difference between the PCD count value of the master M (one earphone 3a, 3b) and the PCD count value of the slaves S1 and S2 (the other earphone 3a, 3b) is calculated.
  • step S30 the PCD count values of the slaves S1 and S2 are adjusted based on the calculated difference.
  • clock recovery processing Next, the clock recovery process will be described in detail. As shown in the flowcharts of FIGS. 7 to 9, the clock recovery process is also performed when the master M is the information providing terminal 2 and the slaves S1 and S2 are the earphones 3a and 3b, and the master M is one of them. This is also performed when the slave S is the other earphone 3a, 3b in the earphones 3a, 3b.
  • the inside of the broken line frame in the block diagram of FIG. 5 is the processing block related to the clock recovery processing.
  • the PCD latch unit 17f and the PCD control unit 11g are used as hardware, and the software functional blocks include the omission / wrap-around detection unit 38, the out-of-tolerance data removal unit 39, and so on.
  • BLE parameter extraction unit 40 ideal PCD value calculation unit 41, PCD difference extraction unit 42, velocity component extraction unit 43, acceleration component extraction unit 44, ideal PCD control value calculation unit 45, and possible PCD control value calculation.
  • a portion 46 is provided.
  • 10 to 12 are diagrams showing the procedure of the clock recovery process performed by the slaves S1 and S2 with arrows.
  • the PCD count value counted by the PCD counter 12a is latched by the PCD latch unit 17f.
  • the difference between the latched PCD count value and the ideal PCD count value calculated by the ideal PCD value calculation unit 41 is calculated by the PCD difference extraction unit 42.
  • the ideal PCD control value calculation unit 45 calculates the ideal PCD control value through the processing of the velocity component extraction unit 43 and the acceleration component extraction unit 44.
  • the possible PCD control value calculation unit 46 calculates the PCD control value, and the frequency of the reference clock signal for operating the PCD counter 12a is controlled based on the PCD control value.
  • the clock recovery process is performed by the slaves S1 and S2 when the master M is the information providing terminal 2.
  • the other earphones 3a and 3b are also used.
  • the clock recovery process in this case is the process of step S35 in FIG.
  • the PCD count values of the earphones 3a and 3b of the master M are sent to the other earphones 3a and 3b which are slaves S1 and S2.
  • the slaves S1 and S2 calculate the difference between the PCD count value of the own device and the PCD count value of the master M (step S14 in FIG. 9), and adjust the frequency of the reference clock signal so that the difference becomes zero. (Step S15).
  • the left and right earphones 3a and 3b continuously receive audio data from the information providing terminal 2 which is the master M, and become the information providing terminal 2.
  • the left and right earphones 3a and 3b can also be synchronized between the two earphones 3a and 3b.
  • FIG. 13 is a conceptual diagram of sound output timing adjustment of the left and right earphones 3a and 3b.
  • one of the left earphone 3b and the right earphone 3a is the master M
  • the other is the slave S
  • the count value (BLE-PHY count value) of the BLE-PHY counter 14c of the master M is 2 to 2. While changing to 7, the count value (PCD count value) of the PCD counter 12a changes from 100 to 600.
  • the BLE-PHY count values of the slaves S1 and S2 are changing from 2 to 7, the PCD count value is changing from 110 to 610.
  • the BLE-PHY count values match between the master M and the slave.
  • the reason is that each time a packet is received, a process of matching the BLE-PHY count value of the slaves S1 and S2 with the BLE-PHY count value of the master M is performed.
  • the PCD count value may deviate between the master M and the slaves S1 and S2. The reason is that the frequencies of the source oscillation signals output from the crystal oscillators 11a in the master M and the slaves S1 and S2 do not always match, so that the PCD count value deviates.
  • FIG. 13 shows an example in which it is determined to output sound when the BLE-PHY count value is 7 and the PCD count value is subsequently counted up by 60.
  • the master M has a BLE-PHY count value of 7 and the PCD count value is 660, which is the sound output timing
  • the slaves S1 and S2 have a BLE-PHY count value of 7 and the PCD count.
  • the sound output timing is set.
  • FIGS. 14 to 18 are diagrams showing the procedure of adjusting the sound output timing of the left and right earphones 3a and 3b and the process of confirming the deviation of the sound output timing performed by the slave S by arrows.
  • the processing of FIGS. 14 to 18 is performed with either one of the left and right earphones 3a and 3b as the master M and the other as the slave S.
  • the BLE-PCD counter pair acquisition unit 31 acquires a pair of the count value of the BLE-PHY counter 14c of the own device (slave S) and the count value of the PCD counter 12a.
  • the left-right PCD deviation calculation unit calculates the difference between the count value of the PCD counter 12a of the master M and the count value of the PCD counter 12a of the slave S.
  • the BLE-PHY counter 14c of the master M is referred to as a first counter
  • the PCD counter 12a of the master M is referred to as a second counter
  • the BLE-PHY counter 14c of the slave S is referred to as a third counter
  • the PCD counter 12a of the slave S. May be called the fourth counter.
  • the Presentation Delay calculation unit 34 calculates the Presentation Delay from the Synchronous Delay included in the received packet.
  • the output PCD calculation unit 33 calculates the count value of the PCD counter 12a corresponding to the playback time of the audio data based on the difference between the count values of the PCD counter 12a calculated by the left and right PCD deviation calculation unit 32 and the Presentation Delay. To do. Then, when the count value of the PCD counter 12a reaches the count value corresponding to the reproduction time, the audio data decoded by the audio decoder 35 is output from the speaker 20 via the BIF 17, AIF 18, and the audio output unit 19.
  • the audio data decoded by the audio decoder 35 is also sent to the audio frame counter 36 as shown in FIG.
  • the audio frame counter 36 counts the number of audio frames.
  • the audio PCD counter pair acquisition unit 37 acquires the count value and the PCD count value of the BLE-PHY counter 14c of the own device (slave S) in synchronization with the timing when the audio frame counter 36 counts up.
  • the acquired count value and PCD count value of the BLE-PHY counter 14c are transmitted to the master M as shown in FIG.
  • the sound output timing adjustment and the sound output timing deviation adjustment shown in FIGS. 14 to 18 are performed while the left and right earphones 3a and 3b receive a packet containing audio data from the information providing terminal 2.
  • the left and right earphones 3a and 3b operate as slaves S1 and S2 when receiving a packet including audio data from the information providing terminal 2.
  • the sound output timing adjustment and the sound output timing deviation adjustment shown in FIGS. 14 to 18 are performed between the left and right earphones 3a and 3b, one of the earphones 3a and 3b becomes the master M, and the other earphone 3a, 3b becomes the slave S.
  • the left and right earphones 3a and 3b continuously receive audio data from the information providing terminal 2 which is the master M, and become the information providing terminal 2. While performing the synchronization processing of, the left and right earphones 3a and 3b can also perform the synchronization processing.
  • the slaves S1 and S2 when the master M and the slaves S1 and S2 perform BLE-compliant packet communication, the slaves S1 and S2 perform the clock recovery process, so that the master M and the slaves S1 and S2 perform time series. Data can be synchronized.
  • the clock recovery process when packet communication is performed between the information providing terminal 2 that functions as the master M and the slaves S1 and S2 that receive packets from the information providing terminal 2, the PCD counter 12a of the slaves S1 and S2 is used. The interval of the packet transmitted from the master M is measured, the ideal PCD count value is calculated from the BLE parameter included in the packet, and the difference between the PCD count value and the ideal PCD count value is calculated.
  • the PCD count values of the slaves S1 and S2 can be matched with the PCD count value of the master M, or the difference between the two can be made constant.
  • the synchronization device 1 performs such clock recovery processing with the information providing terminal 2 such as a smartphone as the master M and the left and right earphones 3a and 3b as the slaves S1 and S2, and then the left and right earphones 3a and 3b. Adjust the sound output timing of.
  • the playback time of the audio data is set to the master M and the slave S1 by using the Synchronous Delay included in the packet, the Presentation Delay calculated from the Synchronous Delay, the PCD count value, and the difference information thereof. , S2 can be adjusted.
  • one earphone 3a and 3b can be used as the master M, and the other earphones 3a and 3b can be used as the slaves S1 and S2 to check and adjust the sound output timing deviation.
  • the master M and the slaves S1 and S2 exchange the BLE-PHY count value and the PCD count value as a pair, and for example, the slaves S1 and S2 detect the difference in the PCD count value. Then, the timing of the audio output is adjusted according to the difference. As a result, even if the PCD count values of the left and right earphones 3a and 3b deviate with the passage of time, the audio output timing can be matched between the left and right earphones 3a and 3b.
  • At least a part of the synchronization device 1 described in the above-described embodiment may be configured by hardware or software.
  • a program that realizes at least a part of the functions of the synchronization device 1 may be stored in a recording medium such as a flexible disk or a CD-ROM, read by a computer, and executed.
  • the recording medium is not limited to a removable one such as a magnetic disk or an optical disk, and may be a fixed recording medium such as a hard disk device or a memory.
  • a program that realizes at least a part of the functions of the synchronization device 1 may be distributed via a communication line (including wireless communication) such as the Internet. Further, the program may be encrypted, modulated, compressed, and distributed via a wired line or wireless line such as the Internet, or stored in a recording medium.
  • a communication line including wireless communication
  • the program may be encrypted, modulated, compressed, and distributed via a wired line or wireless line such as the Internet, or stored in a recording medium.
  • the present technology can have the following configurations.
  • a synchronization device that synchronizes time-series data between a master and a slave by wireless communication.
  • the master A packet generator that generates multiple packets and It has a packet transmission unit that transmits an arbitrary packet in the plurality of packets to the slave at predetermined intervals.
  • the slave A packet receiver that receives the arbitrary packet and A counter that counts the interval of the arbitrary packet based on the reference clock signal is provided.
  • a synchronization device that synchronizes between the master and the plurality of slaves by adjusting the frequency of the reference clock signal based on the count value of the counter.
  • a synchronization device that synchronizes time-series data between a master and a plurality of slaves by wireless communication.
  • the master A packet generator that generates multiple packets and It has a packet transmission unit that transmits an arbitrary packet in the plurality of packets to one of the plurality of slaves at a predetermined interval.
  • One of the plurality of slaves A packet receiver that receives the arbitrary packet and A counter that counts the interval of the arbitrary packet based on the reference clock signal is provided.
  • a synchronization device that synchronizes between the master and the plurality of slaves by adjusting the frequency of the reference clock signal based on the count value of the counter.
  • the plurality of packets include information on packet intervals and time-series data. Each time a new packet is received by the packet receiving unit, a latching unit that latches the count value of the counter and a latching unit.
  • An information extraction unit that extracts information on packet intervals included in packets received by the packet reception unit, and an information extraction unit.
  • An ideal count value calculation unit that calculates an ideal count value based on the information regarding the interval of the extracted packets, and an ideal count value calculation unit.
  • a difference calculation unit that calculates the difference between the count value of the counter latched by the latch unit and the ideal count value, and The synchronization device according to (1) or (2), comprising a frequency adjusting unit that adjusts the frequency of the reference clock signal based on the difference. (4) If the count value of the counter latched by the latch portion is larger than the ideal count value, the frequency adjusting unit lowers the frequency of the reference clock signal and is latched by the latch portion.
  • the synchronization device wherein if the count value of the counter is smaller than the ideal count value, the frequency of the reference clock signal is increased.
  • the slave is It has a control value calculation unit that calculates a control value for adjusting the frequency of the reference clock signal so that the difference becomes equal to or less than a predetermined value based on the time change of the difference.
  • the synchronization device according to (3) or (4), wherein the frequency adjusting unit adjusts the frequency of the reference clock signal based on the control value.
  • the slave is A velocity component extraction unit that extracts a velocity component indicating a change value of the difference per unit time, and a velocity component extraction unit. It has an acceleration component extraction unit that extracts an acceleration component indicating a change value of the velocity component per unit time.
  • the synchronization device wherein the control value calculation unit calculates the control value based on the velocity component and the acceleration component.
  • the slave has a control value adjusting unit that adjusts the variation of the control value within a predetermined range.
  • the synchronization device according to (5) or (6), wherein the frequency adjusting unit adjusts the frequency of the reference clock signal based on the control value adjusted by the control value adjusting unit.
  • the packet transmission unit transmits a packet group including the plurality of packets a plurality of times at predetermined intervals.
  • the counter in the slave measures the interval of each packet included in the packet group, respectively.
  • the slave Among the intervals of each packet included in the packet group, if there is an interval of packets for which the count value cannot be measured, an interpolation unit that interpolates the count value and Among the count values counted by the counter, the exclusion unit for removing the count values that deviate from the permissible range is provided.
  • the difference calculation unit calculates the difference between the count value obtained by the interpolation by the interpolation unit and the exclusion by the exclusion unit and the ideal count value, whichever is one of (3) to (7).
  • the synchronous device described in the section. (9) The synchronization device according to any one of (1) to (8), wherein the time series data is data including biometric information or audio data.
  • the packet receiving unit in each of the plurality of slaves performs wireless communication at a timing different from that of the master, and receives the plurality of packets including unique time series data transmitted from the master.
  • the synchronization device according to any one of (3) to (9).
  • the master is an information providing terminal having a storage unit for storing audio data. It is equipped with two slaves that perform wireless communication at different timings from the information providing terminal. One of the two slaves is an earphone that reproduces the audio data for the left ear transmitted from the master, and the other is an earphone that reproduces the audio data for the right ear transmitted from the master.
  • the synchronization device according to any one of 1) to (10).
  • a synchronization device that synchronizes time-series data between a master and a slave by wireless communication.
  • the master A first counter that counts based on the first reference clock signal, A second counter that counts the intervals between a plurality of packets transmitted from the information providing terminal based on the second reference clock signal, and It has a first packet transmission unit that transmits a packet including the count value of the first counter and the count value of the second counter to the slave.
  • the slave A third counter that counts based on the third reference clock signal, A fourth counter that counts the intervals between the plurality of packets transmitted from the information providing terminal based on the fourth reference clock signal, and A second packet transmission unit that transmits a packet containing the count value of the third counter and the count value of the fourth counter to the master.
  • a synchronization device including a frequency adjusting unit that adjusts the frequency of the fourth reference clock signal based on the count value of the second counter transmitted from the master and the count value of the fourth counter.
  • a difference calculation unit for calculating the difference between the count value of the second counter and the count value of the fourth counter transmitted from the master is provided.
  • the count value of the first counter and the count value of the third counter are the same value or the difference is the same each time the master and the slave perform packet communication.
  • the slave An end time information acquisition unit that acquires information on transmission end times included in a plurality of packets transmitted from the information providing terminal, and an end time information acquisition unit.
  • a start time calculation unit that calculates information on the start time of reproduction or processing of time-series data based on the information on the transmission end time.
  • the count value of the third counter, the count value of the fourth counter after adjusting the frequency of the fourth reference clock signal by the frequency adjusting unit, and the frequency of the fourth reference clock signal are adjusted by the frequency adjusting unit.
  • a synchronization unit that synchronizes the time for reproducing or processing the time-series data with the master based on the difference calculated later by the difference calculation unit and the information regarding the start time.
  • the synchronization device according to (13).
  • the slave A fifth counter that counts the breaks in time-series data that has been played or processed, Each time the fifth counter counts up, a count value acquisition unit for acquiring the count value of the third counter and the count value of the fourth counter is provided.
  • the second packet transmission unit transmits the count value of the third counter acquired by the count value acquisition unit and the count value of the fourth counter to the master, any of (12) to (15).
  • the synchronization device according to one item.
  • the time series data is audio data, and is The synchronization device according to (16), wherein the fifth counter counts the number of frames of the audio data.
  • the frequency adjusting unit adjusts the frequency of the fourth reference clock signal based on the difference.
  • the synchronization unit synchronizes the time for reproducing or processing time-series data with the master while the master and the slave perform packet communication with the information providing terminal (12).
  • the synchronization device according to any one of (17).
  • One of the master and the slave is a first earphone that receives audio data for the left ear from the information providing terminal, and the other is a timing different from that of the first earphone from the information providing terminal.
  • the synchronization device according to any one of (12) to (18), which is a second earphone that receives audio data for the right ear.
  • Each of the first earphone and the second earphone sends and receives packets to and from each other, and the own device uses profile information included in the packets received by each of the first earphone and the second earphone.
  • the master Generate multiple packets and Arbitrary packets in the plurality of packets are transmitted to one of the plurality of slaves at predetermined intervals.
  • One of the plurality of slaves Receive the arbitrary packet and Based on the reference clock signal, the interval of the arbitrary packet is counted by the counter, and the interval is counted.
  • (23) A synchronization method for synchronizing time-series data between a master and a slave by wireless communication.
  • the master The counting operation is performed by the first counter based on the first reference clock signal, and the counting operation is performed.
  • the interval between a plurality of packets transmitted from the information providing terminal is counted by the second counter, and the interval is counted.
  • a packet containing the count value of the first counter and the count value of the second counter is transmitted to the slave.
  • the slave The count operation is performed by the third counter based on the third reference clock signal, and the count operation is performed.
  • the interval between the plurality of packets transmitted from the information providing terminal is counted by the fourth counter, and the interval is counted.
  • a packet containing the count value of the third counter and the count value of the fourth counter is transmitted to the master.
  • a synchronization method in which the frequency of the fourth reference clock signal is adjusted based on the count value of the second counter and the count value of the fourth counter transmitted from the master.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Le problème décrit par la présente invention est de synchroniser avec précision un maître et un esclave qui réalisent une communication sans fil. La solution selon l'invention porte sur le présent dispositif de synchronisation qui synchronise des données de série temporelle par communication sans fil entre un maître et un esclave, le maître comprenant une unité de génération de paquets qui génère une pluralité de paquets, et une unité de transmission de paquets qui transmet à l'esclave selon un intervalle prescrit des paquets discrétionnaires parmi la pluralité de paquets ; l'esclave est pourvu d'une unité de réception de paquets qui reçoit les paquets discrétionnaires, et d'un compteur qui compte l'intervalle des paquets discrétionnaires sur la base d'un signal d'horloge de référence ; et le maître et une pluralité d'esclaves sont synchronisés par réglage de la fréquence du signal d'horloge de référence sur la base de la valeur de comptage du compteur.
PCT/JP2020/045105 2019-12-25 2020-12-03 Dispositif de synchronisation et procédé de synchronisation WO2021131583A1 (fr)

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WO2023153299A1 (fr) * 2022-02-14 2023-08-17 ソニーセミコンダクタソリューションズ株式会社 Système de traitement d'informations et procédé de traitement d'informations

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JP2001186180A (ja) * 1999-12-24 2001-07-06 Oki Electric Ind Co Ltd Ｉｐ端末装置、周波数誤差範囲推定方法、周波数差推定方法及び推定所要時間算出方法
JP2002252606A (ja) * 2001-02-26 2002-09-06 Oki Electric Ind Co Ltd 同期補正回路
JP2003273853A (ja) * 2002-03-13 2003-09-26 Oki Electric Ind Co Ltd 音声データ同期補正回路
JP2018011204A (ja) * 2016-07-13 2018-01-18 株式会社ディーアンドエムホールディングス ワイヤレスオーディオシステム、ワイヤレススピーカ、およびコンピュータで読み取り可能なプログラム

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JP2001186180A (ja) * 1999-12-24 2001-07-06 Oki Electric Ind Co Ltd Ｉｐ端末装置、周波数誤差範囲推定方法、周波数差推定方法及び推定所要時間算出方法
JP2002252606A (ja) * 2001-02-26 2002-09-06 Oki Electric Ind Co Ltd 同期補正回路
JP2003273853A (ja) * 2002-03-13 2003-09-26 Oki Electric Ind Co Ltd 音声データ同期補正回路
JP2018011204A (ja) * 2016-07-13 2018-01-18 株式会社ディーアンドエムホールディングス ワイヤレスオーディオシステム、ワイヤレススピーカ、およびコンピュータで読み取り可能なプログラム

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023153299A1 (fr) * 2022-02-14 2023-08-17 ソニーセミコンダクタソリューションズ株式会社 Système de traitement d'informations et procédé de traitement d'informations

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