WO2021130965A1 - Power receiving device and wireless power feed system - Google Patents

Power receiving device and wireless power feed system Download PDF

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Publication number
WO2021130965A1
WO2021130965A1 PCT/JP2019/051150 JP2019051150W WO2021130965A1 WO 2021130965 A1 WO2021130965 A1 WO 2021130965A1 JP 2019051150 W JP2019051150 W JP 2019051150W WO 2021130965 A1 WO2021130965 A1 WO 2021130965A1
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WO
WIPO (PCT)
Prior art keywords
power
power receiving
circuit
receiving device
current
Prior art date
Application number
PCT/JP2019/051150
Other languages
French (fr)
Japanese (ja)
Inventor
秀人 吉田
友一 坂下
卓哉 中西
Original Assignee
三菱電機株式会社
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Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2019/051150 priority Critical patent/WO2021130965A1/en
Priority to CN201980103080.4A priority patent/CN114846734A/en
Priority to DE112019008002.4T priority patent/DE112019008002T5/en
Priority to KR1020227020060A priority patent/KR20220100665A/en
Priority to US17/773,616 priority patent/US20220376553A1/en
Priority to JP2020539011A priority patent/JP6847316B1/en
Publication of WO2021130965A1 publication Critical patent/WO2021130965A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J50/12—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/0085—Partially controlled bridges
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0064—Magnetic structures combining different functions, e.g. storage, filtering or transformation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage

Definitions

  • This application relates to a power receiving device and a wireless power supply system.
  • the control method disclosed in Patent Document 1 includes a short-circuit mode in which the power receiving coil is short-circuited by the operation of the first power converter and power is not supplied to the first power converter and thereafter.
  • This is a method applicable to the configuration of a resonator in which the output from is a current source operation.
  • a resonator that operates as a voltage source is configured, an overcurrent is generated, and there is a risk of heat generation and destruction of the switching element. Therefore, when the method described in Patent Document 1 is performed, it is necessary to configure a specific resonator.
  • the present application discloses a technique for solving the above-mentioned problems, and provides a power receiving device capable of interrupting power from a power receiving coil by opening a circuit and realizing power control by a power converter on the power receiving side.
  • the purpose is.
  • the power receiving device disclosed in the present application is a power receiving device of a wireless power feeding system, which has a power receiving coil and receives AC power sent from a power transmission circuit, and DC power obtained by the power receiving circuit.
  • a power converter that converts to, a voltage detecting means that detects the output voltage of the power receiving circuit, at least one switch that switches between conduction and opening of the circuit between the power receiving circuit and the power converter, and the voltage. It includes a control device that controls the switch based on the voltage detected by the detection means.
  • the power from the power receiving coil can be cut off by opening the circuit. Therefore, the power converter on the power receiving side is used for the configuration of the resonator that operates as a voltage source. It becomes possible to perform power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining a basic control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining a basic control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining a basic control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining an example of a control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining another example of a control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining still another example of a control method of power control. It is a schematic circuit diagram which shows the structure of the power receiving device which concerns on Embodiment 2. FIG. It is a figure which shows the current path of the non-feeding period in the configuration of FIG.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the second embodiment, and is a diagram for explaining an example of a control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the second embodiment, and is a diagram for explaining an example of a control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the second embodiment, and is a diagram for explaining an example of a control method of power control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the second embodiment, and is a diagram for explaining an example of a control method of power control. It is a schematic circuit diagram which shows the structure of the power receiving device which concerns on Embodiment 3.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern I used for reactor current control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern II used for reactor current control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern III used for reactor current control.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern IV used for reactor current control. It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3.
  • FIG. It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3.
  • FIG. It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3.
  • FIG. It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device which concerns on Embodiment 3.
  • FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the fourth embodiment, and is a diagram for explaining an example of a control method of power control.
  • FIG. 5 is a schematic diagram of another waveform of each signal in the power receiving device according to the fourth embodiment, and is a diagram for explaining an example of a control method of power control. It is a figure for demonstrating the example of the control method of power control with the schematic diagram of the waveform of each signal in the power receiving device which concerns on Embodiment 4.
  • FIG. It is a hardware block diagram of a control device.
  • FIG. 1 is a diagram showing a schematic configuration of a wireless power supply system according to the first embodiment.
  • the wireless power supply system 1 includes a power transmission circuit 11 that transmits power supplied from an AC power source 5 that is a main power source, and a power receiving device 10 that receives power from the power transmission circuit 11 and outputs it to a load 15. .
  • the power receiving device 10 includes a power receiving circuit 12, a power converter 13, and an LC filter 14.
  • the electric power supplied from the AC power source 5 is transmitted in a non-contact manner between the power transmission circuit 11 and the power reception circuit 12.
  • the power converter 13 plays the role of a power converter that converts the AC power received by the power receiving circuit 12 into DC power and adjusts the received power to preset power.
  • the LC filter 14 attenuates the AC component included in the output power of the power converter 13. The electric power output from the LC filter 14 is consumed or stored in the load 15.
  • the power transmission circuit 11 is a circuit including at least one coil, and in FIG. 1, the power transmission coil 111 and the power transmission side capacitor 112 are connected in series.
  • the power transmission side capacitor 112 is not indispensable for wireless power supply, but if the power transmission side capacitor 112 is not provided, the power transmission efficiency between the power transmission / reception coils is significantly reduced. Therefore, it is desirable to use the power transmission side capacitor 112 to perform power factor compensation.
  • the power receiving circuit 12 is a circuit including at least one coil, and in FIG. 1, the power receiving coil 121 and the power receiving side capacitor 122 are connected in parallel.
  • the power receiving side capacitor 122 is not indispensable for wireless power supply, but if the power receiving side capacitor 122 is not provided, the power transmission efficiency between the power transmitting and receiving coils is significantly reduced. Therefore, it is desirable to use the power receiving side capacitor 122 to perform power factor compensation.
  • the output of the power reception circuit 12 becomes a voltage source operation or a current source operation.
  • the output of the power reception circuit 12 operates as a voltage source.
  • the configuration of the power transmission circuit 11 and the power reception circuit 12 shown in FIG. 1 is an example, and the configuration of each is not limited. However, in the present embodiment, the output of the power reception circuit 12 operates as a voltage source. It is targeted.
  • FIG. 2 is a schematic circuit diagram showing the configuration of the power receiving device 10 according to the first embodiment.
  • the rectifier circuit 13a includes four diodes 131, 132, 133, 134 and two semiconductor switches 135a and 136a, the diode 132 and the semiconductor switch 135a are connected in series, and the diode 134 and the semiconductor switch 136a are connected in series. It has become.
  • a switch such as a MOS-FET (Metal-Oxide-Semiconductor Field-Effective Transistor: MOS type field effect transistor) or an IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor) or the like and a diode are reversed in parallel with the switch. It is an electrical component having connected characteristics.
  • the semiconductor switch 135a is connected in series with the diode 132 in a direction in which no current flows through the diode 132 when the switch is off.
  • the semiconductor switch 136a is connected in series with the diode 134 in a direction in which no current flows through the diode 134 when the switch is off.
  • the semiconductor switches 135a and 136a are connected in series to the diode 132 and the diode 134, which are the lower arms on the negative side of the rectifier circuit 13a, respectively, but the semiconductor is connected to the diode 131 and the diode 133, which are the upper arms on the positive side.
  • the switches 135a and 136a may be connected in series, respectively.
  • the LC filter 14 is composed of a DC reactor 141 and a DC capacitor 142, and has a role of attenuating the AC component of the output voltage and current of the rectifier circuit 13a.
  • the load 15 is a motor that consumes electric power, a battery for storing electricity, or the like.
  • the voltage detecting means 16 detects the output voltage (input voltage of the rectifier circuit 13a) V2 of the power receiving circuit 12.
  • the control device 17 generates a drive signal for controlling the on / off of the semiconductor switches 135a and 136a of the rectifier circuit 13a based on the information of the voltage V2 detected by the voltage detecting means 16.
  • the output of the power receiving circuit 12 is opened depending on the on / off state of the semiconductor switches 135a and 136a, and the power supply from the power receiving circuit 12 to the load 15 is cut off.
  • the output of the power reception circuit 12 operates as a voltage source. Therefore, when the output of the power reception circuit 12 is open, it is viewed from the AC power supply 5. The impedance becomes a very large value. As a result, the output power of the AC power supply 5 is reduced.
  • the on / off states and circuit operations of the semiconductor switches 135a and 136a will be described.
  • FIG. 3A and 3B are diagrams for explaining the circuit operation of the power receiving device 10 in the steady state when the semiconductor switch 135a is off and the semiconductor switch 136a is on.
  • the arrows in the figure indicate the current path.
  • FIG. 3A illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is positive, and shows the operation during the power supply period in which power is sent from the power receiving circuit 12 to the load.
  • the output voltage V2 of the power receiving circuit 12 is positive, the diode 131, the diode 134, and the semiconductor switch 136a are electrically connected, and power is supplied from the power receiving circuit 12 to the load 15.
  • the output voltage of the rectifier circuit 13a becomes equal to the input voltage V2.
  • a potential difference between the load voltage Vout and the output voltage of the rectifier circuit 13a is applied to the DC reactor 141 of the LC filter 14, and the load current increases or decreases according to this potential difference and the inductance value of the DC reactor 141.
  • FIG. 3B illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is negative, and shows the operation during the non-power supply period in which the power supply from the power receiving circuit 12 is cut off.
  • the diode 133, the diode 134, and the semiconductor switch 136a become conductive, and the power supply from the power receiving circuit 12 to the load 15 is stopped.
  • the output voltage of the rectifier circuit 13a becomes 0.
  • the current supplied to the load 15 is the energy stored in the DC reactor 141, and the load current decreases with a slope determined by the load voltage Vout and the inductance value of the DC reactor 141.
  • FIG. 4A and 4B are diagrams for explaining the circuit operation of the power receiving device 10 in the steady state when the semiconductor switch 135a is on and the semiconductor switch 136a is off.
  • the arrows in the figure indicate the current path.
  • FIG. 4A illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is positive, and shows the operation during the non-power supply period in which the power supply from the power receiving circuit 12 is cut off.
  • the output voltage V2 of the power receiving circuit 12 is positive, the diode 131, the diode 132, and the semiconductor switch 135a become conductive, and the power supply from the power receiving circuit 12 to the load 15 is stopped.
  • the output voltage of the rectifier circuit 13a becomes 0.
  • the current supplied to the load 15 is the energy stored in the DC reactor 141, and the load current decreases with a slope determined by the load voltage Vout and the inductance value of the DC reactor 141.
  • FIG. 4B illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is negative, and shows the operation during the power supply period in which power is sent from the power receiving circuit 12 to the load.
  • the rectifier circuit 13a behaves as a full bridge diode rectifier circuit. That is, when the output voltage V2 of the power receiving circuit 12 is positive, the circuit operation is shown in FIG. 3A, and when the output voltage V2 of the power receiving circuit 12 is negative, the circuit operation is shown in FIG. Since the power is supplied from the circuit 12 to the load 15, the power supply period is always reached.
  • 5A, 5B, and 5C are diagrams for explaining a basic control method of power control in the power receiving device 10 according to the first embodiment, and are schematic views of waveforms of each signal.
  • the approximate waveforms of the output voltage V2 of the power receiving circuit 12, the input current of the rectifier circuit 13a, and the drive signals of the semiconductor switches 135a and 136a are shown in order from the top.
  • the drive signal represents an on state when the waveform is 1, and an off state when the waveform is 0.
  • FIG. 5A shows the signal waveform when the output power from the power receiving device 10 is maximized.
  • the output voltage V2 and the input current of the power receiving circuit 12 have a sine wave shape and a square wave shape, respectively, and the two semiconductor switches 135a and 136a are always on. That is, FIG. 5A shows a state in which power supply is continued.
  • FIG. 5B shows a signal waveform when the output power from the power receiving device 10 is set to be smaller than that in FIG. 5A.
  • the semiconductor switches 135a and 136a are switched on and off at the zero cross or near the zero cross of the output voltage V2 of the power receiving circuit 12 detected by the voltage detecting means 16 as shown by the dotted line position in FIG. 5B. That is, the switching between the power supply period PS and the non-power supply period NPS described above is performed at zero cross or near zero cross of the output voltage V2 of the power receiving circuit 12. Further, the power control is performed by controlling the time ratio between the total power supply period and the total non-power supply period within a predetermined period.
  • the predetermined period is set in advance as an integral multiple of the half cycle of the output voltage V2 of the power receiving circuit 12, and can be changed according to the required power.
  • the repetition period of the drive signal of the semiconductor switches 135a and 136a is set to the same time as the three cycles of the output voltage V2 of the power receiving circuit 12, the time of two cycles of the output voltage V2 of the power receiving circuit 12 is the power supply period PS, and the remaining The time of one cycle is set to the non-power supply period NPS.
  • the average output voltage value of the rectifier circuit 13a in FIG. 5B is 2/3 of the average output voltage value of the rectifier circuit 13a in FIG. 5A. Therefore, when the load 15 is a resistive load, the output power in FIG.
  • the zero cross or the vicinity of the zero cross of the output voltage V2 indicates the time for which the voltage value becomes sufficiently smaller than the maximum value of the output voltage V2 of the power receiving circuit 12 detected by the voltage detecting means 16, and is approximately the absolute value of the output voltage V2. The time during which the value is 20% or less of the maximum value.
  • FIG. 5C shows a signal waveform when the output power from the power receiving device 10 is set to be smaller than that in FIGS. 5A and 5B.
  • the repetition cycle of the drive signals of the semiconductor switches 135a and 136a is set to the same time as the two cycles of the output voltage V2 of the power receiving circuit 12, the time of one cycle of the output voltage V2 of the power receiving circuit 12 is the power supply period PS, and the rest One cycle is set to the non-power supply period NPS.
  • the average output voltage value of the rectifier circuit 13a in FIG. 5C is 1/2 of the average output voltage value of the rectifier circuit 13a in FIG. 5A. Therefore, when the load 15 is a resistive load, the output power in FIG. 5C is 1/4 of the output power in the signal waveform shown in FIG. 5A.
  • the output voltage of the rectifier circuit 13a can be controlled by adjusting the ratio of the power supply period to the non-power supply period within a preset predetermined period, and as a result, the output power can be controlled. Further, by performing the on / off switching operation of all the semiconductor switches at the timing of zero cross or near zero cross of the output voltage V2 of the power receiving circuit 12, the switching loss represented by the product of the voltage and current of the semiconductor switch is reduced to a small value. Can be suppressed.
  • FIGS. 5A, 5B, and 5C show an example in which the semiconductor switches 135a and 136a are driven so as to be switched on and off in a complementary manner, a circuit is provided even if both semiconductor switches are turned on during the power supply period. The operation is the same.
  • FIGS. 6A, 6B, and 6C are diagrams for explaining a control method by different power control of the power receiving device 10 according to the first embodiment. Similar to FIGS. 5A, 5B, and 5C, FIGS. 6A, 6B, and 6C show approximate waveforms of the input voltage V2 of the rectifier circuit 13a, the input current of the rectifier circuit 13a, and the drive signals of the semiconductor switches 135a and 136a, respectively, in order from the top. Shown. Then, in each of the three examples shown in FIGS.
  • the output voltage V2 of the power receiving circuit 12 is 3
  • the power supply period is provided for only one cycle in the cycle, and the drive signals of the semiconductor switches 135a and 136a are set so that the average value of the output voltage is 1/3 of the maximum state (the state where the two switches are always on). It is set.
  • the power supply period PS is set with one cycle of the frequency of the output voltage V2 of the power receiving circuit 12 as one unit, as in the example of FIGS. 5A, 5B, and 5C.
  • the power supply period PS is set with the half cycle of the frequency of the output voltage V2 of the power receiving circuit 12 as one unit, and the power supply period PS of this one unit is further set. Is intermittently provided, and the same time as one cycle of the output voltage V2 of the power receiving circuit 12 is set as the total power feeding period within the repeating cycle of the drive signal.
  • the signal waveform of FIG. 6C shows an example of a method of setting the power supply period and the non-power supply period according to the polarity of the output voltage V2 of the power receiving circuit 12. That is, in FIG. 6C, the first two positive periods of the output voltage V2 of the power receiving circuit 12 are set to the feeding period PS, and the negative period is always set to the non-feeding period NPS. Then, as in FIG. 6B, the power supply period PS is set with the half cycle of the frequency of the output voltage V2 of the power receiving circuit 12 as one unit, and the power supply period PS of this one unit is intermittently provided to repeat the drive signal cycle. The total power supply period is the same as one cycle of the output voltage V2 of the power receiving circuit 12.
  • the average value of the output voltage is set to 1/3 of the maximum state (the state in which the two switches are always on), but as a drive signal for the semiconductor switches 135a and 136a. Achieves this using different waveforms.
  • the magnitude of the ripple current included in the output current of the rectifier circuit differs depending on the difference in the waveform of the drive signal. For example, in the waveform of the drive signal of FIG. 6A, the non-feeding period is the time of two cycles of the output voltage V2 of the power receiving circuit 12, but in the waveform of the drive signal of FIG. 6B, the non-feeding period is 2 within the repetition cycle of the drive signal.
  • the non-power supply period per time is the time of one cycle of the output voltage V2 of the power receiving circuit 12.
  • the ripple current of the input current of the rectifier circuit 13a becomes smaller, so that the ripple current in FIG. 6B becomes smaller than that in the case of the waveform of the drive signal in FIG. 6A.
  • the ripple current which is an AC component, needs to be attenuated by the LC filter 14, if the ripple current is small, the LC filter 14 can be miniaturized.
  • the power receiving device 10 detects the voltage detection of the power receiving circuit 12 for receiving the power from the power transmitting circuit 11 and the output voltage V2 of the power receiving circuit 12.
  • a power converter 13 rectifying circuit 13a having means 16 and semiconductor switches 135a and 136a and converting AC power received by the power receiving circuit 12 into DC power, and an output voltage V2 of the power receiving circuit 12 detected by the voltage detecting means 16.
  • At least a control device for controlling the semiconductor switches 135a and 136a is provided based on the above, and the conduction state and the cutoff state with the power receiving circuit 12 are switched by the operation of the semiconductor switches 135a and 136a. In this configuration, a cutoff state can be formed between the power receiving circuit and the power converter by opening instead of short-circuiting, and there is no risk of damage to the elements constituting the power converter due to overcurrent.
  • the ratio of the power supply period in which the power converter 13 and the power receiving circuit 12 are in a conductive state and the ratio of the non-power supply period in which the power converter 13 and the power receiving circuit 12 are cut off is adjusted.
  • the output voltage of the power converter 13 can be controlled, and as a result, the output power can be controlled.
  • switching loss can be suppressed and highly efficient power control becomes possible.
  • FIG. 7 is a schematic circuit diagram showing the configuration of the power receiving device according to the second embodiment.
  • the same or corresponding parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.
  • the arrangement of the two semiconductor switches 135b and 136b in the rectifier circuit 13b is different from that of the first embodiment, and the diode 133 and the diode 134 are connected in series, respectively.
  • the arrangement of the semiconductor switches 135b and 136b in FIG. 7 is an example, and the diode 131 and the diode 132 may be connected in series. That is, it may be connected in series to the diode on the leg side of either of the two left and right legs constituting the rectifier circuit 13b.
  • FIG. 8 illustrates one of the current paths during the non-feeding period in the configuration of FIG. 7.
  • the energy stored in the DC reactor 141 can be recirculated via the load 15, the diode 132, and the diode 131, and the recirculation path does not include a semiconductor switch.
  • the non-feeding period in the first embodiment is shown in FIGS. 3B and 4A, the energy recirculation path of the DC reactor 141 includes a semiconductor switch.
  • the recirculation path is cut off if the semiconductor switch is damaged or malfunctions, and the energy stored in the DC reactor 141 causes an overvoltage in the circuit, causing the entire device to be affected. There is a risk of losing functionality.
  • FIGS. 9A, 9B, and 9C are diagrams for explaining an example of a control method of power control of the power receiving device according to the second embodiment, and are schematic views of waveforms of each signal of the power receiving device. From the top, the output voltage V2 of the power receiving circuit 12, the input current of the rectifier circuit 13b, and the approximate waveforms of the drive signals of the semiconductor switches 135b and 136b are shown. In each of the three examples shown in FIGS. 9A, 9B, and 9C, the semiconductor switch is such that the average value of the output voltage from the power receiving device is 1/3 of the maximum state (the state in which the two switches are always on). The drive signals of 135b and 136b are set.
  • a power control method for driving a semiconductor switch with one cycle of the output voltage V2 of the power receiving circuit 12 as one unit and in the signal waveform of FIG. 9B, a half cycle of the output voltage V2 of the power receiving circuit 12 is used.
  • a power control method for driving a semiconductor switch as one unit, and a power control method for setting a power supply period PS and a non-power supply period NPS according to the polarity of the output voltage V2 of the power receiving circuit 12 are shown in the signal waveform of FIG. 9C. It is a thing.
  • the state of the other semiconductor switch may be either on or off.
  • the semiconductor switch 135b and 136b even if both the semiconductor switches 135b and 136b are on, if the output voltage V2 of the power receiving circuit 12 is positive, the semiconductor switch 136b side becomes the current path, while the output voltage of the power receiving circuit 12 When V2 is negative, the semiconductor switch 135b side becomes the current path. Therefore, in the drive signals of the semiconductor switches 135b and 136b of FIGS. 9A, 9B, and 9C, the time indicated as on (the signal is 1) is the time, and the time indicated by the diagonal line is off even if it is on. It is a good period. Further, in FIG. 9C, the drive signal of the semiconductor switch 135b is switched on and off, but the circuit operation is the same even in the constantly off state.
  • the power receiving device of the second embodiment has the same effect as that of the first embodiment.
  • the semiconductor switches 135b and 136b are connected in series to the diode on the leg side of either of the two left and right legs constituting the rectifier circuit 13b which is the power converter 13. It is possible to provide a non-power supply period by turning off the semiconductor switches 135b and 136b at the same time. As a result, it is possible to suppress the generation of an excessive voltage due to the state of the semiconductor switch in the recirculation path of the energy stored in the DC reactor 141 during the non-feeding period. Further, since the two semiconductor switches 135b and 136b can be controlled by one drive signal, there is an effect that the control device can be simplified as compared with the first embodiment.
  • FIG. 10 is a schematic circuit diagram showing the configuration of the power receiving device according to the third embodiment.
  • the same or corresponding parts as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted.
  • the power receiving device according to the third embodiment further includes a current detecting means 18 for detecting the current ILdc flowing through the DC reactor 141 and a voltage detecting means 19 for detecting the voltage Vout of the load 15.
  • the current and voltage information detected by the current detecting means 18 and the voltage detecting means 19 is input to the control device 17.
  • the control device 17 sets the output power command value Pout * so that the output from the power receiving device becomes a preset predetermined output power, and generates a drive signal for the semiconductor switch. This was an example of controlling a semiconductor switch and controlling power.
  • the control device 17 divides the output power command value Pout * by the load voltage Vout detected by the voltage detecting means 19 to calculate the current command value ILdc * of the DC reactor 141 and detect the current.
  • the output power is controlled by using current control that controls the semiconductor switch so that the current ILdc of the DC reactor 141 detected by the means 18 becomes the current command value ILdc *.
  • 11A, 11B, 11C, and 11D are schematic views of waveforms of each signal in the power receiving device according to the third embodiment, and are diagrams for explaining a drive signal pattern used for reactor current control.
  • the drive signal pattern for controlling the semiconductor switches 135b and 136b so as to have the following four voltages with respect to the maximum voltage of the average output voltage of the rectifier circuit 13b is set to the non-power supply state. Is added to set five drive signal patterns.
  • Drive signal pattern I A pattern in which the average output voltage is the maximum voltage
  • Drive signal pattern II A pattern in which the average output voltage is 3/4 of the maximum voltage
  • Drive signal pattern III A pattern in which the average output voltage is 1/2 of the maximum voltage
  • Drive signal pattern IV A pattern in which the average output voltage is 1/4 of the maximum voltage
  • Drive signal pattern V A pattern in which no power is supplied. The control device 17 holds and executes these drive signal patterns.
  • FIG. 11A is a diagram showing the drive signal pattern I, indicating that the power supply state is continuing.
  • FIG. 11B is a diagram showing the drive signal pattern II. Focusing on two cycles of the output voltage V2 of the power receiving circuit 12, the 1.5 cycle period is the power supply period PS, and the half cycle period is the non-power supply period NPS. This is a pattern in which the average output voltage of the rectifier circuit 13b is 3/4 of the maximum voltage.
  • FIG. 11C is a diagram showing the drive signal pattern III. Focusing on the two cycles of the output voltage V2 of the power receiving circuit 12, the power supply period PS for half a cycle and the non-power supply period NPS for half a cycle are repeated.
  • FIG. 11D is a diagram showing the drive signal pattern IV. Focusing on two cycles of the output voltage V2 of the power receiving circuit 12, the half cycle period is the power supply period PS, and the 1.5 cycle period is the non-power supply period NPS. This is a pattern in which the average output voltage of the rectifier circuit 13b is 1/4 of the maximum voltage.
  • the drive signal pattern V is not shown, both the semiconductor switches 135b and 136b are off (the drive signal is 0), and the power supply is not supplied.
  • step S101 is the non-power supply state, which corresponds to the execution of the drive signal pattern V.
  • the control device 17 divides the set output power command value Pout * by the load voltage Vout detected by the voltage detecting means 19 to calculate the current command value ILdc * of the DC reactor 141. Further, the current ILdc of the DC reactor 141 detected by the current detecting means 18 is input to the control device 17.
  • step S102 When the drive signal pattern IV is executed in step S102 of the start of power supply, the current ILdc of the DC reactor 141 increases.
  • step S103 it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S201 shown in the flowchart of FIG. 12B. move on. If the current ILdc of the detected DC reactor 141 does not reach the current command value ILdc * in step S103 (NO), the drive signal pattern III is executed in step S104.
  • step S104 When the drive signal pattern III is executed in step S104, the current ILdc of the DC reactor 141 is further increased.
  • step S105 it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S301 shown in the flowchart of FIG. 12C. move on. If the current ILdc of the detected DC reactor 141 does not reach the current command value ILdc * in step S105 (NO), the drive signal pattern II is executed in step S106.
  • step S106 When the drive signal pattern II is executed in step S106, the current ILdc of the DC reactor 141 is further increased.
  • step S107 it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S401 shown in the flowchart of FIG. 12D. move on. If the current ILdc of the detected DC reactor 141 does not reach the current command value ILdc * in step S107 (NO), the drive signal pattern I is executed in step S108.
  • step S109 it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S501 shown in the flowchart of FIG. 12E. move on. If the current ILdc of the DC reactor 141 detected in step S109 does not reach the current command value ILdc * (NO), there is a concern that there is a problem in setting the current command value ILdc *, so control is performed in step S110. Stop power supply as impossible.
  • steps S103, S105, S107, and S109 it is determined as follows whether the detected current ILdc of the DC reactor 141 does not reach the current command value ILdc * or exceeds the current command value ILdc *. For example, if the detected current ILdc of the DC reactor 141 does not fluctuate for a certain period of time and does not reach the current command value ILdc *, it is determined that the current command value ILdc * is not reached. Alternatively, if the current command value ILdc * is not reached even after three times the repetition period of the drive signal has elapsed, it is determined that the current command value ILdc * is not reached.
  • the elapsed time can be set arbitrarily. In this way, the determination is made based on the saturation status or transition of the current ILdc of the detected DC reactor 141.
  • step S201 When the current ILdc of the detected DC reactor 141 becomes equal to or higher than the current command value ILdc * in step S103, the process proceeds to step S201 of FIG. 12B, and the drive signal pattern V is executed. That is, it is in a non-powered state. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S202, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the non-power supply state in step S201 is continued.
  • step S202 When the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S202, the drive signal pattern IV is executed in step S203, and the current ILdc of the DC reactor 141 increases. After that, the drive signal pattern V and the drive signal pattern IV are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
  • step S301 the process proceeds to step S301 of FIG. 12C, and the drive signal pattern IV is executed. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S302, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the execution of the drive signal pattern IV in step S301 is continued.
  • step S302 If the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S302, the drive signal pattern III is executed in step S303, and the current ILdc of the DC reactor 141 increases. After that, the drive signal pattern IV and the drive signal pattern III are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
  • step S107 when the current ILdc of the detected DC reactor 141 becomes equal to or higher than the current command value ILdc * in step S107, the process proceeds to step S401 of FIG. 12D, and the drive signal pattern III is executed. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S402, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the execution of the drive signal pattern III in step S401 is continued.
  • step S402 If the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S402, the drive signal pattern II is executed in step S403, and the current ILdc of the DC reactor 141 increases. After that, the drive signal pattern III and the drive signal pattern II are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
  • step S109 when the current ILdc of the detected DC reactor 141 becomes equal to or higher than the current command value ILdc * in step S109, the process proceeds to step S501 of FIG. 12E, and the drive signal pattern II is executed. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S502, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the execution of the drive signal pattern II in step S501 is continued.
  • step S502 If the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S502, the drive signal pattern I is executed in step S503, and the current ILdc of the DC reactor 141 increases. After that, the drive signal pattern II and the drive signal pattern I are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
  • the current is controlled at a voltage close to the load voltage Vout. It can be performed.
  • the current ILdc of the DC reactor 141 does not exceed the current command value ILdc * even when the drive signal pattern I is executed in step S109, the power supply is stopped as uncontrollable in step S110, but the current
  • the current In addition to problems with the setting of the command value ILdc *, there is a possibility that current control cannot be performed in principle. Therefore, it is necessary to change the test conditions or circuit constants.
  • the current control method according to the third embodiment is performed rather than operating the power receiving device only with the drive signal pattern I which is the maximum voltage and the drive signal pattern V in the non-powered state. If it is applied, the inductance value required for the DC reactor 141 can be designed to be smaller, so that the size can be reduced.
  • the drive signal pattern and control method shown above are examples of the third embodiment.
  • the number of drive signal patterns may be increased or decreased to five or less, or the type of drive method may be changed to a different one. It is also possible to do it.
  • the control device 17 has at least three drive signal patterns, and based on the current ILdc detected by the current detecting means 18, two drive signal patterns in which the ratio of the power supply period to the non-power supply period is close are obtained from a plurality of drive signal patterns. It may be used to control the semiconductor switch so that the output power command value Pout * is set in a stepwise manner.
  • the power receiving device has the same effect as that of the second embodiment. Further, a current detecting means 18 for detecting the current ILdc flowing through the DC reactor 141 and a voltage detecting means 19 for detecting the voltage Vout of the load 15 are provided, and the current ILdc of the DC reactor 141 detected by the current detecting means 18 is the current command value. Since the output power is controlled by using the current control that controls the semiconductor switch so that it becomes ILdc *, the average output voltage of the rectifying circuit 13b is gradually increased to a voltage close to the load voltage Vout. By controlling the current, it is possible to suppress the fluctuation amount of the applied voltage and the applied voltage to the DC reactor 141, and it is possible to reduce the output current ripple of the rectifying circuit 13b.
  • FIG. 7 of the second embodiment shows an example in which the current detecting means 18 for detecting the current ILdc flowing in the DC reactor 141 and the voltage detecting means 19 for detecting the voltage Vout of the load 15 are provided.
  • the current detecting means 18 for detecting the current ILdc flowing through the DC reactor 141 and the voltage detecting means 19 for detecting the voltage Vout of the load 15 may be provided.
  • FIG. 13 is a schematic circuit diagram showing the configuration of the power receiving device according to the fourth embodiment.
  • the bidirectional switch 20 is connected between the power receiving circuit 12 and the rectifier circuit 13c.
  • the rectifier circuit 13c which is a power converter, is composed of only four diodes.
  • the power receiving device controls the output power with the bidirectional switch 20.
  • the bidirectional switch 20 When the bidirectional switch 20 is on, the power supply period is high, and when the bidirectional switch 20 is off, the power supply period is non-power supply. It becomes.
  • the power receiving circuit and the power converter are not short-circuited but open and cut off, so that the power due to overcurrent is cut off. There is no risk of damage to the elements that make up the converter, that is, the diode and the like.
  • the timing of switching the bidirectional switch 20 on and off is performed at zero cross or near zero cross of the input voltage V2 of the rectifier circuit 13c. As a result, it is possible to suppress the switching loss of the bidirectional switch 20 as in the above-described first to third embodiments.
  • the output power can be controlled by the time when the bidirectional switch is on, and can be controlled regardless of the polarity of the input voltage V2 of the rectifier circuit 13c. Therefore, the program of the control device can be simplified and the calculation load of the control device can be reduced. Further, since the rectifier circuit 13c becomes a full bridge diode rectifier circuit, modularized parts can be applied, and an effect of simplifying circuit mounting can be obtained.
  • 14A, 14B, and 14C are diagrams for explaining a control method by power control of the power receiving device according to the fourth embodiment.
  • 14A, 14B, and 14C show approximate waveforms of the input voltage V2 of the rectifier circuit 13c, the input current of the rectifier circuit 13c, and the drive signal of the bidirectional switch 20 in this order from the top.
  • the power supply period is set to one cycle among the three cycles of the output voltage V2 of the power receiving circuit 12.
  • the drive signal of the bidirectional switch 20 is set so that the average value of the output voltage is 1/3 of the maximum state (the bidirectional switch is always on).
  • 14A and 14C correspond to the output power controls of FIGS. 6A and 6C of the first embodiment, respectively.
  • the same output power control as in the first embodiment can be performed.
  • FIG. 14B shows an example in which a half cycle of the output voltage V2 of the power receiving circuit 12 is set as one unit of the power feeding period PS, and the repeating cycle of the drive signal is 1.5 cycles of the output voltage V2 of the power receiving circuit 12.
  • the drive signal of the bidirectional switch 20 is set so that the average value of the output voltage is 1/3 of the maximum state (the bidirectional switch is always on).
  • FIG. 14B corresponds to the output power control of FIG. 9B of the second embodiment. As described above, in the fourth embodiment using the bidirectional switch 20, the same output power control as in the first embodiment can be performed.
  • FIG. 13 shows a configuration in which only the voltage detecting means 16 for detecting the output voltage V2 of the power receiving circuit 12 is provided as the means for detecting the current or the voltage, the voltage detecting means of the load 15 and the LC filter 14 are provided.
  • the current detecting means of the included DC reactor 141 it is also possible to carry out power control by the reactor current control as shown in the third embodiment.
  • the bidirectional switch 20 is provided between the power receiving circuit 12 and the rectifier circuit 13c which is a power converter, and the power supply period and the non-power supply period are switched. Therefore, not only the effects of the first to third embodiments can be obtained, but also the device configuration can be simplified, and the effects of miniaturization and cost reduction can be obtained.
  • the control device 17 is composed of a processor 170 and a storage device 171 as shown in FIG. 15 as an example of hardware.
  • the storage device includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory. Further, an auxiliary storage device of a hard disk may be provided instead of the flash memory.
  • the processor 170 executes the program input from the storage device 171. In this case, a program is input from the auxiliary storage device to the processor 170 via the volatile storage device. Further, the processor 170 may output data such as a calculation result to the volatile storage device of the storage device 171 or may store the data in the auxiliary storage device via the volatile storage device.

Abstract

A power receiving device (10) of a wireless power feed system (1) that is connected to an electric power source (5) and that receives electric power from a power transmission circuit (11) having a power transmission coil (111), the power receiving device (10) including: a power receiving circuit (12); a power converter (13a); an LC filter (14); and switches (135a, 136b) that are controlled by a control device (17) on the basis of voltage (V2) detected by a voltage detecting means (16) that detects output voltage of the power receiving circuit (12) and that cuts off between the power receiving circuit (12) and the power converter (13a) when power is not being supplied.

Description

受電装置及びワイヤレス給電システムPower receiving device and wireless power supply system
　本願は、受電装置及びワイヤレス給電システムに関する。 This application relates to a power receiving device and a wireless power supply system.
　空間を隔てた２つのコイル間での磁界結合により電力を伝送するワイヤレス給電技術がある。ワイヤレス給電技術において給電電力を調整する方法は様々であり、その多くは送電側の電力変換器を制御することにより行われる。しかしながら、ワイヤレス給電技術の適用先における負荷の多くはバッテリなどの蓄電要素であるため、その蓄電要素の充電状況に応じて給電電力を調整するためには負荷側（受電側）にある電力変換器で電力制御を行うことが望ましい。以上の理由から、受電側の電力変換器のみにより伝送電力制御する方法について、種々の手法が報告されている（例えば、特許文献１参照）。 There is a wireless power supply technology that transmits power by magnetic field coupling between two coils that separate a space. There are various methods of adjusting the power supply in wireless power supply technology, and most of them are performed by controlling the power converter on the transmission side. However, since most of the load to which the wireless power supply technology is applied is a power storage element such as a battery, a power converter on the load side (power receiving side) is required to adjust the power supply power according to the charging status of the power storage element. It is desirable to control the power with. For the above reasons, various methods have been reported as methods for controlling transmission power only by the power converter on the power receiving side (see, for example, Patent Document 1).
　特許文献１に開示された受電装置は、送電側から交流電力を受電するコイルに２つの電力変換器が接続され、コイル側の第１の電力変換器は交流電圧を直流電圧に整流し、第１の電力変換器に接続された第２の電力変換器は整流された直流電圧を、任意の直流電圧または交流電圧に変換する。そして、一方の電力変換器により、伝送側との間の伝送効率を制御し、他方の電力変換器により受電電力を制御することで、受電側の電力変換器のみで伝送効率の制御と給電電力の電力制御の両立を図っている。 In the power receiving device disclosed in Patent Document 1, two power converters are connected to a coil that receives AC power from the transmitting side, and the first power converter on the coil side rectifies the AC voltage to a DC voltage, and the first The second power converter connected to the power converter of 1 converts the rectified DC voltage into an arbitrary DC voltage or AC voltage. Then, by controlling the transmission efficiency with and from the transmission side by one power converter and controlling the received power by the other power converter, the transmission efficiency can be controlled and the power supply power is supplied only by the power converter on the power receiving side. We are trying to achieve both power control.
特開２０１７－９３０９４号公報JP-A-2017-93094
　特許文献１に開示された制御方法では、第１の電力変換器の動作によって受電コイルが短絡し、第１の電力変換器以降に電力を供給しないようにする短絡モードを含んでいるため、コイルからの出力が電流源的動作となる共振器の構成に適用可能な方法である。しかし、電圧源的動作となる共振器を構成すると過電流が発生し、スイッチング素子の発熱及び破壊のおそれがある。そのため、特許文献１に記載の方法を行う場合は、特定の共振器の構成にする必要があった。 The control method disclosed in Patent Document 1 includes a short-circuit mode in which the power receiving coil is short-circuited by the operation of the first power converter and power is not supplied to the first power converter and thereafter. This is a method applicable to the configuration of a resonator in which the output from is a current source operation. However, if a resonator that operates as a voltage source is configured, an overcurrent is generated, and there is a risk of heat generation and destruction of the switching element. Therefore, when the method described in Patent Document 1 is performed, it is necessary to configure a specific resonator.
　本願は、上記の課題を解決するための技術を開示するものであり、受電コイルからの電力を回路の開放によって遮断可能とし、受電側の電力変換器により電力制御を実現できる受電装置を提供することを目的とする。 The present application discloses a technique for solving the above-mentioned problems, and provides a power receiving device capable of interrupting power from a power receiving coil by opening a circuit and realizing power control by a power converter on the power receiving side. The purpose is.
　本願に開示される受電装置は、ワイヤレス給電システムの受電装置であって、受電コイルを有し、送電回路より送られる交流電力を受電する受電回路と、前記受電回路が受電した交流電力を直流電力に変換する電力変換器と、前記受電回路の出力電圧を検出する電圧検出手段と、前記受電回路と前記電力変換器との間の回路の導通と開放とを切り替える少なくとも１つのスイッチと、前記電圧検出手段により検出された電圧に基づいて、前記スイッチを制御する制御装置と、を備えたものである。 The power receiving device disclosed in the present application is a power receiving device of a wireless power feeding system, which has a power receiving coil and receives AC power sent from a power transmission circuit, and DC power obtained by the power receiving circuit. A power converter that converts to, a voltage detecting means that detects the output voltage of the power receiving circuit, at least one switch that switches between conduction and opening of the circuit between the power receiving circuit and the power converter, and the voltage. It includes a control device that controls the switch based on the voltage detected by the detection means.
　本願に開示される受電装置によれば、受電コイルからの電力を回路の開放によって遮断可能となるため、電圧源的動作となる共振器の構成に対して、受電側の電力変換器を用いた電力制御を行うことが可能となる。 According to the power receiving device disclosed in the present application, the power from the power receiving coil can be cut off by opening the circuit. Therefore, the power converter on the power receiving side is used for the configuration of the resonator that operates as a voltage source. It becomes possible to perform power control.
実施の形態１に係るワイヤレス給電システムの例を示す概略構成図である。It is a schematic block diagram which shows the example of the wireless power supply system which concerns on Embodiment 1. FIG. 実施の形態１に係る受電装置の構成を示す概略回路図である。It is a schematic circuit diagram which shows the structure of the power receiving device which concerns on Embodiment 1. FIG. 図２に示す受電装置の動作を説明する図である。It is a figure explaining the operation of the power receiving device shown in FIG. 図２に示す受電装置の動作を説明する図である。It is a figure explaining the operation of the power receiving device shown in FIG. 図２に示す受電装置の動作を説明する図である。It is a figure explaining the operation of the power receiving device shown in FIG. 図２に示す受電装置の動作を説明する図である。It is a figure explaining the operation of the power receiving device shown in FIG. 実施の形態１に係る受電装置における各信号の波形の概略図で、電力制御の基本的な制御方法を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining a basic control method of power control. 実施の形態１に係る受電装置における各信号の波形の概略図で、電力制御の基本的な制御方法を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining a basic control method of power control. 実施の形態１に係る受電装置における各信号の波形の概略図で、電力制御の基本的な制御方法を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining a basic control method of power control. 実施の形態１に係る受電装置における各信号の波形の概略図で、電力制御の制御方法の例を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining an example of a control method of power control. 実施の形態１に係る受電装置における各信号の波形の概略図で、電力制御の制御方法の別の例を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining another example of a control method of power control. 実施の形態１に係る受電装置における各信号の波形の概略図で、電力制御の制御方法のさらに別の例を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the first embodiment, and is a diagram for explaining still another example of a control method of power control. 実施の形態２に係る受電装置の構成を示す概略回路図である。It is a schematic circuit diagram which shows the structure of the power receiving device which concerns on Embodiment 2. FIG. 図７の構成における非給電期間の電流経路を示す図である。It is a figure which shows the current path of the non-feeding period in the configuration of FIG. 実施の形態２に係る受電装置における各信号の波形の概略図で、電力制御の制御方法の例を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the second embodiment, and is a diagram for explaining an example of a control method of power control. 実施の形態２に係る受電装置における各信号の波形の概略図で、電力制御の制御方法の例を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the second embodiment, and is a diagram for explaining an example of a control method of power control. 実施の形態２に係る受電装置における各信号の波形の概略図で、電力制御の制御方法の例を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the second embodiment, and is a diagram for explaining an example of a control method of power control. 実施の形態３に係る受電装置の構成を示す概略回路図である。It is a schematic circuit diagram which shows the structure of the power receiving device which concerns on Embodiment 3. 実施の形態３に係る受電装置における各信号の波形の概略図で、リアクトル電流制御に用いる駆動信号パターンＩを説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern I used for reactor current control. 実施の形態３に係る受電装置における各信号の波形の概略図で、リアクトル電流制御に用いる駆動信号パターンＩＩを説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern II used for reactor current control. 実施の形態３に係る受電装置における各信号の波形の概略図で、リアクトル電流制御に用いる駆動信号パターンＩＩＩを説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern III used for reactor current control. 実施の形態３に係る受電装置における各信号の波形の概略図で、リアクトル電流制御に用いる駆動信号パターンＩＶを説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the third embodiment, and is a diagram for explaining a drive signal pattern IV used for reactor current control. 実施の形態３に係る受電装置におけるリアクトル電流制御による電力制御を行うフローチャート図である。It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3. FIG. 実施の形態３に係る受電装置におけるリアクトル電流制御による電力制御を行うフローチャート図である。It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3. FIG. 実施の形態３に係る受電装置におけるリアクトル電流制御による電力制御を行うフローチャート図である。It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3. FIG. 実施の形態３に係る受電装置におけるリアクトル電流制御による電力制御を行うフローチャート図である。It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3. FIG. 実施の形態３に係る受電装置におけるリアクトル電流制御による電力制御を行うフローチャート図である。It is a flowchart which performs power control by reactor current control in the power receiving device which concerns on Embodiment 3. FIG. 実施の形態４に係る受電装置の構成を示す概略回路図である。It is a schematic circuit diagram which shows the structure of the power receiving device which concerns on Embodiment 4. FIG. 実施の形態４に係る受電装置における各信号の波形の概略図で、電力制御の制御方法の例を説明するための図である。FIG. 5 is a schematic diagram of a waveform of each signal in the power receiving device according to the fourth embodiment, and is a diagram for explaining an example of a control method of power control. 実施の形態４に係る受電装置における各信号の別波形の概略図で、電力制御の制御方法の例を説明するための図である。FIG. 5 is a schematic diagram of another waveform of each signal in the power receiving device according to the fourth embodiment, and is a diagram for explaining an example of a control method of power control. 実施の形態４に係る受電装置における各信号のさらに別の波形の概略図で、電力制御の制御方法の例を説明するための図である。It is a figure for demonstrating the example of the control method of power control with the schematic diagram of the waveform of each signal in the power receiving device which concerns on Embodiment 4. FIG. 制御装置のハードウエア構成図である。It is a hardware block diagram of a control device.
　以下、本実施の形態について図を参照して説明する。なお、各図中、同一符号は、同一または相当する部分を示すものとする。 Hereinafter, the present embodiment will be described with reference to the drawings. In each figure, the same reference numerals indicate the same or corresponding parts.
実施の形態１． 
　以下、実施の形態１に係るワイヤレス給電システムについて説明する。
　図１は、本実施の形態１に係るワイヤレス給電システムの概略構成を示す図である。図１において、ワイヤレス給電システム１は、主電源である交流電源５から供給された電力を送電する送電回路１１と、送電回路１１からの電力を受電し、負荷１５に出力する受電装置１０を備える。受電装置１０は、受電回路１２、電力変換器１３、及びＬＣフィルタ１４を備える。 Embodiment 1.
Hereinafter, the wireless power supply system according to the first embodiment will be described.
FIG. 1 is a diagram showing a schematic configuration of a wireless power supply system according to the first embodiment. In FIG. 1, the wireless power supply system 1 includes a power transmission circuit 11 that transmits power supplied from an AC power source 5 that is a main power source, and a power receiving device 10 that receives power from the power transmission circuit 11 and outputs it to a load 15. .. The power receiving device 10 includes a power receiving circuit 12, a power converter 13, and an LC filter 14.
　交流電源５から供給された電力は、送電回路１１と受電回路１２との間において非接触で送られる。電力変換器１３は、受電回路１２にて受電した交流電力を直流電力に変換し、受電電力を予め設定された電力に調整する電力変換器の役割を担う。ＬＣフィルタ１４では電力変換器１３の出力電力に含まれる交流成分を減衰させる。ＬＣフィルタ１４から出力された電力は負荷１５にて消費あるいは蓄電等が行われる。 The electric power supplied from the AC power source 5 is transmitted in a non-contact manner between the power transmission circuit 11 and the power reception circuit 12. The power converter 13 plays the role of a power converter that converts the AC power received by the power receiving circuit 12 into DC power and adjusts the received power to preset power. The LC filter 14 attenuates the AC component included in the output power of the power converter 13. The electric power output from the LC filter 14 is consumed or stored in the load 15.
　送電回路１１は、少なくとも一つのコイルを含む回路であり、図１においては送電コイル１１１と送電側コンデンサ１１２が直列接続された構成となっている。ワイヤレス給電を行う上で送電側コンデンサ１１２は必須ではないが、送電側コンデンサ１１２がない場合は送受電コイル間の電力伝送効率が大幅に低下する。そのため、送電側コンデンサ１１２を使用して力率補償を行うことが望ましい。 The power transmission circuit 11 is a circuit including at least one coil, and in FIG. 1, the power transmission coil 111 and the power transmission side capacitor 112 are connected in series. The power transmission side capacitor 112 is not indispensable for wireless power supply, but if the power transmission side capacitor 112 is not provided, the power transmission efficiency between the power transmission / reception coils is significantly reduced. Therefore, it is desirable to use the power transmission side capacitor 112 to perform power factor compensation.
　受電回路１２は、少なくとも一つのコイルを含む回路であり、図１においては受電コイル１２１と受電側コンデンサ１２２が並列接続された構成となっている。ワイヤレス給電を行う上で受電側コンデンサ１２２は必須ではないが、受電側コンデンサ１２２がない場合は送受電コイル間の電力伝送効率が大幅に低下する。そのため、受電側コンデンサ１２２を使用して力率補償を行うことが望ましい。 The power receiving circuit 12 is a circuit including at least one coil, and in FIG. 1, the power receiving coil 121 and the power receiving side capacitor 122 are connected in parallel. The power receiving side capacitor 122 is not indispensable for wireless power supply, but if the power receiving side capacitor 122 is not provided, the power transmission efficiency between the power transmitting and receiving coils is significantly reduced. Therefore, it is desirable to use the power receiving side capacitor 122 to perform power factor compensation.
　上述した送電回路１１と受電回路１２の構成に依存して、受電回路１２の出力が電圧源的動作もしくは電流源的動作となる。図１に示す送電回路１１と受電回路１２の構成においては、電源が電圧源であり、共振器がイミタンス変換特性を有しないため、受電回路１２の出力は電圧源的動作となる。なお、図１に示す送電回路１１と受電回路１２の構成は一例であり、それぞれの構成を限定するものではないが、本実施の形態では受電回路１２の出力が電圧源的動作となる構成を対象としている。 Depending on the configuration of the power transmission circuit 11 and the power reception circuit 12 described above, the output of the power reception circuit 12 becomes a voltage source operation or a current source operation. In the configuration of the power transmission circuit 11 and the power reception circuit 12 shown in FIG. 1, since the power supply is the voltage source and the resonator does not have the imittance conversion characteristic, the output of the power reception circuit 12 operates as a voltage source. The configuration of the power transmission circuit 11 and the power reception circuit 12 shown in FIG. 1 is an example, and the configuration of each is not limited. However, in the present embodiment, the output of the power reception circuit 12 operates as a voltage source. It is targeted.
　図２は実施の形態１に係る受電装置１０の構成を示す概略回路図である。本実施の形態においては、電力変換器１３として整流回路１３ａを用いた例で説明する。整流回路１３ａは４つのダイオード１３１、１３２、１３３、１３４と２つの半導体スイッチ１３５ａ、１３６ａを備えており、ダイオード１３２と半導体スイッチ１３５ａが直列接続され、ダイオード１３４と半導体スイッチ１３６ａが直列接続された構成となっている。半導体スイッチ１３５ａ、１３６ａは、例えばＭＯＳ－ＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ：ＭＯＳ型電界効果トランジスタ）あるいはＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲートバイポーラトランジスタ）等のスイッチとダイオードが逆並列に接続された特性を有する電気部品である。半導体スイッチ１３５ａは、スイッチがオフの状態において、ダイオード１３２に電流が流れない向きにダイオード１３２と直列接続される。同様に、半導体スイッチ１３６ａは、スイッチがオフの状態において、ダイオード１３４に電流が流れない向きにダイオード１３４と直列接続される。図２では、整流回路１３ａの負側の下アームであるダイオード１３２とダイオード１３４に半導体スイッチ１３５ａ、１３６ａがそれぞれ直列に接続されているが、正側の上アームであるダイオード１３１とダイオード１３３に半導体スイッチ１３５ａ、１３６ａがそれぞれ直列接続された構成でも良い。 FIG. 2 is a schematic circuit diagram showing the configuration of the power receiving device 10 according to the first embodiment. In this embodiment, an example in which the rectifier circuit 13a is used as the power converter 13 will be described. The rectifier circuit 13a includes four diodes 131, 132, 133, 134 and two semiconductor switches 135a and 136a, the diode 132 and the semiconductor switch 135a are connected in series, and the diode 134 and the semiconductor switch 136a are connected in series. It has become. In the semiconductor switches 135a and 136a, for example, a switch such as a MOS-FET (Metal-Oxide-Semiconductor Field-Effective Transistor: MOS type field effect transistor) or an IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor) or the like and a diode are reversed in parallel with the switch. It is an electrical component having connected characteristics. The semiconductor switch 135a is connected in series with the diode 132 in a direction in which no current flows through the diode 132 when the switch is off. Similarly, the semiconductor switch 136a is connected in series with the diode 134 in a direction in which no current flows through the diode 134 when the switch is off. In FIG. 2, the semiconductor switches 135a and 136a are connected in series to the diode 132 and the diode 134, which are the lower arms on the negative side of the rectifier circuit 13a, respectively, but the semiconductor is connected to the diode 131 and the diode 133, which are the upper arms on the positive side. The switches 135a and 136a may be connected in series, respectively.
　ＬＣフィルタ１４は、ＤＣリアクトル１４１とＤＣコンデンサ１４２から構成されており、整流回路１３ａの出力電圧および電流が有する交流成分を減衰させる役割を有する。
　負荷１５は、電力消費を行うモータまたは蓄電用のバッテリなどである。
　電圧検出手段１６は、受電回路１２の出力電圧（整流回路１３ａの入力電圧）Ｖ２を検出する。 The LC filter 14 is composed of a DC reactor 141 and a DC capacitor 142, and has a role of attenuating the AC component of the output voltage and current of the rectifier circuit 13a.
The load 15 is a motor that consumes electric power, a battery for storing electricity, or the like.
The voltage detecting means 16 detects the output voltage (input voltage of the rectifier circuit 13a) V2 of the power receiving circuit 12.
　制御装置１７は、電圧検出手段１６により検出された電圧Ｖ２の情報に基づいて、整流回路１３ａの半導体スイッチ１３５ａ、１３６ａのオン、オフを制御する駆動信号を生成する。
　本実施の形態に係る受電装置１０は、半導体スイッチ１３５ａ、１３６ａのオン、オフの状態によっては、受電回路１２の出力が開放状態となり、受電回路１２から負荷１５への電力供給が遮断される。上述したように、本実施の形態の送電回路１１と受電回路１２の構成では、受電回路１２の出力が電圧源的動作となるので、受電回路１２の出力が開放状態において、交流電源５から見たインピーダンスが非常に大きな値になる。その結果、交流電源５の出力電力は減少する。
　以下、半導体スイッチ１３５ａ、１３６ａのオン、オフの状態及び回路動作について説明する。 The control device 17 generates a drive signal for controlling the on / off of the semiconductor switches 135a and 136a of the rectifier circuit 13a based on the information of the voltage V2 detected by the voltage detecting means 16.
In the power receiving device 10 according to the present embodiment, the output of the power receiving circuit 12 is opened depending on the on / off state of the semiconductor switches 135a and 136a, and the power supply from the power receiving circuit 12 to the load 15 is cut off. As described above, in the configuration of the power transmission circuit 11 and the power reception circuit 12 of the present embodiment, the output of the power reception circuit 12 operates as a voltage source. Therefore, when the output of the power reception circuit 12 is open, it is viewed from the AC power supply 5. The impedance becomes a very large value. As a result, the output power of the AC power supply 5 is reduced.
Hereinafter, the on / off states and circuit operations of the semiconductor switches 135a and 136a will be described.
　図３Ａ、３Ｂは、半導体スイッチ１３５ａがオフ、半導体スイッチ１３６ａがオンの時の定常状態での受電装置１０の回路動作を説明するための図である。図中の矢印は電流経路を示している。
　図３Ａは、受電回路１２の出力電圧Ｖ２が正の場合の回路動作を図示しており、受電回路１２から負荷に電力が送られる給電期間の動作を表している。受電回路１２の出力電圧Ｖ２が正の場合、ダイオード１３１、ダイオード１３４、および半導体スイッチ１３６ａが導通し、受電回路１２から負荷１５に給電される。この時、整流回路１３ａの出力電圧は入力電圧Ｖ２と等しくなる。ＬＣフィルタ１４のＤＣリアクトル１４１には、負荷電圧Ｖｏｕｔと整流回路１３ａの出力電圧との電位差が印加され、この電位差とＤＣリアクトル１４１のインダクタンス値に応じて負荷電流が増減する。 3A and 3B are diagrams for explaining the circuit operation of the power receiving device 10 in the steady state when the semiconductor switch 135a is off and the semiconductor switch 136a is on. The arrows in the figure indicate the current path.
FIG. 3A illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is positive, and shows the operation during the power supply period in which power is sent from the power receiving circuit 12 to the load. When the output voltage V2 of the power receiving circuit 12 is positive, the diode 131, the diode 134, and the semiconductor switch 136a are electrically connected, and power is supplied from the power receiving circuit 12 to the load 15. At this time, the output voltage of the rectifier circuit 13a becomes equal to the input voltage V2. A potential difference between the load voltage Vout and the output voltage of the rectifier circuit 13a is applied to the DC reactor 141 of the LC filter 14, and the load current increases or decreases according to this potential difference and the inductance value of the DC reactor 141.
　図３Ｂは、受電回路１２の出力電圧Ｖ２が負の場合の回路動作を図示しており、受電回路１２からの電力供給が遮断される非給電期間の動作を表している。受電回路１２の出力電圧Ｖ２が負の場合、ダイオード１３３、ダイオード１３４、および半導体スイッチ１３６ａが導通し、受電回路１２から負荷１５への給電が停止する。この時、整流回路１３ａの出力電圧は０となる。負荷１５に供給される電流はＤＣリアクトル１４１に蓄えられたエネルギーであり、負荷電流は負荷電圧ＶｏｕｔとＤＣリアクトル１４１のインダクタンス値により決まる傾きで減少する。 FIG. 3B illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is negative, and shows the operation during the non-power supply period in which the power supply from the power receiving circuit 12 is cut off. When the output voltage V2 of the power receiving circuit 12 is negative, the diode 133, the diode 134, and the semiconductor switch 136a become conductive, and the power supply from the power receiving circuit 12 to the load 15 is stopped. At this time, the output voltage of the rectifier circuit 13a becomes 0. The current supplied to the load 15 is the energy stored in the DC reactor 141, and the load current decreases with a slope determined by the load voltage Vout and the inductance value of the DC reactor 141.
　図４Ａ、４Ｂは、半導体スイッチ１３５ａがオン、半導体スイッチ１３６ａがオフの時の定常状態での受電装置１０の回路動作を説明するための図である。図中の矢印は電流経路を示している。
　図４Ａは、受電回路１２の出力電圧Ｖ２が正の場合の回路動作を図示しており、受電回路１２からの電力供給が遮断される非給電期間の動作を表している。受電回路１２の出力電圧Ｖ２が正の場合、ダイオード１３１、ダイオード１３２、および半導体スイッチ１３５ａが導通し、受電回路１２から負荷１５への給電が停止する。この時、整流回路１３ａの出力電圧は０となる。負荷１５に供給される電流はＤＣリアクトル１４１に蓄えられたエネルギーであり、負荷電流は負荷電圧ＶｏｕｔとＤＣリアクトル１４１のインダクタンス値により決まる傾きで減少する。 4A and 4B are diagrams for explaining the circuit operation of the power receiving device 10 in the steady state when the semiconductor switch 135a is on and the semiconductor switch 136a is off. The arrows in the figure indicate the current path.
FIG. 4A illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is positive, and shows the operation during the non-power supply period in which the power supply from the power receiving circuit 12 is cut off. When the output voltage V2 of the power receiving circuit 12 is positive, the diode 131, the diode 132, and the semiconductor switch 135a become conductive, and the power supply from the power receiving circuit 12 to the load 15 is stopped. At this time, the output voltage of the rectifier circuit 13a becomes 0. The current supplied to the load 15 is the energy stored in the DC reactor 141, and the load current decreases with a slope determined by the load voltage Vout and the inductance value of the DC reactor 141.
　図４Ｂは、受電回路１２の出力電圧Ｖ２が負の場合の回路動作を図示しており、受電回路１２から負荷に電力が送られる給電期間の動作を表している。受電回路１２の出力電圧Ｖ２が負の場合、ダイオード１３３、ダイオード１３２、および半導体スイッチ１３５ａが導通し、受電回路１２から負荷１５に給電される。したがって、整流回路１３ａの出力電圧は入力電圧Ｖ２と等しくなる。このとき、ＤＣリアクトル１４１には、負荷電圧Ｖｏｕｔと整流回路１３ａの出力電圧との電位差が印加され、前記電位差とＤＣリアクトル１４１のインダクタンス値に応じて負荷電流が増減する。 FIG. 4B illustrates the circuit operation when the output voltage V2 of the power receiving circuit 12 is negative, and shows the operation during the power supply period in which power is sent from the power receiving circuit 12 to the load. When the output voltage V2 of the power receiving circuit 12 is negative, the diode 133, the diode 132, and the semiconductor switch 135a become conductive, and power is supplied from the power receiving circuit 12 to the load 15. Therefore, the output voltage of the rectifier circuit 13a becomes equal to the input voltage V2. At this time, a potential difference between the load voltage Vout and the output voltage of the rectifier circuit 13a is applied to the DC reactor 141, and the load current increases or decreases according to the potential difference and the inductance value of the DC reactor 141.
　半導体スイッチ１３５ａ、１３６ａが共にオンの場合、整流回路１３ａはフルブリッジダイオード整流回路として振る舞う。すなわち、受電回路１２の出力電圧Ｖ２が正の場合は図３Ａ、受電回路１２の出力電圧Ｖ２が負の場合は図４Ｂの回路動作となり、受電回路１２の出力電圧Ｖ２の極性に依存せず受電回路１２から負荷１５に給電されるため、常に給電期間となる。 When both the semiconductor switches 135a and 136a are on, the rectifier circuit 13a behaves as a full bridge diode rectifier circuit. That is, when the output voltage V2 of the power receiving circuit 12 is positive, the circuit operation is shown in FIG. 3A, and when the output voltage V2 of the power receiving circuit 12 is negative, the circuit operation is shown in FIG. Since the power is supplied from the circuit 12 to the load 15, the power supply period is always reached.
　一方、半導体スイッチ１３５ａ、１３６ａが共にオフの場合、受電回路１２から負荷１５に給電される経路がなくなる。また、ＤＣリアクトル１４１に蓄えられたエネルギーの環流経路もなくなるため、半導体スイッチ１３５ａまたは１３６ａに過電圧が発生する。過電圧の発生は半導体スイッチの破壊に繋がる虞があるため、半導体スイッチ１３５ａ、１３６ａが共にオフとならないように駆動信号を生成する必要がある。そのため、半導体スイッチ１３５ａ、１３６ａを相補的にオンとオフとの切り替えを行う場合には、両方のスイッチが共にオンとなるようなオーバーラップタイムを設けることが望ましい。 On the other hand, when both the semiconductor switches 135a and 136a are off, there is no path for power to be supplied from the power receiving circuit 12 to the load 15. Further, since the recirculation path of the energy stored in the DC reactor 141 is also eliminated, an overvoltage is generated in the semiconductor switch 135a or 136a. Since the generation of overvoltage may lead to the destruction of the semiconductor switch, it is necessary to generate a drive signal so that both the semiconductor switches 135a and 136a are not turned off. Therefore, when the semiconductor switches 135a and 136a are switched on and off in a complementary manner, it is desirable to provide an overlap time so that both switches are turned on.
　図５Ａ、５Ｂ、５Ｃは、実施の形態１に係る受電装置１０における電力制御の基本的な制御方法を説明するための図で、各信号の波形の概略図である。それぞれ上から順に、受電回路１２の出力電圧Ｖ２、整流回路１３ａの入力電流、半導体スイッチ１３５ａ、１３６ａの駆動信号の概略の波形を示している。なお、駆動信号は波形が１の時はオン、波形が０の時はオフの状態を表す。 5A, 5B, and 5C are diagrams for explaining a basic control method of power control in the power receiving device 10 according to the first embodiment, and are schematic views of waveforms of each signal. The approximate waveforms of the output voltage V2 of the power receiving circuit 12, the input current of the rectifier circuit 13a, and the drive signals of the semiconductor switches 135a and 136a are shown in order from the top. The drive signal represents an on state when the waveform is 1, and an off state when the waveform is 0.
　図５Ａは、受電装置１０からの出力電力が最大となるときの信号波形を示している。受電回路１２の出力電圧Ｖ２と入力電流はそれぞれ正弦波と矩形波形状となっており、二つの半導体スイッチ１３５ａ、１３６ａは常時オンの状態である。すなわち、図５Ａは、給電が継続している状態を示している。 FIG. 5A shows the signal waveform when the output power from the power receiving device 10 is maximized. The output voltage V2 and the input current of the power receiving circuit 12 have a sine wave shape and a square wave shape, respectively, and the two semiconductor switches 135a and 136a are always on. That is, FIG. 5A shows a state in which power supply is continued.
　図５Ｂは、図５Ａよりも受電装置１０からの出力電力を小さく設定したときの信号波形を示している。半導体スイッチ１３５ａ、１３６ａのオンとオフとの切り替えは、図５Ｂ中の点線の位置で示すように、電圧検出手段１６によって検出された受電回路１２の出力電圧Ｖ２のゼロクロスまたはゼロクロス近傍で行う。すなわち、上記した給電期間ＰＳと非給電期間ＮＰＳの切り替えは受電回路１２の出力電圧Ｖ２のゼロクロスまたはゼロクロス近傍で行われる。また、電力制御については所定期間内におけるトータルの給電期間とトータルの非給電期間の時比率を制御することで行われる。所定期間は受電回路１２の出力電圧Ｖ２の半周期の整数倍の時間に予め設定され、必要とする電力に応じて変えることができる。図５Ｂでは、半導体スイッチ１３５ａ、１３６ａの駆動信号の繰り返し周期を受電回路１２の出力電圧Ｖ２の３周期と同じ時間とし、受電回路１２の出力電圧Ｖ２の２周期の時間を給電期間ＰＳ、残りの１周期の時間を非給電期間ＮＰＳに設定している。図５Ｂにおける整流回路１３ａの出力電圧平均値は、図５Ａにおける整流回路１３ａの出力電圧平均値の２／３となる。したがって、負荷１５が抵抗負荷である場合には、図５Ｂの出力電力は図５Ａに示された信号波形での出力電力の４／９となる。
　ここで出力電圧Ｖ２のゼロクロスまたはゼロクロス近傍とは、電圧検出手段１６によって検出された受電回路１２の出力電圧Ｖ２の最大値から十分小さくなった電圧値となる時間を示し、概ね出力電圧Ｖ２の絶対値が最大値に対して２０％以下である時間である。 FIG. 5B shows a signal waveform when the output power from the power receiving device 10 is set to be smaller than that in FIG. 5A. The semiconductor switches 135a and 136a are switched on and off at the zero cross or near the zero cross of the output voltage V2 of the power receiving circuit 12 detected by the voltage detecting means 16 as shown by the dotted line position in FIG. 5B. That is, the switching between the power supply period PS and the non-power supply period NPS described above is performed at zero cross or near zero cross of the output voltage V2 of the power receiving circuit 12. Further, the power control is performed by controlling the time ratio between the total power supply period and the total non-power supply period within a predetermined period. The predetermined period is set in advance as an integral multiple of the half cycle of the output voltage V2 of the power receiving circuit 12, and can be changed according to the required power. In FIG. 5B, the repetition period of the drive signal of the semiconductor switches 135a and 136a is set to the same time as the three cycles of the output voltage V2 of the power receiving circuit 12, the time of two cycles of the output voltage V2 of the power receiving circuit 12 is the power supply period PS, and the remaining The time of one cycle is set to the non-power supply period NPS. The average output voltage value of the rectifier circuit 13a in FIG. 5B is 2/3 of the average output voltage value of the rectifier circuit 13a in FIG. 5A. Therefore, when the load 15 is a resistive load, the output power in FIG. 5B is 4/9 of the output power in the signal waveform shown in FIG. 5A.
Here, the zero cross or the vicinity of the zero cross of the output voltage V2 indicates the time for which the voltage value becomes sufficiently smaller than the maximum value of the output voltage V2 of the power receiving circuit 12 detected by the voltage detecting means 16, and is approximately the absolute value of the output voltage V2. The time during which the value is 20% or less of the maximum value.
　図５Ｃは、図５Ａおよび図５Ｂよりも受電装置１０からの出力電力を小さく設定したときの信号波形を示している。図５Ｃでは、半導体スイッチ１３５ａ、１３６ａの駆動信号の繰り返し周期を受電回路１２の出力電圧Ｖ２の２周期と同じ時間とし、受電回路１２の出力電圧Ｖ２の１周期の時間を給電期間ＰＳ、残りの１周期を非給電期間ＮＰＳに設定している。図５Ｃにおける整流回路１３ａの出力電圧平均値は、図５Ａにおける整流回路１３ａの出力電圧平均値の１／２となる。したがって、負荷１５が抵抗負荷である場合には、図５Ｃの出力電力は図５Ａに示された信号波形での出力電力の１／４となる。 FIG. 5C shows a signal waveform when the output power from the power receiving device 10 is set to be smaller than that in FIGS. 5A and 5B. In FIG. 5C, the repetition cycle of the drive signals of the semiconductor switches 135a and 136a is set to the same time as the two cycles of the output voltage V2 of the power receiving circuit 12, the time of one cycle of the output voltage V2 of the power receiving circuit 12 is the power supply period PS, and the rest One cycle is set to the non-power supply period NPS. The average output voltage value of the rectifier circuit 13a in FIG. 5C is 1/2 of the average output voltage value of the rectifier circuit 13a in FIG. 5A. Therefore, when the load 15 is a resistive load, the output power in FIG. 5C is 1/4 of the output power in the signal waveform shown in FIG. 5A.
　以上のように、予め設定された所定期間内における給電期間と非給電期間の比率を調整することで、整流回路１３ａの出力電圧を制御し、結果として出力電力を制御することができる。また、全ての半導体スイッチのオン、オフのスイッチング動作を受電回路１２の出力電圧Ｖ２のゼロクロスまたはゼロクロス近傍のタイミングで行うことで、半導体スイッチの電圧と電流の積で表されるスイッチング損失を小さい値に抑制することが可能となる。 As described above, the output voltage of the rectifier circuit 13a can be controlled by adjusting the ratio of the power supply period to the non-power supply period within a preset predetermined period, and as a result, the output power can be controlled. Further, by performing the on / off switching operation of all the semiconductor switches at the timing of zero cross or near zero cross of the output voltage V2 of the power receiving circuit 12, the switching loss represented by the product of the voltage and current of the semiconductor switch is reduced to a small value. Can be suppressed.
　なお、図５Ａ、５Ｂ、５Ｃでは半導体スイッチ１３５ａ、１３６ａのオンとオフの切り替えが相補的となるように駆動する例を示したが、給電期間において二つの半導体スイッチを共にオン状態にしても回路動作は同様となる。 Although FIGS. 5A, 5B, and 5C show an example in which the semiconductor switches 135a and 136a are driven so as to be switched on and off in a complementary manner, a circuit is provided even if both semiconductor switches are turned on during the power supply period. The operation is the same.
　次に、異なる電力制御により受電装置１０から同じ出力電力を得る方法について説明する。
　図６Ａ、６Ｂ、６Ｃは、実施の形態１に係る受電装置１０の異なる電力制御による制御方法を説明するための図である。図６Ａ、６Ｂ、６Ｃは、図５Ａ、５Ｂ、５Ｃと同様、それぞれ上から順に、整流回路１３ａの入力電圧Ｖ２、整流回路１３ａの入力電流、半導体スイッチ１３５ａ、１３６ａの駆動信号の概略の波形を示している。そして、図６Ａ、６Ｂ、６Ｃに示された３つの例は、いずれも駆動信号の繰り返し周期を受電回路１２の出力電圧Ｖ２の３周期と同じ時間とすると、受電回路１２の出力電圧Ｖ２の３周期の中で１周期だけ給電期間を設けており、出力電圧の平均値が最大の状態（二つのスイッチが常時オンの状態）の１／３となるように半導体スイッチ１３５ａ、１３６ａの駆動信号が設定されている。 Next, a method of obtaining the same output power from the power receiving device 10 by different power controls will be described.
6A, 6B, and 6C are diagrams for explaining a control method by different power control of the power receiving device 10 according to the first embodiment. Similar to FIGS. 5A, 5B, and 5C, FIGS. 6A, 6B, and 6C show approximate waveforms of the input voltage V2 of the rectifier circuit 13a, the input current of the rectifier circuit 13a, and the drive signals of the semiconductor switches 135a and 136a, respectively, in order from the top. Shown. Then, in each of the three examples shown in FIGS. 6A, 6B, and 6C, assuming that the repetition cycle of the drive signal is the same time as the three cycles of the output voltage V2 of the power receiving circuit 12, the output voltage V2 of the power receiving circuit 12 is 3 The power supply period is provided for only one cycle in the cycle, and the drive signals of the semiconductor switches 135a and 136a are set so that the average value of the output voltage is 1/3 of the maximum state (the state where the two switches are always on). It is set.
　図６Ａの信号波形において、図５Ａ、５Ｂ、５Ｃの例と同様に受電回路１２の出力電圧Ｖ２の周波数の１周期を一単位として給電期間ＰＳを設定した場合のものである。出力電力の平均値を最大の状態のＭ／Ｎに設定する場合は、駆動信号の繰り返し周期をＮ（ここではＮ＝３）、給電期間ＰＳをＭ周期（ここではＭ＝１）、とすると、給電期間ＰＳをＭ周期と非給電期間ＮＰＳを（Ｎ－Ｍ）周期（ここではＮ－Ｍ＝２）とが繰り返されるパターンとなる。 In the signal waveform of FIG. 6A, the power supply period PS is set with one cycle of the frequency of the output voltage V2 of the power receiving circuit 12 as one unit, as in the example of FIGS. 5A, 5B, and 5C. When setting the average value of the output power to the maximum M / N, assume that the drive signal repetition cycle is N (here, N = 3) and the power supply period PS is the M cycle (here, M = 1). The pattern is such that the power supply period PS is the M cycle and the non-power supply period NPS is the (NM) cycle (here, NM = 2).
　図６Ｂの信号波形においては、図６Ａに示された信号波形と異なり、受電回路１２の出力電圧Ｖ２の周波数の半周期を一単位として給電期間ＰＳを設定し、さらにこの一単位の給電期間ＰＳを間欠的に設けて、駆動信号の繰り返し周期内で受電回路１２の出力電圧Ｖ２の１周期と同じ時間をトータルの給電期間としている。 In the signal waveform of FIG. 6B, unlike the signal waveform shown in FIG. 6A, the power supply period PS is set with the half cycle of the frequency of the output voltage V2 of the power receiving circuit 12 as one unit, and the power supply period PS of this one unit is further set. Is intermittently provided, and the same time as one cycle of the output voltage V2 of the power receiving circuit 12 is set as the total power feeding period within the repeating cycle of the drive signal.
　図６Ｃの信号波形では、受電回路１２の出力電圧Ｖ２の極性に応じて給電期間と非給電期間を設定する方法の例を示している。すなわち、図６Ｃにおいて、受電回路１２の出力電圧Ｖ２の最初の２つの正の期間を給電期間ＰＳに設定し、負の期間を常に非給電期間ＮＰＳに設定している。そして、図６Ｂと同様に、受電回路１２の出力電圧Ｖ２の周波数の半周期を一単位として給電期間ＰＳを設定し、この一単位の給電期間ＰＳを間欠的に設けて、駆動信号の繰り返し周期内で受電回路１２の出力電圧Ｖ２の１周期と同じ時間をトータルの給電期間としている。 The signal waveform of FIG. 6C shows an example of a method of setting the power supply period and the non-power supply period according to the polarity of the output voltage V2 of the power receiving circuit 12. That is, in FIG. 6C, the first two positive periods of the output voltage V2 of the power receiving circuit 12 are set to the feeding period PS, and the negative period is always set to the non-feeding period NPS. Then, as in FIG. 6B, the power supply period PS is set with the half cycle of the frequency of the output voltage V2 of the power receiving circuit 12 as one unit, and the power supply period PS of this one unit is intermittently provided to repeat the drive signal cycle. The total power supply period is the same as one cycle of the output voltage V2 of the power receiving circuit 12.
　図６Ａ、６Ｂ、６Ｃは、いずれも出力電圧の平均値が最大の状態（二つのスイッチが常時オンの状態）の１／３となるようにしているが、半導体スイッチ１３５ａ、１３６ａの駆動信号としては異なる波形を用いてこれを実現している。この駆動信号の波形の違いにより整流回路の出力電流に含まれるリプル電流の大きさが異なってくる。たとえば、図６Ａの駆動信号の波形では非給電期間が受電回路１２の出力電圧Ｖ２の２周期の時間であるが、図６Ｂの駆動信号の波形では駆動信号の繰り返し周期内で非給電期間は２回あり、１回あたりの非給電期間は受電回路１２の出力電圧Ｖ２の１周期の時間となっている。非給電期間の時間が短くなると整流回路１３ａの入力電流のリプル電流が小さくなるため、図６Ｂの方が図６Ａの駆動信号の波形の場合よりもリプル電流が小さくなる。最終的に交流成分であるリプル電流はＬＣフィルタ１４にて減衰させる必要があるため、リプル電流が小さければＬＣフィルタ１４を小形化することが可能となる。 In FIGS. 6A, 6B, and 6C, the average value of the output voltage is set to 1/3 of the maximum state (the state in which the two switches are always on), but as a drive signal for the semiconductor switches 135a and 136a. Achieves this using different waveforms. The magnitude of the ripple current included in the output current of the rectifier circuit differs depending on the difference in the waveform of the drive signal. For example, in the waveform of the drive signal of FIG. 6A, the non-feeding period is the time of two cycles of the output voltage V2 of the power receiving circuit 12, but in the waveform of the drive signal of FIG. 6B, the non-feeding period is 2 within the repetition cycle of the drive signal. There are times, and the non-power supply period per time is the time of one cycle of the output voltage V2 of the power receiving circuit 12. When the non-feeding period time is shortened, the ripple current of the input current of the rectifier circuit 13a becomes smaller, so that the ripple current in FIG. 6B becomes smaller than that in the case of the waveform of the drive signal in FIG. 6A. Finally, since the ripple current, which is an AC component, needs to be attenuated by the LC filter 14, if the ripple current is small, the LC filter 14 can be miniaturized.
　同様に、図６Ｃの駆動信号の波形では駆動信号の繰り返し周期内で非給電期間は２回あり、いずれの非給電期間も図６Ａにおける非給電期間の時間よりも短いため、図６Ａの駆動信号の波形の場合よりもリプル電流を小さくすることが可能である。
　図５Ａ、５Ｂ、５Ｃ、及び図６Ａ、６Ｂ、６Ｃに示された駆動信号の波形からもわかるように、半導体スイッチ１３５ａ、１３６ａの駆動信号の波形を変えることにより、電力制御を行うことが可能であり、また半導体スイッチ１３５ａ、１３６ａのオン、オフのスイッチング動作を受電回路１２の出力電圧Ｖ２のゼロクロスまたはゼロクロス近傍のタイミングで行うことで、スイッチング損失を抑制することが可能となる。 Similarly, in the waveform of the drive signal of FIG. 6C, there are two non-feeding periods within the repetition cycle of the drive signal, and each non-feeding period is shorter than the time of the non-feeding period in FIG. It is possible to make the ripple current smaller than in the case of the waveform of.
As can be seen from the waveforms of the drive signals shown in FIGS. 5A, 5B, 5C, and 6A, 6B, and 6C, power control can be performed by changing the waveforms of the drive signals of the semiconductor switches 135a and 136a. Further, by performing the on / off switching operation of the semiconductor switches 135a and 136a at the timing of zero crossing or near zero crossing of the output voltage V2 of the power receiving circuit 12, it is possible to suppress the switching loss.
　以上のように実施の形態１に係るワイヤレス給電システムの受電装置１０によれば、受電装置１０は送電回路１１からの電力を受電する受電回路１２、受電回路１２の出力電圧Ｖ２を検出する電圧検出手段１６、半導体スイッチ１３５ａ、１３６ａを有し受電回路１２で受電した交流電力を直流電力に変換する電力変換器１３（整流回路１３ａ）、電圧検出手段１６で検出された受電回路１２の出力電圧Ｖ２に基づいて半導体スイッチ１３５ａ、１３６ａを制御する制御装置を少なくとも備え、半導体スイッチ１３５ａ、１３６ａの動作により受電回路１２との導通状態及び遮断状態を切り替えるようにしたので、電圧源的動作となる共振器の構成において、受電回路と電力変換器との間で短絡でなく開放により遮断状態を形成でき、過電流による電力変換器を構成する素子の破壊等の虞がなくなる。 As described above, according to the power receiving device 10 of the wireless power feeding system according to the first embodiment, the power receiving device 10 detects the voltage detection of the power receiving circuit 12 for receiving the power from the power transmitting circuit 11 and the output voltage V2 of the power receiving circuit 12. A power converter 13 (rectifying circuit 13a) having means 16 and semiconductor switches 135a and 136a and converting AC power received by the power receiving circuit 12 into DC power, and an output voltage V2 of the power receiving circuit 12 detected by the voltage detecting means 16. At least a control device for controlling the semiconductor switches 135a and 136a is provided based on the above, and the conduction state and the cutoff state with the power receiving circuit 12 are switched by the operation of the semiconductor switches 135a and 136a. In this configuration, a cutoff state can be formed between the power receiving circuit and the power converter by opening instead of short-circuiting, and there is no risk of damage to the elements constituting the power converter due to overcurrent.
　また、予め設定された所定期間内において、電力変換器１３と受電回路１２との導通状態である給電期間及び電力変換器１３と受電回路１２との遮断状態である非給電期間の比率を調整することで、電力変換器１３の出力電圧を制御し、結果として出力電力を制御することができる。また、全ての半導体スイッチのオン、オフのスイッチング動作を受電回路１２の出力電圧Ｖ２のゼロクロスまたはゼロクロス近傍のタイミングで行うことで、スイッチング損失を抑制でき、高効率な電力制御が可能となる。 Further, within a predetermined period set in advance, the ratio of the power supply period in which the power converter 13 and the power receiving circuit 12 are in a conductive state and the ratio of the non-power supply period in which the power converter 13 and the power receiving circuit 12 are cut off is adjusted. As a result, the output voltage of the power converter 13 can be controlled, and as a result, the output power can be controlled. Further, by performing the on / off switching operation of all the semiconductor switches at the timing of zero crossing or near zero crossing of the output voltage V2 of the power receiving circuit 12, switching loss can be suppressed and highly efficient power control becomes possible.
実施の形態２．
　以下、実施の形態２に係るワイヤレス給電システムの受電装置について説明する。本実施の形態２に係る受電装置も実施の形態１の図１で示したワイヤレス給電システムに適用されるものである。
　図７は、本実施の形態２に係る受電装置の構成を示す概略回路図である。なお、図２と同一または相当部分については同一符号を付し、その説明を省略する。実施の形態２では整流回路１３ｂにおける二つの半導体スイッチ１３５ｂ、１３６ｂの配置が実施の形態１とは異なり、ダイオード１３３とダイオード１３４にそれぞれ直列に接続している。なお、図７において半導体スイッチ１３５ｂ、１３６ｂの配置は一例であり、ダイオード１３１とダイオード１３２に直列に接続してもよい。すなわち、整流回路１３ｂを構成する左右２つのレグのうちいずれかのレグ側のダイオードに直列に接続すればよい。 Embodiment 2.
Hereinafter, the power receiving device of the wireless power supply system according to the second embodiment will be described. The power receiving device according to the second embodiment is also applied to the wireless power feeding system shown in FIG. 1 of the first embodiment.
FIG. 7 is a schematic circuit diagram showing the configuration of the power receiving device according to the second embodiment. The same or corresponding parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. In the second embodiment, the arrangement of the two semiconductor switches 135b and 136b in the rectifier circuit 13b is different from that of the first embodiment, and the diode 133 and the diode 134 are connected in series, respectively. Note that the arrangement of the semiconductor switches 135b and 136b in FIG. 7 is an example, and the diode 131 and the diode 132 may be connected in series. That is, it may be connected in series to the diode on the leg side of either of the two left and right legs constituting the rectifier circuit 13b.
　実施の形態１との動作の差異は、非給電期間においてＤＣリアクトル１４１で蓄積されたエネルギーの環流経路が半導体スイッチ１３５ｂ、１３６ｂの状態に影響されない点である。図８は、図７の構成における非給電期間の電流経路の一つを図示したものである。ＤＣリアクトル１４１で蓄積されたエネルギーは負荷１５、ダイオード１３２、およびダイオード１３１を経由して環流することが可能であり、環流経路に半導体スイッチが含まれていない。しかし、実施の形態１における非給電期間は図３Ｂ、図４Ａで示されるが、ＤＣリアクトル１４１のエネルギーの環流経路に半導体スイッチを含む。ＤＣリアクトル１４１で蓄積されたエネルギーの環流時に、半導体スイッチが損傷あるいは誤動作した場合に環流経路が断たれることになり、ＤＣリアクトル１４１で蓄積されたエネルギーにより回路中に過電圧が生じ、装置全体が機能を失う虞がある。しかし、本実施の形態２の構成では、ＤＣリアクトル１４１で蓄積されたエネルギーの環流経路に半導体スイッチはなく、半導体スイッチ１３５ｂ、１３６ｂの状態に影響されることはない。 The difference in operation from the first embodiment is that the recirculation path of the energy stored in the DC reactor 141 during the non-feeding period is not affected by the state of the semiconductor switches 135b and 136b. FIG. 8 illustrates one of the current paths during the non-feeding period in the configuration of FIG. 7. The energy stored in the DC reactor 141 can be recirculated via the load 15, the diode 132, and the diode 131, and the recirculation path does not include a semiconductor switch. However, although the non-feeding period in the first embodiment is shown in FIGS. 3B and 4A, the energy recirculation path of the DC reactor 141 includes a semiconductor switch. When the energy stored in the DC reactor 141 is recirculated, the recirculation path is cut off if the semiconductor switch is damaged or malfunctions, and the energy stored in the DC reactor 141 causes an overvoltage in the circuit, causing the entire device to be affected. There is a risk of losing functionality. However, in the configuration of the second embodiment, there is no semiconductor switch in the recirculation path of the energy stored in the DC reactor 141, and the state of the semiconductor switches 135b and 136b is not affected.
　図９Ａ、９Ｂ、９Ｃは、実施の形態２に係る受電装置の電力制御の制御方法の例を説明するための図で、受電装置の各信号の波形の概略図である。それぞれ上から順に、受電回路１２の出力電圧Ｖ２、整流回路１３ｂの入力電流、半導体スイッチ１３５ｂ、１３６ｂの駆動信号の概略の波形を示している。図９Ａ、９Ｂ、９Ｃに示された３つの例は、いずれも受電装置からの出力電圧の平均値が最大の状態（二つのスイッチが常時オンの状態）の１／３となるように半導体スイッチ１３５ｂ、１３６ｂの駆動信号が設定されている。 9A, 9B, and 9C are diagrams for explaining an example of a control method of power control of the power receiving device according to the second embodiment, and are schematic views of waveforms of each signal of the power receiving device. From the top, the output voltage V2 of the power receiving circuit 12, the input current of the rectifier circuit 13b, and the approximate waveforms of the drive signals of the semiconductor switches 135b and 136b are shown. In each of the three examples shown in FIGS. 9A, 9B, and 9C, the semiconductor switch is such that the average value of the output voltage from the power receiving device is 1/3 of the maximum state (the state in which the two switches are always on). The drive signals of 135b and 136b are set.
　図９Ａの信号波形においては、受電回路１２の出力電圧Ｖ２の１周期を一単位として半導体スイッチを駆動する電力制御方法、図９Ｂの信号波形においては、受電回路１２の出力電圧Ｖ２の半周期を一単位として半導体スイッチを駆動する電力制御方法、また、図９Ｃの信号波形においては、受電回路１２の出力電圧Ｖ２の極性に応じて給電期間ＰＳと非給電期間ＮＰＳを設定する電力制御方法を示すものである。 In the signal waveform of FIG. 9A, a power control method for driving a semiconductor switch with one cycle of the output voltage V2 of the power receiving circuit 12 as one unit, and in the signal waveform of FIG. 9B, a half cycle of the output voltage V2 of the power receiving circuit 12 is used. A power control method for driving a semiconductor switch as one unit, and a power control method for setting a power supply period PS and a non-power supply period NPS according to the polarity of the output voltage V2 of the power receiving circuit 12 are shown in the signal waveform of FIG. 9C. It is a thing.
　図９Ａ、９Ｂ、９Ｃからわかるように、実施の形態２においては、二つの半導体スイッチ１３５ｂ、１３６ｂをオンにすれば給電期間ＰＳとなり、二つの半導体スイッチ１３５ｂ、１３６ｂをオフにすれば非給電期間ＮＰＳにできる。そのため、二つの半導体スイッチ１３５ｂ、１３６ｂを共通の駆動信号で動作させることが可能である。
　図９Ｂの信号波形においては、受電回路１２の出力電圧Ｖ２の半周期を給電期間ＰＳの一単位としており、駆動信号の繰り返し周期は受電回路１２の出力電圧Ｖ２の１．５周期の時間となり、図９Ａ及び図９Ｃの半分の時間となる。 As can be seen from FIGS. 9A, 9B, and 9C, in the second embodiment, turning on the two semiconductor switches 135b and 136b results in a power supply period PS, and turning off the two semiconductor switches 135b and 136b results in a non-power supply period. Can be NPS. Therefore, it is possible to operate the two semiconductor switches 135b and 136b with a common drive signal.
In the signal waveform of FIG. 9B, a half cycle of the output voltage V2 of the power receiving circuit 12 is set as one unit of the power feeding period PS, and the repeating cycle of the drive signal is 1.5 cycles of the output voltage V2 of the power receiving circuit 12. It takes half the time of FIGS. 9A and 9C.
　なお、給電期間ＰＳにおいては二つの半導体スイッチの一方のみが電流経路となるため、他方の半導体スイッチの状態はオンとオフのどちらでもよい。例えば、図７において、半導体スイッチ１３５ｂ、１３６ｂの両方がオンの状態であっても、受電回路１２の出力電圧Ｖ２が正の場合は、半導体スイッチ１３６ｂ側が電流経路となり、一方受電回路１２の出力電圧Ｖ２が負の場合は、半導体スイッチ１３５ｂ側が電流経路となる。そのため、図９Ａ、９Ｂ、９Ｃの半導体スイッチ１３５ｂ、１３６ｂの駆動信号において、それぞれオンで示されている（信号が１）時間であって、斜線で示された時間はオンであってもオフであってもよい期間である。
　また、図９Ｃでは半導体スイッチ１３５ｂの駆動信号をオンとオフに切り替えているが、常時オフの状態でも回路動作は同一となる。 Since only one of the two semiconductor switches serves as the current path during the power supply period PS, the state of the other semiconductor switch may be either on or off. For example, in FIG. 7, even if both the semiconductor switches 135b and 136b are on, if the output voltage V2 of the power receiving circuit 12 is positive, the semiconductor switch 136b side becomes the current path, while the output voltage of the power receiving circuit 12 When V2 is negative, the semiconductor switch 135b side becomes the current path. Therefore, in the drive signals of the semiconductor switches 135b and 136b of FIGS. 9A, 9B, and 9C, the time indicated as on (the signal is 1) is the time, and the time indicated by the diagonal line is off even if it is on. It is a good period.
Further, in FIG. 9C, the drive signal of the semiconductor switch 135b is switched on and off, but the circuit operation is the same even in the constantly off state.
　以上のように、実施の形態２の受電装置は実施の形態１と同様の効果を奏する。さらに、実施の形態２によれば、電力変換器１３である整流回路１３ｂを構成する左右２つのレグのうちいずれかのレグ側のダイオードに半導体スイッチ１３５ｂ、１３６ｂをそれぞれ直列に接続したので、二つの半導体スイッチ１３５ｂ、１３６ｂを同時にオフの状態にして非給電期間を設けることが可能となる。これにより、非給電期間にＤＣリアクトル１４１で蓄積されたエネルギーの環流経路中に半導体スイッチの状態に起因する過大電圧の発生を抑制できる。また、二つの半導体スイッチ１３５ｂ、１３６ｂを１つの駆動信号で制御することが可能なため、実施の形態１と比較して制御装置を簡素化できる効果がある。 As described above, the power receiving device of the second embodiment has the same effect as that of the first embodiment. Further, according to the second embodiment, the semiconductor switches 135b and 136b are connected in series to the diode on the leg side of either of the two left and right legs constituting the rectifier circuit 13b which is the power converter 13. It is possible to provide a non-power supply period by turning off the semiconductor switches 135b and 136b at the same time. As a result, it is possible to suppress the generation of an excessive voltage due to the state of the semiconductor switch in the recirculation path of the energy stored in the DC reactor 141 during the non-feeding period. Further, since the two semiconductor switches 135b and 136b can be controlled by one drive signal, there is an effect that the control device can be simplified as compared with the first embodiment.
実施の形態３．
　以下、実施の形態３に係るワイヤレス給電システムの受電装置について説明する。本実施の形態３に係る受電装置も実施の形態１の図１で示したワイヤレス給電システムに適用されるものである。
　図１０は、本実施の形態３に係る受電装置の構成を示す概略回路図である。なお、図７と同一または相当部分については同一符号を付し、その説明を省略する。実施の形態３に係る受電装置では、ＤＣリアクトル１４１に流れる電流ＩＬｄｃを検出する電流検出手段１８と負荷１５の電圧Ｖｏｕｔを検出する電圧検出手段１９をさらに備える。電流検出手段１８と電圧検出手段１９によって検出された電流及び電圧情報は制御装置１７に入力される。実施の形態１及び２において、制御装置１７は、受電装置からの出力が予め設定された所定の出力電力となるように、出力電力指令値Ｐｏｕｔ＊を設定し、半導体スイッチの駆動信号を生成することで半導体スイッチを制御し、電力制御を行う例であった。本実施の形態３では、制御装置１７は、出力電力指令値Ｐｏｕｔ＊を電圧検出手段１９により検出された負荷電圧Ｖｏｕｔで除して、ＤＣリアクトル１４１の電流指令値ＩＬｄｃ＊を算出し、電流検出手段１８により検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊となるように半導体スイッチの制御を行う電流制御を用いて出力電力を制御する。 Embodiment 3.
Hereinafter, the power receiving device of the wireless power supply system according to the third embodiment will be described. The power receiving device according to the third embodiment is also applied to the wireless power feeding system shown in FIG. 1 of the first embodiment.
FIG. 10 is a schematic circuit diagram showing the configuration of the power receiving device according to the third embodiment. The same or corresponding parts as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted. The power receiving device according to the third embodiment further includes a current detecting means 18 for detecting the current ILdc flowing through the DC reactor 141 and a voltage detecting means 19 for detecting the voltage Vout of the load 15. The current and voltage information detected by the current detecting means 18 and the voltage detecting means 19 is input to the control device 17. In the first and second embodiments, the control device 17 sets the output power command value Pout * so that the output from the power receiving device becomes a preset predetermined output power, and generates a drive signal for the semiconductor switch. This was an example of controlling a semiconductor switch and controlling power. In the third embodiment, the control device 17 divides the output power command value Pout * by the load voltage Vout detected by the voltage detecting means 19 to calculate the current command value ILdc * of the DC reactor 141 and detect the current. The output power is controlled by using current control that controls the semiconductor switch so that the current ILdc of the DC reactor 141 detected by the means 18 becomes the current command value ILdc *.
　以下に、半導体スイッチ１３５ｂ、１３６ｂによりＤＣリアクトル１４１の電流を制御することで、出力電力制御を行う方法について説明する。
　図１１Ａ、１１Ｂ、１１Ｃ、１１Ｄは、実施の形態３に係る受電装置における各信号の波形の概略図で、リアクトル電流制御に用いる駆動信号パターンを説明するための図である。本実施の形態では、整流回路１３ｂの出力電圧平均値の最大電圧に対し、以下の４つの電圧となるように半導体スイッチ１３５ｂ、１３６ｂを制御する駆動信号パターンに、非給電状態とする駆動信号パターンを加え５つの駆動信号パターンを設定している。
　　駆動信号パターンＩ：出力電圧平均値が最大電圧となるパターン、
　　駆動信号パターンＩＩ：出力電圧平均値が最大電圧の３／４となるパターン、
　　駆動信号パターンＩＩＩ：出力電圧平均値が最大電圧の１／２となるパターン、
　　駆動信号パターンＩＶ：出力電圧平均値が最大電圧の１／４となるパターン、
　　駆動信号パターンＶ：非給電状態とするパターン。
　制御装置１７は、これら駆動信号パターンを保持し、実行する。 Hereinafter, a method of controlling the output power by controlling the current of the DC reactor 141 by the semiconductor switches 135b and 136b will be described.
11A, 11B, 11C, and 11D are schematic views of waveforms of each signal in the power receiving device according to the third embodiment, and are diagrams for explaining a drive signal pattern used for reactor current control. In the present embodiment, the drive signal pattern for controlling the semiconductor switches 135b and 136b so as to have the following four voltages with respect to the maximum voltage of the average output voltage of the rectifier circuit 13b is set to the non-power supply state. Is added to set five drive signal patterns.
Drive signal pattern I: A pattern in which the average output voltage is the maximum voltage,
Drive signal pattern II: A pattern in which the average output voltage is 3/4 of the maximum voltage.
Drive signal pattern III: A pattern in which the average output voltage is 1/2 of the maximum voltage,
Drive signal pattern IV: A pattern in which the average output voltage is 1/4 of the maximum voltage.
Drive signal pattern V: A pattern in which no power is supplied.
The control device 17 holds and executes these drive signal patterns.
　図１１Ａは、駆動信号パターンＩを示す図で、給電状態が継続していることを示している。図１１Ｂは、駆動信号パターンＩＩを示す図で、受電回路１２の出力電圧Ｖ２の２周期分に着目すると、１．５周期の期間が給電期間ＰＳ、半周期の期間が非給電期間ＮＰＳであり、整流回路１３ｂの出力電圧平均値が最大電圧の３／４となるパターンである。図１１Ｃは、駆動信号パターンＩＩＩを示す図で、受電回路１２の出力電圧Ｖ２の２周期分に着目すると、半周期分の給電期間ＰＳ、と半周期分の非給電期間ＮＰＳが繰り返されており、整流回路１３ｂの出力電圧平均値が最大電圧の１／２となるパターンである。図１１Ｄは、駆動信号パターンＩＶを示す図で、受電回路１２の出力電圧Ｖ２の２周期分に着目すると、半周期の期間が給電期間ＰＳ、１．５周期の期間が非給電期間ＮＰＳであり、整流回路１３ｂの出力電圧平均値が最大電圧の１／４となるパターンである。駆動信号パターンＶは図示していないが、半導体スイッチ１３５ｂ、１３６ｂの両方がオフ（駆動信号が０）の、非給電状態である。 FIG. 11A is a diagram showing the drive signal pattern I, indicating that the power supply state is continuing. FIG. 11B is a diagram showing the drive signal pattern II. Focusing on two cycles of the output voltage V2 of the power receiving circuit 12, the 1.5 cycle period is the power supply period PS, and the half cycle period is the non-power supply period NPS. This is a pattern in which the average output voltage of the rectifier circuit 13b is 3/4 of the maximum voltage. FIG. 11C is a diagram showing the drive signal pattern III. Focusing on the two cycles of the output voltage V2 of the power receiving circuit 12, the power supply period PS for half a cycle and the non-power supply period NPS for half a cycle are repeated. This is a pattern in which the average value of the output voltage of the rectifier circuit 13b is 1/2 of the maximum voltage. FIG. 11D is a diagram showing the drive signal pattern IV. Focusing on two cycles of the output voltage V2 of the power receiving circuit 12, the half cycle period is the power supply period PS, and the 1.5 cycle period is the non-power supply period NPS. This is a pattern in which the average output voltage of the rectifier circuit 13b is 1/4 of the maximum voltage. Although the drive signal pattern V is not shown, both the semiconductor switches 135b and 136b are off (the drive signal is 0), and the power supply is not supplied.
　次に、５つの駆動信号パターンを用いてＤＣリアクトル１４１の電流を制御することで、出力電力制御を行う方法について、図１２Ａから図１２Ｅのフローチャートに従って説明する。
　図１２Ａにおいて、まずステップＳ１０１の初期状態は非給電状態であり、駆動信号パターンＶが実行されていることに相当する。給電開始すると、制御装置１７では、設定された出力電力指令値Ｐｏｕｔ＊を電圧検出手段１９により検出された負荷電圧Ｖｏｕｔで除して、ＤＣリアクトル１４１の電流指令値ＩＬｄｃ＊が算出される。また、電流検出手段１８により検出されたＤＣリアクトル１４１の電流ＩＬｄｃが制御装置１７に入力される。 Next, a method of controlling the output power by controlling the current of the DC reactor 141 using the five drive signal patterns will be described with reference to the flowcharts of FIGS. 12A to 12E.
In FIG. 12A, first, the initial state of step S101 is the non-power supply state, which corresponds to the execution of the drive signal pattern V. When the power supply is started, the control device 17 divides the set output power command value Pout * by the load voltage Vout detected by the voltage detecting means 19 to calculate the current command value ILdc * of the DC reactor 141. Further, the current ILdc of the DC reactor 141 detected by the current detecting means 18 is input to the control device 17.
　給電開始のステップＳ１０２で、駆動信号パターンＩＶが実行されると、ＤＣリアクトル１４１の電流ＩＬｄｃは増加する。ステップＳ１０３で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となったか判定し、電流指令値ＩＬｄｃ＊以上となった場合（ＹＥＳ）は図１２Ｂのフローチャートに示されるステップＳ２０１に進む。ステップＳ１０３で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に達しない場合（ＮＯ）は、ステップＳ１０４において、駆動信号パターンＩＩＩが実行される。 When the drive signal pattern IV is executed in step S102 of the start of power supply, the current ILdc of the DC reactor 141 increases. In step S103, it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S201 shown in the flowchart of FIG. 12B. move on. If the current ILdc of the detected DC reactor 141 does not reach the current command value ILdc * in step S103 (NO), the drive signal pattern III is executed in step S104.
　ステップＳ１０４で、駆動信号パターンＩＩＩが実行されると、ＤＣリアクトル１４１の電流ＩＬｄｃはさらに増加する。ステップＳ１０５で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となったか判定し、電流指令値ＩＬｄｃ＊以上となった場合（ＹＥＳ）は図１２Ｃのフローチャートに示されるステップＳ３０１に進む。ステップＳ１０５で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に達しない場合（ＮＯ）は、ステップＳ１０６において、駆動信号パターンＩＩが実行される。 When the drive signal pattern III is executed in step S104, the current ILdc of the DC reactor 141 is further increased. In step S105, it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S301 shown in the flowchart of FIG. 12C. move on. If the current ILdc of the detected DC reactor 141 does not reach the current command value ILdc * in step S105 (NO), the drive signal pattern II is executed in step S106.
　ステップＳ１０６で、駆動信号パターンＩＩが実行されると、ＤＣリアクトル１４１の電流ＩＬｄｃはさらに増加する。ステップＳ１０７で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となったか判定し、電流指令値ＩＬｄｃ＊以上となった場合（ＹＥＳ）は図１２Ｄのフローチャートに示されるステップＳ４０１に進む。ステップＳ１０７で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に達しない場合（ＮＯ）は、ステップＳ１０８において、駆動信号パターンＩが実行される。 When the drive signal pattern II is executed in step S106, the current ILdc of the DC reactor 141 is further increased. In step S107, it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S401 shown in the flowchart of FIG. 12D. move on. If the current ILdc of the detected DC reactor 141 does not reach the current command value ILdc * in step S107 (NO), the drive signal pattern I is executed in step S108.
　ステップＳ１０８で、駆動信号パターンＩが実行されると、ＤＣリアクトル１４１の電流ＩＬｄｃはさらに増加する。ステップＳ１０９で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となったか判定し、電流指令値ＩＬｄｃ＊以上となった場合（ＹＥＳ）は図１２Ｅのフローチャートに示されるステップＳ５０１に進む。ステップＳ１０９で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に達しない場合（ＮＯ）は、電流指令値ＩＬｄｃ＊の設定に問題があるなど懸念されるため、ステップＳ１１０において、制御不可として給電を停止する。 When the drive signal pattern I is executed in step S108, the current ILdc of the DC reactor 141 is further increased. In step S109, it is determined whether the detected current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *, and if it is equal to or greater than the current command value ILdc * (YES), the process proceeds to step S501 shown in the flowchart of FIG. 12E. move on. If the current ILdc of the DC reactor 141 detected in step S109 does not reach the current command value ILdc * (NO), there is a concern that there is a problem in setting the current command value ILdc *, so control is performed in step S110. Stop power supply as impossible.
　なお、ステップＳ１０３、Ｓ１０５、Ｓ１０７、Ｓ１０９において、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に達しないか、あるいは電流指令値ＩＬｄｃ＊以上となったかの判定は次のように行う。例えば、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが一定期間変動せず、電流指令値ＩＬｄｃ＊に達しない場合は、電流指令値ＩＬｄｃ＊に達しないと判定する。あるいは、駆動信号の繰り返し周期の３倍の時間経過しても電流指令値ＩＬｄｃ＊に達しない場合は、電流指令値ＩＬｄｃ＊に達しないと判定する。ここで経過時間の設定は任意に行うことができる。このように、検出されたＤＣリアクトル１４１の電流ＩＬｄｃの飽和状況あるいは推移で判定を行う。 In steps S103, S105, S107, and S109, it is determined as follows whether the detected current ILdc of the DC reactor 141 does not reach the current command value ILdc * or exceeds the current command value ILdc *. For example, if the detected current ILdc of the DC reactor 141 does not fluctuate for a certain period of time and does not reach the current command value ILdc *, it is determined that the current command value ILdc * is not reached. Alternatively, if the current command value ILdc * is not reached even after three times the repetition period of the drive signal has elapsed, it is determined that the current command value ILdc * is not reached. Here, the elapsed time can be set arbitrarily. In this way, the determination is made based on the saturation status or transition of the current ILdc of the detected DC reactor 141.
　ステップＳ１０３で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となった場合、図１２ＢのステップＳ２０１に進み、駆動信号パターンＶが実行される。すなわち、非給電状態とする。すると、ＤＣリアクトル１４１の電流ＩＬｄｃは減少するので、ステップＳ２０２に進み、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上であるか判定する。ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上が継続していれば（ＹＥＳ）、ステップＳ２０１の非給電状態が継続される。ステップＳ２０２で、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊を下回った場合、ステップＳ２０３で駆動信号パターンＩＶが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃは増加する。
　以降、給電停止の指令があるまで、駆動信号パターンＶと駆動信号パターンＩＶが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に近づくように制御される。 When the current ILdc of the detected DC reactor 141 becomes equal to or higher than the current command value ILdc * in step S103, the process proceeds to step S201 of FIG. 12B, and the drive signal pattern V is executed. That is, it is in a non-powered state. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S202, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the non-power supply state in step S201 is continued. When the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S202, the drive signal pattern IV is executed in step S203, and the current ILdc of the DC reactor 141 increases.
After that, the drive signal pattern V and the drive signal pattern IV are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
　同様に、ステップＳ１０５で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となった場合、図１２ＣのステップＳ３０１に進み、駆動信号パターンＩＶが実行される。すると、ＤＣリアクトル１４１の電流ＩＬｄｃは減少するので、ステップＳ３０２に進み、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上であるか判定する。ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上が継続していれば（ＹＥＳ）、ステップＳ３０１の駆動信号パターンＩＶの実行が継続される。ステップＳ３０２で、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊を下回った場合、ステップＳ３０３で駆動信号パターンＩＩＩが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃは増加する。
　以降、給電停止の指令があるまで、駆動信号パターンＩＶと駆動信号パターンＩＩＩが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に近づくように制御される。 Similarly, when the current ILdc of the detected DC reactor 141 becomes equal to or higher than the current command value ILdc * in step S105, the process proceeds to step S301 of FIG. 12C, and the drive signal pattern IV is executed. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S302, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the execution of the drive signal pattern IV in step S301 is continued. If the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S302, the drive signal pattern III is executed in step S303, and the current ILdc of the DC reactor 141 increases.
After that, the drive signal pattern IV and the drive signal pattern III are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
　同様に、ステップＳ１０７で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となった場合、図１２ＤのステップＳ４０１に進み、駆動信号パターンＩＩＩが実行される。すると、ＤＣリアクトル１４１の電流ＩＬｄｃは減少するので、ステップＳ４０２に進み、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上であるか判定する。ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上が継続していれば（ＹＥＳ）、ステップＳ４０１の駆動信号パターンＩＩＩの実行が継続される。ステップＳ４０２で、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊を下回った場合、ステップＳ４０３で駆動信号パターンＩＩが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃは増加する。
　以降、給電停止の指令があるまで、駆動信号パターンＩＩＩと駆動信号パターンＩＩが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に近づくように制御される。 Similarly, when the current ILdc of the detected DC reactor 141 becomes equal to or higher than the current command value ILdc * in step S107, the process proceeds to step S401 of FIG. 12D, and the drive signal pattern III is executed. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S402, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the execution of the drive signal pattern III in step S401 is continued. If the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S402, the drive signal pattern II is executed in step S403, and the current ILdc of the DC reactor 141 increases.
After that, the drive signal pattern III and the drive signal pattern II are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
　同様に、ステップＳ１０９で、検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上となった場合、図１２ＥのステップＳ５０１に進み、駆動信号パターンＩＩが実行される。すると、ＤＣリアクトル１４１の電流ＩＬｄｃは減少するので、ステップＳ５０２に進み、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上であるか判定する。ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上が継続していれば（ＹＥＳ）、ステップＳ５０１の駆動信号パターンＩＩの実行が継続される。ステップＳ５０２で、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊を下回った場合、ステップＳ５０３で駆動信号パターンＩが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃは増加する。
　以降、給電停止の指令があるまで、駆動信号パターンＩＩと駆動信号パターンＩが実行され、ＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊に近づくように制御される。 Similarly, when the current ILdc of the detected DC reactor 141 becomes equal to or higher than the current command value ILdc * in step S109, the process proceeds to step S501 of FIG. 12E, and the drive signal pattern II is executed. Then, since the current ILdc of the DC reactor 141 decreases, the process proceeds to step S502, and it is determined whether the current ILdc of the DC reactor 141 is equal to or greater than the current command value ILdc *. If the current ILdc of the DC reactor 141 continues to be equal to or higher than the current command value ILdc * (YES), the execution of the drive signal pattern II in step S501 is continued. If the current ILdc of the DC reactor 141 falls below the current command value ILdc * in step S502, the drive signal pattern I is executed in step S503, and the current ILdc of the DC reactor 141 increases.
After that, the drive signal pattern II and the drive signal pattern I are executed until there is a command to stop the power supply, and the current ILdc of the DC reactor 141 is controlled to approach the current command value ILdc *.
　以上のように、整流回路１３ｂの出力電圧平均値を段階的に上げていき、電流指令値ＩＬｄｃ＊に制御可能な二つの駆動信号パターンを選択することで、負荷電圧Ｖｏｕｔに近い電圧で電流制御を行うことができる。
　なお、上述したが、ステップＳ１０９において、駆動信号パターンＩを実行してもＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊以上にならない場合、ステップＳ１１０において、制御不可として給電を停止したが、電流指令値ＩＬｄｃ＊の設定に問題等がある他、原理的に電流制御ができない状態である可能性もある。そのため、試験条件あるいは回路定数の変更が必要となる。 As described above, by gradually increasing the average output voltage of the rectifier circuit 13b and selecting two drive signal patterns that can be controlled to the current command value ILdc *, the current is controlled at a voltage close to the load voltage Vout. It can be performed.
As described above, if the current ILdc of the DC reactor 141 does not exceed the current command value ILdc * even when the drive signal pattern I is executed in step S109, the power supply is stopped as uncontrollable in step S110, but the current In addition to problems with the setting of the command value ILdc *, there is a possibility that current control cannot be performed in principle. Therefore, it is necessary to change the test conditions or circuit constants.
　また、本電流制御を適用することでＤＣリアクトル１４１への印加電圧及び印加電圧の変動量を最小限にすることができ、整流回路１３ｂの出力電流リプルを低減することが可能となる。また、電流リプルを一定値とする場合、最大電圧となる駆動信号パターンＩと非給電の状態の駆動信号パターンＶのみで受電装置を動作させるよりも、本実施の形態３に係る電流制御法を適用したほうがＤＣリアクトル１４１に必要とされるインダクタンス値を小さく設計できるため小形化することが可能となる。 Further, by applying this current control, it is possible to minimize the fluctuation amount of the applied voltage and the applied voltage to the DC reactor 141, and it is possible to reduce the output current ripple of the rectifier circuit 13b. Further, when the current ripple is set to a constant value, the current control method according to the third embodiment is performed rather than operating the power receiving device only with the drive signal pattern I which is the maximum voltage and the drive signal pattern V in the non-powered state. If it is applied, the inductance value required for the DC reactor 141 can be designed to be smaller, so that the size can be reduced.
　以上に示した駆動信号パターン及び制御方法は実施の形態３の一例であり、例えば、駆動信号パターンの数を５つより多くまたは少なくして実施したり、駆動方法の種類を異なるものに変更したりすることも可能である。制御装置１７は少なくとも３つの駆動信号パターンを有し、電流検出手段１８で検出された電流ＩＬｄｃに基づき、複数の駆動信号パターンから給電期間と非給電期間との比率が近い２つの駆動信号パターンを用いて、段階的に予め設定された出力電力指令値Ｐｏｕｔ＊となるように、半導体スイッチを制御すればよい。 The drive signal pattern and control method shown above are examples of the third embodiment. For example, the number of drive signal patterns may be increased or decreased to five or less, or the type of drive method may be changed to a different one. It is also possible to do it. The control device 17 has at least three drive signal patterns, and based on the current ILdc detected by the current detecting means 18, two drive signal patterns in which the ratio of the power supply period to the non-power supply period is close are obtained from a plurality of drive signal patterns. It may be used to control the semiconductor switch so that the output power command value Pout * is set in a stepwise manner.
　以上のように実施の形態３に係る受電装置によれば、実施の形態２と同様の効果を奏する。さらに、ＤＣリアクトル１４１に流れる電流ＩＬｄｃを検出する電流検出手段１８と負荷１５の電圧Ｖｏｕｔを検出する電圧検出手段１９を備え、電流検出手段１８により検出されたＤＣリアクトル１４１の電流ＩＬｄｃが電流指令値ＩＬｄｃ＊となるように半導体スイッチの制御を行う電流制御を用いて出力電力を制御するようにしたので、整流回路１３ｂの出力電圧平均値を段階的に上げていき、負荷電圧Ｖｏｕｔに近い電圧で電流制御を行うことでＤＣリアクトル１４１への印加電圧及び印加電圧の変動量を抑制でき、整流回路１３ｂの出力電流リプルを低減することが可能となる。 As described above, the power receiving device according to the third embodiment has the same effect as that of the second embodiment. Further, a current detecting means 18 for detecting the current ILdc flowing through the DC reactor 141 and a voltage detecting means 19 for detecting the voltage Vout of the load 15 are provided, and the current ILdc of the DC reactor 141 detected by the current detecting means 18 is the current command value. Since the output power is controlled by using the current control that controls the semiconductor switch so that it becomes ILdc *, the average output voltage of the rectifying circuit 13b is gradually increased to a voltage close to the load voltage Vout. By controlling the current, it is possible to suppress the fluctuation amount of the applied voltage and the applied voltage to the DC reactor 141, and it is possible to reduce the output current ripple of the rectifying circuit 13b.
　なお、上記実施の形態３では、実施の形態２の図７にＤＣリアクトル１４１に流れる電流ＩＬｄｃを検出する電流検出手段１８と負荷１５の電圧Ｖｏｕｔを検出する電圧検出手段１９を備えた例を示したが、実施の形態１の図２において、ＤＣリアクトル１４１に流れる電流ＩＬｄｃを検出する電流検出手段１８と負荷１５の電圧Ｖｏｕｔを検出する電圧検出手段１９を備えてもよい。実施の形態１においても、整流回路１３ａの出力電圧平均値を段階的に上げていく、駆動信号パターンを作成することは可能であり、整流回路１３ａの出力電圧平均値を段階的に上げていき、負荷電圧Ｖｏｕｔに近い電圧で電流制御を行うことでＤＣリアクトル１４１への印加電圧及び印加電圧の変動量を抑制でき、整流回路１３ａの出力電流リプルを低減することが可能となる。 In the third embodiment, FIG. 7 of the second embodiment shows an example in which the current detecting means 18 for detecting the current ILdc flowing in the DC reactor 141 and the voltage detecting means 19 for detecting the voltage Vout of the load 15 are provided. However, in FIG. 2 of the first embodiment, the current detecting means 18 for detecting the current ILdc flowing through the DC reactor 141 and the voltage detecting means 19 for detecting the voltage Vout of the load 15 may be provided. Also in the first embodiment, it is possible to create a drive signal pattern in which the average output voltage of the rectifier circuit 13a is gradually increased, and the average output voltage of the rectifier circuit 13a is gradually increased. By controlling the current at a voltage close to the load voltage Vout, it is possible to suppress the fluctuation amount of the applied voltage and the applied voltage to the DC reactor 141, and it is possible to reduce the output current ripple of the rectifier circuit 13a.
実施の形態４．
　以下、実施の形態４に係るワイヤレス給電システムの受電装置について説明する。本実施の形態４に係る受電装置も実施の形態１の図１で示したワイヤレス給電システムに適用されるものである。
　図１３は、本実施の形態４に係る受電装置の構成を示す概略回路図である。なお、図１、７、１０と同一または相当部分については同一符号を付し、その説明を省略する。実施の形態４に係る受電装置では、受電回路１２と整流回路１３ｃとの間に双方向スイッチ２０が接続されている。また、電力変換器である整流回路１３ｃが４つのダイオードのみで構成される。 Embodiment 4.
Hereinafter, the power receiving device of the wireless power supply system according to the fourth embodiment will be described. The power receiving device according to the fourth embodiment is also applied to the wireless power feeding system shown in FIG. 1 of the first embodiment.
FIG. 13 is a schematic circuit diagram showing the configuration of the power receiving device according to the fourth embodiment. The same or corresponding parts as those in FIGS. 1, 7 and 10 are designated by the same reference numerals, and the description thereof will be omitted. In the power receiving device according to the fourth embodiment, the bidirectional switch 20 is connected between the power receiving circuit 12 and the rectifier circuit 13c. Further, the rectifier circuit 13c, which is a power converter, is composed of only four diodes.
　本実施の形態４に係る受電装置は、双方向スイッチ２０で出力電力制御を行うものであって、双方向スイッチ２０がオンのときは給電期間、双方向スイッチ２０がオフの時は非給電期間となる。電圧源的動作となるワイヤレス給電システムの共振器の構成において、双方向スイッチ２０がオフの時は、受電回路と電力変換器との間が短絡でなく開放となり遮断されるので、過電流による電力変換器を構成する素子、すなわちダイオード等の破壊等の虞がなくなる。双方向スイッチ２０のオンとオフとの切り替えのタイミングは、整流回路１３ｃの入力電圧Ｖ２のゼロクロスあるいはゼロクロス近傍の時間で行う。これにより、上述した実施の形態１から３と同様、双方向スイッチ２０のスイッチング損失を抑制することが可能となる。 The power receiving device according to the fourth embodiment controls the output power with the bidirectional switch 20. When the bidirectional switch 20 is on, the power supply period is high, and when the bidirectional switch 20 is off, the power supply period is non-power supply. It becomes. In the configuration of the resonator of the wireless power supply system that operates as a voltage source, when the bidirectional switch 20 is off, the power receiving circuit and the power converter are not short-circuited but open and cut off, so that the power due to overcurrent is cut off. There is no risk of damage to the elements that make up the converter, that is, the diode and the like. The timing of switching the bidirectional switch 20 on and off is performed at zero cross or near zero cross of the input voltage V2 of the rectifier circuit 13c. As a result, it is possible to suppress the switching loss of the bidirectional switch 20 as in the above-described first to third embodiments.
　また、出力電力は、双方向スイッチがオンの時間で制御可能であり、かつ整流回路１３ｃの入力電圧Ｖ２の極性によらず制御可能である。そのため、制御装置のプログラムを簡素化可能で制御装置の演算負荷を低減できる効果を奏する。さらに、整流回路１３ｃがフルブリッジダイオード整流回路となることからモジュール化された部品が適用可能となり、回路実装を簡素化できる効果も得られる。 Further, the output power can be controlled by the time when the bidirectional switch is on, and can be controlled regardless of the polarity of the input voltage V2 of the rectifier circuit 13c. Therefore, the program of the control device can be simplified and the calculation load of the control device can be reduced. Further, since the rectifier circuit 13c becomes a full bridge diode rectifier circuit, modularized parts can be applied, and an effect of simplifying circuit mounting can be obtained.
　図１４Ａ、１４Ｂ、１４Ｃは、実施の形態４に係る受電装置の電力制御による制御方法を説明するための図である。図１４Ａ、１４Ｂ、１４Ｃは、それぞれ上から順に、整流回路１３ｃの入力電圧Ｖ２、整流回路１３ｃの入力電流、双方向スイッチ２０の駆動信号の概略の波形を示している。そして、図１４Ａと図１４Ｃは、駆動信号の繰り返し周期を受電回路１２の出力電圧Ｖ２の３周期と同じ時間とすると、受電回路１２の出力電圧Ｖ２の３周期の中で１周期だけ給電期間を設けており、出力電圧の平均値が最大の状態（双方向スイッチが常時オンの状態）の１／３となるように双方向スイッチ２０の駆動信号が設定されている。図１４Ａと図１４Ｃは、それぞれ実施の形態１の図６Ａと図６Ｃの出力電力制御に相当する。このように、双方向スイッチ２０を用いた実施の形態４においても実施の形態１と同様の出力電力制御が可能である。 14A, 14B, and 14C are diagrams for explaining a control method by power control of the power receiving device according to the fourth embodiment. 14A, 14B, and 14C show approximate waveforms of the input voltage V2 of the rectifier circuit 13c, the input current of the rectifier circuit 13c, and the drive signal of the bidirectional switch 20 in this order from the top. Then, in FIGS. 14A and 14C, assuming that the repetition cycle of the drive signal is the same time as the three cycles of the output voltage V2 of the power receiving circuit 12, the power supply period is set to one cycle among the three cycles of the output voltage V2 of the power receiving circuit 12. The drive signal of the bidirectional switch 20 is set so that the average value of the output voltage is 1/3 of the maximum state (the bidirectional switch is always on). 14A and 14C correspond to the output power controls of FIGS. 6A and 6C of the first embodiment, respectively. As described above, in the fourth embodiment using the bidirectional switch 20, the same output power control as in the first embodiment can be performed.
　また、図１４Ｂは、受電回路１２の出力電圧Ｖ２の半周期を給電期間ＰＳの一単位としており、駆動信号の繰り返し周期は受電回路１２の出力電圧Ｖ２の１．５周期の時間とした例で、出力電圧の平均値が最大の状態（双方向スイッチが常時オンの状態）の１／３となるように双方向スイッチ２０の駆動信号が設定されている。図１４Ｂは、実施の形態２の図９Ｂの出力電力制御に相当する。このように、双方向スイッチ２０を用いた実施の形態４においても実施の形態１と同様の出力電力制御が可能である。 Further, FIG. 14B shows an example in which a half cycle of the output voltage V2 of the power receiving circuit 12 is set as one unit of the power feeding period PS, and the repeating cycle of the drive signal is 1.5 cycles of the output voltage V2 of the power receiving circuit 12. The drive signal of the bidirectional switch 20 is set so that the average value of the output voltage is 1/3 of the maximum state (the bidirectional switch is always on). FIG. 14B corresponds to the output power control of FIG. 9B of the second embodiment. As described above, in the fourth embodiment using the bidirectional switch 20, the same output power control as in the first embodiment can be performed.
　なお、図１３において、電流または電圧を検出する手段として、受電回路１２の出力電圧Ｖ２を検出する電圧検出手段１６のみ備えた構成を示しているが、負荷１５の電圧検出手段及びＬＣフィルタ１４に含まれるＤＣリアクトル１４１の電流検出手段を追加することで、実施の形態３で示したようなリアクトル電流制御による電力制御を実施することも可能である。 Although FIG. 13 shows a configuration in which only the voltage detecting means 16 for detecting the output voltage V2 of the power receiving circuit 12 is provided as the means for detecting the current or the voltage, the voltage detecting means of the load 15 and the LC filter 14 are provided. By adding the current detecting means of the included DC reactor 141, it is also possible to carry out power control by the reactor current control as shown in the third embodiment.
　以上のように、本実施の形態４の受電装置よれば、受電回路１２と電力変換器である整流回路１３ｃとの間に双方向スイッチ２０を設けて、給電期間、非給電期間を切り替えるようにしたので、実施の形態１から３の効果を奏するだけでなく、装置構成を簡素化可能で小型化及び低コスト化の効果も得られる。 As described above, according to the power receiving device of the fourth embodiment, the bidirectional switch 20 is provided between the power receiving circuit 12 and the rectifier circuit 13c which is a power converter, and the power supply period and the non-power supply period are switched. Therefore, not only the effects of the first to third embodiments can be obtained, but also the device configuration can be simplified, and the effects of miniaturization and cost reduction can be obtained.
　なお、制御装置１７は、ハードウエアの一例を図１５に示すように、プロセッサ１７０と記憶装置１７１から構成される。記憶装置は図示していないが、ランダムアクセスメモリ等の揮発性記憶装置と、フラッシュメモリ等の不揮発性の補助記憶装置とを具備する。また、フラッシュメモリの代わりにハードディスクの補助記憶装置を具備してもよい。プロセッサ１７０は、記憶装置１７１から入力されたプログラムを実行する。この場合、補助記憶装置から揮発性記憶装置を介してプロセッサ１７０にプログラムが入力される。また、プロセッサ１７０は、演算結果等のデータを記憶装置１７１の揮発性記憶装置に出力してもよいし、揮発性記憶装置を介して補助記憶装置にデータを保存してもよい。 The control device 17 is composed of a processor 170 and a storage device 171 as shown in FIG. 15 as an example of hardware. Although the storage device is not shown, it includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory. Further, an auxiliary storage device of a hard disk may be provided instead of the flash memory. The processor 170 executes the program input from the storage device 171. In this case, a program is input from the auxiliary storage device to the processor 170 via the volatile storage device. Further, the processor 170 may output data such as a calculation result to the volatile storage device of the storage device 171 or may store the data in the auxiliary storage device via the volatile storage device.
　本開示は、様々な例示的な実施の形態及び実施例が記載されているが、１つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、または様々な組み合わせで実施の形態に適用可能である。
　従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。 Although the present disclosure describes various exemplary embodiments and examples, the various features, embodiments, and functions described in one or more embodiments are those of a particular embodiment. It is not limited to application, but can be applied to embodiments alone or in various combinations.
Therefore, innumerable variations not illustrated are envisioned within the scope of the techniques disclosed herein. For example, it is assumed that at least one component is modified, added or omitted, and further, at least one component is extracted and combined with the components of other embodiments.
　１：ワイヤレス給電システム、　５：交流電源、　１１：送電回路、　１２：受電回路、　１３：電力変換器、　１３ａ、１３ｂ、１３ｃ：整流回路、　１４：ＬＣフィルタ、　１５：負荷、　１６：電圧検出手段、　１７：制御装置、　１９：電圧検出手段、　１１１：送電コイル、　１１２：送電側コンデンサ、　１２１：受電コイル、　１２２：受電側コンデンサ、　１３１、１３２、１３３、１３４：ダイオード、　１３５ａ、１３５ｂ、１３６ａ、１３６ｂ：半導体スイッチ、　１４１：ＤＣリアクトル、　１４２：ＤＣコンデンサ、　１７０：プロセッサ、　１７１：記憶装置。 1: Wireless power supply system, 5: AC power supply, 11: Transmission circuit, 12: Power receiving circuit, 13: Power converter, 13a, 13b, 13c: Capacitor circuit, 14: LC filter, 15: Load, 16: Voltage detection means , 17: Control device, 19: Voltage detection means, 111: Transmission coil, 112: Transmission side capacitor, 121: Power receiving coil, 122: Power receiving side capacitor, 131, 132, 133, 134: Diode, 135a, 135b, 136a, 136b: Semiconductor switch, 141: DC reactor, 142: DC capacitor, 170: Processor, 171: Storage device.

Claims (14)

  1. 　ワイヤレス給電システムの受電装置であって、
    　受電コイルを有し、送電回路より送られる交流電力を受電する受電回路と、
    　前記受電回路が受電した交流電力を直流電力に変換する電力変換器と、
    　前記受電回路の出力電圧を検出する電圧検出手段と、
    　前記受電回路と前記電力変換器との間の回路の導通と開放とを切り替える少なくとも１つのスイッチと、
    　前記電圧検出手段により検出された電圧に基づいて、前記スイッチを制御する制御装置と、を備えた受電装置。     A power receiving device for a wireless power supply system
    A power receiving circuit that has a power receiving coil and receives AC power sent from the power transmission circuit,
    A power converter that converts AC power received by the power receiving circuit into DC power, and
    A voltage detecting means for detecting the output voltage of the power receiving circuit and
    At least one switch that switches between conduction and opening of the circuit between the power receiving circuit and the power converter, and
    A power receiving device including a control device that controls the switch based on the voltage detected by the voltage detecting means.
  2. 　前記スイッチのオンとオフを切り替える時間を、前記電圧検出手段により検出された電圧の絶対値が最大値に対して２０％以下である時間とする請求項１に記載の受電装置。 The power receiving device according to claim 1, wherein the time for switching the switch on and off is a time during which the absolute value of the voltage detected by the voltage detecting means is 20% or less of the maximum value.
  3. 　前記スイッチは、前記電力変換器の具備する半導体スイッチであり、前記制御装置により前記半導体スイッチのオンとオフとを制御することで、前記受電回路と前記電力変換器とが導通する給電期間及び前記受電回路と前記電力変換器との間が開放される非給電期間を切り替えて出力する電力の制御を行う請求項１または２に記載の受電装置。 The switch is a semiconductor switch included in the power converter, and by controlling the on / off of the semiconductor switch by the control device, the power supply period in which the power receiving circuit and the power converter are conducted and the power supply period and the said The power receiving device according to claim 1 or 2, wherein the power to be output is controlled by switching the non-power supply period in which the power receiving circuit and the power converter are opened.
  4. 　前記制御装置は、前記半導体スイッチのオンとオフとを切り替える繰り返し周期あたりの前記給電期間と前記非給電期間との比率により、前記出力する電力の制御を行う請求項３に記載の受電装置。 The power receiving device according to claim 3, wherein the control device controls the output power according to the ratio of the power supply period to the non-power supply period per the repetition cycle of switching the semiconductor switch on and off.
  5. 　前記電力変換器は４つのダイオードを有するフルブリッジ回路であり、前記フルブリッジ回路を構成する上下アームのいずれかのアーム側の前記ダイオードに、前記半導体スイッチがそれぞれ直列に接続された請求項４に記載の受電装置。 The power converter is a full-bridge circuit having four diodes, and the semiconductor switch is connected in series to the diode on the arm side of any of the upper and lower arms constituting the full-bridge circuit. The power receiving device described.
  6. 　前記電力変換器は４つのダイオードを有するフルブリッジ回路であり、前記フルブリッジ回路を構成する２つのレグのいずれかのレグ側の前記ダイオードに、前記半導体スイッチがそれぞれ直列に接続された請求項４に記載の受電装置。 The power converter is a full-bridge circuit having four diodes, and the semiconductor switch is connected in series to the diode on the leg side of either of the two legs constituting the full-bridge circuit. The power receiving device described in.
  7. 　前記制御装置は、前記半導体スイッチのオンとオフの制御を前記電圧検出手段により検出された電圧の半周期単位として行う請求項４から６のいずれか１項に記載の受電装置。 The power receiving device according to any one of claims 4 to 6, wherein the control device controls on and off of the semiconductor switch as a half-cycle unit of the voltage detected by the voltage detecting means.
  8. 　リアクトルを有し、前記電力変換器に接続されたＬＣフィルタと、
    前記リアクトルに流れる電流を検出する電流検出手段と、をさらに設け、
    前記制御装置は前記検出された電流に基づき、予め設定された出力電力指令値となるように、前記半導体スイッチを制御する請求項４から７のいずれか１項に記載の受電装置。     An LC filter having a reactor and connected to the power converter,
    A current detecting means for detecting the current flowing through the reactor is further provided.
    The power receiving device according to any one of claims 4 to 7, wherein the control device controls the semiconductor switch so that the output power command value is set in advance based on the detected current.
  9. 　前記制御装置は、前記半導体スイッチのオンとオフとを切り替える繰り返し周期あたりの前記給電期間の比率が異なる、前記半導体スイッチを制御する駆動信号パターンを少なくとも３つ以上有し、
    前記電流検出手段で検出された電流値に基づき、前記複数の駆動信号パターンから前記給電期間と前記非給電期間との比率が近い２つの前記駆動信号パターンを用いて、段階的に予め設定された前記出力電力指令値となるように、前記半導体スイッチを制御する請求項８に記載の受電装置。     The control device has at least three or more drive signal patterns for controlling the semiconductor switch, which have different ratios of the power supply period per repetition period for switching on and off of the semiconductor switch.
    Based on the current value detected by the current detecting means, two drive signal patterns in which the ratio of the power supply period and the non-power supply period are close to each other from the plurality of drive signal patterns are set in a stepwise preset manner. The power receiving device according to claim 8, wherein the semiconductor switch is controlled so as to have the output power command value.
  10. 　前記スイッチは、前記受電回路と前記電力変換器との間に設けられた双方向スイッチであり、前記制御装置により前記双方向スイッチのオンとオフを制御することで、前記受電回路と前記電力変換器とが導通する給電期間及び前記受電回路と前記電力変換器との間が開放される非給電期間を切り替えて出力する電力の制御を行う請求項１または２に記載の受電装置。 The switch is a bidirectional switch provided between the power receiving circuit and the power converter, and the power receiving circuit and the power conversion are performed by controlling the on / off of the bidirectional switch by the control device. The power receiving device according to claim 1 or 2, wherein the power receiving device controls the power output by switching between the power feeding period in which the device is conductive and the non-power supply period in which the power receiving circuit and the power converter are opened.
  11. 　前記制御装置は、前記双方向スイッチのオンとオフとを切り替える繰り返し周期あたりの前記給電期間と前記非給電期間との比率により、出力する電力の制御を行う請求項１０に記載の受電装置。 The power receiving device according to claim 10, wherein the control device controls output power according to a ratio of the power supply period to the non-power supply period per a repetition cycle for switching on and off of the bidirectional switch.
  12. 　リアクトルを有し、前記電力変換器に接続されたＬＣフィルタと、
    前記リアクトルに流れる電流を検出する電流検出手段と、をさらに設け、
    前記制御装置は前記検出された電流に基づき、予め設定された出力電力指令値となるように、前記双方向スイッチを制御する請求項１１に記載の受電装置。     An LC filter having a reactor and connected to the power converter,
    A current detecting means for detecting the current flowing through the reactor is further provided.
    The power receiving device according to claim 11, wherein the control device controls the bidirectional switch so that the output power command value is set in advance based on the detected current.
  13. 　前記制御装置は、前記双方向スイッチのオンとオフとを切り替える繰り返し周期あたりの前記給電期間の比率が異なる、前記双方向スイッチを制御する駆動信号パターンを少なくとも３つ以上有し、
    前記電流検出手段で検出された電流値に基づき、前記複数の駆動信号パターンから前記給電期間と前記非給電期間との比率が近い２つの前記駆動信号パターンを用いて、段階的に予め設定された前記出力電力指令値となるように、前記双方向スイッチを制御する請求項１２に記載の受電装置。     The control device has at least three or more drive signal patterns for controlling the bidirectional switch, wherein the ratio of the power feeding period per the repetition cycle for switching the bidirectional switch on and off is different.
    Based on the current value detected by the current detecting means, two drive signal patterns in which the ratio of the power supply period and the non-power supply period are close to each other from the plurality of drive signal patterns are set in a stepwise preset manner. The power receiving device according to claim 12, wherein the bidirectional switch is controlled so as to have the output power command value.
  14. 　電力源に接続され、送電コイルを有する送電回路と、
    　請求項１から１３のいずれか１項に記載の受電装置と、を備え、
    　前記送電回路から非接触で前記受電装置に電力が送られるワイヤレス給電システム。     A power transmission circuit that is connected to a power source and has a power transmission coil,
    The power receiving device according to any one of claims 1 to 13 is provided.
    A wireless power supply system in which power is transmitted from the power transmission circuit to the power receiving device in a non-contact manner.
PCT/JP2019/051150 2019-12-26 2019-12-26 Power receiving device and wireless power feed system WO2021130965A1 (en)

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KR1020227020060A KR20220100665A (en) 2019-12-26 2019-12-26 Power receiving device and wireless power feeding system
US17/773,616 US20220376553A1 (en) 2019-12-26 2019-12-26 Power receiving device and wireless power transfer system
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