WO2021129646A1 - 一种超宽带两位移相器 - Google Patents

一种超宽带两位移相器 Download PDF

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Publication number
WO2021129646A1
WO2021129646A1 PCT/CN2020/138542 CN2020138542W WO2021129646A1 WO 2021129646 A1 WO2021129646 A1 WO 2021129646A1 CN 2020138542 W CN2020138542 W CN 2020138542W WO 2021129646 A1 WO2021129646 A1 WO 2021129646A1
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Prior art keywords
transistor
switch tube
inductor
differential amplifier
series
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PCT/CN2020/138542
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English (en)
French (fr)
Inventor
刘尧
潘晓枫
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中电国基南方集团有限公司
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Priority to EP20907874.0A priority Critical patent/EP4080765A4/en
Publication of WO2021129646A1 publication Critical patent/WO2021129646A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/16—Networks for phase shifting
    • H03H11/20—Two-port phase shifters providing an adjustable phase shift
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/06—A balun, i.e. balanced to or from unbalanced converter, being present at the input of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7221—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the output of the amplifier

Definitions

  • the invention belongs to the radio frequency microwave integrated circuit technology of microelectronics and solid-state electronics, in particular to an ultra-wideband two phase shifter.
  • the phase shifter is a key element in the modern antenna phased array and microwave communication system. It is used to control the phase change of the microwave signal, thereby controlling the beam scanning of the antenna, and realizing the search and tracking of the target.
  • the size of the phase shifter, phase shift accuracy, cost, operating temperature, and mass production capacity are directly related to the performance of the entire phased array radar, and its bandwidth represents the overall bandwidth bottleneck of the transceiver system.
  • monolithic integrated phase shifter circuits mainly include transmission line type, reflection type and all-pass network type based on magnetic coupling.
  • Transmission line type phase shifters usually have a narrow working bandwidth. In order to expand the bandwidth, a multi-stage series connection is generally used. This will increase the area of the circuit and increase the loss of the circuit, and it is difficult for the bandwidth to reach 9 octaves.
  • the reflective phase shifter can expand the bandwidth, but is limited by the quarter-wavelength line, and the circuit area is relatively large, which is not conducive to chip miniaturization. Although the working bandwidth of the all-pass network phase shifter based on magnetic coupling can reach multiple octaves, the amount of phase shift achieved is limited.
  • the purpose of the present invention is to provide an ultra-wideband two phase shifter with high phase shift accuracy, good amplitude balance, simple control mode and high integration.
  • an ultra-wideband two phase shifter including an active balun, first to third differential amplifiers, a switch matrix, an RC quadrature network and a single-pole double-throw switch, in which:
  • the active balun receives a single-ended signal and converts the single-ended signal into a double-ended signal, the two output ends adopt an asymmetric structure, and the two output signals are respectively connected to the two input ends of the first differential amplifier;
  • the first differential amplifier performs waveform shaping and gain compensation on the two received signals, and selects different branches through the switch matrix to achieve a phase shift of 180°;
  • the two-terminal signal generates a quadrature signal through a cascaded RC quadrature network, and the rear stage of the RC quadrature network is respectively cascaded with a second and a third differential amplifier;
  • the single-pole double-throw switch selects different branches of the second and third differential amplifiers to generate a 90° phase shift step amount, thereby realizing three phase shift amounts of 90°, 180°, and 270°.
  • the single-ended signal is transmitted to the active balun through the input matching network.
  • the input matching network includes a ninth series capacitor, a ninth parallel inductor, a tenth series inductor, and a fifth parallel resistor; the ninth series capacitor and the ninth parallel inductor are sequentially connected in series from the input end to the output end of the input matching network , The common terminal of the ninth series capacitor and the ninth parallel inductor are grounded through the tenth series inductor; on the one hand, the output terminal of the input matching network is grounded through the fifth parallel resistor, and on the other hand, it is connected to the input terminal of the active balun.
  • the active balun includes an eleventh inductor, a first resistor, a first transistor, a second transistor, a first capacitor, a second capacitor, a first inductor, and a second inductor;
  • the sources of the first transistor and the second transistor are connected, the common terminal is connected in series with the first resistor and the eleventh inductor to ground; the gate of the first transistor is connected to the output terminal of the matching network, and the gate of the second transistor is grounded;
  • the drain of the first transistor is connected in series with the first capacitor and the first inductor as the first differential output port of the active balun, and the drain of the second transistor is connected in series with the second capacitor and the second inductor, respectively, as the first differential output port of the active balun. Two differential output ports.
  • the first differential amplifier includes a third transistor, a fourth transistor, a third capacitor, a fourth capacitor, a third inductor, a fourth inductor, a second resistor, and a twelfth inductor;
  • the first differential output port of the active balun is connected to the gate of the third transistor of the first differential amplifier, and the second differential output port is connected to the gate of the fourth transistor of the first differential amplifier;
  • the source of the third transistor is connected to the source of the fourth transistor, and the common terminal is connected in series with the second resistor and the twelfth inductor to ground; the drain of the third transistor is connected in series with the third resistor and the third inductor as the first differential amplifier.
  • a differential output port, a fourth resistor and a fourth inductor are connected in series with the drain of the fourth transistor as the second differential output port of the first differential amplifier.
  • the switch matrix includes ninth to twentieth switching tubes ⁇ , wherein the ninth to twelfth switching tubes ⁇ are connected in series in sequence, and the thirteenth to sixteenth switching tubes ⁇ are connected in series in sequence;
  • the common terminal of the ninth switch tube and the tenth switch tube is connected to one end of the seventeenth switch tube through a microstrip, and the other end of the seventeenth switch tube is used as the first output terminal of the switch matrix and is connected to the eighteenth switch tube.
  • One end of the eighteenth switching tube is connected to the common end of the thirteenth switching tube and the fourteenth switching tube through a microstrip; the common end of the fifteenth switching tube and the sixteenth switching tube is connected to the common terminal of the fifteenth switching tube through a microstrip.
  • the belt is connected to one end of the twentieth switch tube, and the other end of the twentieth switch tube is used as the second output terminal of the switch matrix, and is connected to one end of the nineteenth switch tube.
  • the other end of the nineteenth switch tube passes through a micro
  • the belt is connected to the common terminal of the eleventh switch tube and the twelfth switch tube; the first differential output port of the first differential amplifier is connected to the common terminal of the tenth switch tube and the eleventh switch tube, and the second The differential output port is connected to the common terminal of the fourteenth switch tube and the fifteenth switch tube.
  • the second differential amplifier includes a fifth transistor, a sixth transistor, a fifth resistor, a sixth resistor, a fifth inductor, a sixth inductor, and a third resistor;
  • the third differential amplifier includes a seventh transistor, a Eight transistors, seventh resistor, eighth resistor, seventh inductor, eighth inductor and fourth resistor;
  • phase reference terminal and the -180° terminal of the RC quadrature network are respectively connected to the gates of the fifth transistor and the sixth transistor of the second differential amplifier; the -270° terminal and the -90° terminal are respectively connected to the second differential amplifier The gates of the seventh transistor and the eighth transistor;
  • the sources of the fifth transistor and the sixth transistor are connected, and the common terminal is connected in series with a third resistor to ground; the drain of the fifth transistor is connected in series with a fifth resistor and a fifth inductor as the first differential output port of the second differential amplifier.
  • the drains of the six transistors are respectively connected in series with the sixth resistor and the sixth inductor as the second differential output port of the second differential amplifier; the first differential output port of the second differential amplifier is connected to the first 50 ohm load, and the second differential amplifier’s
  • the two differential output ports are connected to a branch of the rear-stage single-pole double-throw switch;
  • the source of the seventh transistor is connected to the source of the eighth transistor, and the common terminal is connected in series with a fourth resistor to ground; the drain of the seventh transistor is connected in series with the seventh resistor and the seventh inductor as the second differential output port of the third differential amplifier.
  • the drains of the eight transistors are connected in series with the eighth resistor and the eighth inductor as the first differential output port of the third differential amplifier, the first differential output port of the third differential amplifier is connected to the second 50 ohm load, and the second The differential output port is connected to the other branch of the rear-stage single-pole double-throw switch.
  • control levels of the ninth switch tube, the eleventh switch tube, the fourteenth switch tube, the sixteenth switch tube, the eighteenth switch tube, and the nineteenth switch tube are the same; the tenth switch tube, The control levels of the twelfth switch tube, the thirteenth switch tube, the fifteenth switch tube, the seventeenth switch tube, and the twentieth switch tube are the same, and are the same as those of the ninth switch tube, the eleventh switch tube, and the tenth switch tube.
  • the control levels of the four switching tubes, the sixteenth switching tube, the eighteenth switching tube, and the nineteenth switching tube are opposite.
  • the present invention has significant advantages: (1) After the single-ended signal achieves a 180° phase shift through the active balun, differential amplification and switch matrix, it enters the RC network to generate a quadrature signal, and finally passes through the differential Amplification and single-pole double-throw switch output realize an ultra-wideband two-phase shifter with a phase shift step of 90°; (2) Phase and amplitude balance is good, high electrical performance indicators, high integration, low insertion loss, control The method is simple and convenient to use, and can be mass-produced.
  • Fig. 1 is a schematic diagram of the structure of an ultra-wideband two phase shifter of the present invention.
  • Fig. 2 is a circuit structure diagram of the present invention.
  • Fig. 3 is a circuit structure diagram of the switch matrix in the present invention.
  • Fig. 4 is a circuit structure diagram of a third-order RC orthogonal network in the present invention.
  • Fig. 5 is a circuit layout of an ultra-wideband two-phase shifter of 2-18GHz of the embodiment of the present invention.
  • Fig. 6 is a 90° phase shift curve diagram of the 2-18GHz ultra-wideband two phase shifter of the present invention.
  • Fig. 7 is a 180° phase shift curve diagram of the 2-18GHz ultra-wideband two phase shifter of the present invention.
  • Fig. 8 is a 270° phase shift curve diagram of the 2-18GHz ultra-wideband two phase shifter of the present invention.
  • Fig. 9 is a graph showing the input return loss parameters of the base state and 90°, 180°, and 270° phase shift states of the 2-18GHz ultra-wideband two phase shifter of the embodiment of the present invention.
  • Fig. 10 is a graph of insertion loss parameters of the base state and 90°, 180°, and 270° phase shift states of the 2-18GHz ultra-wideband two phase shifter of the embodiment of the present invention.
  • Fig. 11 is a graph of output return loss parameters of the base state and 90°, 180°, and 270° phase shift states of the ultra-wideband two phase shifter of the embodiment of the present invention from 2 to 18 GHz.
  • the ultra-wideband two phase shifter of the present invention includes an input active balun, a first to a third differential amplifier, a switch matrix, an RC quadrature network and a single-pole double-throw switch.
  • the single-ended signal is outputted by the active balun to realize the differential signal output, and then the first differential amplifier circuit performs waveform shaping and gain compensation, and the switch matrix selects different branches to achieve a phase shift of 180°, through the cascaded RC quadrature network Generate quadrature signals, and the subsequent stages are respectively cascaded with the second differential amplifier and the third differential amplifier.
  • different branches are selected by the single-pole double-throw switch to generate a 90° phase shift step amount to achieve 90°, 180°, 270° three kinds of phase shift amount.
  • the phase shifter has the characteristics of ultra-wideband, high phase shift accuracy, good amplitude balance, simple control mode, and high integration.
  • an ultra-wideband two phase shifter of the present invention includes an active balun, first to third differential amplifiers, a switch matrix, an RC quadrature network and a single-pole double-throw switch, in which:
  • the active balun receives a single-ended signal and converts the single-ended signal into a double-ended signal, the two output ends adopt an asymmetric structure, and the two output signals are respectively connected to the two gates of the first differential amplifier;
  • the first differential amplifier performs waveform shaping and gain compensation on the two received signals, and selects different branches through the switch matrix to achieve a phase shift of 180°;
  • the two-terminal signal generates a quadrature signal through a cascaded RC quadrature network, and the rear stage of the RC quadrature network is respectively cascaded with a second and a third differential amplifier;
  • the single-pole double-throw switch selects different branches of the second and third differential amplifiers to generate a 90° phase shift step amount, thereby realizing three phase shift amounts of 90°, 180°, and 270°.
  • the single-ended signal is transmitted to the active balun through an input matching network, which includes a ninth series capacitor C9, a ninth parallel inductor L9, a tenth series inductor L10, and a fifth parallel resistor R5;
  • the ninth series capacitor C9 and the ninth parallel inductor L9 are connected in series from the input end to the output end of the input matching network.
  • the common end of the ninth series capacitor C9 and the ninth parallel inductor L9 is grounded through the tenth series inductor L10;
  • the output terminal is grounded through the fifth parallel resistor R5 on the one hand, and connected to the input terminal of the active balun on the other hand.
  • the active balun includes an eleventh inductor L11, a first resistor R1, a first transistor AF1, a second transistor AF2, a first capacitor C1, a second capacitor C2, a first inductor L1, and a Two inductors L2;
  • the sources of the first transistor AF1 and the second transistor AF2 are connected, and the common terminal is connected in series with the first resistor R1 and the eleventh inductor L11 to the ground; the gate of the first transistor AF1 is connected to the output terminal of the matching network, and the second transistor The gate of AF2 is grounded; the drain of the first transistor AF1 is connected in series with the first capacitor C1 and the first inductor L1 to serve as the first differential output port of the active balun, and the drain of the second transistor AF2 is connected in series with the second capacitor C2, respectively
  • the second inductor L2 serves as the second differential output port of the active balun.
  • the first differential amplifier includes a third transistor AF3, a fourth transistor AF4, a third capacitor C3, a fourth capacitor C4, a third inductor L3, a fourth inductor L4, a second resistor R2, and a tenth transistor.
  • the first differential output port of the active balun is connected to the gate of the third transistor AF3 of the first differential amplifier, and the second differential output port is connected to the gate of the fourth transistor AF4 of the first differential amplifier;
  • the source of the third transistor AF3 and the fourth transistor AF4 are connected, and the common terminal is connected in series with the second resistor R2 and the twelfth inductor L12 to ground; the drain of the third transistor AF3 is connected in series with the third resistor C3 and the third inductor L3 as The first differential output port of the first differential amplifier, and the drain of the fourth transistor AF4 are connected in series with the fourth resistor C4 and the fourth inductor L4 as the second differential output port of the first differential amplifier.
  • the switch matrix includes ninth to twentieth switch tubes AF9 to AF20, wherein the ninth to twelfth switch tubes AF9 to AF12 are connected in series, and the thirteenth to sixteenth switch tubes AF13 to AF16 are connected in series. In series
  • the common terminal of the ninth switch tube AF9 and the tenth switch tube AF10 is connected to one end of the seventeenth switch tube AF17 through a microstrip, and the other end of the seventeenth switch tube AF17 serves as the first output terminal of the switch matrix and is connected to One end of the eighteenth switch tube AF18 and the other end of the eighteenth switch tube AF18 are connected to the common end of the thirteenth switch tube AF13 and the fourteenth switch tube AF14 through a microstrip; the fifteenth switch tube AF15 and the tenth switch tube
  • the common end of the six switching tubes AF16 is connected to one end of the twentieth switching tube AF20 through a microstrip.
  • the other end of the twentieth switching tube AF20 is used as the second output terminal of the switch matrix and connected to the nineteenth switching tube AF19.
  • One end, the other end of the nineteenth switching tube AF19 is connected to the common terminal of the eleventh switching tube AF11 and the twelfth switching tube AF12 through a microstrip; the first differential output port of the first differential amplifier is connected to the tenth switching tube AF10
  • the common terminal of the eleventh switch tube AF11 and the second differential output port of the first differential amplifier are connected to the common terminal of the fourteenth switch tube AF14 and the fifteenth switch tube AF15.
  • the second differential amplifier includes a fifth transistor AF5, a sixth transistor AF6, a fifth resistor C5, a sixth resistor C6, a fifth inductor L5, a sixth inductor L6, and a third resistor R3;
  • the third differential amplifier includes a seventh transistor AF7, an eighth transistor AF8, a seventh resistor C7, an eighth resistor C8, a seventh inductor L7, an eighth inductor L8, and a fourth resistor R4;
  • phase reference terminal and the -180° terminal of the RC quadrature network are respectively connected to the gates of the fifth transistor AF5 and the sixth transistor AF6 of the second differential amplifier; the -270° terminal and the -90° terminal are respectively connected to the second The gates of the seventh transistor AF7 and the eighth transistor AF8 of the differential amplifier;
  • the sources of the fifth transistor AF5 and the sixth transistor AF6 are connected, and the common end is connected in series with the third resistor R3 to ground; the drain of the fifth transistor AF5 is connected in series with the fifth resistor C5 and the fifth inductor L5 as the second differential amplifier.
  • a differential output port, the drain of the sixth transistor AF6 is connected in series with the sixth resistor C6 and the sixth inductor L6 respectively as the second differential output port of the second differential amplifier;
  • the first differential output port of the second differential amplifier is connected to the first 50 Ohmic load RL1, the second differential output port of the second differential amplifier is connected to a branch of the rear-stage single-pole double-throw switch;
  • the source of the seventh transistor AF7 and the eighth transistor AF8 are connected, and the common terminal is connected in series with the fourth resistor R4 to ground; the drain of the seventh transistor AF7 is connected in series with the seventh resistor C7 and the seventh inductor L7 as the third differential amplifier.
  • Two differential output ports, the drain of the eighth transistor AF8 is connected in series with the eighth resistor C8 and the eighth inductor L8 as the first differential output port of the third differential amplifier, and the first differential output port of the third differential amplifier is connected to the second 50 ohm Load RL2, the second differential output port of the third differential amplifier is connected to the other branch of the rear-stage single-pole double-throw switch.
  • the control of the ninth switch tube AF9, the eleventh switch tube AF11, the fourteenth switch tube AF14, the sixteenth switch tube AF16, the eighteenth switch tube AF18, and the nineteenth switch tube AF19 The levels are the same; the control levels of the tenth switch tube AF10, the twelfth switch tube AF12, the thirteenth switch tube AF13, the fifteenth switch tube AF15, the seventeenth switch tube AF17, and the twentieth switch tube AF20 are the same, And it is opposite to the control levels of the ninth switch tube AF9, the eleventh switch tube AF11, the fourteenth switch tube AF14, the sixteenth switch tube AF16, the eighteenth switch tube AF18, and the nineteenth switch tube AF19.
  • This embodiment is an ultra-wideband two phase shifter operating at 2-18 GHz.
  • the circuit principle block diagram is shown in Figure 1.
  • the phase shifter consists of an active balun, first to third differential amplifier circuits, a switch matrix, RC orthogonal network and single-pole double-throw switch.
  • the active balun realizes the signal conversion from single-ended to double-ended, in which the drains of transistors AF1 and AF2 are directly biased by resistors, and an asymmetric structure is adopted at the two output terminals to improve their balance, as shown in Figure 2 in series
  • the capacitor C1 and the inductor L1 at the drain of AF1 and the capacitor C2 and the inductor L2 at the drain of AF2 are connected in series.
  • the sources of AF1 and AF2 are connected, and the middle series resistor R1 and inductor L0 are connected to the ground to realize the self-biasing of the differential tube and the improvement of the differential performance of the active balun.
  • the two signal output ends of the active balun are respectively connected to the gates of the differential amplifier, as shown in Figure 2 for the gates of the transistors AF3 and AF4.
  • the drains of AF3 and AF4 also adopt direct resistance bias mode, and the source stage is connected to the ground through a series resistor R2 and an inductance L0 to realize the self-biasing of the differential tube and better differential performance.
  • the output terminal adopts the series structure of capacitor C3 and inductor L3 to realize broadband output matching.
  • the switch matrix shown in Figure 3 is designed. Among them, the switch tube is equivalent to a small resistance when it is turned on, and it is equivalent to a small capacitor when it is turned off.
  • Vcon When Vcon is high, When it is low, the signal goes from port 1 to port 3 through AF10 and AF17, and another signal goes from port 2 to port 4 through AF15 and AF20; when Vcon is low, When it is high, the signal goes from port 1 to port 4 through AF11 and AF19, and another signal goes from port 2 to port 3 through AF14 and AF18. Therefore, through the Vcon and Synchronous control of, realizes the interchange of signal path, thus realizes 180° phase shift.
  • the differential signal enters the third-order RC quadrature network cascaded in the subsequent stages to generate four quadrature signal outputs, as shown in Figure 4.
  • the 0° and -180° ports are respectively connected to the grids of AF5 and AF6; the -90° and -270° ports are respectively connected to the grids of AF8 and AF7.
  • AF5, AF6, C4, L4 and R3 form a rear differential amplifier
  • AF8, AF7, C4, L4 and R3 form another rear differential amplifier.
  • One of the two output ports of the differential amplifier is connected to the load impedance, and the other port is connected to the rear-stage single-pole double-throw switch.
  • the 90° phase shift can be realized by selecting the two branches of the single-pole double-throw switch, and then through the common control of the switch matrix and the single-pole double throw switch, 90°, 180° and 270° phase shifts can be realized.
  • the circuit layout of the 2-18GHz ultra-wideband two phase shifter of the present invention is shown in Figure 5.
  • the layout is mainly composed of GaAs PHEMT transistors, microstrip lines, resistors, capacitors, ground holes, power-on ports, and radio frequency ports.
  • the single-ended signal enters from the signal input port 1, and is converted into a differential signal output through the active balun 2, and then enters the differential amplifier circuit 3 through the matching network, and then enters the switch matrix 4 with dual-in and dual-out after amplifying, realizing the signal 180 °Phase shift.
  • the switch matrix 4 Immediately after the differential signal is injected into the RC network 5, two pairs of orthogonal signals are generated.
  • the two pairs of signals enter the differential amplifier 6 for waveform shaping and amplification, and then the single-pole double-throw switch 7 at the end selects the channel to achieve 90° , 180° and 270° phase shift, and finally output from the signal output port 8.
  • the first to fourth ports 9, 10, 11, 12 are the power-on and control ports of the circuit.
  • Figures 6-11 are measured curves of the 2-18GHz ultra-wideband two phase shifter of the present invention.
  • Figure 6 is a 90° phase shift curve
  • Figure 7 is a 180° phase shift curve
  • Figure 8 is a 270° phase shift curve
  • Figures 9-11 are the S-parameter curves of the ground state and each phase shift state. It can be seen from the figure that in the 2-18GHz frequency band, the phase shift accuracy of each phase shift state of this phase shifter chip is less than 5°, and the signal loss is small, with the advantages of high phase shift accuracy and large working bandwidth. .

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Abstract

一种超宽带两位移相器，包括有源巴伦、第一～第三差分放大器、开关矩阵、RC正交网络和单刀双掷开关，其中有源巴伦接收单端信号，将单端信号转换为双端信号，分别连接至第一差分放大器的两个输入端；第一差分放大器对接收到的两路信号进行波形整形和增益补偿，并通过开关矩阵选择不同的支路以实现180°的相移；双端信号经开关矩阵并通过级联RC正交网络产生正交信号，RC正交网络的后级分别级联第二、第三差分放大器；单刀双掷开关选择第二、第三差分放大器不同的支路，产生90°相移步进量，从而实现90°、180°、270°三种移相量。该超宽带两位移相器具有超宽带、移相精度高、幅度平衡性好、控制方式简单、集成度高的优点。

Description

一种超宽带两位移相器 技术领域
本发明属于微电子与固体电子学的射频微波集成电路技术，特别是一种超宽带两位移相器。
背景技术
移相器是现代天线相控阵及微波通讯系统的中的关键元件，用于控制微波信号的相位变化，从而控制天线的波束扫描，实现对目标的搜索及跟踪。移相器的体积大小、移相精度、成本、工作温度、批量生产能力都直接关系到整个相控阵雷达的性能，其带宽代表了收发系统的总体带宽瓶颈。
目前单片集成移相器电路主要有传输线型、反射型以及基于磁耦合的全通网络型。传输线型移相器通常工作带宽较窄，为了拓展带宽，一般采用多级串联的方式，这样会增大电路的面积，增加电路的损耗，而且带宽难以达到9个倍频程。反射型移相器可以拓展带宽，但受限于四分之一波长线，电路面积也比较大，不利于芯片小型化。基于磁耦合的全通网络型移相器的工作带宽虽可以达到多个倍频程，但实现的相移量有限。
发明内容
本发明的目的在于提供一种移相精度高、幅度平衡性好、控制方式简单、集成度高的超宽带两位移相器。
实现本发明目的的技术解决方案为：一种超宽带两位移相器，包括有源巴伦、第一～第三差分放大器、开关矩阵、RC正交网络和单刀双掷开关，其中：
所述有源巴伦接收单端信号，将单端信号转换为双端信号，两路输出端采用不对称结构，输出的两路信号分别连接至第一差分放大器的两个输入端；
所述第一差分放大器对接收到的两路信号进行波形整形和增益补偿，并通过开关矩阵选择不同的支路以实现180°的相移；
所述双端信号通过级联RC正交网络产生正交信号，RC正交网络的后级分别级联第二、第三差分放大器；
所述单刀双掷开关选择第二、第三差分放大器不同的支路，产生90°相移步进量，从而实现90°、180°、270°三种移相量。
进一步地，所述单端信号通过输入匹配网络传输至有源巴伦。
进一步地，所述输入匹配网络包括第九串联电容、第九并联电感、第十串联电感和第五并联电阻；输入匹配网络的输入端至输出端顺次串联第九串联电容、第九并联电感，第九串联电容、第九并联电感的公共端通过第十串联电感接地；输入匹配网络的输出端一方面通过第五并联电阻接地，另一方面接入有源巴伦的输入端。
进一步地，所述有源巴伦包括第十一电感、第一电阻、第一晶体管、第二晶体管、第一电容、第二电容、第一电感和第二电感；
所述第一晶体管和第二晶体管的源极相连，公共端串联第一电阻和第十一电感到 地；第一晶体管的栅极与匹配网络的输出端相连，第二晶体管的栅极接地；第一晶体管的漏极串联第一电容、第一电感后作为有源巴伦的第一差分输出端口，第二晶体管的漏极分别串联第二电容、第二电感后作为有源巴伦的第二差分输出端口。
进一步地，所述第一差分放大器包括第三晶体管、第四晶体管、第三电容、第四电容、第三电感、第四电感、第二电阻和第十二电感；
有源巴伦的第一差分输出端口连接到第一差分放大器的第三晶体管栅极，第二差分输出端口连接到第一差分放大器的第四晶体管栅极；
所述第三晶体管和第四晶体管的源极相连，公共端串联第二电阻和第十二电感到地；第三晶体管的漏极串联第三电阻、第三电感作为第一差分放大器的第一差分输出端口，第四晶体管的漏极串联第四电阻、第四电感作为第一差分放大器的第二差分输出端口。
进一步地，所述开关矩阵包括第九～第二十开关管～，其中第九～第十二开关管～依次串联，第十三～第十六开关管～依次串联；
第九开关管和第十开关管的共同端通过一段微带连接到第十七开关管的一端，第十七开关管的另一端作为开关矩阵的第一输出端，并连接到第十八开关管的一端，第十八开关管的另一端通过一段微带连接到第十三开关管和第十四开关管的共同端；第十五开关管和第十六开关管的共同端通过一段微带连接到第二十开关管的一端，第二十开关管的另一端作为开关矩阵的第二输出端，并连接到第十九开关管的一端，第十九开关管的另一端通过一段微带连接到第十一开关管和第十二开关管的共同端；第一差分放大器的第一差分输出端口连接第十开关管和第十一开关管的共同端，第一差分放大器的第二差分输出端口连接第十四开关管和第十五开关管的共同端。
进一步地，所述第二差分放大器包括第五晶体管、第六晶体管、第五电阻、第六电阻、第五电感、第六电感和第三电阻；所述第三差分放大器包括第七晶体管、第八晶体管、第七电阻、第八电阻、第七电感、第八电感和第四电阻；
所述RC正交网络的相位参考端和-180°端分别连接到第二差分放大器的第五晶体管和第六晶体管的栅极；-270°端和-90°端分别连接到第二差分放大器的第七晶体管和第八晶体管的栅极；
所述第五晶体管和第六晶体管的源极相连，公共端串联第三电阻到地；第五晶体管的漏极串联第五电阻、第五电感作为第二差分放大器的第一差分输出端口，第六晶体管的漏极分别串联第六电阻、第六电感作为第二差分放大器的第二差分输出端口；第二差分放大器的第一差分输出端口连接到第一50欧姆负载，第二差分放大器的第二差分输出端口连接到后级单刀双掷开关的一条支路上；
所述第七晶体管和第八晶体管的源极相连，公共端串联第四电阻到地；第七晶体管的漏极串联第七电阻、第七电感作为第三差分放大器的第二差分输出端口，第八晶体管的漏极串联第八电阻、第八电感作为第三差分放大器的第一差分输出端口，第三差分放大器的第一差分输出端口连接到第二50欧姆负载，第三差分放大器的第二差分输出端口连接到后级单刀双掷开关的另一条支路上。
进一步地，所述第九开关管、第十一开关管、第十四开关管、第十六开关管、第十八开关管、第十九开关管的控制电平相同；第十开关管、第十二开关管、第十三开关管、第十五开关管、第十七开关管、第二十开关管的控制电平相同，并与第九开关管、第十一开关管、第 十四开关管、第十六开关管、第十八开关管、第十九开关管的控制电平相反。
进一步地，通过控制所述第九开关管～第二十开关管的导通与截止，实现180°移相。
进一步地，通过控制所述单刀双掷开关两条支路的导通与截止，实现90°移相。
本发明与现有技术相比，其显著优点在于：(1)单端信号通过有源巴伦、差分放大和开关矩阵实现180°相移后，进入RC网络产生正交信号，最后再经差分放大和单刀双掷开关输出，实现了移相步进为90°的超宽带两位移相器；(2)相位与幅度平衡性较好，电性能指标高，集成度高，插入损耗低，控制方式简单且使用方便，能够大批量生产。
附图说明
图1是本发明一种超宽带两位移相器的结构示意图。
图2是本发明的电路结构图。
图3是本发明中开关矩阵的电路结构图。
图4是本发明中三阶RC正交网络的电路结构图。
图5是本发明实施例2～18GHz超宽带两位移相器的电路版图。
图6是本发明实施例2～18GHz超宽带两位移相器的90°相移量曲线图。
图7是本发明实施例2～18GHz超宽带两位移相器的180°相移量曲线图。
图8是本发明实施例2～18GHz超宽带两位移相器的270°相移量曲线图。
图9是本发明实施例2～18GHz超宽带两位移相器基态和90°、180°、270°移相态的输入回波损耗参数曲线图。
图10是本发明实施例2～18GHz超宽带两位移相器基态和90°、180°、270°移相态的插入损耗参数曲线图。
图11是本发明实施例2～18GHz超宽带两位移相器基态和90°、180°、270°移相态的输出回波损耗参数曲线图。
具体实施方式
本发明超宽带两位移相器，包括输入有源巴伦、第一～第三差分放大器、开关矩阵、RC正交网络和单刀双掷开关。单端信号通过有源巴伦实现差分信号输出，随后由第一差分放大电路进行波形整形和增益补偿，由开关矩阵选择不同的支路以实现180°的相移，通过级联RC正交网络产生正交信号，其后级分别级联第二差分放大器和第三差分放大器，最后由单刀双掷开关选择不同的支路，产生90°相移步进量，从而实现90°、180°、270°三种移相量。该移相器具有超宽带、移相精度高、幅度平衡性好、控制方式简单、集成度高的特点。下面结合附图对本发明作进一步详细描述。
结合图1，本发明一种超宽带两位移相器，包括有源巴伦、第一～第三差分放大器、开关矩阵、RC正交网络和单刀双掷开关，其中：
所述有源巴伦接收单端信号，将单端信号转换为双端信号，两路输出端采用不对称结构，输出的两路信号分别连接至第一差分放大器的两个栅极；
所述第一差分放大器对接收到的两路信号进行波形整形和增益补偿，并通过开关矩阵选择不同的支路以实现180°的相移；
所述双端信号通过级联RC正交网络产生正交信号，RC正交网络的后级分别级联第二、第三差分放大器；
所述单刀双掷开关选择第二、第三差分放大器不同的支路，产生90°相移步进量，从而实现90°、180°、270°三种移相量。
结合图2，所述单端信号通过输入匹配网络传输至有源巴伦，所述输入匹配网络包括第九串联电容C9、第九并联电感L9、第十串联电感L10和第五并联电阻R5；输入匹配网络的输入端至输出端顺次串联第九串联电容C9、第九并联电感L9，第九串联电容C9、第九并联电感L9的公共端通过第十串联电感L10接地；输入匹配网络的输出端一方面通过第五并联电阻R5接地，另一方面接入有源巴伦的输入端。
作为一种具体示例，所述有源巴伦包括第十一电感L11、第一电阻R1、第一晶体管AF1、第二晶体管AF2、第一电容C1、第二电容C2、第一电感L1和第二电感L2；
所述第一晶体管AF1和第二晶体管AF2的源极相连，公共端串联第一电阻R1和第十一电感L11到地；第一晶体管AF1的栅极与匹配网络的输出端相连，第二晶体管AF2的栅极接地；第一晶体管AF1的漏极串联第一电容C1、第一电感L1后作为有源巴伦的第一差分输出端口，第二晶体管AF2的漏极分别串联第二电容C2、第二电感L2后作为有源巴伦的第二差分输出端口。
作为一种具体示例，所述第一差分放大器包括第三晶体管AF3、第四晶体管AF4、第三电容C3、第四电容C4、第三电感L3、第四电感L4、第二电阻R2和第十二电感L12；
有源巴伦的第一差分输出端口连接到第一差分放大器的第三晶体管AF3栅极，第二差分输出端口连接到第一差分放大器的第四晶体管AF4栅极；
所述第三晶体管AF3和第四晶体管AF4的源极相连，公共端串联第二电阻R2和第十二电感L12到地；第三晶体管AF3的漏极串联第三电阻C3、第三电感L3作为第一差分放大器的第一差分输出端口，第四晶体管AF4的漏极串联第四电阻C4、第四电感L4作为第一差分放大器的第二差分输出端口。
作为一种具体示例，所述开关矩阵包括第九～第二十开关管AF9～AF20，其中第九～第十二开关管AF9～AF12依次串联，第十三～第十六开关管AF13～AF16依次串联；
第九开关管AF9和第十开关管AF10的共同端通过一段微带连接到第十七开关管AF17的一端，第十七开关管AF17的另一端作为开关矩阵的第一输出端，并连接到第十八开关管AF18的一端，第十八开关管AF18的另一端通过一段微带连接到第十三开关管AF13和第十四开关管AF14的共同端；第十五开关管AF15和第十六开关管AF16的共同端通过一段微带连接到第二十开关管AF20的一端，第二十开关管AF20的另一端作为开关矩阵的第二输出端，并连接到第十九开关管AF19的一端，第十九开关管AF19的另一端通过一段微带连接到第十一开关管AF11和第十二开关管AF12的共同端；第一差分放大器的第一差分输出端口连接第十开关管AF10和第十一开关管AF11的共同端，第一差分放大器的第二差分输出端口连接第十四开关管AF14和第十五开关管AF15的共同端。
作为一种具体示例，所述第二差分放大器包括第五晶体管AF5、第六晶体管AF6、第五电阻C5、第六电阻C6、第五电感L5、第六电感L6和第三电阻R3；所述第三差分放大器包括第七晶体管AF7、第八晶体管AF8、第七电阻C7、第八电阻C8、第七电感L7、第八电感L8和第四电阻R4；
所述RC正交网络的相位参考端和-180°端分别连接到第二差分放大器的第五晶体管AF5和第六晶体管AF6的栅极；-270°端和-90°端分别连接到第二差分放大器的第七晶体管AF7和第八晶体管AF8的栅极；
所述第五晶体管AF5和第六晶体管AF6的源极相连，公共端串联第三电阻R3到地；第五晶体管AF5的漏极串联第五电阻C5、第五电感L5作为第二差分放大器的第一差分输出端口，第六晶体管AF6的漏极分别串联第六电阻C6、第六电感L6作为第二差分放大器的第二差分输出端口；第二差分放大器的第一差分输出端口连接到第一50欧姆负载RL1，第二差分放大器的第二差分输出端口连接到后级单刀双掷开关的一条支路上；
所述第七晶体管AF7和第八晶体管AF8的源极相连，公共端串联第四电阻R4到地；第七晶体管AF7的漏极串联第七电阻C7、第七电感L7作为第三差分放大器的第二差分输出端口，第八晶体管AF8的漏极串联第八电阻C8、第八电感L8作为第三差分放大器的第一差分输出端口，第三差分放大器的第一差分输出端口连接到第二50欧姆负载RL2，第三差分放大器的第二差分输出端口连接到后级单刀双掷开关的另一条支路上。
作为一种具体示例，所述第九开关管AF9、第十一开关管AF11、第十四开关管AF14、第十六开关管AF16、第十八开关管AF18、第十九开关管AF19的控制电平相同；第十开关管AF10、第十二开关管AF12、第十三开关管AF13、第十五开关管AF15、第十七开关管AF17、第二十开关管AF20的控制电平相同，并与第九开关管AF9、第十一开关管AF11、第十四开关管AF14、第十六开关管AF16、第十八开关管AF18、第十九开关管AF19的控制电平相反。
进一步地，通过控制所述第九开关管～第二十开关管AF9～AF20的导通与截止，实现180°移相。
进一步地，通过控制所述单刀双掷开关两条支路的导通与截止，实现90°移相。
下面结合具体实施例对本发明作进一步详细描述。
实施例
本实施例为一种工作于2～18GHz超宽带两位移相器，其电路原理框图如图1所示，该移相器由有源巴伦、第一～第三差分放大电路、开关矩阵、RC正交网络和单刀双掷开关构成。
有源巴伦实现信号从单端到双端的转换，其中晶体管AF1和AF2的漏极采用电阻直接偏置，并且在两路输出端采用不对称结构以改善其平衡性，如图2中串联在AF1漏极的电容C1和电感L1以及串联在AF2漏极的电容C2和电感L2。AF1和AF2的源极相连，中间串联电阻R1和电感L0到地，实现差分管的自偏和有源巴伦差分性能的改善。
为了对输出信号进行波形整形和增益补偿，有源巴伦的两路信号输出端分别连接差分放大器的栅极，如图2中晶体管AF3和AF4的栅极。AF3和AF4的漏极同样采用电阻直接偏置方式，源级通过串联电阻R2和电感L0到地以实现差分管的自偏和较好的差分性能。输出端采用电容C3和电感L3串联结构实现宽带输出匹配。
单端信号通过有源巴伦及差分放大器后，得到幅度平衡和相位平衡均比较理想的一对差分信号。为实现180°移相，设计了如图3所示的开关矩阵。其中，开关管导通时等效为一个小电阻，截止时等效为一个小电容。当Vcon为高电平，
Figure PCTCN2020138542-appb-000001
为低电平时，信号从端口1经AF10和AF17至端口3，另一路信号从端口2经AF15和AF20至端口4；当Vcon为低电平，
Figure PCTCN2020138542-appb-000002
为高电平时，信号从端口1经AF11和AF19至端口4，另一路信号从端口2经AF14和AF18至端口 3。由此，通过对Vcon和
Figure PCTCN2020138542-appb-000003
的同步控制，实现了信号通路的互换，从而实现了180°移相。
在实现180°相移后，差分信号进入其后级级联的三阶RC正交网络，产生四路正交信号输出，如图4所示。其中，0°和-180°端口分别连接到AF5和AF6的栅极；-90°和-270°的端口分别连接到AF8和AF7的栅极。由AF5、AF6、C4、L4和R3组成后级差分放大器，由AF8、AF7、C4、L4和R3组成另一后级差分放大器。差分放大器的两个输出端口的其中之一接负载阻抗，另一端口接后级单刀双掷开关。通过对单刀双掷开关两条支路的选择实现90°移相，进而通过对开关矩阵及单刀双掷开关的共同控制，即可实现90°、180°和270°移相。
本发明2～18GHz超宽带两位移相器电路版图如图5所示，版图主要由GaAs PHEMT晶体管、微带线、电阻、电容、地孔、加电端口、射频端口组成。单端信号从信号输入端口1进入，通过有源巴伦2转化为差分信号输出，随后经匹配网络进入差分放大电路3，放大后进入双路进双路出的开关矩阵4，实现信号的180°相移。紧接着差分信号注入后级的RC网络5产生两对正交信号，两对信号分别进入差分放大器6进行波形整形和放大后再由最末端的单刀双掷开关7对通道进行选择，实现90°、180°和270°的相移，最后从信号输出端口8输出。第一～第四端口9、10、11、12为电路的加电和控制端口。
图6～图11为本发明2～18GHz超宽带两位移相器的实测曲线，图6为90°相移量曲线，图7为180°相移量曲线，图8是270°相移量曲线，图9～图11为基态和各移相态的S参数曲线。从图中可以看出，在2～18GHz频带内，该款移相器芯片的各个移相态的移相精度均小于5°，并且信号损耗小，具有移相精度高、工作带宽大的优点。

Claims (10)

  1. 一种超宽带两位移相器，其特征在于，包括有源巴伦、第一～第三差分放大器、开关矩阵、RC正交网络和单刀双掷开关，其中：
    所述有源巴伦接收单端信号，将单端信号转换为双端信号，两路输出端采用不对称结构，输出的两路信号分别连接至第一差分放大器的两个输入端；
    所述第一差分放大器对接收到的两路信号进行波形整形和增益补偿，并通过开关矩阵选择不同的支路以实现180°的相移；
    所述双端信号通过级联RC正交网络产生正交信号，RC正交网络的后级分别级联第二、第三差分放大器；
    所述单刀双掷开关选择第二、第三差分放大器不同的支路，产生90°相移步进量，从而实现90°、180°、270°三种移相量。
  2. 根据权利要求1所述的超宽带两位移相器，其特征在于，所述单端信号通过输入匹配网络传输至有源巴伦。
  3. 根据权利要求2所述的超宽带两位移相器，其特征在于，所述输入匹配网络包括第九串联电容(C9)、第九并联电感(L9)、第十串联电感(L10)和第五并联电阻(R5)；输入匹配网络的输入端至输出端顺次串联第九串联电容(C9)、第九并联电感(L9)，第九串联电容(C9)、第九并联电感(L9)的公共端通过第十串联电感(L10)接地；输入匹配网络的输出端一方面通过第五并联电阻(R5)接地，另一方面接入有源巴伦的输入端。
  4. 根据权利要求1、2或3所述的超宽带两位移相器，其特征在于，所述有源巴伦包括第十一电感(L11)、第一电阻(R1)、第一晶体管(AF1)、第二晶体管(AF2)、第一电容(C1)、第二电容(C2)、第一电感(L1)和第二电感(L2)；
    所述第一晶体管(AF1)和第二晶体管(AF2)的源极相连，公共端串联第一电阻(R1)和第十一电感(L11)到地；第一晶体管(AF1)的栅极与匹配网络的输出端相连，第二晶体管(AF2)的栅极接地；第一晶体管(AF1)的漏极串联第一电容(C1)、第一电感(L1)后作为有源巴伦的第一差分输出端口，第二晶体管(AF2)的漏极分别串联第二电容(C2)、第二电感(L2)后作为有源巴伦的第二差分输出端口。
  5. 根据权利要求4所述的超宽带两位移相器，其特征在于，所述第一差分放大器包括第三晶体管(AF3)、第四晶体管(AF4)、第三电容(C3)、第四电容(C4)、第三电感(L3)、第四电感(L4)、第二电阻(R2)和第十二电感(L12)；
    有源巴伦的第一差分输出端口连接到第一差分放大器的第三晶体管(AF3)栅极，第二差分输出端口连接到第一差分放大器的第四晶体管(AF4)栅极；
    所述第三晶体管(AF3)和第四晶体管(AF4)的源极相连，公共端串联第二电阻(R2)和第十二电感(L12)到地；第三晶体管(AF3)的漏极串联第三电阻(C3)、第三电感(L3)作为第一差分放大器的第一差分输出端口，第四晶体管(AF4)的漏极串联第四电阻(C4)、第四电感(L4)作为第一差分放大器的第二差分输出端口。
  6. 根据权利要求5所述的超宽带两位移相器，其特征在于，所述开关矩阵包括第九～第二十开关管(AF9)～(AF20)，其中第九～第十二开关管(AF9)～(AF12)依次串联，第十三～第十六开关管(AF13)～(AF16)依次串联；
    第九开关管(AF9)和第十开关管(AF10)的共同端通过一段微带连接到第十七开关管(AF17)的一端，第十七开关管(AF17)的另一端作为开关矩阵的第一输出端，并连接到第十 八开关管(AF18)的一端，第十八开关管(AF18)的另一端通过一段微带连接到第十三开关管(AF13)和第十四开关管(AF14)的共同端；第十五开关管(AF15)和第十六开关管(AF16)的共同端通过一段微带连接到第二十开关管(AF20)的一端，第二十开关管(AF20)的另一端作为开关矩阵的第二输出端，并连接到第十九开关管(AF19)的一端，第十九开关管(AF19)的另一端通过一段微带连接到第十一开关管(AF11)和第十二开关管(AF12)的共同端；第一差分放大器的第一差分输出端口连接第十开关管(AF10)和第十一开关管(AF11)的共同端，第一差分放大器的第二差分输出端口连接第十四开关管(AF14)和第十五开关管(AF15)的共同端。
  7. 根据权利要求5或6所述的超宽带两位移相器，其特征在于，所述第二差分放大器包括第五晶体管(AF5)、第六晶体管(AF6)、第五电阻(C5)、第六电阻(C6)、第五电感(L5)、第六电感(L6)和第三电阻(R3)；所述第三差分放大器包括第七晶体管(AF7)、第八晶体管(AF8)、第七电阻(C7)、第八电阻(C8)、第七电感(L7)、第八电感(L8)和第四电阻(R4)；
    所述RC正交网络的相位参考端和-180°端分别连接到第二差分放大器的第五晶体管(AF5)和第六晶体管(AF6)的栅极；-270°端和-90°端分别连接到第二差分放大器的第七晶体管(AF7)和第八晶体管(AF8)的栅极；
    所述第五晶体管(AF5)和第六晶体管(AF6)的源极相连，公共端串联第三电阻(R3)到地；第五晶体管(AF5)的漏极串联第五电阻(C5)、第五电感(L5)作为第二差分放大器的第一差分输出端口，第六晶体管(AF6)的漏极分别串联第六电阻(C6)、第六电感(L6)作为第二差分放大器的第二差分输出端口；第二差分放大器的第一差分输出端口连接到第一50欧姆负载(RL1)，第二差分放大器的第二差分输出端口连接到后级单刀双掷开关的一条支路上；
    所述第七晶体管(AF7)和第八晶体管(AF8)的源极相连，公共端串联第四电阻(R4)到地；第七晶体管(AF7)的漏极串联第七电阻(C7)、第七电感(L7)作为第三差分放大器的第二差分输出端口，第八晶体管(AF8)的漏极串联第八电阻(C8)、第八电感(L8)作为第三差分放大器的第一差分输出端口，第三差分放大器的第一差分输出端口连接到第二50欧姆负载(RL2)，第三差分放大器的第二差分输出端口连接到后级单刀双掷开关的另一条支路上。
  8. 根据权利要求6所述的超宽带两位移相器，其特征在于，所述第九开关管(AF9)、第十一开关管(AF11)、第十四开关管(AF14)、第十六开关管(AF16)、第十八开关管(AF18)、第十九开关管(AF19)的控制电平相同；第十开关管(AF10)、第十二开关管(AF12)、第十三开关管(AF13)、第十五开关管(AF15)、第十七开关管(AF17)、第二十开关管(AF20)的控制电平相同，并与第九开关管(AF9)、第十一开关管(AF11)、第十四开关管(AF14)、第十六开关管(AF16)、第十八开关管(AF18)、第十九开关管(AF19)的控制电平相反。
  9. 根据权利要求8所述的超宽带两位移相器，其特征在于，通过控制所述第九开关管～第二十开关管(AF9～AF20)的导通与截止，实现180°移相。
  10. 根据权利要求8或9所述的超宽带两位移相器，其特征在于，通过控制所述单刀双掷开关两条支路的导通与截止，实现90°移相。
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