WO2021128874A1

WO2021128874A1 - Internal memory interface write-leveling control method and device

Info

Publication number: WO2021128874A1
Application number: PCT/CN2020/109396
Authority: WO
Inventors: 叶佳星; 傅祥; 欧阳志光
Original assignee: 晶晨半导体(上海)股份有限公司
Priority date: 2019-12-25
Filing date: 2020-08-14
Publication date: 2021-07-01
Also published as: CN111190540A; CN111190540B

Abstract

Provided are an internal memory interface write-leveling control method and device, belonging to the technical field of communications. In the internal memory interface write-leveling control method and device, during the process of controlling a sampling signal to be sent to an internal memory device at a preset delay step, on the basis of the effective level of the sampling signal corresponding to each delay step, sampling information of a first preset length is generated; the sampling information is analyzed, and a write-leveling phase value of the sampling signal is determined according to the location of the region where the sum of the effective levels in the sampling information is the largest, thus sampling errors caused by jitter, noise, and other interference in the sampling process are shielded, and the optimal delay position of the sampling signal is determined, and adaptability is strong.

Description

Control method and device for writing balance of memory interface

Technical field

The present invention relates to the field of communication technology, and in particular to a method and device for controlling write balance of a memory interface.

Background technique

Write leveling is an indicator established by the Electronics Industry Association (JEDEC). The so-called write balance means that the sampling data clock in the data sending and writing direction and the DRAM (Dynamic Random Access Memory) external bus working clock must be in the same phase state (for example, the tDQSS indicator in the DDR4 standard JEDEC79-4B), so that the data is being written When entering, the sampling clock and data in the memory can be aligned with the bus working clock, so as to ensure that the DDR (Double Data Rate) memory can write data correctly.

At present, in the production process of the product, in order to achieve the indicator of write balance, the best value obtained (such as sampling data clock) can only be used for a single application scenario, and cannot adapt to different board-level wiring styles, shielding jitter, noise, etc. Interference causes delay differences, and the application scenarios have strong limitations. Since the write balance training precedes other read and write training, if the wrong optimal value is obtained, it will cause errors in the training of other parameters of the later stage, which will affect the subsequent read and write process of the entire DDR interface, and eventually lead to read and write failures.

Summary of the invention

In view of the problem that the existing write equalization training is susceptible to interference from jitter, noise, etc., a memory interface write equalization control method and device aiming at strong adaptive ability and shielding interference from jitter, noise, etc. is provided.

The present invention provides a method for controlling write balance of a memory interface, which includes:

Send the sampling signal to the memory device with a preset delay step;

Generating sampling information of a first preset length according to the effective level of the sampling signal corresponding to each delay step;

Acquiring the location of the area where the sum of the effective levels in the sampling information is the largest;

The write equalization delay step of the sampling signal is determined according to the location of the region.

Preferably, sending the sampling signal to the memory device at a preset delay step includes:

Starting from the initial position of the sampling signal, each time a preset delay step is increased, the sampling signal is sent to the memory device until the delay step reaches a second preset length.

Preferably, generating the sampling information of the first preset length according to the effective level of the sampling signal corresponding to each delay step includes:

Sampling the sampling signal corresponding to each delay step N times to obtain the level value of each sampling; where N is an odd number;

In N samplings, accumulate the sampling times of the same level value, and use the level value corresponding to the accumulated sampling times greater than (N-1)/2 as the effective level;

Combining the effective levels of the sampling signals corresponding to each of the delay steps according to the sequence of the delay steps to generate the sampling information of the first preset length.

Preferably, obtaining the location of the area where the sum of the effective levels in the sampling information is the largest includes:

Acquire the area position where the sum of the effective levels of the third preset length is the largest in the sampling information.

Preferably, determining the write equalization delay step of the sampling signal according to the location of the region includes:

The area position is an area position where the starting point is an effective level of 1, and the write equalization phase value of the sampling signal is obtained according to the delay step of the sampling signal corresponding to the starting point of the area position.

The present invention also provides a control device for writing balance of a memory interface, including:

The control unit is used to send the sampling signal to the memory device with a preset delay step;

A generating unit, configured to generate sampling information of a first preset length according to the effective level of the sampling signal corresponding to each delay step;

An acquiring unit, configured to acquire the location of the area where the sum of the effective levels in the sampling information is the largest;

The determining unit is configured to determine the write equalization delay step of the sampling signal according to the location of the region.

Preferably, the control unit is configured to start from the initial position of the sampling signal, each time a preset delay step is increased, and send the sampling signal to the memory device until the delay step reaches the second preset length.

Preferably, the generating unit includes:

The sampling module is used to sample the sampling signal corresponding to each delay step N times to obtain the level value of each sampling; where N is an odd number;

The processing module is used to accumulate the sampling times of the same level value in N sampling times, and use the level value corresponding to the accumulated sampling times greater than (N-1)/2 as the effective level;

The combination module is configured to combine the effective level of the sampling signal corresponding to each delay step according to the sequence of the delay step to generate the sampling information of the first preset length.

Preferably, the acquiring unit is configured to acquire, in the sampling information, the location of the area where the sum of the effective levels of the third preset length is the largest.

Preferably, the determining unit is configured to obtain the write equalization phase value of the sampling signal according to the delay step of the sampling signal corresponding to the starting point of the area position; the area position being the starting point is valid The location of the area where the level is 1.

The beneficial effects of the above technical solutions:

In this technical solution, the memory interface write equalization control method and device, in the process of controlling the sampling signal to be sent to the memory device at a preset delay step, based on the effective level of the sampling signal corresponding to each delay step , Generate the sampling information of the first preset length; analyze the sampling information, and determine the write equalization phase value of the sampling signal according to the location of the area where the sum of the effective levels in the sampling information is the largest, so as to shield the sampling process due to jitter and noise Wait for the sampling error caused by interference, and then determine the best delay position of the sampled signal, with strong adaptability.

Description of the drawings

FIG. 1 is a flowchart of an embodiment of a method for controlling write balance of a memory interface according to the present invention;

2 is a flowchart of an embodiment of generating sampling information according to the effective level of the sampling signal according to the present invention;

FIG. 3 is a block diagram of an embodiment of the control device for writing balance of a memory interface according to the present invention;

Fig. 4 is a block diagram inside the generating unit of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

The data acquisition method defined by JEDEC for the write equalization algorithm is: DRAM enters the specified DRAM write equalization training mode by configuring the mode register of DRAM, and then DRAM automatically uses the rising edge of the data sampling clock (write dqs) to correct the system bus clock (clk). ) Sampling, the voltage level sampled is fed back and output from the data line (dq).

The general algorithm in the industry is: increase the delay phase of the data sampling clock through continuous linear adjustment, until the final sampled level on the data line changes from a low level to a high level for the first time, that is, the data sampling clock and the system bus The clock reaches the same rising edge phase, so that the optimal phase value of the sampling clock for writing the balanced data is obtained.

However, in actual situations, the method of increasing the delay phase of the data sampling clock by linear adjustment is only suitable for situations where the waveform quality is very good. Since signal acquisition requires a certain signal retention time and signal retention threshold level, when the waveform quality is better and the signal rises and falls faster, the acquired signal is correct. But when the signal begins to deteriorate, the collected signal is very error-tolerant; for the differences in PCB (printed circuit board) design, the board-level signals are different, so the system bus clock signal is prone to have a slow slope or collapse caused by signal reflection. The signal is also very error-tolerant.

Since signal acquisition requires a certain signal retention time and signal retention threshold level, when the quality of the waveform begins to deteriorate, it is easy to make a level metastable judgment error. When the data sampling clock waveform is not good due to the entire signal transmission path, a signal step will occur. Phenomenon, it may lead to the process of sampling the rising edge of the wrong small step. When the signal rise and fall rate is relatively slow, there may even be a situation where the falling edge is incorrectly collected as a rising edge. The false acquisition of the falling edge as the rising edge is mainly because the amplitude of the data sampling clock relative to the reference level of the comparator is not large enough when the falling edge of the falling edge crosses the intermediate level, and the threshold level is not fully reached, and the metastable state occurs, so it is easy Data output errors due to noise interference will lead to edge judgment errors.

In order to solve the defect of incorrect sampling caused by the step, collapse and metastable state of the sampled signal, the present invention proposes a method that can avoid the influence of step, collapse and metastable state on sampling, can be applied to different scenarios, and can A control method and device for memory interface writing equalization that ensure the accuracy of the sampled signal. The present invention will be further described below in conjunction with the drawings and specific embodiments, but it is not a limitation of the present invention. Referring to FIG. 1, it is a schematic flow chart of a method for controlling write balance of a memory interface according to a preferred embodiment of the present invention. As can be seen from the figure, the method for controlling write balance of a memory interface provided in this embodiment mainly It includes the following steps:

S1. Send the sampling signal to the memory device with a preset delay step;

In this embodiment, the memory device may be a dynamic random access memory, or a double-rate synchronous dynamic random access memory.

The sampling signal in this embodiment is a signal that the data sampling clock (dqs) reaches the memory device.

Further, step S1 includes:

In this embodiment, the second preset length is greater than the cycle length CLK of the sampling signal. For example, the second preset length may be 1.5 CLK cycles, or 2 CLK cycles.

Specifically, the preset delay step is 1/64CLK cycle length, the second preset length is 2 CLK cycles, and the delay step of the sampling signal is gradually increased, and a total of 128 rounds of data are collected to realize the coverage of 2 CLKs. Periodic sampling signal. Theoretically corresponding to the analysis of the standard waveform, a high-level pulse can be collected within 1.5 CLK cycles. Considering the possible jitter of the sampled signal, the extension length is appropriate and the second preset length is set to 2 CLK Period to facilitate subsequent analysis of the sampled signal.

S2. Generate sampling information of a first preset length according to the effective level of the sampling signal corresponding to each delay step;

In this embodiment, the first preset length may be 2 CLK cycles.

With reference to FIG. 2 further, step S2 may include:

S21. Sampling the sampling signal corresponding to each delay step N times to obtain the level value of each sampling; where N is an odd number (for example: N=3,5,7,9, etc.);

S22. In N samplings, accumulate the sampling times of the same level value, and use the level value corresponding to the accumulated sampling times greater than (N-1)/2 as the effective level;

S23. Combine the effective levels of the sampling signals corresponding to each of the delay steps according to the sequence of the delay steps to generate the sampling information of the first preset length.

Specifically, taking N=9 as an example, each delay step is sampled 9 times, and the level value of each sample is recorded. If the number of 0 (low level) in 9 samples is greater than (9 -1)/2=4, the corresponding effective level value of the corresponding delay step is 0; if the number of 1 (high level) in 9 samples is greater than 4, the corresponding delay step corresponds to The effective level value is 1. The effective level corresponding to each delay step is combined according to the sequence of the delay step, so as to obtain the sampling information of the length of 2 CLK cycles.

In step S2, multiple sampling is performed for each delay step, and a level value with a high probability is extracted as an effective level, so as to avoid affecting the accuracy of the sampling signal due to poor waveform quality.

S3. Obtain the location of the area where the sum of the effective levels in the sampling information is the largest;

Specifically, step S3 is to obtain, in the sampling information, the position of the area where the sum of the effective levels of the third preset length is the largest.

Wherein, the third preset length is 0.5 CLK cycle length.

In this embodiment, considering that the purpose of write equalization is to align the rising edge of the data sampling clock with the rising edge of the system bus clock, it is equivalent to the larger the number of valid level 1 in the sampling information, the more the data sampling clock The higher the probability that the rising edge of is aligned with the rising edge of the system bus clock. Therefore, starting from the initial effective level of the sampling information, traverse 0.5 CLK cycles in sequence, traversing one by one, and extract the location of the region with the largest sum of the first effective levels (0.5 CLK cycle length), and obtain the validity through statistical methods. The position where the sum of the levels is the largest, so as to extract the interference of the metastable state on the sampled signal.

S4. Determine the write equalization delay step of the sampling signal according to the location of the region.

Further, in step S4, the region position is the region position whose starting point is the effective level of 1, and the writing of the sample signal is obtained according to the delay step of the sampling signal corresponding to the starting point of the region position. Enter the balanced phase value.

In step S4, the area position is the starting point or the area position where the effective level is 0.

In this embodiment, in the process of controlling the sampling signal to be sent to the memory device at a preset delay step, the sampling information of the first preset length is generated based on the effective level of the sampling signal corresponding to each delay step; Analyze the sampling information, and determine the write equalization phase value of the sampling signal according to the location of the area where the sum of the effective levels in the sampling information is the largest, so as to shield the sampling error caused by jitter, noise and other interference during the sampling process, and then determine the sampling signal The best time delay position, strong adaptability.

The control method of memory interface write balance can automatically adapt to the delay difference caused by different board-level wiring styles and automatically eliminate noise. It can be widely used in different DDR standards (such as: DDR3, DDR4, LPDDR3, LPDDR4, etc.), with Efficient, accurate, and self-adaptive.

As shown in Figures 3 to 4, the present invention also provides a memory interface write equalization control device 1 which may include: a control unit 11, a generation unit 12, an acquisition unit 13, and a determination unit 14;

The control unit 11 is configured to send the sampling signal to the memory device in a preset delay step;

The control unit 11 is configured to start from the initial position of the sampling signal, each time a preset delay step is increased, and send the sampling signal to the memory device until the delay step reaches a second preset length.

The generating unit 12 is configured to generate sampling information of a first preset length according to the effective level of the sampling signal corresponding to each delay step;

In this embodiment, the first preset length may be 2 CLK cycles.

Further referring to FIG. 4, the generating unit 12 may include: a sampling module 121, a processing module 122, and a combining module 123;

The sampling module 121 is used for sampling the sampling signal corresponding to each delay step N times to obtain the level value of each sampling; where N is an odd number (for example: N=3,5,7,9, etc.) ；

The processing module 122 is configured to accumulate the sampling times of the same level value in N sampling times, and use the level value corresponding to the accumulated sampling times greater than (N-1)/2 as the effective level;

The combination module 123 is configured to combine the effective levels of the sampling signals corresponding to each of the delay steps according to the sequence of the delay steps to generate the first preset length of sampling information.

In this embodiment, by sampling each delay step multiple times, a level value with a high probability is extracted as an effective level, so as to avoid affecting the accuracy of the sampled signal when the waveform quality is not good.

The acquiring unit 13 is configured to acquire the location of the area where the sum of the effective levels in the sampling information is the largest;

The acquiring unit 13 is configured to acquire, from the sampling information, the location of the area where the sum of the effective levels of the third preset length is the largest.

Wherein, the third preset length is 0.5 CLK cycle length.

The determining unit 14 is configured to determine the write equalization delay step of the sampling signal according to the location of the region.

The determining unit 14 is configured to obtain the write equalization phase value of the sampling signal according to the delay step of the sampling signal corresponding to the starting point of the area position; the area position is the starting point and the effective level Is the area position of 1.

In this embodiment, the area position is the starting point or the area position where the effective level is zero.

The invention can adapt to different PCB design styles at the same time, adapt to the delay difference caused by the data sampling clock and the bus clock caused by different routing, and can also resist the distortion of the routing signal very well, which greatly simplifies the PCB routing design. Pressure, and can maximize the satisfaction of the write equalization index parameters defined by JEDEC, so that the relevant front-end performance and stability and reliability of the DDR system are stabilized.

The foregoing descriptions are only preferred embodiments of the present invention, and do not limit the implementation and protection scope of the present invention. For those skilled in the art, they should be able to realize that all equivalents made using the description and illustrations of the present invention are equivalent. The solutions obtained by substitutions and obvious changes should all be included in the protection scope of the present invention.

Claims

A method for controlling write balance of a memory interface, which is characterized in that it comprises:

Send the sampling signal to the memory device with a preset delay step;

Generating sampling information of a first preset length according to the effective level of the sampling signal corresponding to each delay step;

Acquiring the location of the area where the sum of the effective levels in the sampling information is the largest;

The write equalization phase value of the sampling signal is determined according to the location of the region.
The method for controlling write equalization of a memory interface according to claim 1, wherein sending the sampling signal to the memory device at a preset delay step comprises:

Starting from the initial position of the sampling signal, each time a preset delay step is increased, the sampling signal is sent to the memory device until the delay step reaches a second preset length.
The method for controlling write equalization of a memory interface according to claim 1, wherein generating the sampling information of the first preset length according to the effective level of the sampling signal corresponding to each delay step comprises:

Sampling the sampling signal corresponding to each delay step N times to obtain the level value of each sampling; where N is an odd number;

In N sampling, accumulate the sampling times of the same level value, and use the level value corresponding to the accumulated sampling times greater than (N-1)/2 as the effective level;

Combining the effective levels of the sampling signals corresponding to each of the delay steps according to the sequence of the delay steps to generate the sampling information of the first preset length.
The method for controlling write equalization of a memory interface according to claim 1, wherein obtaining the location of the region with the largest sum of effective levels in the sampling information comprises:

Acquire the area position where the sum of the effective levels of the third preset length is the largest in the sampling information.
The method for controlling write equalization of a memory interface according to claim 1, wherein determining the write equalization phase value of the sampling signal according to the location of the region comprises:

The area position is an area position where the starting point is an effective level of 1, and the write equalization phase value of the sampling signal is obtained according to the delay step of the sampling signal corresponding to the starting point of the area position.
A control device for writing balance of a memory interface, which is characterized in that it comprises:

The control unit is used to send the sampling signal to the memory device with a preset delay step;

A generating unit, configured to generate sampling information of a first preset length according to the effective level of the sampling signal corresponding to each delay step;

An acquiring unit, configured to acquire the location of the area where the sum of the effective levels in the sampling information is the largest;

The determining unit is configured to determine the write equalization phase value of the sampling signal according to the location of the region.
The control device for writing equalization of a memory interface according to claim 6, wherein the control unit is used to start from the initial position of the sampling signal, each time a preset delay step is increased, and the The sampling signal is sent to the memory device until the delay step reaches the second preset length.
The device for controlling write equalization of a memory interface according to claim 6, wherein the generating unit comprises:

The sampling module is used to sample the sampling signal corresponding to each delay step N times to obtain the level value of each sampling; where N is an odd number;

The processing module is used to accumulate the sampling times of the same level value in N sampling times, and use the level value corresponding to the accumulated sampling times greater than (N-1)/2 as the effective level;

The combination module is configured to combine the effective levels of the sampling signals corresponding to each of the delay steps according to the sequence of the delay steps to generate the sampling information of the first preset length.
7. The control device for write equalization of a memory interface according to claim 6, wherein the acquiring unit is configured to acquire, from the sampling information, the location of the region where the sum of the effective levels of the third preset length is the largest.
The control device for writing equalization of a memory interface according to claim 6, wherein the determining unit is configured to obtain the sample according to the delay step of the sample signal corresponding to the starting point of the region position The write-in equalization phase value of the signal; the area position is the area position where the starting point is the effective level of 1.