WO2021128639A1

WO2021128639A1 - Array substrate, display panel, and electrical test method

Info

Publication number: WO2021128639A1
Application number: PCT/CN2020/082720
Authority: WO
Inventors: 安喜锋; 潘鹏鹏
Original assignee: 武汉华星光电技术有限公司
Priority date: 2019-12-23
Filing date: 2020-04-01
Publication date: 2021-07-01
Also published as: CN111048020A; CN111048020B

Abstract

An array substrate (10), a display panel (1), and an electrical test method. The array substrate (10) comprises: a substrate (100), comprising a display area (1001) and an electrical test area (1002); a thin film transistor layer, which is disposed on the substrate (100) and which comprises a test thin film transistor (900) disposed in the electrical test area (1002), wherein the test thin film transistor (900) comprises an active layer (104), a gate layer (106), and an electrode layer (109, 116), one end of the active layer (104) is connected to a first electrode (109) of the electrode layer (109, 116), and the other end of the active layer (104) is suspended; a planarization layer (110), which is disposed on the electrode layer (109, 116) of the thin film transistor, a first via (114) being disposed at the first electrode (109) of the electrode layer (109, 116) corresponding to the planarization layer (110); and a common electrode layer (111), which is disposed on a side of the planarization layer (110) away from the electrode layer (109, 116) and which is connected, by means of the first via (114), to the first electrode (109) of the electrode layer (109, 116).

Description

Array substrate, display panel, and electrical testing method

Technical field

This application relates to the field of display technology, and specifically to an array substrate, a display panel, and an electrical test method for the array substrate.

Background technique

With the gradual popularity of low temperature poly-silicon (LTPS) liquid crystal display panels, the circuit design of the thin film transistor layer has become more and more refined, and the pixel density (pixels per inch, PPI) of small-sized panels has gradually increased. LTPS liquid crystal The display panel needs to undergo multiple manufacturing processes in the array substrate manufacturing process. During the manufacturing process, a dummy thin-film transistor (dummy thin-film transistor) exists at the outermost periphery of the thin-film transistor layer. transistors), only as a reference boundary when printing polyimide (PI) film, and does not play a display role.

technical problem

When the gate insulator (GI) film of the outermost dummy thin-film transistors (dummy thin-film transistors) falls off between the gate layer and the active layer, the gate layer and the active layer will Electricity leakage due to short circuit causes horizontal line-shaped abnormalities on the display screen. However, due to the limitation of the capabilities of the electrical testing machine itself, it is impossible to detect the area at a distance of about five pixels on the left and right sides of the panel. Therefore, the problem cannot be detected by the electrical testing machine immediately after the thin film transistor manufacturing process is completed. Waste.

Technical solutions

The purpose of this application is to provide an array substrate, a display panel, and an electrical test method. The common electrode layer of the outermost thin film transistor of the array substrate is designed without openings, which can improve the gate of the outermost thin film transistor. The abnormal detection rate of leakage between the electrode layer and the active layer due to a short circuit.

In order to achieve the above objective, this application proposes an array substrate, including: a substrate including a display area and an electrical test area; a thin film transistor layer provided on the substrate, and the thin film transistor layer includes a thin film transistor layer provided on the electrical test area; Area of the test thin film transistor, wherein the test thin film transistor includes an active layer, a gate layer, and an electrode layer, one end of the active layer is connected to the first electrode of the electrode layer, and the active layer The other end is suspended, that is, not connected to the second electrode of the electrode layer; the planarization layer is provided on the electrode layer of the thin film transistor, wherein the planarization layer corresponds to the first electrode of the electrode layer A first via is provided; a common electrode layer is provided on a side of the planarization layer away from the electrode layer, and the common electrode layer is connected to the first electrode of the electrode layer through the first via.

The active layer may be amorphous silicon, low-temperature polysilicon, or organic semiconductor. Wherein, when a short-circuit occurs between the gate layer located in the electrical test area and the active layer, the current from the gate layer is conducted through the active layer and the first electrode of the test thin film transistor To the common electrode layer, and raise the voltage of the common electrode layer in the electrical test area.

Preferably, the electrode layer of the test thin film transistor further includes a second electrode, wherein the second electrode is suspended, that is, not connected to one end of the active layer.

Preferably, the test thin film transistor further includes an insulating protection layer, the insulating protection layer is disposed on the surface of the common electrode layer away from the common electrode layer, and a second electrode layer, the second electrode layer is disposed on the surface of the common electrode layer. On the insulating protection layer, the second electrode layer is connected to the electrode layer through a via hole in the display area to form a pixel electrode.

Preferably, the test thin film transistor further includes an interlayer dielectric layer disposed between the active layer and the electrode layer, wherein the interlayer dielectric layer is provided with a second via hole, and the The first electrode is connected to one end of the active layer through the second via hole.

Preferably, the gate layer of the test thin film transistor is provided between the active layer and the electrode layer, wherein a gate insulating layer is provided between the gate layer and the active layer, The second via hole penetrates the interlayer dielectric layer and the gate insulating layer.

Preferably, the gate layer of the test thin film transistor is provided on the surface of the active layer on the side away from the electrode layer, wherein a gate insulating layer is provided between the gate layer and the active layer , The second via hole penetrates the interlayer dielectric layer.

Preferably, the common electrode layer and the second electrode layer are composed of indium tin oxide.

The present application additionally provides a display panel, including the aforementioned array substrate, and further including a color filter substrate disposed opposite to the array substrate, wherein a third surface of the color filter substrate close to the array substrate is provided. The electrode layer, wherein the common electrode layer is connected to the third electrode layer.

The present application additionally provides an electrical test method for the aforementioned display panel, including: providing the array substrate; energizing the array substrate; performing electrical test on a plurality of block-shaped common electrodes in the electrical test area. Test to obtain multiple sets of voltage values; confirm whether there are abnormal values among the multiple sets of voltage values, the abnormal values can be defined as 1-3 standard deviations higher than the average of the multiple sets of voltage values, for example And if an abnormal value occurs in any of the plurality of sets of voltage values, it is determined that the array substrate is abnormal.

Beneficial effect

Through the design of the array substrate of the embodiment of this application, when the outermost periphery is thin

When the gate insulator thin film at the film transistor falls off between the gate layer and the active layer, the gate layer and the active layer are short-circuited to cause leakage, and the first electrode leaks to the common electrode layer, This causes the bulk common electrode layer voltage to rise, so it can be detected by the electrical testing machine in advance. The poor display of the module segment caused by the short circuit between the gate electrode line and the active layer of the test thin film transistor was reduced from 1.1% to 0%.

Description of the drawings

FIG. 1 is a schematic top view of an array substrate according to an embodiment of the application;

2 is a schematic cross-sectional view of an electrical test area of an array substrate according to an embodiment of the application;

FIG. 3 is a schematic diagram of a display panel according to an embodiment of the application; and

FIG. 4 is a flowchart of a method for electrical testing of an array substrate according to an embodiment of the application.

Embodiments of the present invention

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that can be implemented in the present application. The directional terms mentioned in this application, such as [Up], [Down], [Front], [Back], [Left], [Right], [Inner], [Outer], [Side], etc., are for reference only The direction of the additional schema. Therefore, the directional terms used are used to illustrate and understand the application, rather than to limit the application.

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of this application.

In the conventional array substrate, there is a dummy TFT on the outermost periphery, and the common electrode layer is disconnected near the upper via hole where the second electrode layer meets the first electrode, and is not connected to the first electrode. When an electrode is connected, when the gate insulator film at the place falls off between the gate traces and the active layer, it will cause a short circuit between the gate layer and the active layer, resulting in leakage. After the group is completed, a horizontal line-shaped display abnormality will appear in the display screen, but it cannot be detected in advance by the electrical testing machine when the thin film transistor side process is completed. In response to this problem, the common electrode layer of the Dummy TFT is designed to facilitate the early detection of the electrical test machine and avoid losses in the module stage.

Please refer to FIG. 1, which is a schematic top view of an array substrate according to an embodiment of the application, including a display area 1001 and an electrical test area 1002, wherein the second electrode layer 113 and the common electrode layer 111 (a And refer to Figure 2) Not drilled.

Please refer to FIG. 2, which is a schematic cross-sectional view of an electrical test area of an array substrate according to an embodiment of the application. The array substrate includes:

The glass substrate 100; the light shielding layer 101 provided on the glass substrate 100; the thin film transistor layer is provided on the glass substrate 100, and the thin film transistor layer includes a test thin film transistor 900 (please 1), wherein the test thin film transistor 900 includes an active layer 104, a gate layer 106, and an electrode layer (109, 116). The electrode layer (109, 116) is, for example, a source electrode and a drain electrode. An electrode layer, one end of the active layer 104 is connected to the first electrode 109 of the electrode layer, and the other end of the active layer 104 is suspended, that is, it is not connected to the second electrode 116 of the electrode layer; The planarization layer 110 is provided on the electrode layers (109, 116) of the thin film transistor, wherein the planarization layer 110 is provided with a first via 114 corresponding to the first electrode 109 of the electrode layer; a common electrode layer 111. Located on the side of the planarization layer 110 away from the electrode layers (109, 116), the common electrode layer 111 is connected to the first electrode 109 of the electrode layer through the first via 114. Wherein, when the gate layer 106 and the active layer 104 in the electrical test area 1002 are short-circuited, the current from the gate layer 106 is conducted to the common electrode layer through the active layer 104 and the first electrode 109 of the test thin film transistor. 111, and the voltage of the common electrode layer 111 in the electrical test area 1002 is increased.

In a specific embodiment, the electrode layer of the test thin film transistor 900 further includes a second electrode 116, wherein the second electrode 116 is suspended, that is, not connected to the active layer 104.

In a specific embodiment, the test thin film transistor 900 further includes an insulating protection layer 112 disposed on the surface of the common electrode layer 111 away from the common electrode layer 111, and a second electrode layer 113. The second electrode layer 113 is disposed on the insulating protection layer 112; the second electrode layer 113 is connected to the electrode layers (109, 116) in the display area 1001 through via holes to form a pixel electrode.

In a specific embodiment, the test thin film transistor 900 further includes an interlayer dielectric layer 107 composed of silicon nitride and a silicon layer between the active layer 104 and the electrode layer (109, 116). The interlayer dielectric layer 108 composed of oxide, wherein the interlayer dielectric layer (107, 108) is provided with a second via 115, and the first electrode 109 passes through the second via 115 and the One end of the active layer 104 is connected.

In a specific embodiment, the gate layer 106 of the test thin film transistor 900 is disposed between the active layer 104 and the electrode layer (109, 116), wherein the gate layer 106 is connected to the active layer (109, 116). A gate insulating layer 105 composed of silicon oxide is also provided between the source layer 104, and the second via 115 penetrates the interlayer dielectric layer (107, 108) and the gate insulating layer 105.

In a specific embodiment, the gate layer 106 of the test thin film transistor 900 is provided on the surface of the active layer 104 on the side away from the electrode layer (109, 116), wherein the gate layer 106 and the A gate insulating layer 105 is provided between the active layer 104, and the second via 115 penetrates the interlayer dielectric layer (107, 108).

In a specific embodiment, the common electrode layer 111 and the second electrode layer 113 are composed of indium tin oxide.

FIG. 3 is a schematic diagram of a display panel 1 according to an embodiment of the application, including:

As mentioned above, the array substrate 10 further includes a color filter substrate 20 disposed opposite to the array substrate 10, wherein a third electrode layer is provided on the surface of the color filter substrate 20 close to the side of the array substrate 10 201, wherein the common electrode layer 111 is connected to the third electrode layer 201.

As shown in FIG. 4, it is a flowchart of a method for performing electrical testing on an array substrate according to an embodiment of the application, and the method includes:

Provide an array substrate; energize the array substrate; conduct an electrical test on a plurality of block-shaped common electrical levels in the electrical test area to obtain multiple sets of voltage values; confirm that there are any of the multiple sets of voltage values No abnormal value occurs. The abnormal value can be defined as, for example, 2 standard deviations higher than the average value of the plurality of sets of voltage values; and if any of the plurality of sets of voltage values has an abnormal value, it is determined that the The array substrate is abnormal.

Through the design of the array substrate of the embodiment of the present application, when the gate insulator film at the outermost thin film transistor falls off between the gate layer 106 and the active layer 104, because the gate layer 106 and the active layer 104 is short-circuited and leaked, and leaks to the common electrode layer 111 through the first electrode 109, causing the bulk common electrode layer 111 to increase in voltage, so it can be detected by the electrical testing machine in advance. The poor display of the module segment caused by the short circuit between the gate electrode line and the active layer of the test thin film transistor was reduced from 1.1% to 0%.

In summary, although the application has been disclosed as above in preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the application, and those of ordinary skill in the art can make various decisions without departing from the spirit and scope of the application. Such changes and modifications, so the protection scope of this application is subject to the scope defined by the claims.

Claims

An array substrate, including:

Substrate, including display area and electrical test area;

The thin film transistor layer is arranged on the substrate, and the thin film transistor

The layer includes a test thin film transistor provided in the electrical test area, wherein the test thin film transistor includes an active layer, a gate layer, and an electrode layer, one end of the active layer and the first electrode layer The electrodes are connected, and the other end of the active layer is suspended;

The planarization layer is arranged on the electrode layer of the thin film transistor, wherein

The planarization layer is provided with a first via hole corresponding to the first electrode of the electrode layer;

The common electrode layer is provided on the planarization layer away from the electrode layer

On one side, the common electrode layer is connected to the first electrode of the electrode layer through the first via hole.
5. The array substrate of claim 1, wherein when located in the electrical

When a short circuit occurs between the gate layer of the test area and the active layer, the current from the gate layer is conducted to the common electrode layer via the active layer and the first electrode of the test thin film transistor, and The voltage of the common electrode layer in the electrical test area is increased.
The array substrate of claim 1 or 2, wherein the test thin

The electrode layer of the film transistor further includes a second electrode, wherein the second electrode is suspended.
The array substrate of claim 1, wherein the test thin film crystal

The body tube further includes an insulating protection layer provided on the surface of the common electrode layer away from the common electrode layer, and a second electrode layer, the second electrode layer being provided on the insulating protection layer.
The array substrate of claim 1, wherein the test thin film crystal

The body tube further includes an interlayer dielectric layer disposed between the active layer and the electrode layer, wherein the interlayer dielectric layer is provided with a second via hole, and the first electrode passes through the first Two via holes are connected to one end of the active layer.
The array substrate of claim 5, wherein the test thin film crystal

The gate layer of the body tube is provided between the active layer and the electrode layer, wherein a gate insulating layer is provided between the gate layer and the active layer, and the second via hole penetrates The interlayer dielectric layer and the gate insulating layer.
The array substrate of claim 5, wherein the test thin film crystal

The gate layer of the body tube is provided on the surface of the active layer away from the electrode layer, wherein a gate insulating layer is provided between the gate layer and the active layer, and the second via hole Through the interlayer dielectric layer.
The array substrate of claim 4, wherein the common electrode layer

And the second electrode layer is composed of indium tin oxide.
A display panel, comprising the array substrate according to claim 1,

It also includes a color filter substrate disposed opposite to the array substrate, wherein a third electrode layer is provided on the surface of the color filter substrate close to the side of the array substrate, wherein the common electrode layer and the third electrode layer The electrode layer is connected.
An electrical test for the display panel of claim 9

Methods, including:

Providing the array substrate;

Energize the array substrate;

Performing electrical testing on multiple common electrodes in the electrical testing area to obtain multiple sets of voltage values;

Confirm whether there is any abnormal value among the multiple sets of voltage values; and

If an abnormal value occurs in any one of the multiple sets of voltage values, it is determined that the array substrate is abnormal.