WO2021128159A1

WO2021128159A1 - Synchronization detection method and device

Info

Publication number: WO2021128159A1
Application number: PCT/CN2019/128652
Authority: WO
Inventors: 芦嘉; 张建功; 马鹤鸣; 滑福宁; 付佳彬
Original assignee: 哈尔滨海能达科技有限公司
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2021-07-01

Abstract

Provided by the present invention are a synchronization detection method and device. The method comprises: acquiring a synchronization code in a frame signal and determining a reference synchronization code and a calibration synchronization code; and determining a start position of the frame signal by using frame synchronization detection. Clock calibration and/or carrier frequency calibration are performed on the basis of the reference synchronization code and the calibration synchronization code. During the clock calibration process, by means of selecting a calibration clock that has the optimal synchronization performance in a preset calibration clock interval as a calibration clock of the frame signal, an accumulative clock error inside of the frame signal is calibrated, so that the problem of erroneous determination caused by the accumulative clock error may be solved. During the carrier frequency calibration process, synchronization codes distributed in different positions of the frame signal are used to obtain carrier frequency sampling points at different positions of the frame signal, and the obtained carrier frequency sampling points are used to predict or fit the change trend of the carrier frequency of the entire frame signal, so that the problem of degraded determination performance caused by frequency drift within the frame may be solved.

Description

Synchronous detection method and device

Technical field

The present invention belongs to the field of communication technology, and in particular, relates to a synchronization detection method and device.

Background technique

Ultra-narrowband technology is a communication technology that reduces the system bandwidth by reducing the communication rate. In the process of ultra-narrowband communication, the performance of ultra-narrowband synchronization detection and demodulation is affected by the clock error and carrier frequency offset accumulated in the communication process.

Take the police digital trunking communication system (police digital trunking, PDT) as an example. The PDT adopts 4FSK modulation with a bandwidth of 12.5 kHz, and the transmitted signal is a broadband signal relative to an ultra-narrowband signal. In the process of broadband signal transmission, the synchronization code is used to obtain clock synchronization and carrier frequency synchronization. Among them, for clock synchronization, the synchronization code is located in the middle position of a frame signal, and the determined middle position is used as a reference, and the symbols of the valid information on both sides are extracted at a predetermined sampling interval. This process does not consider the influence of the accumulated error of the clock.

That is to say, the existing synchronization code is only suitable for wideband signals, and cannot solve the effect of the accumulated clock error during the transmission of the ultra-narrowband signal on the ultra-narrowband synchronization detection and demodulation performance.

Summary of the invention

In view of this, the purpose of the present invention is to provide a synchronization detection method and device to solve the problem that the accumulated clock error during the transmission of ultra-narrowband signals affects the performance of ultra-narrowband synchronization detection and demodulation.

In order to achieve the above objectives, this application provides the following technical solutions:

The first aspect of the embodiments of the present invention discloses a synchronization detection method, and the method includes:

Obtain the synchronization code in a frame signal, and determine the reference synchronization code and the calibration synchronization code;

Using frame synchronization detection to determine the start position of the one frame signal;

Performing clock calibration and/or carrier frequency calibration based on the reference synchronization code and the calibration synchronization code;

The clock calibration process includes:

Within a preset calibration clock interval, extract the first digital information carried by the calibration synchronization code according to different calibration clocks, and the preset calibration clock interval is set according to the sampling points included in the symbol;

The extracted first digital information is compared with the true value, the information that is the same as the true value in the first digital information is determined to be the second digital information, and the best calibration is determined based on the calibration clock corresponding to the second digital information Clock calibration;

The carrier frequency calibration process includes:

Respectively calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code, and fitting the carrier frequency sampling values, and using the obtained fitting value as the carrier frequency estimation value;

Carrier frequency calibration is performed based on the estimated carrier frequency.

Preferably, the process of setting the preset calibration clock interval according to the sampling points included in the symbol includes:

Determine the number of sampling points in the symbol, and use the number of sampling points as an equivalent clock;

Using the equivalent clock as a reference, obtaining a preset number of calibration clocks according to a preset quantization interval constitutes the preset calibration clock interval.

Preferably, the determining an optimal calibration clock to perform clock calibration based on the calibration clock corresponding to the second digital information includes:

Calculate the average value of the calibration clock corresponding to the second digital information, and use the average value as the best calibration clock for clock calibration; or,

The decision variance of the calibration clock corresponding to the second digital information is calculated, and the calibration clock corresponding to the smallest decision variance is used as the best calibration clock for clock calibration.

Preferably, the calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and fitting the carrier frequency sampling values, and using the obtained fitting value as the carrier frequency estimation value includes:

Calculating the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code;

Fitting the first carrier frequency sampling value and the second carrier frequency sampling value, and using the obtained first fitting value as the carrier frequency estimation value; or,

Splitting the reference synchronization code and the calibration synchronization code, and calculating the carrier frequency sampling values of each part of the synchronization code after the splitting;

Fitting the carrier frequency sampling values of each part of the synchronization code, and using the obtained second fitting value as the carrier frequency estimation value.

Fitting the first carrier frequency sampling value and the second carrier frequency sampling value to obtain a first fitting value;

Fitting the carrier frequency sampling values of each part of the synchronization code to obtain a second fitting value;

The first fitting value and the second fitting value are averaged, and the obtained average value is used as the carrier frequency estimation value.

In a second aspect of the embodiments of the present invention, a synchronization detection device is disclosed, and the device includes:

The acquiring unit is used to acquire the synchronization code in a frame signal, and determine the reference synchronization code and the calibration synchronization code;

A frame synchronization detection unit, configured to use frame synchronization detection to determine the start position of the one frame signal;

The clock calibration unit is configured to extract the first digital information carried by the calibration synchronization code according to different calibration clocks within a preset calibration clock interval, and the preset calibration clock interval is set according to the sampling points contained in the symbols, and The extracted first digital information is compared with the true value, it is determined that the information that is the same as the true value in the first digital information is the second digital information, and the optimal calibration clock is determined based on the calibration clock corresponding to the second digital information Perform clock calibration;

The carrier frequency calibration unit is used to calculate the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and to fit the carrier frequency sampling values, and use the fitted value as the carrier frequency estimation value based on the carrier frequency sampling value. Carrier frequency calibration is performed on the estimated frequency.

Preferably, the device further includes:

The preset unit is used to determine the number of sampling points in the symbol, use the number of sampling points as an equivalent clock, and use the equivalent clock as a reference to obtain a preset number of samples according to a preset quantization interval. The calibration clock constitutes the preset calibration clock interval.

Preferably, the clock calibration unit includes:

An extraction module, configured to extract the first digital information carried by the calibration synchronization code according to different calibration clocks within a preset calibration clock interval, and the preset calibration clock interval is set according to the sampling points included in the symbol;

The comparison module is used to compare and determine the second digital information that is the same as the preset digital information in the first digital information;

The first calculation module is configured to calculate the average value of the calibration clock corresponding to the second digital information;

The clock calibration module is configured to use the average value as the best calibration clock for clock calibration; or,

The first calculation module is configured to calculate the decision variance of the calibration clock corresponding to the second digital information;

The clock calibration module is configured to use the calibration clock corresponding to the smallest decision variance as the best calibration clock for clock calibration.

Preferably, the carrier frequency calibration unit is configured to calculate the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and to fit the carrier frequency sampling values, and use the obtained fitted values as the carrier frequency estimation values. ,include:

The second calculation module is configured to calculate the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code;

The first fitting module is configured to fit the first carrier frequency sampling value and the second carrier frequency sampling value, and use the obtained first fitting value as the carrier frequency estimation value; or,

The carrier frequency calibration unit for calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and fitting the carrier frequency sampling values, and using the obtained fitting value as the carrier frequency estimation value, includes:

The third calculation module is configured to split the reference synchronization code and the calibration synchronization code, and calculate the carrier frequency sampling values of each part of the synchronization code after the split;

The second fitting module is used to fit the carrier frequency sampling values of each part of the synchronization code, and use the obtained second fitting value as the carrier frequency estimation value.

The third calculation module is used to calculate the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code, and to split the reference synchronization code and the calibration synchronization code, Calculate the carrier frequency sampling value of each part of the synchronization code after splitting;

The second fitting module is used to fit the first carrier frequency sampling value and the second carrier frequency sampling value to obtain the first fitted value, and to fit the carrier frequency sampling values of each part of the synchronization code to obtain the first Two fitting values;

The averaging module is used to average the first fitting value and the second fitting value, and use the obtained average value as the carrier frequency estimate value.

A third aspect of the embodiments of the present invention discloses a synchronization detection device, including a memory and a processor, the processor is used to run a program, wherein the program executes the synchronization detection method disclosed in the first aspect of the embodiment of the present invention when the program is running.

The fourth aspect of the embodiment of the present invention discloses a computer storage medium, the computer storage medium includes a stored program, wherein the synchronization detection method disclosed in the first aspect of the embodiment of the present invention is implemented when the program is executed by a processor.

It can be seen from the above technical solutions that the embodiment of the present invention discloses a synchronization detection method and device, by setting synchronization codes in different positions of a frame signal, and selecting the calibration clock with the best synchronization performance in the preset calibration clock interval as a The calibration clock of the frame signal, thereby calibrating the cumulative error of the clock within a frame signal, can solve the problem of decision errors caused by the cumulative clock error. In the process of carrier frequency calibration, use synchronization codes distributed in different positions of a frame of signal to obtain carrier frequency sampling points at different positions of a frame of signal, and use the obtained carrier frequency sampling points to predict or fit the carrier frequency of the entire frame of signal The changing trend can solve the problem of degraded decision performance caused by frequency drift within the frame.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some of the embodiments of the present invention, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

FIG. 1 is a flowchart of a synchronization detection method provided by an embodiment of the present invention;

2 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

FIG. 3 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

4 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

5 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

FIG. 6 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

FIG. 7 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

FIG. 8 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

FIG. 9 is a diagram of a specific example of a synchronization detection method provided by an embodiment of the present invention;

10 is a structural block diagram of a synchronization detection device provided by an embodiment of the present invention;

FIG. 11 is a structural block diagram of a synchronization detection device provided by an embodiment of the present invention;

FIG. 12 is a structural block diagram of a synchronization detection device provided by an embodiment of the present invention;

FIG. 13 is a structural block diagram of a synchronization detection device provided by an embodiment of the present invention;

FIG. 14 is a structural block diagram of a synchronization detection device provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

In this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such existence between these entities or operations. The actual relationship or order. Moreover, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes those that are not explicitly listed Other elements of, or also include elements inherent to this process, method, article or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other same elements in the process, method, article, or equipment that includes the element.

Referring to FIG. 1, a flowchart of a synchronization detection method provided by an embodiment of the present invention is shown, including the following steps:

Step S101: Obtain a synchronization code in a frame signal, and determine a reference synchronization code and a calibration synchronization code.

In the process of specifically implementing step S101, the synchronization code in a frame signal is obtained, and the reference synchronization code and the calibration synchronization code are determined from the obtained synchronization codes.

In a specific implementation, the reference synchronization code is a synchronization code that contains the most symbols among multiple synchronization codes located at different positions of the one frame signal, and the calibration synchronization code is the number of symbols in the reference synchronization code. Contains all synchronization codes with fewer symbols than the number.

It is understandable that the reference synchronization code referred to above is a synchronization code containing the most symbols, and the calibration synchronization code is all synchronization codes containing fewer symbols, and is only used for illustration. It is also possible to select the reference synchronization code and the calibration synchronization code from the acquired synchronization codes according to actual conditions. How to specifically select the reference synchronization code and the manner of the calibration synchronization code is not specifically limited in the embodiment of the present invention.

Among them, the reference synchronization code is mainly used for frame signal detection, initial estimation of clock and carrier frequency parameters, etc. Therefore, it can be optimally selected to contain relatively more symbols. The calibration synchronization code is to calibrate or calculate the change of the clock and carrier frequency parameters caused by time changes on the basis of the estimated clock and carrier frequency parameters of the reference synchronization code. Therefore, the number of symbols that can be optimally selected is less than the reference Sync code.

Step S102: Use frame synchronization detection to determine the start position of the one frame signal.

In the process of performing step S102, frame synchronization detection is performed on the one-frame signal, and the starting position of the one-frame signal is determined. One way of specifically how to perform frame synchronization detection is to use the reference synchronization code to perform conventional frame synchronization detection, which can determine the time position of the one frame signal, for example, determine the start position of the one frame signal.

Correspondingly, other synchronization codes can also be used to perform frame synchronization detection on the one-frame signal. In the embodiment of the present invention, there is no specific limitation on how to perform frame synchronization detection on one-frame signal.

Step S103: Perform clock calibration and/or carrier frequency calibration based on the reference synchronization code and the calibration synchronization code.

In the process of specifically implementing step S103, the clock calibration process is detailed in the following steps S104 and S105, and the carrier frequency calibration process is detailed in the following steps S106 and S107.

Step S104: within the preset calibration clock interval, extract the first digital information carried by the calibration synchronization code according to different calibration clocks.

In the process of specifically implementing step S104, the preset calibration clock interval is set according to the sampling points included in the symbol. Alternatively, the preset calibration clock interval can be calculated by the maximum frequency deviation index of the transmitter and receiver crystal oscillators of the PDT system, and the calibration clock can also be set according to a priori value obtained during product pre-research Interval.

Step S105: Compare the extracted first digital information with the true value, determine that the information that is the same as the true value in the first digital information is the second digital information, and determine based on the calibration clock corresponding to the second digital information The best calibration clock performs clock calibration. It should be noted that in the process of performing step S105, the second digital information is a true value, that is, the digital information carried by the agreed calibration synchronization code. Due to the instability or inconsistency of the transmitter and receiver components, if the receiver uses the transmitter’s clock, the received signal cannot be decoded correctly due to deviations. The receiver must use a value closer to the transmitter’s clock as the clock to correct The received signal is correctly decoded, and the clock used by the receiver is called the calibration clock. The average value of all the calibration clocks that can correctly decode the received signal is used as the best calibration clock, or the clock with the smallest decision variance is selected from all the calibration clocks as the best calibration clock.

Step S106: Calculate the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and fit the carrier frequency sampling values, and use the obtained fitting value as the carrier frequency estimation value.

Step S107: Carry out carrier frequency calibration based on the estimated carrier frequency.

In the embodiment of the present invention, the synchronization code is set at different positions of a frame signal, and the calibration clock with the best synchronization performance in the preset calibration clock interval is selected as the calibration clock of the frame signal, thereby calibrating the internal clock of the frame signal Cumulative error can solve the problem of decision error caused by accumulated clock error. In the process of carrier frequency calibration, use synchronization codes distributed in different positions of a frame of signal to obtain carrier frequency sampling points at different positions of a frame of signal, and use the obtained carrier frequency sampling points to predict or fit the carrier frequency of the entire frame of signal The changing trend can solve the problem of degraded decision performance caused by frequency drift within the frame.

According to the synchronization detection method disclosed in FIG. 1 of the above embodiment of the present invention, in the process of clock calibration, step S104 is executed to obtain the first digital information, and step S105 is executed to obtain the optimal calibration clock and perform clock calibration. . For the specific clock calibration process, please refer to the following detailed description.

Referring to FIG. 2, there is shown a flowchart of setting a preset calibration clock interval and obtaining the best calibration clock for clock calibration according to an embodiment of the present invention, which may include the following steps:

Step S201: Determine the number of sampling points in the symbol, and use the number of sampling points as an equivalent clock.

To better explain step S201, the following examples illustrate how to determine the number of sampling points and determine the equivalent clock:

The sampling rate of the system clock to the 1s signal is 2.88MHz, that is, for the 1s signal, 2880000 data points are collected at even and equal intervals. Assuming that the 1s signal contains 100 symbols, each symbol contains 28800 data points, so the number of points to be processed for each processing symbol is 28,800, which is a huge amount of calculation. In order to reduce the amount of calculation, in the 1s signal processing process, the sampling rate will be reduced in several times. Assuming that when the sampling rate is reduced to 16kHz, each symbol contains only 16 sampling points, where 16 is determined by the system clock Conversion and correspondence, 16 can be regarded as the equivalent clock, so that the number of sampling points and the equivalent clock are obtained.

It should be noted that the use of the number of sampling points as the equivalent clock in the embodiment of the present invention is not limited to the above examples.

Step S202: Using the equivalent clock as a reference, obtain a preset number of calibration clocks according to a preset quantization interval to form the preset calibration clock interval.

In the process of performing step S202, the quantization interval refers to equal interval values that divide the value area into multiple parts at equal intervals. The calibration clock interval can be calculated by the maximum frequency deviation index of the receiver and the transmitter to calculate the maximum clock offset, or set according to a priori value obtained during product pre-research. Take the setting of the calibration clock interval based on the prior value as an example: assuming that the equivalent clock is 16, in actual product development, it is observed that the clock offset does not exceed 15.95 and 16.05, then this can be used as an appropriate basis for expanding the calibration clock The interval, for example, set to 15.80-16.20, this interval covers the maximum clock offset range under normal circumstances.

Referring to FIG. 3, it shows a flowchart of determining the best calibration clock and performing clock calibration according to an embodiment of the present invention, including the following steps:

Step S301: Calculate the average value of the calibration clock corresponding to the second digital information, and use the average value as the best calibration clock. Step S303 is executed.

In the process of performing step S301, the specific operation of calculating the average value of the calibration clock corresponding to the second digital information and obtaining the optimal calibration clock interval, refer to the content corresponding to step S105 disclosed in FIG. 1 of the above embodiment of the present invention .

Step S302: Calculate the decision variance of the calibration clock corresponding to the second digital information, and use the calibration clock corresponding to the smallest decision variance as the best calibration clock.

In the process of performing step S302, calculating the decision variance of the calibration clock corresponding to the second digital information and obtaining the specific operation of the optimal calibration clock interval, refer to the step S104 disclosed in FIG. 1 of the above embodiment of the present invention. content.

Step S303: Perform clock calibration according to the best calibration clock.

In order to better explain the Figure 1, Figure 2 and Figure 3 disclosed in the embodiment of the present invention, referring to Figure 4, taking the reference synchronization code at the head of the frame signal and the calibration synchronization code at the tail as an example, the clock is shown For the calibration process, refer to the following processes (1) to (4) for the detailed process:

(1) Use the reference synchronization code in the header to perform regular frame synchronization detection to determine the starting position of the one-frame signal.

(2) Reduce the sampling rate of the one-frame signal to 16 kHz, that is, each symbol contains only 16 sampling points, and the original system clock can be equivalent to 16.

(3) Set the clock calibration interval to 15.80-16.20, and divide the clock calibration interval into multiple parts at equal intervals. If the equal interval is 0.01, the symbol includes 41 calibration clocks.

(4) Extract the calibration synchronization code at the tail at each calibration clock, and compare the extraction result with the true value, see Figure 4, the true value is 1110010, and it can be seen from Figure 4 that the calibration clock is 16.07-16.11 The results extracted in the interval are all 1110010, which is consistent with the true value, and the judgment is correct. Calculate the average value of the 16.07-16.11 clock interval, that is, (16.07+16.08+16.09+16.10+16.11)/5=16.09, and the best calibration clock is 16.09.

In the embodiment of the present invention, the synchronization code is set at different positions of a frame signal, and the calibration clock with the best synchronization performance in the preset calibration clock interval is selected as the calibration clock of the frame signal, thereby calibrating the internal clock of the frame signal Cumulative error can solve the problem of decision error caused by accumulated clock error.

With reference to Fig. 1 and Fig. 5, a flow chart of calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code and fitting to obtain the carrier frequency estimation value provided by an embodiment of the present invention is shown, including the following steps:

Step S501: Calculate the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code.

Step S502: Fit the first carrier frequency sampling value and the second carrier frequency sampling value, and use the obtained first fitting value as the carrier frequency estimation value.

Referring to FIG. 6, there is shown another flow chart of calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code and fitting to obtain the carrier frequency estimation value provided by the embodiment of the present invention, which may include the following steps:

Step S601: Split the reference synchronization code and the calibration synchronization code, and calculate the carrier frequency sampling value of each part of the synchronization code after the split.

In the process of specifically implementing step S601, the specific operation of splitting the reference synchronization code and the calibration synchronization code is described in the following example: Assume that the reference synchronization code at the head of a frame signal and the calibration synchronization code at the tail contain 10 symbols. , You can use 10 symbols to estimate a frequency together, which is equivalent to the frequency at the 5.5th symbol. Or the reference synchronization code of the header and the calibration of the tail are divided into two groups, 5 symbols in each group, and a frequency is estimated for every 5 symbols, which is equivalent to the 2.5th symbol and the 7.5th code The frequency at the element. In this way, 4 frequencies can be estimated at the head and tail.

Step S602: Fit the carrier frequency sampling values of each part of the synchronization code, and use the obtained second fitting value as the carrier frequency estimation value.

Referring to FIG. 7, there is shown another flow chart of calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code and fitting to obtain the carrier frequency estimation value provided by the embodiment of the present invention, which may include the following steps:

Step S701: Calculate the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code.

Step S702: Fit the first carrier frequency sample value and the second carrier frequency sample value to obtain a first fitted value.

Step S703: Split the reference synchronization code and the calibration synchronization code, and calculate the carrier frequency sampling value of each part of the synchronization code after the split.

In the process of specifically implementing step S703, for the specific operation of splitting the reference synchronization code and the calibration synchronization code, refer to the content corresponding to step S601 disclosed in FIG. 6 of the embodiment of the present invention.

Step S704: Fit the carrier frequency sampling values of each part of the synchronization code to obtain a second fitted value.

Step S705: Average the first fitting value and the second fitting value, and use the obtained average value as the carrier frequency estimation value.

In order to better explain the steps disclosed in FIG. 5, FIG. 6 and FIG. 7 in the embodiment of the present invention, FIG. 5, FIG. 6 and FIG. 7 are combined. Figures 8 and 9 take the reference synchronization code at the head of the one frame signal and the calibration synchronization code at the tail as examples, showing a schematic diagram of carrier frequency calibration of a synchronization detection method under extreme conditions and ordinary conditions. The curve 810 in FIG. 8 and FIG. 9 is the drift change of the carrier frequency within the signal frame. For the detailed process of the carrier frequency calibration, refer to the following processes (1)-(5).

(1) Using the reference synchronization code at the head of the frame signal and the calibration synchronization code at the tail to obtain two carrier frequency sampling values, which are the first carrier frequency sampling value 801 and the second carrier frequency sampling value 804, respectively.

(2) Connect the first carrier frequency sampling value 801 and the second carrier frequency sampling value 804 to obtain a diagonal approximation line 807. The diagonal approximation line 807 is the first fitting value, and the first fitting value As the carrier frequency estimate.

(3) Split the first carrier frequency sample value 801 into carrier frequency sample values 802 and 803, and split the second carrier frequency sample value 804 into carrier frequency sample values 805 and 806. For the specific operation of the fission of the first carrier frequency sampling value 801 and the second carrier frequency sampling value 804, refer to the content corresponding to step S601 disclosed in FIG. 6 of the foregoing embodiment of the present invention.

(4) Connecting the carrier frequency sampling values 802 and 803, connecting the carrier frequency sampling values 805 and 806, and connecting and intersecting the two oblique lines obtained can obtain a broken line approximation line 809. The broken line approximation line 809 is the second fitting value. The second fitting value is used as the carrier frequency estimation value.

(5) Average the points corresponding to the diagonal approximation line 807 and the broken line approximation line 809 to obtain a mean approximation line 808, the mean approximation line is the third fitting value, and the third fitting The value is used as the carrier frequency estimate.

It should be noted that it can be seen from FIG. 8 and FIG. 9 that the three approximation lines have different degrees of approximation to the carrier frequency in different situations. In practical applications, the carrier frequency estimation method can be selected in combination with the specific characteristics of the communication chip. Referring to the process (2), process (4), and process (5) disclosed in Figures 8 and 9 of the above embodiment of the present invention, these three methods for obtaining carrier frequency estimation values are only three of the carrier frequency estimation methods. Frequency estimation methods, the rest will not be illustrated one by one.

The embodiment of the present invention discloses a synchronization detection method. By setting synchronization codes at different positions of a frame of signal, using synchronization codes at different positions of a frame of signal, obtain carrier frequency sampling points at different positions of a frame of signal, and use The obtained frequency sampling points predict or fit the carrier frequency change trend of the entire frame signal, so as to solve the problem of degraded decision performance caused by the carrier frequency drift within a frame signal.

It should be noted that when the system processes a frame of signal, the best calibration clock obtained from step S301-step S302 disclosed in Figure 3 of the embodiment of the present invention is used to replace the original system clock for sampling point data extraction, and the implementation diagram of the present invention is used. 5. The carrier frequency estimated value obtained by the steps disclosed in Figs. 6 and 7 is used as a frequency reference value to perform conventional processing on the received signal, and the conventional processing includes frequency domain filtering, down-mixing, down-sampling, and the like. In order to achieve a better processing effect and simple processing of a frame of signal, multiple segments of synchronization codes should be distributed over a larger time span, or distributed in key positions of known signal prior information, and each segment of synchronization code should be easy to calculate the carrier frequency. At the same time, when processing the one-frame signal, clock calibration and frequency calibration can be performed separately, or two can be completed.

Corresponding to the flowchart of the synchronization detection method provided in the above embodiment of the present invention, referring to FIG. 10, a structural block diagram of a synchronization detection apparatus provided by an embodiment of the present invention is shown, including: an acquisition unit 1001, frame synchronization detection Unit 1002, clock calibration unit 1003, and carrier frequency calibration unit 1004;

among them:

The acquiring unit 1001 is used to acquire the synchronization code in a frame signal and determine the reference synchronization code and the calibration synchronization code. For the specific definition of the reference synchronization code and the calibration synchronization code, refer to the step S101 disclosed in FIG. 1 of the above embodiment of the present invention. Corresponding content.

The frame synchronization detection unit 1002 is configured to use frame synchronization detection to determine the start position of the one frame signal. For how to determine the start position of the one frame signal, refer to the step S102 disclosed in FIG. 1 of the above embodiment of the present invention. content.

The clock calibration unit 1003 is configured to extract the first digital information carried by the calibration synchronization code according to different calibration clocks within a preset calibration clock interval, and the preset calibration clock interval is set according to the sampling points included in the symbols, The extracted first digital information is compared with the true value, the information that is the same as the true value in the first digital information is determined to be the second digital information, and the best calibration is determined based on the calibration clock corresponding to the second digital information The clock performs clock calibration, and the specific manner of setting the calibration clock interval and performing the clock calibration can refer to the content corresponding to steps S104 and S105 disclosed in FIG. 1 of the above embodiment of the present invention.

The carrier frequency calibration unit 1004 is configured to calculate the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and to fit the carrier frequency sampling values, and use the obtained fitting value as the carrier frequency estimation value based on the carrier frequency sampling value. Carrier frequency calibration is performed on the estimated value of the carrier frequency.

Preferably, in conjunction with FIG. 10 and referring to FIG. 11, the synchronization detection device provided by the embodiment of the present invention further includes: a preset unit 1005;

The preset unit 1005 is configured to determine the number of sampling points in the symbol, use the number of sampling points as an equivalent clock, and use the equivalent clock as a reference to obtain a preset number according to a preset quantization interval The calibration clock constitutes the preset calibration clock interval. For the specific process of constituting the calibration clock interval, refer to the corresponding content of step S201 and step S202 disclosed in FIG. 2 of the above embodiment of the present invention.

Preferably, in conjunction with FIG. 11 and referring to FIG. 12, in a synchronization detection device provided by an embodiment of the present invention, the clock calibration unit 1003 includes: an extraction module 10031, a comparison module 10032, a first calculation module 11032, and a clock calibration module 11033;

among them:

Extraction module 10031: used to extract the first digital information carried by the calibration synchronization code according to different calibration clocks within a preset calibration clock interval. The preset calibration clock interval is set according to the sampling points contained in the symbols, specifically For the process, refer to the content corresponding to step S104 disclosed in FIG. 1 of the foregoing embodiment of the present invention.

The comparison module 10032 is used to compare and determine the second digital information that is the same as the preset digital information in the first digital information.

The first calculation module 10033 is configured to calculate the average value of the calibration clock corresponding to the second digital information, or to calculate the decision variance of the calibration clock corresponding to the second digital information.

The clock calibration module 10034 is configured to use the average value as the best calibration clock for clock calibration, or use the calibration clock corresponding to the smallest decision variance as the best calibration clock for clock calibration, and the specific process of determining the best calibration clock Refer to the content corresponding to step S105 disclosed in FIG. 1 of the above embodiment of the present invention.

Preferably, referring to FIG. 12 and FIG. 13, according to an embodiment of the present invention, in a synchronization detection device, the carrier frequency calibration unit 1004 includes:

The second calculation module 10041 is configured to calculate the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code.

The first fitting module 10042 is configured to fit the first carrier frequency sampling value and the second carrier frequency sampling value, and use the obtained first fitting value as the carrier frequency estimation value.

Preferably, in conjunction with FIG. 13 and referring to FIG. 14, in a synchronization detection device provided by an embodiment of the present invention, the carrier frequency calibration unit 1004 includes:

The third calculation module 10043 is configured to split the reference synchronization code and the calibration synchronization code, calculate the carrier frequency sampling values of each part of the synchronization code after the split, and split the reference synchronization code and the calibration synchronization code For the specific process, refer to the content corresponding to step S601 disclosed in FIG. 6 of the foregoing embodiment of the present invention.

The second fitting module 10044 is configured to fit the carrier frequency sampling values of each part of the synchronization code, and use the obtained second fitting value as the carrier frequency estimation value.

Optionally, the third calculation module 10043 is configured to calculate the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code, and to split the reference synchronization code and the The calibration synchronization code is described, and the carrier frequency sampling value of each part of the synchronization code after splitting is calculated.

Optionally, a second fitting module 10044 is used to fit the first carrier frequency sample value and the second carrier frequency sample value to obtain a first fitted value, and to fit the carrier frequency of each part of the synchronization code Sampling values to obtain the second fitted value.

The averaging module 10045 is configured to average the first fitted value and the second fitted value, and use the obtained average value as the carrier frequency estimate value.

Preferably, an embodiment of the present invention further provides a synchronization detection device, including a memory and a processor, the processor is configured to run a program, wherein the program executes the synchronization detection method disclosed in the foregoing embodiment of the present invention when the program is running.

Preferably, the embodiment of the present invention further provides a computer storage medium, the computer storage medium includes a stored program, wherein the synchronization detection method disclosed in the above embodiment of the present invention is implemented when the program is executed by the processor.

In summary, the embodiment of the present invention discloses a synchronization detection method and device. By setting synchronization codes in different positions of a frame signal, and selecting the calibration clock with the best synchronization performance in the preset calibration clock interval as a frame The signal is calibrated to the clock, so as to calibrate the cumulative error of the clock within a frame of signal, which can solve the problem of decision errors caused by the cumulative clock error. At the same time, use synchronization codes at different positions of a frame of signal to obtain carrier frequency sampling points at different positions of a frame of signal, and use the obtained frequency sampling points to predict or fit the carrier frequency change trend of the entire frame of signal, thereby solving the problem of The problem of degraded decision performance caused by carrier frequency drift within a frame of signal.

For the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described sequence of actions, because according to the present invention, Some steps can be performed in other order or at the same time. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same and similar parts between the various embodiments, refer to each other. can. As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.

The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in this document, but should conform to the widest scope consistent with the principles and novel features disclosed in this document.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.

Claims

A synchronization detection method, characterized in that the method includes:

Obtain the synchronization code in a frame signal, and determine the reference synchronization code and the calibration synchronization code;

Using frame synchronization detection to determine the start position of the one frame signal;

Performing clock calibration and/or carrier frequency calibration based on the reference synchronization code and the calibration synchronization code;

The clock calibration process includes:

Within a preset calibration clock interval, extract the first digital information carried by the calibration synchronization code according to different calibration clocks, and the preset calibration clock interval is set according to the sampling points included in the symbol;

The extracted first digital information is compared with the true value, the information that is the same as the true value in the first digital information is determined to be the second digital information, and the best calibration is determined based on the calibration clock corresponding to the second digital information Clock calibration;

The carrier frequency calibration process includes:

Respectively calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code, and fitting the carrier frequency sampling values, and using the obtained fitting value as the carrier frequency estimation value;

Carrier frequency calibration is performed based on the estimated carrier frequency.
The method according to claim 1, wherein the process of setting the preset calibration clock interval according to the sampling points included in the symbol comprises:

Determine the number of sampling points in the symbol, and use the number of sampling points as an equivalent clock;

Using the equivalent clock as a reference, obtaining a preset number of calibration clocks according to a preset quantization interval constitutes the preset calibration clock interval.
The method according to claim 1, wherein the determining an optimal calibration clock to perform clock calibration based on the calibration clock corresponding to the second digital information comprises:

Calculate the average value of the calibration clock corresponding to the second digital information, and use the average value as the best calibration clock for clock calibration; or,

The decision variance of the calibration clock corresponding to the second digital information is calculated, and the calibration clock corresponding to the smallest decision variance is used as the best calibration clock for clock calibration.
The method according to any one of claims 1-3, wherein the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code are calculated separately, and the carrier frequency sampling values are fitted to obtain The fitted value is used as the carrier frequency estimate, including:

Calculating the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code;

Fitting the first carrier frequency sampling value and the second carrier frequency sampling value, and using the obtained first fitting value as the carrier frequency estimation value; or,

Splitting the reference synchronization code and the calibration synchronization code, and calculating the carrier frequency sampling values of each part of the synchronization code after the splitting;

Fitting the carrier frequency sampling values of each part of the synchronization code, and using the obtained second fitting value as the carrier frequency estimation value.
The method according to any one of claims 1-3, wherein the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code are calculated separately, and the carrier frequency sampling values are fitted to obtain The fitted value of is used as the carrier frequency estimate, including:

Calculating the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code;

Fitting the first carrier frequency sampling value and the second carrier frequency sampling value to obtain a first fitting value;

Splitting the reference synchronization code and the calibration synchronization code, and calculating the carrier frequency sampling values of each part of the synchronization code after the splitting;

Fitting the carrier frequency sampling values of each part of the synchronization code to obtain a second fitting value;

The first fitting value and the second fitting value are averaged, and the obtained average value is used as the carrier frequency estimation value.
A synchronization detection device, characterized in that the device includes:

The acquiring unit is used to acquire the synchronization code in a frame signal, and determine the reference synchronization code and the calibration synchronization code;

A frame synchronization detection unit, configured to use frame synchronization detection to determine the start position of the one frame signal;

The clock calibration unit is configured to extract the first digital information carried by the calibration synchronization code according to different calibration clocks within a preset calibration clock interval. The preset calibration clock interval is set according to the sampling points contained in the symbol, and the extracted The first digital information is compared with the true value, the information that is the same as the true value in the first digital information is determined to be the second digital information, and the best calibration clock is determined based on the calibration clock corresponding to the second digital information. calibration;

The carrier frequency calibration unit is used to calculate the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and to fit the carrier frequency sampling values, and use the fitted value as the carrier frequency estimation value based on the carrier frequency sampling value. Carrier frequency calibration is performed on the estimated frequency.
The device according to claim 6, further comprising:

The preset unit is used to determine the number of sampling points in the symbol, use the number of sampling points as an equivalent clock, and use the equivalent clock as a reference to obtain a preset number of samples according to a preset quantization interval. The calibration clock constitutes the preset calibration clock interval.
The device according to claim 6, wherein the clock calibration unit comprises:

An extraction module, configured to extract the first digital information carried by the calibration synchronization code according to different calibration clocks within a preset calibration clock interval, and the preset calibration clock interval is set according to the sampling points included in the symbol;

The comparison module is used to compare and determine the second digital information that is the same as the preset digital information in the first digital information;

The first calculation module is configured to calculate the average value of the calibration clock corresponding to the second digital information;

The clock calibration module is configured to use the average value as the best calibration clock for clock calibration; or,

The first calculation module is configured to calculate the decision variance of the calibration clock corresponding to the second digital information;

The clock calibration module is configured to use the calibration clock corresponding to the smallest decision variance as the best calibration clock for clock calibration.
The device according to claim 6, characterized in that it is used to calculate the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and to fit the carrier frequency sampling values, and use the obtained fitted values as the carrier frequency sampling values. The carrier frequency calibration unit of the frequency estimation value includes:

The first fitting module is configured to fit the first carrier frequency sampling value and the second carrier frequency sampling value, and use the obtained first fitting value as the carrier frequency estimation value; or,

The carrier frequency calibration unit for calculating the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and fitting the carrier frequency sampling values, and using the obtained fitting value as the carrier frequency estimation value, includes:

The third calculation module is configured to split the reference synchronization code and the calibration synchronization code, and calculate the carrier frequency sampling values of each part of the synchronization code after the split;

The second fitting module is used to fit the carrier frequency sampling values of each part of the synchronization code, and use the obtained second fitting value as the carrier frequency estimation value.
The device according to claim 6, characterized in that it is used to calculate the carrier frequency sampling values of the reference synchronization code and the calibration synchronization code respectively, and to fit the carrier frequency sampling values, and use the obtained fitted values as the carrier frequency sampling values. The carrier frequency calibration unit of the frequency estimation value includes:

The third calculation module is used to calculate the first carrier frequency sampling value of the reference synchronization code and the second carrier frequency sampling value of the calibration synchronization code, and to split the reference synchronization code and the calibration synchronization code, Calculate the carrier frequency sampling value of each part of the synchronization code after splitting;

The second fitting module is used to fit the first carrier frequency sampling value and the second carrier frequency sampling value to obtain the first fitted value, and to fit the carrier frequency sampling values of each part of the synchronization code to obtain the first Two fitting values;

The averaging module is used to average the first fitting value and the second fitting value, and use the obtained average value as the carrier frequency estimate value.
A synchronous detection device is characterized by comprising a memory and a processor, the memory is used to store a computer program, and the processor is used to run the program stored in the storage, wherein the program executes the The synchronization detection method described in any one of 1-5 is required.
A computer storage medium, wherein the computer storage medium includes a stored program, wherein the synchronization detection method according to any one of claims 1-5 is implemented when the program is executed by a processor.