CN104579566A - Synchronous information detection method, system and general correlator - Google Patents
Synchronous information detection method, system and general correlator Download PDFInfo
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- CN104579566A CN104579566A CN201410857622.6A CN201410857622A CN104579566A CN 104579566 A CN104579566 A CN 104579566A CN 201410857622 A CN201410857622 A CN 201410857622A CN 104579566 A CN104579566 A CN 104579566A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
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Abstract
The invention discloses a synchronous information detection method, a system and a general correlator. The method includes the steps that a sampling clock performs sampling on data to be measured to generate first sampling data, and the first sampling data are stored; distances between pre-stored synchronous codes are used as position intervals in sequence, and stored second sampling data are read from corresponding storage positions at every two position intervals; exclusive-or operation is performed on all the second sampling data and the pre-stored synchronous codes to generate exclusive-or results corresponding to all the storage positions respectively; all the exclusive-or results are obtained and are used for identifying the sum of the number of identification information of different bytes between the second sampling data and the pre-stored synchronous codes, and then different byte numbers corresponding to all the storage positions can be generated respectively; corresponding synchronization relevant indications are generated when the different byte numbers are matched with preset byte tolerance. By the implementation of the method, synchronization correlation between the data to be measured and multiple segments of the synchronous codes distributed in any position in a time domain can be detected quickly and accurately.
Description
[technical field]
The present invention relates to communication technical field, particularly relate to a kind of synchronizing information detection method, system and general correlator.
[background technology]
The synchronous method of achieve frame mainly inserts the end to end mark of some special code characters as every frame in data message stream, receiving terminal find out these special code characters position just can achieve frame synchronous.Frame synchronizer utilizes the autocorrelation performance of frame synchronization code character and identifies from the data flow of eating dishes without rice or wine received through correlation operator.
First frame synchronizer carries out serioparallel exchange to reception data, with local synchronization code character carry out with or computing or XOR, mask useless relevant bits, again through entirely adding network, realize correlation sum operation, compare with judging threshold, obtain synchronization frame mark.
But the above frame synchronizer can not adapt to the detection of multistage synchronous code.
[summary of the invention]
Based on this, be necessary the test problems that can not adapt to multistage synchronous code for above-mentioned frame synchronizer, a kind of synchronizing information detection method, system and general correlator are provided.
A kind of synchronizing information detection method, comprises the following steps:
According to sampling clock, sampling generation first sampled data is carried out to testing data, and store described first sampled data;
Successively with each intersymbol distance of the synchronous code prestored for location interval, read the second sampled data stored from respective memory locations every a location interval, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore;
Second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generates XOR result corresponding with each respective memory locations respectively;
Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively;
Judge whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
A kind of synchronizing information detection system, comprising:
Sampling module, for carrying out sampling generation first sampled data according to sampling clock to testing data, and stores described first sampled data;
Read module, for successively with each intersymbol distance of the synchronous code prestored for location interval, read the second sampled data stored from respective memory locations every a location interval, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore;
XOR module, generates XOR result corresponding with each respective memory locations respectively for the second sampled data described in each is carried out XOR with the described synchronous code prestored respectively;
Statistical module, for obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generates different bit numbers corresponding from each respective memory locations respectively;
Indicating module, for judging whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
A kind of general correlator, comprise the sampling clock that prestores, oversampling clock rate, synchronous code, each intersymbol Distance geometry control appliance of presetting error bit tolerance limit of synchronous code and the system clock that is connected with described control appliance respectively and generate equipment, sample devices, memory device and at least two associated assay devices, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore, wherein:
Described system clock generates equipment for generating the system clock of general correlator;
Described sample devices is used for carrying out sampling generation first sampled data according to sampling clock to testing data and sending to described control appliance;
Described control appliance is used for each memory location described first sampled data being stored into described memory device, and with each intersymbol distance of the synchronous code prestored for location interval, reads the second sampled data stored every a location interval from respective memory locations;
Described control appliance also for the second sampled data described in control signal and each is transported to each associated assay devices respectively, wherein, carries the second sampled data read from a respective memory locations to an associated assay devices;
Second sampled data described in each and the described synchronous code prestored are carried out XOR generate XOR result corresponding with each respective memory locations respectively for being responded described control signal by each associated assay devices respectively; Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively; Judge whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
Above-described synchronizing information detection method, system and general correlator, with the distance between each adjacent two sections of associated codes of the synchronous code prestored for location interval reads the second sampled data stored from respective memory locations; Second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generates XOR result corresponding with each respective memory locations respectively; Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively; Corresponding synchronous relevantly to indicate is generated when different bit number mates to default error bit tolerance limit.The synchronous correlation of testing data and the multistage synchronous code of optional position in the time domain of distributing can be detected quickly and accurately by the distance between each adjacent two sections of associated codes of synchronous code of prestoring.
[accompanying drawing explanation]
Fig. 1 is the schematic flow sheet of synchronizing information detection method first execution mode of the present invention;
Fig. 2 is the shift LD matrix schematic diagram of shift register in synchronizing information detection method of the present invention;
Fig. 3 is the Statistics schematic diagram of different bit number in synchronizing information detection method of the present invention;
Fig. 4 is the schematic flow sheet of synchronizing information detection method second execution mode of the present invention;
Fig. 5 is the schematic flow sheet of synchronizing information detection method the 3rd execution mode of the present invention;
Fig. 6 is the structural representation of synchronizing information detection system first execution mode of the present invention;
Fig. 7 is the structural representation of synchronizing information detection system the 3rd execution mode of the present invention;
Fig. 8 is the structural representation of the present invention's general correlator first execution mode;
Fig. 9 is the sequential chart of shift register access data in the general correlator of the present invention;
Figure 10 is the structural representation of enabled devices in the general correlator of the present invention;
Figure 11 is the structural representation of the general correlator of the present invention the 3rd execution mode.
[embodiment]
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
Refer to Fig. 1, Fig. 1 is the schematic flow sheet of synchronizing information detection method first execution mode of the present invention.
The described synchronizing information detection method of present embodiment, can comprise the following steps:
Step S101, carries out sampling generation first sampled data according to sampling clock to testing data, and stores described first sampled data.
Step S102, successively with each intersymbol distance of the synchronous code prestored for location interval, read the second sampled data stored from respective memory locations every a location interval, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore.
Step S103, carries out XOR with the described synchronous code prestored respectively by the second sampled data described in each and generates XOR result corresponding with each respective memory locations respectively.
Step S104, obtains for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generates different bit numbers corresponding from each respective memory locations respectively.
Step S105, judges whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
Present embodiment, with the distance between each adjacent two sections of associated codes of the synchronous code prestored for location interval reads the second sampled data stored from respective memory locations; Second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generates XOR result corresponding with each respective memory locations respectively; Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively; Corresponding synchronous relevantly to indicate is generated when different bit number mates to default error bit tolerance limit.The synchronous correlation of testing data and the multistage synchronous code of optional position in the time domain of distributing can be detected quickly and accurately by the distance between each adjacent two sections of associated codes of synchronous code of prestoring.
Wherein, for step S101, described sampling clock preferably can be preset according to the signal length of testing data or signal period.Can sample to described testing data at the rising edge of described sampling clock.Each sampling period reading times is the hop count of the synchronous code (associated code) prestored.The sampled data read is stored in the length shift register equal with each segment length of associated code successively.
For step S102, described in the synchronous code that prestores can be multistage synchronous code, also can be single hop synchronous code.Each section of associated code of multistage synchronous code can be the synchronous code of identical type, also can be different types of synchronous code.
Preferably, when pre-stored sync code, can prestore a kind of synchronous code at every turn, each detection testing data and the synchronous correlation between a kind of synchronous code.Can be prestored multiple synchronization code several times, detects the synchronous correlation of testing data and multiple synchronization intersymbol accordingly several times respectively.
Preferably, each intersymbol distance be respectively to obtain successively by priority ordering described in distance between each adjacent two sections of associated codes of synchronous code of prestoring.When reading the second sampled data, by priority ordering, the distance chosen between two sections of adjacent associated codes is positional distance, and read sampled data, the location interval of the memory location of the second sampled data of adjacent twi-read is followed successively by each intersymbol distance.
Further, when reading the second sampled data, read from the memory address of the data of current up-to-date storage, then by priority ordering, the distance chosen between two sections of adjacent associated codes is positional distance, reads sampled data.
In one embodiment, can after distance stores two system clock cycles of the memory time of described sampled data, successively with each intersymbol distance of the synchronous code prestored for location interval, every a location interval from respective memory locations read store the second sampled data.
Wherein, after two system clock cycles, the first sampled data is at memory location stable storage, and from being sampled for the first time, be used to carry out XOR at most only consumes 4 system clocks to each first sampled data.
For step S103, by each XOR equipment, the second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generate XOR result corresponding with each respective memory locations respectively, an XOR equipment carries out XOR to described second sampled data and the described synchronous code prestored.
In one embodiment, the second sampled data described in each is carried out respectively the step that XOR generates XOR result corresponding with each respective memory locations respectively to comprise the following steps with the described synchronous code prestored:
Second sampled data described in each is cached to different shift registers respectively, wherein, described shift register for columns, with the sampling rate of sampling to described testing data for line number, builds shift LD matrix with the maximum length of the described synchronous code prestored.
Respectively the data that the output from each shift register exports are carried out XOR with the described synchronous code prestored and generate XOR result corresponding with each respective memory locations respectively.
Preferably, the shift LD matrix of described shift register as shown in Figure 2, carries out XOR at every turn, and the output of shift register exports data line, is convenient to monitor XOR.
For step S104, preferably, the identification information for identifying different bit between described second sampled data from the described synchronous code prestored can be the numeral 1 in XOR result.
Further, the memory location of the second sampling location that identifies for described different bit number, the memory location corresponding to different bit numbers of generation.
In one embodiment, obtain for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, the step generating different bit numbers corresponding from each respective memory locations is respectively further comprising the steps of:
By pipelining, the XOR result corresponding with each respective memory locations is divided into four groups of XOR results.
The identification information for identifying different bit between described second sampled data from the described synchronous code prestored is inquired about respectively from four groups of XOR results.
The number of the identification information of the different bits from four groups of XOR result queries is added, generates the different bit numbers corresponding from described respective memory locations.
The present embodiment, can adapt to system clock more at a high speed, meets higher timing requirements.
Preferably, described pipelining adds up the principle of different bit number as shown in Figure 3.
For step S105, described synchronous relevant instruction comprises positive correlation instruction and inverse correlation instruction, for representing the synchronous correlation between the testing data of collection with the described synchronous code prestored.
Preferably, described default error bit tolerance limit for when there is correlation between described second sampled data from described default synchronous code allow the maximum of the number of the different bits occurred.If different bit number is in described default error bit tolerance limit, then different bit number mates with default error bit tolerance limit.
Refer to Fig. 4, Fig. 4 is the schematic flow sheet of the second execution mode of synchronizing information detection method of the present invention.
The described synchronizing information detection method of present embodiment is from the difference of the first execution mode: judge whether the different bit number corresponding with each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then the step of the corresponding synchronous relevant instruction of corresponding each respective memory locations generation is further comprising the steps of respectively:
Step S401, compares the different bit numbers corresponding from each respective memory locations and whether is less than described default error bit tolerance limit.
Step S402, if be less than, then corresponding described respective memory locations generates the instruction of corresponding synchronous positive correlation.
Step S403, if be not less than, then deducts the different bit numbers corresponding from described respective memory locations by the length of the described synchronous code prestored, and generates difference.
Step S404, whether more described difference is less than described default error bit tolerance limit.
Step S405, if be less than, then corresponding described respective memory locations generates corresponding synchronous inverse correlation instruction.
Present embodiment, can generate corresponding relevant instruction fast.
Preferably, described in the length of synchronous code that prestores deduct the different bit numbers corresponding from described respective memory locations, be the number of same bits between the second sampled data of reading from described respective memory locations and the described synchronous code prestored.
Further, described difference is not less than described default error bit tolerance limit, does not generate synchronous relevant instruction.
Refer to Fig. 5, Fig. 5 is the schematic flow sheet of the 3rd execution mode of synchronizing information detection method of the present invention.
The described synchronizing information detection method of present embodiment is to the difference of the first execution mode: after generating the corresponding synchronous relevant step indicated, further comprising the steps of:
Step S501, judges whether there is synchronous relevant instruction corresponding to M respective memory locations in the sampled data of continuous K sampling clock sampling, and wherein, M is to described the testing data sampling rate of sampling and the relevant difference indicating tolerance limit of mistake preset.
Step S502, if so, then generates for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted.
Present embodiment, can reduce mistake relevant relevant with leakage.
Preferably, K and M is positive integer, corresponding to a continuous N respective memory locations synchronous relevantly to indicate is there is in the sampled data of continuous K sampling clock sampling, then judge that described testing data and the described synchronous code prestored are as correct relevant, and generate for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted; There is not corresponding to a continuous N respective memory locations synchronous relevantly to indicate in the sampled data of continuous K sampling clock sampling, then judge that described testing data is relevant as mistake to the described synchronous code prestored.
Further, generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate the step of interrupting after, further comprising the steps of:
Export relevant instruction interruption, corresponding phase synchronization information and frame synchronization information.
In one embodiment, generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate the step of interrupting after, further comprising the steps of:
Obtain described relevant instruction interrupt preset correlation window in position coordinates, described correlation window with frequency hopping burst trailing edge for initial point, with the rising edge of described sampling clock for scale, length in units of the cycle of described sampling clock.
With the Data Position of described testing data corresponding to described position coordinates for relevant position.
Present embodiment, can obtain the relevant position between synchronous code that testing data and institute's number prestore fast.
Wherein, described relevant position is for representing the position of synchronous code.Obtain described relevant instruction and interrupt the position coordinate value in the correlation window preset, deduct the product of described associated code length and sampling rate, then divided by 2 i.e. described relevant positions.
Preferably, frequency hopping burst is not exclusive can be used for the signal determining relevant position, and it is just used for providing initial position to determine the signal of relevant position in frequency-hopping system, and in other embodiments, other system can replace with other signals.
Further, the information such as relevant instruction, relevant misdirection rate (sampling rate with from the relevant difference of interrupting that indicates again divided by M), different bit number, relevant position can be stored.
In another embodiment, generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate the step of interrupting after, further comprising the steps of:
If total number N of synchronous relevant instruction is even number, then the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase of N/2 sampling location with described testing data or N/2+1 sampling location.
If total number N of synchronous relevant instruction is odd number, the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase with a sampling location, (N+1)/2 of described testing data.
Present embodiment, can realize Phase synchronization fast.
When testing data is digital signal, the sampling location of its best is the middle position of signal.When initial synchronisation, the phase place of the sampling pulse (sampled data) of reception and the testing data of transmission is inconsistent, needs adjustment.After synchronous foundation, may move due to transmitting terminal or receiving terminal, cause transmitting terminal and receiving terminal relative position to change, cause the phase place of the testing data receiving sampling pulse and transmission inconsistent.In order to sampling pulse can be allowed in the centre position of digital signal received to signal sampling, carry out sampled data by multiple sampling pulse, carry out Phase synchronization, after synchronous, horizontal phasing control is entered to sampling pulse.For the synchronous code that the pulse of N sampling is adopted, N number of relevant instruction should be had in theory to produce, N/2 (N is even number) or N/2+1 (N is even number) or (N+1)/2 (N is odd number) individual sampling location are exactly centre position, namely optimum sampling position.Sampling pulse is adjusted to and can complete the synchronous of phase place with the sampling clock same-phase of this position of synchronous code.
Refer to Fig. 6, Fig. 6 is the structural representation of synchronizing information detection system first execution mode of the present invention.
The described synchronizing information detection system of present embodiment, can comprise sampling module 100, read module 200, XOR module 300, statistical module 400 and indicating module 500, wherein:
Sampling module 100, for carrying out sampling generation first sampled data according to sampling clock to testing data, and stores described first sampled data.
Read module 200, for successively with each intersymbol distance of the synchronous code prestored for location interval, read the second sampled data stored from respective memory locations every a location interval, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore.
XOR module 300, generates XOR result corresponding with each respective memory locations respectively for the second sampled data described in each is carried out XOR with the described synchronous code prestored respectively.
Statistical module 400, for obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generates different bit numbers corresponding from each respective memory locations respectively.
Indicating module 500, for judging whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
Present embodiment, with the distance between each adjacent two sections of associated codes of the synchronous code prestored for location interval reads the second sampled data stored from respective memory locations; Second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generates XOR result corresponding with each respective memory locations respectively; Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively; Corresponding synchronous relevantly to indicate is generated when different bit number mates to default error bit tolerance limit.The synchronous correlation of testing data and the multistage synchronous code of optional position in the time domain of distributing can be detected quickly and accurately by the distance between each adjacent two sections of associated codes of synchronous code of prestoring.
Wherein, for sampling module 100, described sampling clock preferably can be preset according to the signal length of testing data or signal period.Can sample to described testing data at the rising edge of described sampling clock.
For read module 200, described in the synchronous code that prestores can be multistage synchronous code, also can be single hop synchronous code.Each section of associated code of multistage synchronous code can be the synchronous code of identical type, also can be different types of synchronous code.
Preferably, when pre-stored sync code, can prestore a kind of synchronous code at every turn, each detection testing data and the synchronous correlation between a kind of synchronous code.Can be prestored multiple synchronization code several times, detects the synchronous correlation of testing data and multiple synchronization intersymbol accordingly several times respectively.
Preferably, each intersymbol distance be respectively to obtain successively by priority ordering described in distance between each adjacent two sections of associated codes of synchronous code of prestoring.When reading the second sampled data, by priority ordering, the distance chosen between two sections of adjacent associated codes is positional distance, and read sampled data, the location interval of the memory location of the second sampled data of adjacent twi-read is followed successively by each intersymbol distance.
Further, when reading the second sampled data, read from the memory address of the data of current up-to-date storage, then by priority ordering, the distance chosen between two sections of adjacent associated codes is positional distance, reads sampled data.
In one embodiment, read module 200 can after distance stores two system clock cycles of the memory time of described sampled data, successively with each intersymbol distance of the synchronous code prestored for location interval, every a location interval from respective memory locations read store the second sampled data.
Wherein, after two system clock cycles, the first sampled data is at memory location stable storage, and from being sampled for the first time, be used to carry out XOR at most only consumes 4 system clocks to each first sampled data.
For XOR module 300, by each XOR equipment, the second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generate XOR result corresponding with each respective memory locations respectively, an XOR equipment carries out XOR to described second sampled data and the described synchronous code prestored.
In one embodiment, XOR module 300 also can be used for:
Second sampled data described in each is cached to different shift registers respectively, wherein, described shift register for columns, with the sampling rate of sampling to described testing data for line number, builds shift LD matrix with the maximum length of the described synchronous code prestored.
Respectively the data that the output from each shift register exports are carried out XOR with the described synchronous code prestored and generate XOR result corresponding with each respective memory locations respectively.
Preferably, the shift LD matrix of described shift register as shown in Figure 2, carries out XOR at every turn, and the output of shift register exports data line, is convenient to monitor XOR.
For statistical module 400, preferably, the identification information for identifying different bit between described second sampled data from the described synchronous code prestored can be the numeral 1 in XOR result.
Preferably, statistical module 400 also can be used for statistics frame synchronizing information, and described frame synchronization information is for representing described testing data and the described correlation properties of the synchronous code prestored and the quality of channel.
Further, the memory location of the second sampling location that identifies for described different bit number, the memory location corresponding to different bit numbers of generation.
In one embodiment, statistical module 400 also can be used for:
By pipelining, the XOR result corresponding with each respective memory locations is divided into four groups of XOR results.
The identification information for identifying different bit between described second sampled data from the described synchronous code prestored is inquired about respectively from four groups of XOR results.
The number of the identification information of the different bits from four groups of XOR result queries is added, generates the different bit numbers corresponding from described respective memory locations.
The present embodiment, can adapt to system clock more at a high speed, meets higher timing requirements.
Preferably, the principle of described pipelining as shown in Figure 3.
For indicating module 500, described synchronous relevant instruction comprises positive correlation instruction and inverse correlation instruction, for representing the synchronous correlation between the testing data of collection with the described synchronous code prestored.
Preferably, described default error bit tolerance limit for when there is correlation between described second sampled data from described default synchronous code allow the maximum of the number of the different bits occurred.If different bit number is in described default error bit tolerance limit, then different bit number mates with default error bit tolerance limit.
The following stated is the second execution mode of synchronizing information detection system of the present invention.
The described synchronizing information detection system of present embodiment and the difference of the first execution mode are: indicating module 400 also can be further used for:
Relatively whether the different bit numbers corresponding from each respective memory locations are less than described default error bit tolerance limit.
If be less than, then corresponding described respective memory locations generates the instruction of corresponding synchronous positive correlation.
If be not less than, then the length of the described synchronous code prestored is deducted the different bit numbers corresponding from described respective memory locations, generate difference.
Whether more described difference is less than described default error bit tolerance limit.
If be less than, then corresponding described respective memory locations generates corresponding synchronous inverse correlation instruction.
Present embodiment, can generate corresponding relevant instruction fast.
Preferably, described in the length of synchronous code that prestores deduct the different bit numbers corresponding from described respective memory locations, be the number of same bits between the second sampled data of reading from described respective memory locations and the described synchronous code prestored.
Refer to Fig. 7, Fig. 7 is the structural representation of the 3rd execution mode of synchronizing information detection system of the present invention.
The described synchronizing information detection system of present embodiment and the difference of the second execution mode are: also comprise correlated judgment module 600, for:
Judge whether there is synchronous relevant instruction corresponding to M respective memory locations in the sampled data of continuous K sampling clock sampling, wherein, M is to described the testing data sampling rate of sampling and the relevant difference indicating tolerance limit of mistake preset.
If so, then generate for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted.
Present embodiment, can reduce mistake relevant relevant with leakage.
Preferably, K and M is positive integer, corresponding to a continuous N respective memory locations synchronous relevantly to indicate is there is in the sampled data of continuous K sampling clock sampling, then judge that described testing data and the described synchronous code prestored are as correct relevant, and generate for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted; There is not corresponding to a continuous N respective memory locations synchronous relevantly to indicate in the sampled data of continuous K sampling clock sampling, then judge that described testing data is relevant as mistake to the described synchronous code prestored.
In one embodiment, also comprise relevant position module, for generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate interrupt after:
Obtain described relevant instruction interrupt preset correlation window in position coordinates, described correlation window with frequency hopping burst trailing edge for initial point, with the rising edge of described sampling clock for scale, length in units of the cycle of described sampling clock.
With the Data Position of described testing data corresponding to described position coordinates for relevant position.
Present embodiment, can obtain the relevant position between synchronous code that testing data and institute's number prestore fast.
Wherein, described relevant position is for representing the position of synchronous code.Obtain described relevant instruction and interrupt the position coordinate value in the correlation window preset, deduct the product of described associated code length and sampling rate, then divided by 2 i.e. described relevant positions.
Preferably, frequency hopping burst is not exclusive can be used for the signal determining relevant position, and it is just used for providing initial position to determine the signal of relevant position in frequency-hopping system, and in other embodiments, other system can replace with other signals.
Further, the information such as relevant instruction, relevant misdirection rate (sampling rate with from the relevant difference of interrupting that indicates again divided by M), different bit number, relevant position can be stored.
In another embodiment, also comprise Phase synchronization module, for generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate interrupt after:
If total number N of synchronous relevant instruction is even number, then the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase of N/2 sampling location with described testing data or N/2+1 sampling location.
If total number N of synchronous relevant instruction is odd number, the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase with a sampling location, (N+1)/2 of described testing data.
Present embodiment, can realize Phase synchronization fast.
When testing data is digital signal, the sampling location of its best is the middle position of signal.When initial synchronisation, the phase place of the sampling pulse (sampled data) of reception and the testing data of transmission is inconsistent, needs adjustment.After synchronous foundation, may move due to transmitting terminal or receiving terminal, cause transmitting terminal and receiving terminal relative position to change, cause the phase place of the testing data receiving sampling pulse and transmission inconsistent.In order to sampling pulse can be allowed in the centre position of digital signal received to signal sampling, carry out sampled data by multiple sampling pulse, carry out Phase synchronization, after synchronous, horizontal phasing control is entered to sampling pulse.For the synchronous code that the pulse of N sampling is adopted, N number of relevant instruction should be had in theory to produce, N/2 (N is even number) or N/2+1 (N is even number) or (N+1)/2 (N is odd number) individual sampling location are exactly centre position, namely optimum sampling position.Sampling pulse is adjusted to and can complete the synchronous of phase place with the sampling clock same-phase of this position of synchronous code.
Refer to Fig. 8, Fig. 8 is the structural representation of general correlator first execution mode of the present invention.
The described general correlator of present embodiment, the sampling clock that prestores, oversampling clock rate, synchronous code, each intersymbol Distance geometry control appliance 1010 of presetting error bit tolerance limit of synchronous code and the system clock that is connected with control appliance 1010 respectively can be comprised and generate equipment 1060, sample devices 1020, memory device 1030 and at least two associated assay devices 1040, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore, wherein:
System clock generates equipment 1060 for generating the system clock of general correlator.
Sample devices 1020 is for carrying out sampling generation first sampled data according to sampling clock to testing data and sending to control appliance 1010.
Control appliance 1010 for described first sampled data being stored into each memory location of memory device 1030, and with each intersymbol distance of the synchronous code prestored for location interval, reads the second sampled data stored from respective memory locations every a location interval.
Control appliance 1010 also for the second sampled data described in control signal and each is transported to each associated assay devices 1040 respectively, wherein, carries the second sampled data read from a respective memory locations to an associated assay devices 1040.
Second sampled data described in each and the described synchronous code prestored are carried out XOR generate XOR result corresponding with each respective memory locations respectively for being responded described control signal by each associated assay devices 1040 respectively; Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively; Judge whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
The general correlator of present embodiment, with the distance between each adjacent two sections of associated codes of the synchronous code prestored for location interval reads the second sampled data stored from respective memory locations; Second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generates XOR result corresponding with each respective memory locations respectively; Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively; Corresponding synchronous relevantly to indicate is generated when different bit number mates to default error bit tolerance limit.The synchronous correlation of testing data and different multistage synchronous codes or multiclass synchronous code can be detected quickly and accurately by the distance upgraded between each adjacent two sections of associated codes of synchronous code of prestoring.
Wherein, for control appliance 1010, can be used for prestoring or configure various detected parameters, concrete parameter is as shown in table 1.
Table 1 general correlator configurable parameter table:
| Register address | Name | Type | Register Description |
| 00h | LLABS | R/W | Coordinate lower limit |
| 01h | ULABS | R/W | The coordinate upper limit |
| 02h | BET | R/W | Error bit tolerance limit |
| 03h | IET | R/W | Mistake relevant instruction number tolerance limit |
| 04h | SPACE | R/W | Intersymbol distance |
| 05h | ANT | R/W | Associated code hop count |
| 06h | MASK | R/W | Correlation type mask |
| 07h | LEN | R/W | Associated code length |
| 08h | RATE | R/W | Sampling rate |
| 09h | ABS | R | Relevant position |
| 0ah | IES | R | The relevant instruction statistics of mistake |
| 0bh | RES | R | Correlation type |
| 0ch | BES0 | R | Relevant misdirection bit number |
| … | BESn | R | Relevant misdirection bit number |
Wherein, described register address is 16 for system, and the coordinate figure only having relevant instruction to interrupt meets simultaneously just to be thought when being more than or equal to LLABS and being less than or equal to ULABS two conditions and receive synchronous code.
BET error bit tolerance limit: each relevant instruction produces the bit number allowing mistake.
IET mistake relevant instruction number tolerance limit: produce relevant instruction and interrupt needing at least continuously to produce (sampling clock number RATE-IET) relevant instruction in RATE sampling clock.
SPACE intersymbol distance: adjacent two sections of associated code spacings, the bit number from first bit of leading portion associated code to first bit of back segment associated code.
ANT associated code hop count: the hop count needing the associated code detected.
MASK correlation type mask: positive correlation, inverse correlation, positive inverse correlation all detect.
LEN associated code length: the length of every section of associated code.
RATE sampling rate: the sampling clock of synchronous code is relative to the multiple of data sampling clock.
ABS relevant position: receive the coordinate figure that relevant instruction is interrupted.
The relevant instruction statistics of IES mistake: the mistake of generation instruction number of being correlated with is sampling rate and the difference of the correct relevant number indicated.
RES correlation type: the type of the associated code received.Positive correlation is 1, and inverse correlation is 0.
BESn is correlated with misdirection bit number: each relevant instruction is relative to the error bit number of synchronous code.
For sample devices 1020, corresponding to the above sampling module 100.
For associated assay devices 1040, above-described XOR module 300, statistical module 400 and indicating module 500 can be comprised.The number of associated assay devices 1040 can be 8.
Preferably, each associated assay devices 1040 also can be used for:
By pipelining, the XOR result corresponding with each respective memory locations is divided into four groups of XOR results.
The identification information for identifying different bit between described second sampled data from the described synchronous code prestored is inquired about respectively from four groups of XOR results.
The number of the identification information of the different bits from four groups of XOR result queries is added, generates the different bit numbers corresponding from described respective memory locations.
For memory device 1030, preferably, can be dual port random access memory (random accessmemory, RAM).The access sequential of dual port random access memory as shown in Figure 9.
In one embodiment, general correlator of the present invention also comprises enabled devices as shown in Figure 10, for controlling the operating state of each associated assay devices 1040.Comparator is for being less than comparator, and the comparator being only less than or equal to described associated code hop count could export ' 1 ', enable corresponding associated assay devices 1040; Otherwise be 0, corresponding associated assay devices 1040 is enable to be closed.Close the associated assay devices 1040 do not needed, to save power consumption.
In another embodiment, general correlator of the present invention also comprises shift register, control appliance 1010 is for being cached to different shift registers respectively by the second sampled data described in each, wherein, described shift register with the maximum length of the described synchronous code prestored for columns, with the sampling rate of sampling to described testing data for line number, build shift LD matrix.
The data of each associated assay devices 1040 also for being exported by the output from each shift register are respectively carried out XOR with the described synchronous code prestored and are generated XOR result corresponding with each respective memory locations respectively.
General correlator of the present invention has good versatility and configurability.Allow checked object to be distributed on any number of continuous or discrete burst (Burst), or all concentrate in a burst; Adapt to any burst length; Allow associated code subsection setup, obtain the positive and negative correlated results of independent each section; Can to be correlated with fault-tolerant thresholding and correlation window etc. by arbitrary disposition.Be applicable to the demand of various narrow-band communication system and dedicated network, there is good application prospect.
The present invention allows time division multiplexing in systems in which, thus avoids the situation that needs multiple dedicated correlator simultaneously to work in a system.Same correlator can flexible configuration use in any time slot of arbitrary patterns, greatly saves hardware resource.
The configuration interface of correlator is very succinct, powers on to wake up and complete the time that configuration makes it normally required for work to be only several microsecond, has very important significance for the portable mobile apparatus tool paying close attention to energy saving.Correlator only needs operationally gap to be opened, and closes immediately, reach the object of energy saving after completing coherent detection.
The present invention is when exporting correlated results, and also export correlation intensity information, for monitor channel quality, and then it is significant to realize the technology such as channel width self adaptation, channel power self adaptation and channel frequency self adaptation simultaneously.
The following stated is the second execution mode of general correlator of the present invention.
The described general correlator of present embodiment and the difference of the first execution mode are: each associated assay devices 1040 also can be used for:
Relatively whether the different bit numbers corresponding from each respective memory locations are less than described default error bit tolerance limit.
If be less than, then corresponding described respective memory locations generates the instruction of corresponding synchronous positive correlation.
If be not less than, then the length of the described synchronous code prestored is deducted the different bit numbers corresponding from described respective memory locations, generate difference.
Whether more described difference is less than described default error bit tolerance limit.
If be less than, then corresponding described respective memory locations generates corresponding synchronous inverse correlation instruction.
Present embodiment, can generate corresponding relevant instruction fast.
Preferably, described in the length of synchronous code that prestores deduct the different bit numbers corresponding from described respective memory locations, be the number of same bits between the second sampled data of reading from described respective memory locations and the described synchronous code prestored.
Refer to Figure 11, Figure 11 is the structural representation of the 3rd execution mode of general correlator of the present invention.
The described general correlator of present embodiment and the difference of the second execution mode are: also comprise correlated judgment equipment 1050, for:
Judge whether there is synchronous relevant instruction corresponding to M respective memory locations in the sampled data of continuous K sampling clock sampling, wherein, M is to described the testing data sampling rate of sampling and the relevant difference indicating tolerance limit of mistake preset.
If so, then generate for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted.
Present embodiment, can reduce mistake relevant relevant with leakage.
In one embodiment, also comprise relevant position equipment, for generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate interrupt after:
Obtain described relevant instruction interrupt preset correlation window in position coordinates, described correlation window with frequency hopping burst trailing edge for initial point, with the rising edge of described sampling clock for scale, length in units of the cycle of described sampling clock.
With the Data Position of described testing data corresponding to described position coordinates for relevant position.
Present embodiment, can obtain the relevant position between synchronous code that testing data and institute's number prestore fast.
In another embodiment, also comprise Phase synchronization equipment, for generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate interrupt after:
If total number N of synchronous relevant instruction is even number, then the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase of N/2 sampling location with described testing data or N/2+1 sampling location.
If total number N of synchronous relevant instruction is odd number, the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase with a sampling location, (N+1)/2 of described testing data.
Present embodiment, can realize Phase synchronization fast.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (18)
1. a synchronizing information detection method, is characterized in that, comprises the following steps:
According to sampling clock, sampling generation first sampled data is carried out to testing data, and store described first sampled data;
Successively with each intersymbol distance of the synchronous code prestored for location interval, read the second sampled data stored from respective memory locations every a location interval, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore;
Second sampled data described in each is carried out XOR with the described synchronous code prestored respectively and generates XOR result corresponding with each respective memory locations respectively;
Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively;
Judge whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
2. synchronizing information detection method according to claim 1, it is characterized in that, store two system clock cycles of the memory time of described sampled data in distance after, successively with each intersymbol distance of the synchronous code prestored for location interval, every a location interval from respective memory locations read store the second sampled data.
3. synchronizing information detection method according to claim 1, it is characterized in that, the second sampled data described in each is carried out respectively the step that XOR generates XOR result corresponding with each respective memory locations respectively with the described synchronous code prestored and comprise the following steps:
Second sampled data described in each is cached to different shift registers respectively, wherein, described shift register for columns, with the sampling rate of sampling to described testing data for line number, builds shift LD matrix with the maximum length of the described synchronous code prestored;
Respectively the data that the output from each shift register exports are carried out XOR with the described synchronous code prestored and generate XOR result corresponding with each respective memory locations respectively.
4. synchronizing information detection method according to claim 1, it is characterized in that, obtain for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, the step generating different bit numbers corresponding from each respective memory locations is respectively further comprising the steps of:
By pipelining, the XOR result corresponding with each respective memory locations is divided into four groups of XOR results;
The identification information for identifying different bit between described second sampled data from the described synchronous code prestored is inquired about respectively from four groups of XOR results;
The number of the identification information of the different bits from four groups of XOR result queries is added, generates the different bit numbers corresponding from described respective memory locations.
5. synchronizing information detection method according to claim 1, it is characterized in that, judge whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then the step of the corresponding synchronous relevant instruction of corresponding each respective memory locations generation is further comprising the steps of respectively:
Relatively whether the different bit numbers corresponding from each respective memory locations are less than described default error bit tolerance limit;
If be less than, then corresponding described respective memory locations generates the instruction of corresponding synchronous positive correlation;
If be not less than, then the length of the described synchronous code prestored is deducted the different bit numbers corresponding from described respective memory locations, generate difference;
Whether more described difference is less than described default error bit tolerance limit;
If be less than, then corresponding described respective memory locations generates corresponding synchronous inverse correlation instruction.
6. synchronizing information detection method as claimed in any of claims 1 to 5, is characterized in that, after the step generating corresponding synchronous relevant instruction, further comprising the steps of:
Judge whether there is synchronous relevant instruction corresponding to M respective memory locations in the sampled data of continuous K sampling clock sampling, wherein, M is to described the testing data sampling rate of sampling and the relevant difference indicating tolerance limit of mistake preset;
If so, then generate for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted.
7. synchronizing information detection method according to claim 6, is characterized in that, generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate the step of interrupting after, further comprising the steps of:
Obtain described relevant instruction interrupt preset correlation window in position coordinates, described correlation window with frequency hopping burst trailing edge for initial point, with the rising edge of described sampling clock for scale, length in units of the cycle of described sampling clock;
With the Data Position of described testing data corresponding to described position coordinates for relevant position.
8. synchronizing information detection method according to claim 6, is characterized in that, generate for represent between described testing data to the described synchronous code prestored for correct relevant relevant indicate the step of interrupting after, further comprising the steps of:
If total number N of synchronous relevant instruction is even number, then the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase of N/2 sampling location with described testing data or N/2+1 sampling location;
If total number N of synchronous relevant instruction is odd number, the sampling pulse of sampling to described testing data is adjusted to the sampling clock same-phase with a sampling location, (N+1)/2 of described testing data.
9. a synchronizing information detection system, is characterized in that, comprising:
Sampling module, for carrying out sampling generation first sampled data according to sampling clock to testing data, and stores described first sampled data;
Read module, for successively with each intersymbol distance of the synchronous code prestored for location interval, read the second sampled data stored from respective memory locations every a location interval, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore;
XOR module, generates XOR result corresponding with each respective memory locations respectively for the second sampled data described in each is carried out XOR with the described synchronous code prestored respectively;
Statistical module, for obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generates different bit numbers corresponding from each respective memory locations respectively;
Indicating module, for judging whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
10. synchronizing information detection system according to claim 9, is characterized in that, described indicating module also for:
Relatively whether the different bit numbers corresponding from each respective memory locations are less than described default error bit tolerance limit;
If be less than, then corresponding described respective memory locations generates the instruction of corresponding synchronous positive correlation;
If be not less than, then the length of the described synchronous code prestored is deducted the different bit numbers corresponding from described respective memory locations, generate difference;
Whether more described difference is less than described default error bit tolerance limit;
If be less than, then corresponding described respective memory locations generates corresponding synchronous inverse correlation instruction.
11. synchronizing information detection systems according to claim 9 or 10, is characterized in that, also comprise correlated judgment module, for:
Judge whether there is synchronous relevant instruction corresponding to M respective memory locations in the sampled data of continuous K sampling clock sampling, wherein, M is to described the testing data sampling rate of sampling and the relevant difference indicating tolerance limit of mistake preset;
If so, then generate for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted.
12. 1 kinds of general correlators, it is characterized in that, comprise the sampling clock that prestores, oversampling clock rate, synchronous code, each intersymbol Distance geometry control appliance of presetting error bit tolerance limit of synchronous code and the system clock that is connected with described control appliance respectively and generate equipment, sample devices, memory device and at least two associated assay devices, described intersymbol distance for described in distance between the adjacent two sections of associated codes of synchronous code that prestore, wherein:
Described system clock generates equipment for generating the system clock of general correlator;
Described sample devices is used for carrying out sampling generation first sampled data according to sampling clock to testing data and sending to described control appliance;
Described control appliance is used for each memory location described first sampled data being stored into described memory device, and with each intersymbol distance of the synchronous code prestored for location interval, reads the second sampled data stored every a location interval from respective memory locations;
Described control appliance also for the second sampled data described in control signal and each is transported to each associated assay devices respectively, wherein, carries the second sampled data read from a respective memory locations to an associated assay devices;
Second sampled data described in each and the described synchronous code prestored are carried out XOR generate XOR result corresponding with each respective memory locations respectively for being responded described control signal by each associated assay devices respectively; Obtaining for identifying the number summation of the identification information of different bit between described second sampled data from the described synchronous code prestored in each XOR result respectively, generating different bit numbers corresponding from each respective memory locations respectively; Judge whether the different bit number corresponding from each respective memory locations mates with default error bit tolerance limit respectively, if coupling, then corresponding each respective memory locations generates corresponding synchronous relevant instruction respectively.
13. general correlators according to claim 12, it is characterized in that, also comprise shift register, described control appliance is used for the second sampled data described in each to be cached to described shift register respectively, wherein, described shift register for columns, with the sampling rate of sampling to described testing data for line number, builds shift LD matrix with the maximum length of the described synchronous code prestored;
The data of each associated assay devices also for being exported by the output from described shift register are respectively carried out XOR with the described synchronous code prestored and are generated XOR result corresponding with each respective memory locations respectively.
14. general correlators according to claim 12, is characterized in that, each described associated assay devices also for:
By pipelining, the XOR result corresponding with each respective memory locations is divided into four groups of XOR results;
The identification information for identifying different bit between described second sampled data from the described synchronous code prestored is inquired about respectively from four groups of XOR results;
The number of the identification information of the different bits from four groups of XOR result queries is added, generates the different bit numbers corresponding from described respective memory locations.
15. general correlators according to claim 12, is characterized in that, each described associated assay devices also for:
Relatively whether the different bit numbers corresponding from each respective memory locations are less than described default error bit tolerance limit;
If be less than, then corresponding described respective memory locations generates the instruction of corresponding synchronous positive correlation;
If be not less than, then the length of the described synchronous code prestored is deducted the different bit numbers corresponding from described respective memory locations, generate difference;
Whether more described difference is less than described default error bit tolerance limit;
If be less than, then corresponding described respective memory locations generates corresponding synchronous inverse correlation instruction.
16. general correlators according to claim 12, is characterized in that, described memory device is dual port random access memory.
17., according to claim 12 to the general correlator described in any one in 16, is characterized in that, also comprise correlated judgment equipment, for:
Judge whether there is synchronous relevant instruction corresponding to M respective memory locations in the sampled data of continuous K sampling clock sampling, wherein, M is to described the testing data sampling rate of sampling and the relevant difference indicating tolerance limit of mistake preset;
If so, then generate for representing between described testing data to the described synchronous code prestored for correct relevant relevant instruction is interrupted.
18. general correlators according to claim 17, it is characterized in that, also comprise relevant position equipment, the position coordinates in the correlation window preset is interrupted for obtaining described relevant instruction, described correlation window with frequency hopping burst trailing edge for initial point, with the rising edge of described sampling clock for scale, length in units of the cycle of described sampling clock; With the Data Position of described testing data corresponding to described position coordinates for relevant position.
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