CN109842575A - A kind of big tolerance sample circuit of 429 bus receiving nodes - Google Patents
A kind of big tolerance sample circuit of 429 bus receiving nodes Download PDFInfo
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- CN109842575A CN109842575A CN201711212086.4A CN201711212086A CN109842575A CN 109842575 A CN109842575 A CN 109842575A CN 201711212086 A CN201711212086 A CN 201711212086A CN 109842575 A CN109842575 A CN 109842575A
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Abstract
The present invention relates to a kind of sample circuits, the in particular to a kind of big tolerance sample circuit of 429 bus receiving nodes.A kind of big tolerance sample circuit of 429 bus receiving nodes is provided, is solved in the prior art since the clock of sending node and receiving node has deviation, caused by sampled data mistake technical problem.Using the intermediate time of each data bit received from 429 buses as data sampling point, the data to be sampled after synchronizing are sampled by the sampled point.
Description
Technical field
The present invention relates to a kind of sample circuits, the in particular to a kind of big tolerance sample circuit of 429 bus receiving nodes.
Background technique
429 buses have structure simple as a kind of serial data bus in aviation field, and performance is stablized, anti-interference
The advantages that property is strong.In practical applications, since the clock of sending node and receiving node has deviation, baud rate cannot reach reason
Want to be worth, receiving node such as calculates sampled point according to the fixed sampling point clock of this section point and goes sampled data, it will leads to sample error.
Summary of the invention
The purpose of the present invention: providing a kind of big tolerance sample circuit of 429 bus receiving nodes, solve in the prior art due to
The clock of sending node and receiving node have deviation, caused by sampled data mistake technical problem.
Technical solution of the present invention: a kind of big tolerance sample circuit of 429 bus receiving nodes, it is characterized in that: it will be total from 429
The intermediate time for each data bit that line receives as data sampling point, by the sampled point to the data to be sampled after synchronizing into
Row sampling.
Preferably, the sample circuit includes synchronizer module, receives sampled data module and sampled point computing module；
Received data bit and effective indicating bit are synchronized to 429 bus receiving node local clock domains by synchronizer module,
And effective indicating bit data are transmitted to shift register module, when sampled point computing module calculates the centre of each data bit
It carves, and exports sampling instruction at the moment, reception sampled data module is instructed according to the sampling and carried out to the data bit after synchronizing
Sampling.
Preferably, shift register can be used in the sampled point computing module or counter is realized.
Beneficial effects of the present invention: there is provided herein a kind of big tolerance sample circuit of 429 bus receiving nodes, the circuit is logical
It crosses and dynamic calculating is carried out to sampled point, can meet under a certain range baud rate deviation, it is total to receive sending node normal use 429
Line communication, carries out accurate data transmission.
Detailed description of the invention
Fig. 1 is the logic diagram of the embodiment of the present invention one；
Fig. 2 is circuit sampling timing diagram of the present invention.
Specific embodiment
In the following with reference to the drawings and specific embodiments, technical solution of the present invention is clearly and completely stated.Obviously,
The embodiment stated is only a part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention,
Those skilled in the art are not making creative work premise every other embodiment obtained, belong to guarantor of the invention
Protect range.
With a kind of big tolerance sample circuit of 429 bus receiving nodes, for attached drawing 1, Fig. 2, embodiment one: including different
Or door module, synchronizer module, reception sampled data module, sampled point computing module, data buffer storage fifo module, in which:
XOR gate module input 429 receiving end dina/dinb of connection, output signal " din " are given synchronizer a, are used to indicate
Valid data are received from 429 buses；
Synchronizer a is used for " din " signal that will input and is synchronized to receiving node local clock domain, and output signal " rx " is to adopting
Sampling point computing module, wherein " rx " effectively N number of clock cycle；
" dina " signal that synchronizer b is used to input is synchronized to receiving node local clock domain, exports data to be sampled
Signal " ria ", which arrives, receives sampled data module；
Sampled point computing module is realized using shift register, since receiving " rx " signal of input effectively, Mei Geshi
" rx " signal is moved one by the clock period, when " rx " signal is displaced to N/2, exports sampling command signal " rx_ at the moment
en"；
Sampled data module is received to be used to sample data-signal to be sampled when sampling command signal " rx_en " effectively
" ria ", and data buffer storage fifo module is written into sampled result；
Data buffer storage fifo module is used to save from the next sampled result of sampled data module transfer is received, for subsequent conditioning circuit
Using.
Embodiment two: XOR gate module, receives sampled data module, the same example of data buffer storage fifo module at synchronizer module
One, sampled point computing module samples timer and realizes, since receiving " rx " signal of input effectively, each clock cycle timing
Device increases " 1 ", when counter is equal to N/2, exports sampling command signal " rx_en " at the moment.
Finally it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that；It still may be used
To modify to the technical solution that foregoing embodiments are recorded or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit and model of technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution
It encloses.
Claims (3)
1. a kind of big tolerance sample circuit of 429 bus receiving nodes, it is characterized in that: each data that will be received from 429 buses
The intermediate time of position samples the data to be sampled after synchronizing by the sampled point as data sampling point.
2. the big tolerance sample circuit of a kind of 429 bus receiving node according to claim 1, it is characterized in that: described adopts
Sample circuit includes synchronizer module, receives sampled data module and sampled point computing module；
Received data bit and effective indicating bit are synchronized to 429 bus receiving node local clock domains by synchronizer module, and will
Effective indicating bit data are transmitted to shift register module, and sampled point computing module calculates the intermediate time of each data bit, and
Sampling instruction is exported at the moment, sampled data module is received and the data bit after synchronizing is sampled according to sampling instruction.
3. the big tolerance sample circuit of a kind of 429 bus receiving node according to claim 2, it is characterized in that: described adopts
Shift register can be used in sampling point computing module or counter is realized.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711212086.4A CN109842575B (en) | 2017-11-27 | 2017-11-27 | 429 bus receiving node large-tolerance sampling circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711212086.4A CN109842575B (en) | 2017-11-27 | 2017-11-27 | 429 bus receiving node large-tolerance sampling circuit |
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| CN109842575A true CN109842575A (en) | 2019-06-04 |
| CN109842575B CN109842575B (en) | 2021-08-03 |
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Effective date of registration: 20221009 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710000 Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |