CN113726706B - Method, device and storage medium for improving demodulation precision of D8PSK signal - Google Patents
Method, device and storage medium for improving demodulation precision of D8PSK signal Download PDFInfo
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Abstract
The application discloses a method, a device and a storage medium for improving the demodulation precision of a D8PSK signal, relates to the technical field of signal demodulation, and solves the problems of slow frequency offset estimation time, long synchronization time and large algorithm consumption resource in the prior art, and the method comprises the following steps: acquiring an intermediate frequency sampling signal and performing down-conversion treatment to determine a zero intermediate frequency signal; eliminating inherent phase difference, generating a relative phase, determining I, Q paths of zero phase difference signals, sampling the signals, determining I, Q paths of sampling signals, obtaining a plurality of sine and cosine values corresponding to synchronous sequence signals, performing correlation calculation with I, Q paths of sampling signals, determining a plurality of I, Q paths of correlation values, and calculating average value and synchronous time; on the compensation related value data I, Q paths of zero phase difference signals, performing arctangent calculation to determine an angle value; sampling the angle value, and outputting binary code elements of the angle value; the method realizes the saving of algorithm resources and improves the angle resolving precision.
Description
Technical Field
The present disclosure relates to the field of signal demodulation technologies, and in particular, to a method, an apparatus, and a storage medium for improving demodulation accuracy of a D8PSK signal.
Background
The very high frequency data broadcast signal is based on 8-way differential phase shift keying modulated burst signal, and the D8PSK signal belongs to a multi-system dependent keying signal, and the currently adopted method comprises coherent demodulation, differential demodulation and the like. The differential demodulation mode does not need to be locally generated on the carrier waves with strict same frequency and same direction at the transmitting end, and is relatively easy to realize. Coherent demodulation requires the generation of a coherent carrier wave of the same frequency and phase, and the multiplication of the coherent carrier wave with a received intermediate frequency signal to recover a baseband signal.
However, the frequency deviation of the receiving end is not considered in the implementation process of the differential demodulation, and the correct demodulation cannot be realized under the condition of large frequency deviation. At present, a VDB signal adopts a coherent demodulation mode, frequency offset is estimated through a training sequence at the front end of the signal in the demodulation process, and frequency offset compensation is carried out on a local carrier, so that the method is frequently calculated, the calculation process is complicated, and the demodulation precision is affected by errors in the calculation process.
Disclosure of Invention
The embodiment of the application solves the problems of slow frequency offset estimation time, long synchronization time and large algorithm consumption resource in the prior art by providing the method, the device and the storage medium for improving the demodulation precision of the D8PSK signal, realizes the saving of algorithm resources and improves the angle resolving precision.
In a first aspect, an embodiment of the present invention provides a method for improving demodulation accuracy of a D8PSK signal, where the method includes:
acquiring an intermediate frequency sampling signal;
performing down-conversion treatment on the intermediate frequency sampling signal to determine a zero intermediate frequency signal;
the inherent phase difference in the zero intermediate frequency signal is eliminated, a relative phase is generated, and an I-path zero phase difference signal and a Q-path zero phase difference signal are determined;
sampling the I-path zero phase difference signal and the Q-path zero phase difference signal to determine an I-path sampling signal and a Q-path sampling signal;
acquiring a plurality of sine and cosine values corresponding to a synchronous sequence signal, and respectively carrying out correlation calculation on the sine and cosine values, the I-path sampling signal and the Q-path sampling signal to determine a plurality of I-path correlation values and a plurality of Q-path correlation values;
calculating the average value of a plurality of I-path correlation values, and determining the peak time of the average value as the synchronous time;
according to the phase of the synchronous moment, compensating the data of the I-path correlation value and the Q-path correlation value to the I-path zero phase difference signal and the Q-path zero phase difference signal, and determining an I-path compensation signal and a Q-path compensation signal;
performing arctangent calculation on the I path compensation signal and the Q path compensation signal to determine an angle value;
sampling the angle value, and outputting binary code symbols of the angle value.
With reference to the first aspect, in a possible implementation manner, the performing a down-conversion processing on the intermediate frequency sampling signal includes: and mixing the local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter.
With reference to the first aspect, in a possible implementation manner, the removing the phase difference inherent in the zero intermediate frequency signal, generating a relative phase includes:
delaying the intermediate frequency sampling signal and the local carrier signal by one code element period;
mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period;
the phase in the zero intermediate frequency signal delayed by one symbol period is determined as the relative phase.
With reference to the first aspect, in a possible implementation manner, the determining an I-path zero phase difference signal and a Q-path zero phase difference signal includes: and performing cross product dot product operation on the zero intermediate frequency signal.
With reference to the first aspect, in one possible implementation manner, the determining the I-path sampling signal and the Q-path sampling signal includes: and extracting the I-path zero phase difference signal and the Q-path zero phase difference signal by 100 times.
With reference to the first aspect, in one possible implementation manner, the calculating the average value of the I-path correlation value includes determining whether the synchronization sequence signal is aligned with the I-path sampling signal, and when the determination result is aligned, summing according to the I-path correlation value to obtain an average value, and determining the average value.
In a second aspect, an embodiment of the present invention provides an apparatus for improving demodulation accuracy of a D8PSK signal, where the apparatus includes:
the signal acquisition module is used for acquiring an intermediate frequency sampling signal;
the signal down-conversion module is used for performing down-conversion processing on the intermediate frequency sampling signal and determining a zero intermediate frequency signal;
the signal zero phase difference calculation module is used for eliminating inherent phase differences in the zero intermediate frequency signals, generating relative phases and determining I paths of zero phase difference signals and Q paths of zero phase difference signals;
the signal sampling module is used for sampling the I-path zero phase difference signal and the Q-path zero phase difference signal and determining an I-path sampling signal and a Q-path sampling signal;
the correlation value calculation module is used for obtaining a plurality of sine and cosine values corresponding to the synchronous sequence signals, carrying out correlation calculation on the sine and cosine values, the I-path sampling signals and the Q-path sampling signals respectively, and determining a plurality of I-path correlation values and a plurality of Q-path correlation values;
the average value determining module is used for calculating the average value of the plurality of I-path correlation values and determining the peak value moment of the average value as the synchronous moment;
the compensation module is used for compensating the I-path correlation value and the Q-path correlation value data to the I-path zero phase difference signal and the Q-path zero phase difference signal according to the phase of the synchronous moment, and determining an I-path compensation signal and a Q-path compensation signal;
the calculation module is used for performing arctangent calculation on the I-path compensation signal and the Q-path compensation signal to determine an angle value;
and the output module is used for sampling the angle value and outputting binary code elements of the angle value.
With reference to the second aspect, in one possible implementation manner, the signal down-conversion module is configured to: and mixing the local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter.
With reference to the second aspect, in one possible implementation manner, the signal zero phase difference calculating module is configured to eliminate a phase difference inherent in the zero intermediate frequency signal, and generate a relative phase, including:
delaying the intermediate frequency sampling signal and the local carrier signal by one code element period;
mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period;
the phase in the zero intermediate frequency signal delayed by one symbol period is determined as the relative phase.
With reference to the second aspect, in one possible implementation manner, the signal zero phase difference calculating module is configured to determine an I-path zero phase difference signal and a Q-path zero phase difference signal, and includes: and performing cross product dot product operation on the zero intermediate frequency signal.
With reference to the second aspect, in one possible implementation manner, the signal sampling module is configured to determine an I-path sampling signal and a Q-path sampling signal, including: and extracting the I-path zero phase difference signal and the Q-path zero phase difference signal by 100 times.
With reference to the second aspect, in one possible implementation manner, the mean value determining module is configured to calculate a mean value of the I-path correlation values, and includes determining whether the synchronization sequence signal is aligned with the I-path sampling signal, and when the determination result is aligned, summing and taking a mean value according to the I-path correlation values, and determining the mean value.
In a third aspect, an embodiment of the present invention provides a server for improving demodulation accuracy of a D8PSK signal, including a memory and a processor;
the memory is used for storing computer executable instructions;
the processor is configured to execute the computer-executable instructions to implement the method of the first aspect.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium storing executable instructions that when executed by a computer implement the method of the first aspect.
One or more technical solutions provided in the embodiments of the present invention at least have the following technical effects or advantages:
the embodiment of the invention adopts a method for improving the demodulation precision of the D8PSK signal, and the method comprises the steps of obtaining an intermediate frequency sampling signal; performing down-conversion treatment on the intermediate frequency sampling signal to determine a zero intermediate frequency signal; the inherent phase difference in the zero intermediate frequency signal is eliminated, a relative phase is generated, and an I-path zero phase difference signal and a Q-path zero phase difference signal are determined; sampling the I-path zero phase difference signal and the Q-path zero phase difference signal to determine an I-path sampling signal and a Q-path sampling signal; acquiring a plurality of sine and cosine values corresponding to the synchronous sequence signals, and respectively carrying out correlation calculation on the sine and cosine values, the I-path sampling signals and the Q-path sampling signals to determine a plurality of I-path correlation values and a plurality of Q-path correlation values; calculating the average value of the plurality of I-path correlation values, and determining the peak time of the average value as the synchronous time; according to the phase of the synchronous moment, compensating the data of the I-path correlation value and the Q-path correlation value to the I-path zero phase difference signal and the Q-path zero phase difference signal, and determining an I-path compensation signal and a Q-path compensation signal; performing arctangent calculation on the I path compensation signal and the Q path compensation signal to determine an angle value; the angle value is sampled and binary code elements are output, so that the problems of slow frequency offset estimation time, long synchronization time and large algorithm consumption resource in the prior art are effectively solved, the algorithm resource is saved, and the angle resolving precision is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments of the present invention or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of method steps for improving demodulation accuracy of a D8PSK signal according to an embodiment of the present application;
fig. 2 is a schematic diagram of an apparatus for improving demodulation accuracy of a D8PSK signal according to an embodiment of the present application;
fig. 3 is a schematic diagram of a server for improving demodulation accuracy of a D8PSK signal according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A Local Area Augmentation System (LAAS) is an augmentation system that is capable of providing high-precision positioning of a global positioning system within a local area. The basic working principle of the LAAS is that a reference station is set up at a known place with accurate position, error enhancement information (comprising ranging information and differential correction information) is calculated for GPS constellation signals within the receivable range of the reference station and is sent out in a broadcast mode, after an approaching aircraft receives a very high frequency broadcast signal through a VDB receiver, the signal is used in the receiver to calibrate the ranging and differential calculation results, and therefore the positioning performance of the airborne GPS receiver is improved.
The VDB is a burst signal modulated based on 8-ary Differential8-Phase shift keying (D8 PSK). The data transmission rate is 10500 symbols/s, binary data is firstly combined into characters during encoding, each character consists of 3 continuous binary data, and then the characters are converted into D8PSK modulation signals.
At present, considering carrier frequency deviation existing in the receiving process, a coherent demodulation method is generally adopted in engineering to demodulate a VDB signal, a local carrier wave in a local physiological ideal state is generated, and an input intermediate frequency signal is multiplied by the local carrier wave to obtain an I signal and a Q signal; respectively carrying out low-pass filtering on the I, Q two paths of signals to finish digital down-conversion and generate baseband signals with frequency offset, and carrying out cross product and dot product calculation on the two paths of baseband signals to eliminate the phase difference of the symbols before and after the two paths of baseband signals and generate relative phases; then, performing autocorrelation calculation on the I/Q two paths and a local 48-bit synchronous code, capturing a maximum correlation peak value, and performing frame synchronization positioning; performing cross product point product calculation to obtain a phase angle to obtain frequency offset to compensate a local carrier wave when frame synchronization positioning is successful; and finally, sampling judgment is carried out to obtain binary values. The prior art has the problems of slow medium frequency offset estimation time, long synchronization time and high algorithm resource consumption.
Based on the above-mentioned problems, the embodiment of the present invention provides a method for improving the demodulation accuracy of a D8PSK signal, as shown in fig. 1, which includes the following steps.
Step S101, an intermediate frequency sampling signal is acquired.
Step S102, performing down-conversion processing on the intermediate frequency sampling signal to determine a zero intermediate frequency signal.
And step S103, eliminating inherent phase difference in the zero intermediate frequency signal, generating a relative phase, and determining an I-path zero phase difference signal and a Q-path zero phase difference signal.
And step S104, sampling the I-path zero phase difference signal and the Q-path zero phase difference signal to determine an I-path sampling signal and a Q-path sampling signal.
Step S105, a plurality of sine and cosine values corresponding to the synchronous sequence signal are obtained, and the sine and cosine values are respectively subjected to correlation calculation with the I-path sampling signal and the Q-path sampling signal to determine a plurality of I-path correlation values and a plurality of Q-path correlation values.
Step S106, calculating an average value of the plurality of I-path correlation values, and determining the peak time of the average value as the synchronization time.
And step S107, compensating the I-path correlation value and the Q-path correlation value data to the I-path zero phase difference signal and the Q-path zero phase difference signal according to the phase of the synchronous moment, and determining an I-path compensation signal and a Q-path compensation signal.
And S108, performing arctangent calculation on the I-path compensation signal and the Q-path compensation signal, and determining an angle value.
Step S109, sampling the angle value and outputting binary code element of the angle value.
The invention provides a method for improving the demodulation precision of a D8PSK signal, which can finish frame synchronization, bit synchronization and frequency offset estimation within 48 code element time, meets the requirement of a signal to noise ratio of more than 15dB and a ten thousandth bit error rate of large dynamic range change of-90 dB to 0dbm, and solves the problems of slow frequency offset estimation time, long synchronization time, high algorithm consumption resource and the like in the prior art. In the method, on frame synchronization judgment: in the traditional method, after the correlation operation is carried out on the two paths of I/Q and the synchronous sequence, the minimum mean square error is solved, and the moment of judging the minimum value is the synchronous moment. In the invention, the judgment of frame synchronization can be completed by using only I-path signals.
Frequency offset compensation algorithm: according to the traditional method, the phase value is obtained by calculating the inverse tangent through the values of the two paths of the I/Q at the synchronous moment, and then the deviation compensation is calculated and is carried out to the local DDS, so that the frequency correction is carried out. The algorithm is huge in calculation amount, and the accuracy of the final phase angle is affected. The algorithm directly compensates the value of the synchronous moment I\Q to the signal to perform angle calculation through trigonometric function operation, reduces the calculated amount and improves the angle calculation precision.
In step S102, down-conversion processing is performed on the intermediate frequency sampling signal, including: the local carrier signal is mixed with the intermediate frequency sampling signal and then input into the low-pass filter.
In this application, the intermediate frequency sampling signal is denoted as:
wherein f 1 For the frequency of the VDB signal,is the initial phase.
In step S103, the elimination of the inherent phase difference in the zero intermediate frequency signal, resulting in a relative phase, includes:
the intermediate frequency sampling signal and the local carrier signal are both delayed by one symbol period. The intermediate frequency sampling signal delayed by one symbol period is mixed and low-pass filtered using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period. The phase in the zero intermediate frequency signal delayed by one symbol period is determined as the relative phase.
The input signal delayed by one symbol period is:
where T is the symbol period,is the initial phase.
The local carrier signal is:
through mixing and low-pass filtering:
in step S103, determining an I-way zero phase difference signal and a Q-way zero phase difference signal includes: and performing cross product dot product operation on the zero intermediate frequency signal.
For the above-described calculation process, the process,
the following is obtained:
the phase offset of the signal after time delay difference is a fixed value on each character due to frequency offset, namely 2 pi delta fT, so that the influence of the frequency offset on the synchronization effect can be eliminated.
In step S104, determining the I-way sampling signal and the Q-way sampling signal includes: and extracting the I-path zero phase difference signal and the Q-path zero phase difference signal by 100 times.
The sampling frequency of 2.1M is adopted for sampling, the subsequent calculation amount is huge, and logic calculation resources are seriously consumed, so that 100 times of extraction is carried out on the I-path zero phase difference signal and the Q-path zero phase difference signal. The extraction of 100 times is to extract one sampling point for every 100 sampling points of the I-path zero phase difference signal and the Q-path zero phase difference signal, so that the calculation amount is reduced and the calculation result is not influenced. Of course, the extraction of 100 times is a preferred scheme provided in this embodiment, and the extraction of 100 times can be performed as required.
Combining the calculation, solving a plurality of sine and cosine values to determine a plurality of I-path correlation values and a plurality of Q-path correlation values; the following is a detailed synchronization algorithm for demodulating the signal.
The local training sequence is:
correlating zero intermediate frequency signal with local training sequence
According to the trigonometric function principle, when the received signal is fully synchronized with the local training sequence, i.e. in the above formula,the I-path sample signal reaches a peak value.
At this time:
I＝cos(2πΔfT)
Q＝sin(2πΔfT)
in step S106, calculating the average value of the I-channel correlation values includes determining whether the synchronization sequence signal is aligned with the I-channel sampling signal, and when the determination result is aligned, summing the I-channel correlation values to obtain the average value, and determining the average value.
The burst detection and the frame synchronization can be completed by detecting the I-path correlation peak value, and the optimal sampling point is obtained according to the position of the correlation peak, namely, the bit synchronization is realized while the correlation peak is captured, so that the burst detection, the frame synchronization and the bit synchronization are realized simultaneously through a group of synchronization code elements.
After the bit synchronization, the frequency offset must be estimated and corrected due to the existence of the frequency offset, and according to the calculation, the phase of I, Q is a fixed value, the fixed value is 2pi fT, and the fixed value is closely related to the frequency offset of the system, so that the frequency offset can be compensated through I, Q two paths of values. I.e.
Determination of arctangent
Phase decisions are made by the constellation diagram.
The embodiment of the invention provides a device for improving demodulation precision of a D8PSK signal, and as shown in fig. 2, the device 200 comprises: the signal acquisition module 201: for obtaining intermediate frequency sampling signals. Signal down-conversion module 202: the method is used for carrying out down-conversion processing on the intermediate frequency sampling signal and determining a zero intermediate frequency signal. Signal zero phase difference calculation module 203: the method is used for eliminating inherent phase difference in zero intermediate frequency signals, generating relative phases and determining I-path zero phase difference signals and Q-path zero phase difference signals. Signal sampling module 204: the sampling device is used for sampling the I-path zero phase difference signal and the Q-path zero phase difference signal and determining the I-path sampling signal and the Q-path sampling signal. The correlation value calculation module 205: and the method is used for acquiring a plurality of sine and cosine values corresponding to the synchronous sequence signals, respectively carrying out correlation calculation on the sine and cosine values and the I-path sampling signals and the Q-path sampling signals, and determining a plurality of I-path correlation values and a plurality of Q-path correlation values. The mean determination module 206: the method is used for calculating the average value of the plurality of I-path correlation values and determining the peak time of the average value as the synchronous time. Compensation module 207: and the phase compensation circuit is used for compensating the I-path correlation value and the Q-path correlation value data to the I-path zero phase difference signal and the Q-path zero phase difference signal according to the phase of the synchronous moment, and determining an I-path compensation signal and a Q-path compensation signal. The calculation module 208: and the device is used for performing arctangent calculation on the I-path compensation signal and the Q-path compensation signal to determine an angle value. The output module 209: the binary code symbol output device is used for sampling the angle value and outputting the binary code symbol of the angle value.
In the device for improving the demodulation precision of the D8PSK signal, the following two aspects are different innovation points: on the frame synchronization judgment: in the traditional method, after the correlation operation is carried out on the two paths of I/Q and the synchronous sequence, the minimum mean square error is solved, and the moment of judging the minimum value is the synchronous moment. In the invention, the judgment of frame synchronization can be completed by using only I-path signals.
Frequency offset compensation algorithm: according to the traditional method, the phase value is obtained by calculating the inverse tangent through the values of the two paths of the I/Q at the synchronous moment, and then the deviation compensation is calculated and is carried out to the local DDS, so that the frequency correction is carried out. The algorithm is huge in calculation amount, and the accuracy of the final phase angle is affected. The algorithm directly compensates the value of the synchronous moment I\Q to the signal to perform angle calculation through trigonometric function operation, reduces the calculated amount and improves the angle calculation precision.
The signal down-conversion module 202 is used to: the local carrier signal is mixed with the intermediate frequency sampling signal and then input into the low-pass filter. The local carrier signal of 525K is preferably adopted in the signal down-conversion module, mixed with the input intermediate frequency sampling signal and then subjected to low-pass filtering, a Kessel window function filtering function is preferably adopted, the passband is 0.03MHz, the cut-off frequency is 0.3MHz, and the filter coefficient is quantized by 16 bits. After this step, a zero intermediate frequency signal can be generated.
The signal zero phase difference calculating module 203 is configured to eliminate an inherent phase difference in the zero intermediate frequency signal, and generate a relative phase, including: delaying both the intermediate frequency sampling signal and the local carrier signal by one symbol period; mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period; the phase in the zero intermediate frequency signal delayed by one symbol period is determined as the relative phase.
The signal zero phase difference calculating module 203 is configured to determine an I-path zero phase difference signal and a Q-path zero phase difference signal, and includes: and performing cross product dot product operation on the zero intermediate frequency signal.
The signal sampling module 204 is configured to determine an I-way sampling signal and a Q-way sampling signal, including: and extracting the I-path zero phase difference signal and the Q-path zero phase difference signal by 100 times.
The average value determining module 206 is configured to calculate an average value of the I-channel correlation values, and includes determining whether the synchronization sequence signal is aligned with the I-channel sampling signal, and summing the I-channel correlation values to determine an average value when the synchronization sequence signal is aligned with the I-channel sampling signal.
The embodiment of the invention provides a server for improving the demodulation precision of a D8PSK signal, which comprises a memory 301 and a processor 302 as shown in fig. 3; memory 301 is used to store computer executable instructions; processor 302 is configured to perform a method for improving the demodulation accuracy of a D8PSK signal.
The embodiment of the invention provides a computer readable storage medium, wherein the computer readable storage medium stores executable instructions, and a method for improving the demodulation precision of a D8PSK signal can be executed by a computer.
The storage medium includes, but is not limited to, a random access Memory (English: random Access Memory; RAM), a Read-Only Memory (ROM), a Cache Memory (English: cache), a Hard Disk (English: hard Disk Drive; HDD), or a Memory Card (English: memory Card). The memory may be used to store computer program instructions.
Although the present application provides method operational steps as described in the examples or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive labor. The order of steps recited in the present embodiment is only one way of performing the steps in a plurality of steps, and does not represent a unique order of execution. When implemented by an actual device or client product, the method of the present embodiment or the accompanying drawings may be performed sequentially or in parallel (e.g., in a parallel processor or a multithreaded environment).
The apparatus or module set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. For convenience of description, the above devices are described as being functionally divided into various modules, respectively. The functions of the various modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present application. Of course, a module that implements a certain function may be implemented by a plurality of sub-modules or a combination of sub-units.
The methods, apparatus or modules described herein may be implemented in computer readable program code means and in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (english: application Specific Integrated Circuit; abbreviated: ASIC), programmable logic controllers and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller can be regarded as a hardware component, and means for implementing various functions included therein can also be regarded as a structure within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.
Some of the modules of the apparatus described herein may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
From the description of the embodiments above, it will be apparent to those skilled in the art that the present application may be implemented in software plus necessary hardware. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product, or may be embodied in the implementation of data migration. The computer software product may be stored on a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., comprising instructions for causing a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to perform the methods described in various embodiments or portions of embodiments herein.
In this specification, each embodiment is described in a progressive manner, and the same or similar parts of each embodiment are referred to each other, and each embodiment is mainly described as a difference from other embodiments. All or portions of the present application can be used in a number of general purpose or special purpose computer system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the present application; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions.
Claims (5)
1. A method for improving demodulation accuracy of a D8PSK signal, comprising:
acquiring an intermediate frequency sampling signal;
performing down-conversion treatment on the intermediate frequency sampling signal to determine a zero intermediate frequency signal;
the down-conversion processing is performed on the intermediate frequency sampling signal, including: mixing a local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter;
the inherent phase difference in the zero intermediate frequency signal is eliminated, a relative phase is generated, and an I-path zero phase difference signal and a Q-path zero phase difference signal are determined;
the determining the I-path zero phase difference signal and the Q-path zero phase difference signal comprises the following steps: performing cross product dot product operation on the zero intermediate frequency signal;
the intermediate frequency sampling signal is recorded as:
wherein f 1 For the frequency of the VDB signal,is the initial phase;
eliminating the inherent phase difference in the zero intermediate frequency signal, producing a relative phase, comprising:
delaying the intermediate frequency sampling signal and the local carrier signal by one symbol period, mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period, and determining the phase in the zero intermediate frequency signal delayed by one symbol period as a relative phase;
the input signal delayed by one symbol period is:
where T is the symbol period,is the initial phase;
the local carrier signal is:
through mixing and low-pass filtering:
the process is carried out by the steps of,
the following is obtained:
the phase offset of the signal after time delay difference caused by the frequency offset is a fixed value on each character, namely 2 pi delta fT;
sampling the I-path zero phase difference signal and the Q-path zero phase difference signal to determine an I-path sampling signal and a Q-path sampling signal;
the determining the I-way sampling signal and the Q-way sampling signal includes: extracting 100 times of the I-path zero phase difference signal and the Q-path zero phase difference signal;
acquiring a plurality of sine and cosine values corresponding to a synchronous sequence signal, and respectively carrying out correlation calculation on the sine and cosine values, the I-path sampling signal and the Q-path sampling signal to determine a plurality of I-path correlation values and a plurality of Q-path correlation values;
combining the calculation, solving a plurality of sine and cosine values to determine a plurality of I-path correlation values and a plurality of Q-path correlation values; the following is a detailed synchronization algorithm for demodulating signals;
the local training sequence is:
correlating the zero intermediate frequency signal with a local training sequence:
according to the trigonometric function principle, when the received signal is fully synchronized with the local training sequence, i.e. in the above formula,the sampling signal of the I path reaches a peak value;
at this time:calculating the average value of a plurality of I-path correlation values, and determining the peak time of the average value as the synchronous time;
according to the phase of the synchronous moment, compensating the data of the I-path correlation value and the Q-path correlation value to the I-path zero phase difference signal and the Q-path zero phase difference signal, and determining an I-path compensation signal and a Q-path compensation signal;
compensating frequency offset through I, Q two paths of values; i.e.
Performing arctangent calculation on the I path compensation signal and the Q path compensation signal to determine an angle value;
sampling the angle value, and outputting binary code symbols of the angle value.
2. The method of claim 1, wherein calculating the average of the I-way correlation values includes determining whether the synchronization sequence signal is aligned with the I-way sampling signal, and summing the average according to the I-way correlation values when the determination is aligned, and determining the average.
3. An apparatus for improving demodulation accuracy of a D8PSK signal, comprising:
the signal acquisition module is used for acquiring an intermediate frequency sampling signal;
the signal down-conversion module is used for performing down-conversion processing on the intermediate frequency sampling signal and determining a zero intermediate frequency signal;
the down-conversion processing is performed on the intermediate frequency sampling signal, including: mixing a local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter; the signal zero phase difference calculation module is used for eliminating inherent phase differences in the zero intermediate frequency signals, generating relative phases and determining I paths of zero phase difference signals and Q paths of zero phase difference signals;
the determining the I-path zero phase difference signal and the Q-path zero phase difference signal comprises the following steps: performing cross product dot product operation on the zero intermediate frequency signal;
the intermediate frequency sampling signal is recorded as:
wherein f 1 For the frequency of the VDB signal,is the initial phase;
eliminating the inherent phase difference in the zero intermediate frequency signal, producing a relative phase, comprising:
delaying the intermediate frequency sampling signal and the local carrier signal by one symbol period, mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period, and determining the phase in the zero intermediate frequency signal delayed by one symbol period as a relative phase;
the input signal delayed by one symbol period is:
where T is the symbol period,is the initial phase;
the local carrier signal is:
through mixing and low-pass filtering:
the process is carried out by the steps of,the following is obtained:
the phase offset of the signal after time delay difference caused by the frequency offset is a fixed value on each character, namely 2 pi delta fT;
the signal sampling module is used for sampling the I-path zero phase difference signal and the Q-path zero phase difference signal and determining an I-path sampling signal and a Q-path sampling signal;
the determining the I-way sampling signal and the Q-way sampling signal includes: extracting 100 times of the I-path zero phase difference signal and the Q-path zero phase difference signal; the correlation value calculation module is used for obtaining a plurality of sine and cosine values corresponding to the synchronous sequence signals, carrying out correlation calculation on the sine and cosine values, the I-path sampling signals and the Q-path sampling signals respectively, and determining a plurality of I-path correlation values and a plurality of Q-path correlation values;
combining the calculation, solving a plurality of sine and cosine values to determine a plurality of I-path correlation values and a plurality of Q-path correlation values; the following is a detailed synchronization algorithm for demodulating signals;
the local training sequence is:
correlating the zero intermediate frequency signal with a local training sequence:
according to the trigonometric function principle, when the received signal is fully synchronized with the local training sequence, i.e. in the above formula,the sampling signal of the I path reaches a peak value;
at this time:the average value determining module is used for calculating the average value of the plurality of I-path correlation values and determining the peak value moment of the average value as the synchronous moment;
the compensation module is used for compensating the I-path correlation value and the Q-path correlation value data to the I-path zero phase difference signal and the Q-path zero phase difference signal according to the phase of the synchronous moment, and determining an I-path compensation signal and a Q-path compensation signal;
compensating frequency offset through I, Q two paths of values; i.e.
The calculation module is used for performing arctangent calculation on the I-path compensation signal and the Q-path compensation signal to determine an angle value;
and the output module is used for sampling the angle value and outputting binary code elements of the angle value.
4. The server for improving the demodulation precision of the D8PSK signal is characterized by comprising a memory and a processor;
the memory is used for storing computer executable instructions;
the processor is configured to execute the computer-executable instructions to implement the method of any of claims 1-2.
5. A computer readable storage medium storing executable instructions which when executed by a computer enable the method of any one of claims 1-2 to be carried out.
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