WO2021121064A1 - 显示组件、显示装置、数据信号显示方法及传输方法 - Google Patents

显示组件、显示装置、数据信号显示方法及传输方法 Download PDF

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Publication number
WO2021121064A1
WO2021121064A1 PCT/CN2020/134238 CN2020134238W WO2021121064A1 WO 2021121064 A1 WO2021121064 A1 WO 2021121064A1 CN 2020134238 W CN2020134238 W CN 2020134238W WO 2021121064 A1 WO2021121064 A1 WO 2021121064A1
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Prior art keywords
pixel data
data
row
display
timing controller
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PCT/CN2020/134238
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English (en)
French (fr)
Inventor
朱敏
Original Assignee
京东方科技集团股份有限公司
高创(苏州)电子有限公司
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Priority to US17/433,825 priority Critical patent/US11532256B2/en
Publication of WO2021121064A1 publication Critical patent/WO2021121064A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/22—Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display assembly, a display device, a data signal display method and a transmission method.
  • a signal source (Source) device such as a graphics card or a host outputs a signal to a display device.
  • the main control chip (Scaler) inside the display device receives the signal, it decodes the signal, and then, according to the main control chip and timing control
  • the connection interface protocol between the devices is re-encoded and output to the timing controller; the timing controller then controls the signal output of the gate drive circuit and the data drive circuit.
  • a display assembly including K timing controllers, K data driving circuits, and a display panel.
  • Each of the K timing controllers is configured to receive one set of pixel data in the K sets of pixel data divided by the i-th row of pixel data in one frame of image data, and different timing controllers receive different sets of pixel data ;
  • K is a positive integer greater than or equal to 2, i ⁇ 1,2,3, ⁇ ,n ⁇ , n is a positive integer greater than or equal to 1; one of the K data driving circuits and K so
  • the timing controller is connected to a corresponding timing controller;
  • the data driving circuit is configured to receive a set of pixel data from the corresponding timing controller and output a set of data voltages;
  • the display panel is connected to the K
  • the data driving circuit is electrically connected, and is configured to receive and display K groups of data voltages output by the K data driving circuits.
  • the display component further includes a gate driving circuit.
  • the gate drive circuit is electrically connected to one of the K timing controllers and the display panel; the timing controller is also configured to transmit a control signal to the gate drive circuit, and the gate drive The circuit is configured to output a gate scan signal to the display panel according to the received control signal from the timing controller, so that the gate line connected to the pixel in the i-th row in the display panel receives the gate.
  • the pixels in the i-th row receive the K groups of data voltages and display them.
  • the timing controller includes a first eDp interface configured to receive one of the K groups of pixel data divided by the i-th row of pixel data in one frame of image data Pixel data.
  • the timing controller further includes a first buffer; the first buffer is configured to store a set of pixel data received by the timing controller.
  • the display panel includes a display area, the display area is divided into K sub-areas along the row direction of pixels in the display panel, and all pixels in each sub-area are related to the K data driving circuits.
  • a data driving circuit of is electrically connected; the timing controller further includes a memory configured to store the number of pixels in the i-th row in a sub-region corresponding to the timing controller.
  • a display device which includes the display assembly and the main control chip of any one of the above-mentioned embodiments.
  • the main control chip includes a processor; the processor is configured to receive the image data, divide the i-th row of pixel data into K groups of pixel data, and transmit the K groups of pixel data to the display assembly at the same time The K timing controllers.
  • the main control chip includes K second buffers; the i-th row of pixel data includes M pixel data; the processor is further configured to: Every S pixel data from the 1st pixel data to the Mth pixel data is sequentially stored in the first second buffer to the K-1th second buffer; (K-1) ⁇ S ⁇ M ⁇ K ⁇ S; S and M are both positive integers; S pixel data in each buffer from the first second buffer to the K-1th second buffer constitutes a group Pixel data; and, storing the M-(K-1) ⁇ S pixel data to the M-th pixel data in the i-th row of pixel data in the K-th second buffer.
  • the processor is further configured to generate S-[M-(K-1) ⁇ S] pieces of virtual pixel data, and convert the S-[M-(K-1) ⁇ S] Pieces of virtual pixel data are stored in the K-th second buffer; the M-(K-1) ⁇ S-th pixel data in the K-th second buffer to the M-th pixel data and S- [M-(K-1) ⁇ S] pieces of virtual pixel data constitute a group of pixel data.
  • the main control chip further includes K second eDp interfaces, each of the K timing controllers includes a first eDp interface; A second eDp interface is connected to the first eDp interface of one of the K timing controllers; the processor is also configured to pass a set of pixel data in the K sets of pixel data through all One of the K second eDp interfaces is output to the first eDp interface of the corresponding timing controller.
  • the display panel includes a display area, the display area is divided into K sub-areas along the row direction of pixels in the display panel, and all pixels in each sub-area are related to the K data driving circuits.
  • the timing controller includes a memory configured to store the number of pixels in the i-th row in a sub-region corresponding to the timing controller; the processor is further configured to be electrically connected to a data driving circuit of In order to read the number of pixels in the i-th row in a sub-region corresponding to the timing controller stored in each timing controller, so that the processor will match the number of pixels in the i-th row according to the number of pixels in the i-th row.
  • the pixel data of the i-th row corresponding to the pixels of the i-th row is divided into K groups of pixel data.
  • the memory is further configured to store display configuration data of the timing controller, the display configuration data being the number of channels and the transmission rate of each channel; the processor is also configured to read The display configuration data is obtained, and the state of the first eDp interface of the timing controller is obtained according to the display configuration data.
  • the processor is further configured to receive a hot plug detection signal from each of the K timing controllers to confirm that each of the timing controllers and the master Whether the control chip is connected.
  • a data signal display method including: a display panel receives K groups of data voltages output by the K data driving circuits and displays them; wherein, each group of data voltages in the K groups of data voltages is Each of the K data driving circuits outputs according to a group of pixel data received from a corresponding timing controller, and the group of pixel data is a group of pixel data in the K groups of pixel data.
  • the display assembly further includes a gate driving circuit electrically connected to one of the K timing controllers and the display panel; the method further includes : The gate line connected to the i-th row of pixels in the display panel receives the gate scan signal from the gate driving circuit, so that when the gate line connected to the i-th row of pixels receives the gate scan signal , The pixels in the i-th row receive the K groups of data voltages and display them.
  • the gate scan signal is output by the gate drive circuit according to the received control signal from the timing controller connected to the gate drive circuit, and the control signal of the timing controller is based on the K The state of K-1 timing controllers other than the timing controller in the timing controller is output.
  • a data signal transmission method including: the processor receives the image data, divides the pixel data of the i-th row into K groups of pixel data, and simultaneously transmits the K groups of pixel data to all The K timing controllers in the display assembly.
  • the main control chip includes K second buffers; the i-th row of pixel data includes M pixel data; the method further includes: the processor converts the i-th row of pixel data Each S pixel data from the 1st pixel data to the Mth pixel data are sequentially stored in the first second buffer to the K-1th second buffer; the first The S pixel data in each second buffer from the second buffer to the K-1th second buffer constitutes a set of pixel data; the processor converts the Mth row of pixel data in the i-th row of pixel data -(K-1) ⁇ S pixel data to the Mth pixel data are stored in the Kth second buffer.
  • the method further includes: the processor generates S-[M-(K-1) ⁇ S] pieces of virtual pixel data, and the S-[M-(K-1) ⁇ S] pieces of virtual pixel data are stored in the Kth second buffer.
  • the display panel includes a display area, the display area is divided into K sub-areas along the row direction of pixels in the display panel, and all pixels in each sub-area are related to the K data driving circuits.
  • the timing controller includes a memory configured to store the number of pixels in the i-th row in a sub-region corresponding to the timing controller;
  • the method further includes: The processor reads the number of pixels of a row in a sub-region corresponding to the timing controller stored in each timing controller, so that the processor corresponds to each timing controller according to the read The number of pixels in the i-th row in a sub-region of, divides the pixel data of the i-th row corresponding to the pixels in the i-th row into K groups of pixel data.
  • the timing controller includes a memory; the memory is configured to store display configuration data of the timing controller, the display configuration data being the number of channels and the transmission rate of each channel; the The method further includes: the processor reads the display configuration data, and obtains the state of the first eDp interface of the timing controller according to the display configuration data.
  • the method further includes: the processor receives a hot plug detection signal from each of the K timing controllers, and confirms the hot plug detection signal according to the hot plug detection signal. Whether the timing controller is connected to the main control chip.
  • Fig. 1 is a schematic structural diagram of a display assembly according to some embodiments
  • 2A is a schematic structural diagram of another display assembly according to some embodiments.
  • FIG. 2B is a schematic structural diagram of still another display assembly according to some embodiments.
  • 2C is a schematic structural diagram of still another display assembly according to some embodiments.
  • FIG. 3 is a schematic structural diagram of still another display assembly according to some embodiments.
  • FIG. 4 is a schematic structural diagram of still another display assembly according to some embodiments.
  • FIG. 5 is a schematic structural diagram of a display device according to some embodiments.
  • FIG. 6 is a schematic structural diagram of another display device according to some embodiments.
  • FIG. 7 is a schematic structural diagram of still another display device according to some embodiments.
  • FIG. 8 is a schematic structural diagram of still another display device according to some embodiments.
  • FIG. 9 is a schematic flowchart of a data signal transmission method according to some embodiments.
  • FIG. 10 is a schematic flowchart of another data signal transmission method according to some embodiments.
  • FIG. 11 is a schematic structural diagram of a display system according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity.
  • the exemplary embodiments of the present disclosure should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • Some embodiments of the present disclosure provide a display assembly 10, as shown in FIG. 1, including: K timing controllers 11, K data driving circuits, and a display panel.
  • Each of the K timing controllers 11 is configured to receive one set of pixel data in K sets of pixel data (Data) divided by pixel data of the i-th row in one frame of image data, and different timing controllers Receive different sets of pixel data.
  • K is a positive integer greater than or equal to 2
  • i ⁇ 1,2,3,...,n ⁇ , n is a positive integer greater than or equal to 1.
  • the pixel data of the i-th row in a frame of image data is divided into K groups of pixel data, the first timing controller 11 receives the first group of pixel data, the second timing controller 11 receives the second group of pixel data, and so on , The Kth timing controller 11 receives the Kth group of pixel data.
  • the pixel data of the i-th row is any row of pixel data in one frame of image data.
  • each group of pixel data in the K groups of pixel data includes the same number of pixel data.
  • each timing controller 11 receives the corresponding set of pixel data for the same duration.
  • the timing controller 11 corresponding to the group that includes more pixel data takes a longer time to receive one group of pixel data, but includes fewer pixels.
  • the timing controller 11 corresponding to the data group receives a group of pixel data for a relatively short period of time. In this way, before receiving the pixel data of the next row, that is, before receiving the pixel data of the i+1th row, there will be a waiting gap, which leads to the problem of pixel data loss. Therefore, the number of pixel data in each group of pixel data is the same, which can avoid the problem of pixel data loss due to different reception time lengths.
  • one data driving circuit 12 of the K data driving circuits 12 is connected to a corresponding one of the K timing controllers 11, and each data driving circuit 12 is configured to receive a corresponding timing
  • the controller 11 outputs a set of pixel data according to the set of pixel data and outputs a set of data voltages.
  • the first data driving circuit 12 is connected to the first timing controller 11, and the first data driving circuit 12 receives the first set of pixel data from the first timing controller 11, and according to the set of pixel data, Output the first group of data voltage.
  • the second data driving circuit 12 is connected to the second timing controller 11, and the second data driving circuit 12 receives the second set of pixel data from the second timing controller 11, and outputs the second set of pixel data according to the set of pixel data. Group data voltage.
  • the K-th data driving circuit 12 is connected to the K-th timing controller 11, and the K-th data driving circuit 12 receives the K-th group of pixel data from the K-th timing controller 11, and according to the group of pixel data, Output the data voltage of the Kth group.
  • each timing controller 11 in addition to receiving a corresponding set of pixel data, each timing controller 11 also receives a vertical synchronization signal VS, a horizontal synchronization signal HS, and a data enable signal DE.
  • the timing controller 11 controls the corresponding data driving circuit 12 according to the vertical synchronization signal VS, the horizontal synchronization signal HS, and the data enable signal DE, so that the data driving circuit 12 outputs a set of pixel data from the corresponding timing controller 11 Group data voltage.
  • the display panel 14 is electrically connected to K data driving circuits.
  • the display panel 14 is configured to receive and display K groups of data voltages output by the K data driving circuits 12.
  • the display panel 14 includes multiple rows of pixels.
  • the display panel 14 displays one frame of image data
  • the i-th row of pixels of the display panel 14 displays the i-th row of pixel data in the aforementioned one frame of image data.
  • the display assembly 10 provided by the embodiment of the present disclosure includes K timing controllers 11, K data driving circuits 12 and a display panel 14.
  • a plurality of timing controllers 11 respectively receive one set of pixel data in the K sets of pixel data divided by the pixel data of the i-th row in one frame of image data, so that high bandwidth can be transmitted under the condition of limited bandwidth in the transmission technology. Pixel data.
  • the display assembly 10 further includes a gate driving circuit 13.
  • the gate driving circuit 13 is electrically connected to one of the K timing controllers 11 and the display panel 14.
  • the timing controller 11 is also configured to transmit a control signal to the gate drive circuit 13
  • the gate drive circuit 13 is configured to transmit control signals to the gate drive circuit 13 according to the received control signal from the timing controller 11 connected to the gate drive circuit 13.
  • the display panel 14 outputs a gate scan signal so that when the gate line connected to the i-th row of pixels in the display panel 14 receives the gate scan signal, the i-th row of the display panel 14 receives K data driving circuits K groups of data voltage and display.
  • control signal from the timing controller 11 connected to the gate drive circuit 13 is: the timing controller 11 connected to the gate drive circuit 13 according to the K timing controllers 11 other than the timing controller 11
  • the state of the other K-1 timing controllers 11 is output.
  • the display assembly 10 includes two timing controllers 11 (denoted as TCON1 and TCON2, respectively), and two data driving circuits 12 (denoted as DDRV1 and DDRV2, respectively).
  • TCON1 is connected to DDRV1
  • TCON2 is connected to DDRV2
  • the gate drive circuit 13 is connected to TCON1.
  • TCON1 outputs a control signal according to the state of TCON2 to control the gate drive circuit 13, that is, the gate drive circuit 13 outputs a gate scan signal to the display panel 14 according to the control signal.
  • the gate drive circuit 13 can also be connected to TCON2. Based on this, similar to the connection between the gate drive circuit 13 and TCON1 described above, TCON2 outputs a control signal according to the state of TCON1 to control the gate drive circuit 13.
  • TCON1 includes two ports and TCON2 includes two ports.
  • the ports of TCON1 and TCON2 are connected in pairs to form two connection lines L 12 and L 21.
  • L 12 is configured to transmit a signal indicating the state of TCON1 to TCON2.
  • L 21 is configured to transmit a signal indicating the state of TCON2 to TCON1.
  • the port is, for example, a pin of the timing controller 11.
  • the pixel data of the i-th row is divided into 2 groups of pixel data, TCON1 receives the first group of pixel data, and TCON2 receives the second group of pixel data; and the gate drive circuit 13 is connected to TCON1 as an example, S11-S14 are provided for clear explanation TCON1 controls the gate drive circuit (SDRV) process according to the state of TCON2.
  • SDRV gate drive circuit
  • TCON2 After TCON2 outputs all the received second group of pixel data to DDRV2, TCON2 sends a high-level signal to TCON1 through L 21;
  • TCON1 responds to the received high-level signal from TCON2 and determines that all the pixel data of the first group has been output to DDRV1, and outputs a control signal to SDRV, so that SDRV responds to receiving the control signal to the display panel 14 output a gate scan signal; so that when the gate line connected to the i-th row of pixels in the display panel 14 receives the gate scan signal, the i-th row of pixels receives the first set of data voltages from DDRV1 and from DDRV2 The second group of data voltages; that is, the pixel data of the i-th row has been transmitted to the display panel 14.
  • TCON2 response to receiving the high level signal from TCON1 transmits a low level signal to the L 21 TCON1.
  • TCON2 After TCON2 outputs the second group of pixel data divided by the pixel data of the i+1th row to DDRV2, it sends a high-level signal to TCON1 through L 21, and so on.
  • the duration of the high-level signal can be prevented from being too short and TCON2 cannot detect it.
  • the gate drive circuit 13 is connected to TCON2, the process of TCON2 outputting a control signal to control the gate drive circuit 13 according to the state of TCON1 is similar to the above S11-S14, and will not be repeated here.
  • the display assembly 10 includes three timing controllers 11 (denoted as TCON1, TCON2, and TCON3, respectively), and three data driving circuits (denoted as DDRV1, DDRV2, and DDRV3, respectively).
  • TCON1 is connected to DDRV1
  • TCON2 is connected to DDRV2
  • TCON3 is connected to DDRV3
  • the gate drive circuit 13 is connected to TCON1.
  • TCON1 outputs a control signal according to the states of TCON2 and TCON3 to control the gate drive circuit 13, that is, the gate drive circuit 13 outputs a gate scan signal to the display panel 14 according to the control signal.
  • the gate driving circuit 13 may also be connected to TCON2 or TCON3, which is not limited in the embodiment of the present disclosure.
  • the gate drive circuit 13 is connected to TCON3.
  • TCON3 Based on this, similar to the connection of the gate drive circuit 13 to TCON1 described above, TCON3 outputs control signals according to the states of TCON1 and TCON2 to control the gate drive circuit 13.
  • the gate drive circuit 13 is connected to TCON2. Based on this, similar to the connection of the gate drive circuit 13 to TCON1 described above, TCON2 outputs control signals according to the states of TCON1 and TCON3 to control the gate drive circuit 13.
  • TCON1 includes two ports
  • TCON2 includes four ports
  • TCON3 includes two ports.
  • the ports of TCON1 and TCON2 are connected in pairs to form two connection lines L 12 and L 21.
  • L 12 is configured to transmit a signal indicating the state of TCON1 to TCON2
  • L 21 is configured to transmit a signal indicating the state of TCON2 to TCON1.
  • the ports of TCON2 and TCON3 are connected in pairs to form two connection lines L 23 and L 32.
  • L 23 is configured to transmit a signal indicating the state of TCON2 to TCON3
  • L 32 is configured to transmit a signal indicating the state of TCON3 to TCON2.
  • each port is, for example, a pin of each timing controller 11.
  • the pixel data of the i-th row is divided into 3 groups of pixel data.
  • TCON1 receives the first group of pixel data
  • TCON2 receives the second group of pixel data
  • TCON3 receives the third group of pixel data; and the gate drive circuit 13 is connected to TCON1 as an example.
  • S21-S26 are provided to clearly illustrate the process of TCON1 controlling SDRV according to the status of TCON2 and TCON3.
  • TCON3 After S21 and TCON3 output all the received third group of pixel data to DDRV3, TCON3 sends a high-level signal to TCON2 through L 32.
  • TCON2 received to DDRV2, in response to receiving the high level signal from TCON3 transmits a high level signal to the TCON1 through L 21.
  • TCON1 responds to the received high-level signal from TCON2 and determines that all the first group of pixel data has been output to DDRV1, and outputs a control signal to SDRV, so that SDRV responds to receiving the control signal to the display panel 14 output a gate scan signal; so that when the gate line connected to the i-th row of pixels in the display panel 14 receives the gate scan signal, the i-th row of pixels receives the first set of data voltages from DDRV1 and the data from DDRV2 The second set of data voltages and the third set of data voltages from DDRV3; that is, the pixel data of the i-th row has been transmitted to the display panel 14.
  • TCON2 responds to the received high-level signal from TCON1 and sends a high-level signal for a period of time to TCON3 through L 23 , and then sends a low-level signal to inform TCON3 that the pixel data of the i-th row has been sent; at the same time, Send a low-level signal to TCON1 through L 21.
  • TCON3 In response to the received high-level signal from TCON2, TCON3 sends a low-level signal to TCON2 through L 32. After TCON3 outputs the third group of pixel data divided by the pixel data of the i+1th row to DDRV3, it sends a high-level signal to TCON2 through L 32, and so on.
  • TCON2 in S25 sends a high-level signal for a period of time to TCON3 through L 23.
  • the duration of the high-level signal is half of the duration of TCON2 transmitting the second group of pixel data divided by the pixel data of the i-th row to DDRV2. ; In this way, it can prevent the duration of the high-level signal from being too short, which cannot be detected by TCON2 and TCON3.
  • the display assembly 10 includes K timing controllers 11 (respectively denoted as TCON1, TCON2,..., TCONK) and K data driving circuits (respectively denoted as DDRV1, DDRV2,..., DDRVK).
  • TCON1 is connected to DDRV1
  • TCON2 is connected to DDRV2
  • TCONK is connected to DDRVK
  • the gate drive circuit 13 is connected to TCON1.
  • TCON1 outputs a control signal according to the states of TCON2 to TCONK to control the gate drive circuit 13, that is, the gate drive circuit 13 outputs a gate scan signal to the display panel 14 according to the control signal.
  • each timing controller 11 includes a first eDp (Embedded Display Port) interface 102.
  • Each first eDp interface 102 is configured to receive one group of pixel data among the K groups of pixel data divided by the pixel data of the i-th row in one frame of image data.
  • the first eDp interface 102 of the first timing controller 11 receives the first group of pixel data among the K groups of pixel data divided into the i-th row of pixel data in one frame of image data
  • the second timing controller 11 The first eDp interface 102 receives the second group of pixel data among the K groups of pixel data divided by the pixel data of the i-th row in one frame of image data.
  • the first eDP interface 102 includes 4 channels (Lane), the transmission rate in each Lane is one of 1.62Gbps, 2.7Gbps and 5.4Gbps, and the transmission rate in the Lane is controlled by a clock signal, for example , When the frequency of the clock signal is A, the transmission rate in the corresponding Lane is 1.62Gbps.
  • one channel, two channels, or four channels can be selected according to actual needs (when multiple channels are used for transmission, the transmission rate in each channel is the same) for data transmission to support the corresponding Resolution.
  • the first eDP interface 102 of each timing controller 11 in the embodiment of the present disclosure selects 4 channels, and the transmission rate of each channel is 5.4 Gbps, so as to meet the bandwidth requirement for transmitting one frame of image data.
  • each timing controller 11 further includes a first buffer (as shown by B1 in FIG. 4).
  • Each first buffer 101 is configured to store a set of pixel data received by the corresponding timing controller 11. That is, each first buffer 101 is configured to store a set of pixel data received by the first eDp interface 102 of the corresponding timing controller 11.
  • the first buffer of the first timing controller 11 is configured to store the K groups received by the first eDp interface 102 of the first timing controller 11 and divided by the pixel data of the i-th row in one frame of image data
  • the first group of pixel data in the pixel data, the first buffer of the second timing controller 11 is configured and stored as the i-th group of image data received by the first eDp interface 102 of the second timing controller 11
  • the display panel 14 includes a display area.
  • the display area is divided into K sub-areas 104 along the row direction of the pixels in the display panel 14.
  • One data driving circuit 12 in the data driving circuit is electrically connected.
  • K data driving circuits 12 are connected to K groups of data lines 15, and each group of data lines 15 corresponds to multiple columns of pixels connected to one of the K sub-areas 104; one data driving circuit 12 passes a group of data voltages through The connected set of data lines 15 are transmitted to the corresponding multiple columns of pixels in the i-th row of pixels of the display panel 14, so that the multiple columns of pixels display a set of pixel data corresponding to the set of data voltages, so that the K sets of pixels The data is displayed one by one at different positions of the i-th row of pixels.
  • each timing controller 11 further includes a memory, and the memory is configured to store the number of pixels in the i-th row in a sub-region 104 corresponding to the timing controller 11.
  • the number of pixels in the i-th row in each of the K sub-regions 104 is equal.
  • the number of pixels in the i-th row in each of the K sub-regions 104 is not completely equal.
  • not completely equal can be understood as: the number of pixels in the i-th row in the partial sub-region 104 is equal, and the number of pixels in the i-th row in the partial sub-region 104 is not equal.
  • the number of pixels in the i-th row in the first sub-region 104 to the K-1 sub-region 104 is equal
  • the number of pixels in the i-th row in the K-th sub-region 104 is equal to the number of pixels in the i-th row in the first sub-region 104.
  • the numbers are not equal.
  • the memory in each timing controller is also configured to store the display configuration data (Display Port Configuration Data, DPCD) of the timing controller, and the display configuration data includes the number of channels of the first eDp interface and each The transmission rate of the channel.
  • DPCD Display Port Configuration Data
  • the display device 2 includes a main control chip 20 and a display assembly 10 as in any of the above-mentioned embodiments.
  • the main control chip 20 includes a processor.
  • the processor is configured to receive the aforementioned one frame of image data, divide the i-th row of pixel data in the one frame of image data into K groups of pixel data, and transmit the K groups of pixel data to the K timing controllers in the display assembly 10 at the same time .
  • the processor receives a frame of image data by first receiving the first row of pixel data, then the second row of pixel data, and so on, until the last row of pixel data in the frame of image data is received.
  • the processor first receives the first pixel data in the row of pixel data, and then receives the second pixel number in the row of pixel data, and so on, until The last pixel data in the row of pixel data has been received. Therefore, the processor divides the pixel data of the i-th row into K groups of pixel data while receiving the pixel data of the i-th row.
  • the received first pixel data to the Sth pixel data are divided into the first group of pixel data, and the received S+1th pixel data to the 2Sth pixel data are divided into the second group of pixel data. That is to say, when the processor receives the pixel data of the i-th row, it completes the process of dividing the pixel data of the i-th row into K groups of pixel data, and then simultaneously outputs the K groups of pixel data to the corresponding ones in the display component 10. Timing controller 11.
  • the display device 2 provided by the embodiment of the present disclosure divides the pixel data of the i-th row into K groups of pixel data, and sends the K groups of pixel data to the display component 10 at the same time, so that the transmission can be higher when the bandwidth is limited in the transmission technology. Bandwidth pixel data.
  • the main control chip 20 includes K second buffers 201 (shown as B2 in FIG. 6). It is assumed that the pixel data of the i-th row includes M pixel data.
  • the processor is further configured to: sequentially store every S pixel data from the 1st pixel data to the Mth pixel data in the i-th row of pixel data into the first second buffer 201 to the K-1th pixel data.
  • the S pixel data in each buffer from the first second buffer to the K-1th second buffer constitutes a set of pixel data, that is, the first second buffer
  • the S pixel data of is the first group of pixel data divided by the pixel data of the i-th row
  • the S pixel data in the second second buffer is the second group of pixels divided by the pixel data of the i-th row.
  • the S pixel data in the K-1 second buffer is the K-1 group of pixel data divided by the pixel data of the i-th row as described above.
  • the processor is further configured to store the M-(K-1) ⁇ S pixel data to the M-th pixel data in the i-th row of pixel data in the K-th second buffer 201.
  • the processor is further configured to: generate S-[M-(K-1) ⁇ S] virtual pixel data, and convert S-[M-(K-1) ⁇ S] virtual pixel data Stored in the Kth second buffer 201. That is, the M-(K-1) ⁇ S pixel data to the M-th pixel data and S-[M-(K-1) ⁇ S] virtual pixel data in the K-th second buffer A group of pixel data is formed, that is, the above-mentioned K-th group of pixel data divided by the pixel data of the i-th row.
  • the processor generates the above-mentioned S-[M-(K-1) ⁇ S] virtual pixel data according to the situation of dividing the pixel data of the i-th row into K groups of pixel data.
  • the S-[M-(K-1) ⁇ S] virtual pixel data stored in the Kth second buffer 201 is not used for display.
  • the resolution of the display panel 14 is 3440 ⁇ 1440, and the display of the display panel 14 is divided into two sub-areas.
  • the display assembly 10 includes two timing controllers 11, if the widths of the sub-regions of the display panel controlled by the two timing controllers 11 (L area and R area as shown in FIG. 7) are both 1720, That is, the number of pixels in the i-th row in each sub-region is 1720.
  • the processor divides the pixel data of the i-th row equally and stores it in the corresponding second buffer 201, that is, stores the pixel data from the first pixel data to the 1720th pixel data in the pixel data of the i-th row into the first pixel data.
  • the 1721th to 3440th pixel data are stored in the second second buffer 201.
  • the display area of the display panel 14 is divided into two sub-areas, and the widths of the sub-areas of the display panels controlled by the two timing controllers 11 are both 1728, but not equal to half of the bandwidth of the display panel 14.
  • the processor divides the pixel data of the i-th row into two sets of pixel data.
  • the first set of pixel data includes 1728 pixel data
  • the second set of pixel data includes 1712 pixel data.
  • the processor transmits the two sets of pixel data to the timing controller 11, the transmission time of the two sets of pixel data is different, and the problem of pixel data loss may occur.
  • the processor generates 16 virtual pixel data, and stores the 16 virtual pixel data in the second second buffer 201 at the end of the second group of pixel data, so that each of the pixel data included in the two groups of pixel data
  • the number is the same, the transmission time is the same, and the problem of pixel data loss during the transmission process is avoided.
  • the main control chip 20 further includes K second eDp interfaces 202.
  • One second eDp interface 202 of the K second eDp interfaces 202 is connected to the first eDp interface 102 of one of the K timing controllers 11.
  • the first second eDp interface 202 in the main control chip 20 is connected to the first eDp interface 102 of the first timing controller 11 in the display assembly 10.
  • the second second eDp interface 202 in the main control chip 20 is connected to the first eDp interface 102 of the second timing controller 11 in the display assembly 10.
  • the processor is further configured to output one set of pixel data in the K sets of pixel data divided by the pixel data of the i-th row to the corresponding timing controller 11 through one of the K second eDp interfaces 202.
  • the processor is further configured to read the i-th row of pixels in a sub-region 104 corresponding to the timing controller 11 stored in each timing controller 11 through an auxiliary channel (Auxiliary, AUX). According to the number of pixels in the i-th row, the processor divides the pixel data of the i-th row corresponding to the pixels in the i-th row into K groups of pixel data.
  • auxiliary channel Auxiliary, AUX
  • the processor is also configured to read the extended display identification data (EDID) of the display panel 14 through AUX.
  • EDID includes basic parameters of the performance of each display component 10, such as manufacturer identification code and product identification code. , Manufacturing time, maximum display size, color settings, frequency limits and supported resolutions.
  • the display capability of the display panel 14 is acquired by acquiring the extended display identification data, so that the main control chip 20 outputs data matching the extended display identification data to the display assembly 10 so that it can be displayed normally.
  • each timing controller 11 corresponds to the number of pixels in the i-th row in the sub-region 104 of the display panel 14 and the number of pixels corresponding to each sub-region.
  • the processor may not read the number of pixels in the i-th row in a sub-area 104 corresponding to the timing controller 11 stored in each timing controller 11, and the main control chip 20 may directly According to the agreed information, the pixel data of the i-th row is correspondingly divided and transmitted to the corresponding timing controller 11 in the display component 10. In this way, the display speed of the display panel for displaying the pixel data of the i-th row can be accelerated.
  • the processor is further configured to read the DPCD of each timing controller through AUX, and obtain the state of the first eDp interface 102 of the timing controller 11 according to the read DPCD.
  • acquiring the status of the first eDp interface 102 of the timing controller 11 refers to confirming the transmission parameters of the first eDp interface 102, such as the number of channels, the transmission rate, voltage swing, pre-emphasis, equalization, and clock recovery of each channel. Wait.
  • the processor calculates the total bandwidth currently supported by the timing controller 11 by multiplying the number of channels read by the transmission rate of each channel; generally, the transmission rate of each channel is equal.
  • the processor can read DPCD through AUX multiple times to prevent fools.
  • the processor is further configured to receive a hot plug detection signal (Hot-Plug Detect, HPD) from each of the K timing controllers 11 in the display assembly 10 to confirm each Whether each timing controller 11 is connected to the main control chip 20.
  • a hot plug detection signal Het-Plug Detect, HPD
  • the processor receiving the hot plug detection signal from each timing controller 11 is: the processor receives the hot plug detection signal from the first eDp interface 102 of each timing controller 11 through the second eDp interface 202 .
  • a hot plug detection signal from a timing controller 11 if the processor responds to the received hot plug detection signal as a low level signal, it will confirm the corresponding timing controller 11 and the main control chip 20. Not connected, at this time, the handshake process between the main control chip 20 and the timing controller 11 will not proceed. If the processor responds to the received hot plug detection signal as a high-level signal, and before receiving the high-level signal, the received low-level signal lasts for 100ms or more, then confirm the corresponding timing control The device 11 is connected with the main control chip 20, and can transmit the pixel data of the i-th row described above.
  • the processor responds that the hot plug detection signal received from the timing controller 11 is a high level signal, then the hot plug detection signal received from the timing controller 11 is a low level within 2 ms. Signal, and then the received hot plug detection signal from the timing controller 11 is a high level signal again, and the display configuration data is read again.
  • the processor transmits the pixel data of the i-th row through the second eDp interface 202 according to the results of the handshake process (Training) between the K second eDp interfaces 202 and the first eDp interface 102 corresponding to each timing controller 11 To the first eDp interface 102 of the corresponding timing controller 11.
  • the handshake process includes the aforementioned processor reading the extended display identification data through the auxiliary channel, reading the display configuration data through the auxiliary channel, and receiving the hot plug detection signal.
  • Some embodiments of the present disclosure provide a data signal display method, including S10.
  • the display panel receives K groups of data voltages output by the K data driving circuits 12 and displays them.
  • each group of data voltages in the K groups of data voltages is output by each data driving circuit 12 in the K data driving circuits 12 according to a group of pixel data received from the corresponding timing controller 11, and the group of pixels
  • the data is one group of pixel data in the K groups of pixel data.
  • the data signal display method provided by the embodiment of the present disclosure has the same beneficial effects as the display assembly 10 provided above, and will not be repeated here.
  • it further includes:
  • the gate line connected to the i-th row of pixels in the display panel 14 receives the gate scan signal from the gate driving circuit 13, so that when the gate line connected to the i-th row of pixels receives the gate scan signal,
  • the pixels in the i-th row receive K groups of data voltages and display them.
  • the gate scanning signal is output by the gate driving circuit 13 according to the control signal received from the timing controller 11 connected to the gate driving circuit 13; the control signal of the timing controller 11 is divided according to the K timing controllers 11 The state of the K-1 timing controllers 11 other than the timing controller 11 is output.
  • Some embodiments of the present disclosure provide a data signal transmission method, as shown in FIG. 9, including S100-S200.
  • the processor receives pixel data of the i-th row of one frame of image data, and divides the pixel data of the i-th row into K groups of pixel data.
  • one frame of image data includes 1440 rows of pixel data, and each row of pixel data includes 3440 pixel data. Then, the processor first receives the first to 3440th pixel data in the first row, and then receives the second row of pixel data. From the 1st to the 3440th pixel data, and so on.
  • the first pixel data in the pixel data of the first row is received first, and then the second pixel data is received, and so on, until the 3440th pixel data is received.
  • S200 The processor simultaneously transmits the K groups of pixel data to the K timing controllers 11 in the display assembly 10.
  • the data signal transmission method provided by the embodiment of the present disclosure has the same beneficial effects as the display device 2 provided above, and will not be repeated here.
  • the above method further includes S101-S102.
  • the processor sequentially stores each S pixel data from the 1st pixel data to the Mth pixel data in the pixel data of the i-th row into the first second buffer 201 to the K-1th second buffer respectively.
  • the S pixel data in each buffer from the first second buffer to the K-1th second buffer constitutes a set of pixel data.
  • the processor stores the M-(K-1) ⁇ S pixel data to the M-th pixel data in the i-th row of pixel data in the K-th second buffer 201.
  • the above method further includes S103 and S104.
  • the processor generates S-[M-(K-1) ⁇ S] pieces of virtual pixel data.
  • the processor stores the generated S-[M-(K-1) ⁇ S] virtual pixel data into the Kth second buffer 201.
  • the above S200 includes:
  • the processor simultaneously outputs the K sets of pixel data stored in the K second buffers 201 through the K second eDp interfaces 202 to the first of the corresponding timing controller 11 in the K timing controllers 11 in the display assembly 10.
  • An eDp interface simultaneously outputs the K sets of pixel data stored in the K second buffers 201 through the K second eDp interfaces 202 to the first of the corresponding timing controller 11 in the K timing controllers 11 in the display assembly 10.
  • the processor receives 1440 rows of pixel data, and each row of pixel data includes 3440 pixel data.
  • each of the second buffers 201 stores 1728 pixel data
  • the processor starts to receive the first pixel data in the first row of pixel data and It is stored in a second buffer 201 until the 1728th pixel data is received and stored in a second buffer 201; here, the first pixel data stored in a second buffer 201 is
  • the 1728th pixel data is the first group of pixel data divided by the first row of pixel data by the processor; then the 1729th pixel data is received and stored in another second buffer 201 until the 3440th pixel data is received Pixel data and store it in the other second buffer 201, and then continue to store 16 virtual pixel data in the second buffer 201; here, store it in the other second buffer 201
  • the 1729th pixel data to the 3440th pixel data and the 16 dummy pixel data are the second group of pixel data divided by the pixel data of the first row by the processor.
  • the processor After all the pixel data of the first row is stored, while waiting to receive the pixel data of the second row and store it in the second buffer 201, the processor starts to store the pixel data of the first row through the two second eDp interfaces 202 respectively.
  • the two sets of pixel data stored in the two second buffers 201 are simultaneously sent to the first eDp interface 102 of the corresponding timing controller 11; and so on.
  • the data signal transmission method before S100, the data signal transmission method further includes S003.
  • the processor reads the number of pixels in a row in a sub-area 104 corresponding to the timing controller 11 stored in each timing controller 11, so that the processor reads the number of pixels corresponding to each timing controller 11 according to the read
  • the number of pixels in the i-th row in a sub-region 104 corresponding to 11 divides the pixel data of the i-th row corresponding to the pixels in the i-th row into K groups of pixel data.
  • the foregoing S103 is performed after the foregoing S003, and the foregoing S103 may be performed simultaneously with the foregoing S100.
  • the data signal transmission method further includes S002.
  • the processor reads the aforementioned display configuration data through the auxiliary channel, and obtains the state of the first eDp interface of the timing controller 11 according to the display configuration data.
  • the data signal transmission method before S002, the data signal transmission method further includes S001.
  • the processor receives the hot plug detection signal from each timing controller 11 of the K timing controllers 11 in the display assembly 10, and confirms the corresponding hot plug detection signal according to the hot plug detection signal from each timing controller 11 Whether the timing controller 11 and the main control chip 20 are connected.
  • Some embodiments of the present disclosure provide a display system 1, as shown in FIG. 11, comprising: a host 3 and a display device 2 of any of the above embodiments connected to the host 3.
  • the host 3 is configured to send the i-th row of pixel data in the image data to the display device 2.
  • the host 3 transmits one frame of image data to the main control chip 20 in the display device 2, and the frame of image data includes 1440 rows of pixel data, and each row of pixel data includes 3440 pixel data.
  • the host 3 first transmits the pixel data of the first row to the main control chip 20, and after the reception of the main control chip 20 is completed, continues to transmit the pixel data of the second row to the main control chip 20, and so on.
  • Some embodiments of the present disclosure provide a computer-readable storage medium (for example, a non-transitory computer-readable storage medium) in which computer program instructions are stored, and when the computer program instructions are run on a processor, Make the processor execute one or more steps in the pixel data display method described in any one of the above embodiments or one or more of the pixel data transmission method described in any one of the above embodiments Steps.
  • a computer-readable storage medium for example, a non-transitory computer-readable storage medium
  • the foregoing computer-readable storage medium may include, but is not limited to: magnetic storage devices (for example, hard disks, floppy disks, or magnetic tapes, etc.), optical disks (for example, CD (Compact Disk), DVD (Digital Versatile Disk, Digital universal disk), etc.), smart cards and flash memory devices (for example, EPROM (Erasable Programmable Read-Only Memory), cards, sticks or key drives, etc.).
  • Various computer-readable storage media described in this disclosure may represent one or more devices and/or other machine-readable storage media for storing information.
  • the term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.

Abstract

一种显示装置，包括显示组件和主控芯片；显示组件包括K个时序控制器、K个数据驱动电路和显示面板；每个时序控制器被配置为接收由一帧图像数据中第i行像素数据分成的K组像素数据中的一组像素数据；K个数据驱动电路中的一个数据驱动电路与对应的一个时序控制器连接，数据驱动电路被配置为接收来自对应的时序控制器的一组像素数据，并输出一组数据电压；显示面板与K个数据驱动电路电连接，被配置为接收K组数据电压并进行显示。主控芯片包括处理器，处理器被配置为接收图像数据，将第i行像素数据分成K组像素数据，并将K组像素数据同时传输至K个时序控制器。

Description

显示组件、显示装置、数据信号显示方法及传输方法
本申请要求于2019年12月20日提交的、申请号为201911330855.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示组件、显示装置、数据信号显示方法及传输方法。
背景技术
现有技术中，显卡或者主机等信号源(Source)设备将信号输出给显示装置，显示装置内部的主控芯片(Scaler)接收到信号后，将信号解码，然后，根据主控芯片与时序控制器之间的连接接口协议重新编码，输出给时序控制器；时序控制器再控制栅极驱动电路和数据驱动电路的信号输出。
然而，随着信号的分辨率越来越高、刷新率越来越高，就需要非常高的带宽进行传输，而主控芯片与时序控制器的连接接口目前还无法支持如此高的带宽。
发明内容
一方面，提供一种显示组件，包括K个时序控制器、K个数据驱动电路和显示面板。K个时序控制器中的每个时序控制器被配置为接收由一帧图像数据中第i行像素数据分成的K组像素数据中的一组像素数据，且不同时序控制器接收不同组像素数据；K为大于等于2的正整数，i∈{1,2,3,···,n}，n为大于等于1的正整数；K个数据驱动电路中的一个数据驱动电路与K个所述时序控制器中对应的一个时序控制器连接；所述数据驱动电路被配置为接收来自对应的时序控制器的一组像素数据，并输出一组数据电压；所述显示面板与所述K个数据驱动电路电连接，被配置为接收所述K个数据驱动电路输出的K组数据电压并进行显示。
在一些实施例中，显示组件还包括栅极驱动电路。栅极驱动电路与所述K个时序控制器中的一个时序控制器和所述显示面板电连接；该时序控制器还被配置为向所述栅极驱动电路传输控制信号，所述栅极驱动电路被配置为根据接收的来自所述时序控制器的控制信号，向所述显示面板输出栅极扫描信号，以使在所述显示面板中的与第i行像素连接的栅线接收到该栅极扫描信号时，第i行像素接收所述K组数据电压并进行显示。
在一些实施例中，所述时序控制器包括第一eDp接口，所述第一eDp接口被配置为接收所述由一帧图像数据中第i行像素数据分成的K组像素数据中的一组像素数据。
在一些实施例中，所述时序控制器还包括第一缓存器；所述第一缓存器被配置为存储该时序控制器所接收的一组像素数据。
在一些实施例中，所述显示面板包括显示区，所述显示区沿所述显示面板中像素的行方向划分成K个子区，每个子区中的所有像素与所述K个数据驱动电路中的一个数据驱动电路电连接；所述时序控制器还包括存储器，所述存储器被配置为存储与该时序控制器相对应的一个子区中的第i行像素的数量。
第二方面，提供一种显示装置，包括上述任一实施例的显示组件以及主控芯片。主控芯片包括处理器；所述处理器被配置为接收所述图像数据，将所述第i行像素数据分成K组像素数据，并将所述K组像素数据同时传输至所述显示组件中的所述K个时序控制器。
在一些实施例中，所述主控芯片包括K个第二缓存器；所述第i行像素数据包括M个像素数据；所述处理器还被配置为：将所述第i行像素数据中由第1个像素数据至第M个像素数据的每S个像素数据依次分别存入所述第1个第二缓存器至第K-1个第二缓存器中；(K-1)×S＜M≤K×S；S和M均为正整数；所述第1个第二缓存器至所述第K-1个第二缓存器中每个缓存器中的S个像素数据构成一组像素数据；以及，将所述第i行像素数据中的第M-(K-1)×S个像素数据至第M个像素数据存入第K个第二缓存器中。
在一些实施例中，所述处理器还被配置为生成S-[M-(K-1)×S]个虚拟像素数据，并将所述S-[M-(K-1)×S]个虚拟像素数据存入所述第K个第二缓存器中；所述第K个第二缓存器中的第M-(K-1)×S个像素数据至第M个像素数据以及S-[M-(K-1)×S]个虚拟像素数据构成一组像素数据。
在一些实施例中，所述主控芯片还包括K个第二eDp接口，所述K个时序控制器中的每个时序控制器包括第一eDp接口；所述K个第二eDp接口中的一个第二eDp接口与所述K个时序控制器中的一个时序控制器的第一eDp接口相连接；所述处理器还被配置为将所述K组像素数据中的一组像素数据通过所述K个第二eDp接口中的一个第二eDp接口输出至对应的时序控制器的第一eDp接口。
在一些实施例中，所述显示面板包括显示区，所述显示区沿所述显示面板中像素的行方向划分成K个子区，每个子区中的所有像素与所述K个数据驱动电路中的一个数据驱动电路电连接；所述时序控制器包括存储器，所述存储器被配置为存储与该时序控制器相对应的一个子区中的第i行像素的数量；所述处理器还被配置为读取每个时序控制器中存储的与该时序控制器相对应的一个子区中的第i行像素的数量，以使所述处理器根据所述第i行像素的数量，将与所述第i行像素对应的所述第i行像素数据分成K组像素数据。
在一些实施例中，所述存储器还被配置为存储所述时序控制器的显示配置数据，所述显示配置数据为信道的数量以及每个信道的传输速率；所述处理器还被配置为读取所述显示配置数据，并根据所述显示配置数据获取所述时序控制器的第一eDp接口的状态。
在一些实施例中，所述处理器还被配置为接收来自所述K个时序控制器中的每个时序控制器的热插拔检测信号，以确认每个所述时序控制器与所述主控芯片是否连接。
第三方面，提供一种数据信号显示方法，包括：显示面板接收所述K个数据驱动电路输出的K组数据电压并进行显示；其中，所述K组数据电压中的每组数据电压为所述K个数据驱动电路中的每个数据驱动电路根据接收的来自对应的时序控制器的一组像素数据所输出，该组像素数据为所述K组像素数据中的一组像素数据。
在一些实施例中，所述显示组件还包括栅极驱动电路，所述栅极驱动电路与所述K个时序控制器中的一个时序控制器和所述显示面板电连接；所述方法还包括：所述显示面板中的与第i行像素连接的栅线接收来自栅极驱动电路的栅极扫描信号，以使在与所述第i行像素连接的栅线接收到该栅极扫描信号时，第i行像素接收所述K组数据电压并进行显示。其中，所述栅极扫描信号为所述栅极驱动电路根据接收的来自与所述栅极驱动电路连接的时序控制器的控制信号所输出，所述时序控制器的控制信号根据所述K个时序控制器中除该时序控制器外的其他K-1个时序控制器的状态所输出。
第四方面，提供一种数据信号传输方法，包括：所述处理器接收所述图像数据，将所述第i行像素数据分成K组像素数据，并将所述K组像素数据同时传输至所述显示组件中的所述K个时序控制器。
在一些实施例中，所述主控芯片包括K个第二缓存器；所述第i行像素数据包括M个像素数据；所述方法还包括：所述处理器将所述第i行像素数 据中由第1个像素数据至第M个像素数据的每S个像素数据依次分别存入所述第1个第二缓存器至第K-1个第二缓存器中；所述第1个第二缓存器至所述第K-1个第二缓存器中每个第二缓存器中的S个像素数据构成一组像素数据；所述处理器将所述第i行像素数据中的第M-(K-1)×S个像素数据至第M个像素数据存入第K个第二缓存器中。
在一些实施例中，所述方法还包括：所述处理器生成S-[M-(K-1)×S]个虚拟像素数据，并将所述S-[M-(K-1)×S]个虚拟像素数据存入所述第K个第二缓存器中。
在一些实施例中，所述显示面板包括显示区，所述显示区沿所述显示面板中像素的行方向划分成K个子区，每个子区中的所有像素与所述K个数据驱动电路中的一个数据驱动电路电连接；所述时序控制器包括存储器，所述存储器被配置为存储与该时序控制器相对应的一个子区中的第i行像素的数量；所述方法还包括：所述处理器读取每个时序控制器中存储的与该时序控制器相对应的一个子区中的一行像素的数量，以使所述处理器根据所读取的与每个时序控制器相对应的一个子区中的第i行像素的数量，将与所述第i行像素对应的所述第i行像素数据分成K组像素数据。
在一些实施例中，所述时序控制器包括存储器；所述存储器被配置为存储所述时序控制器的显示配置数据，所述显示配置数据为信道的数量以及每个信道的传输速率；所述方法还包括：所述处理器读取所述显示配置数据，并根据所述显示配置数据获取所述时序控制器的第一eDp接口的状态。
在一些实施例中，所述方法还包括：所述处理器接收来自所述K个时序控制器中的每个时序控制器的热插拔检测信号，并根据所述热插拔检测信号确认所述时序控制器与所述主控芯片是否连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种显示组件的结构示意图；
图2A为根据一些实施例的另一种显示组件的结构示意图；
图2B为根据一些实施例的再一种显示组件的结构示意图；
图2C为根据一些实施例的又一种显示组件的结构示意图；
图3为根据一些实施例的又一种显示组件的结构示意图；
图4为根据一些实施例的又一种显示组件的结构示意图；
图5为根据一些实施例的一种显示装置的结构示意图；
图6为根据一些实施例的另一种显示装置的结构示意图；
图7为根据一些实施例的再一种显示装置的结构示意图；
图8为根据一些实施例的又一种显示装置的结构示意图；
图9为根据一些实施例的一种数据信号传输方法的流程示意图；
图10为根据一些实施例的另一种数据信号传输方法的流程示意图；
图11为根据一些实施例的一种显示系统的结构示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部 件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。本公开示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供一种显示组件10，如图1所示，包括：K个时序控制器11、K个数据驱动电路和显示面板。
K个时序控制器11中的每个时序控制器11被配置为接收由一帧图像数据中第i行像素数据分成的K组像素数据(Data)中的一组像素数据，且不同时序控制器接收不同组像素数据。K为大于等于2的正整数，i∈{1,2,3,···,n}，n为大于等于1的正整数。
示例的，一帧图像数据中第i行像素数据分成了K组像素数据，第1个时序控制器11接收第一组像素数据，第2个时序控制器11接收第二组像素数据，依次类推，第K个时序控制器11接收第K组像素数据。这里，第i行像素数据为一帧图像数据中的任意一行像素数据。
示例的，K组像素数据中的每组像素数据均包括相同个数的像素数据。相应的，每个时序控制器11接收对应的一组像素数据的时长相同。
若K组像素数据中的每组像素数据包括的像素数据的个数不同，则包括较多像素数据的组别对应的时序控制器11接收一组像素数据的时长较长，而包括较少像素数据的组别对应的时序控制器11接收一组像素数据的时长较短。这样，在接收下一行像素数据之前，即在接收第i+1行像素数据之前，会 出现等待间隙，导致出现像素数据丢失的问题。因此，每组像素数据中像素数据的个数相同，可避免由于接收时长不同而导致的像素数据丢失问题。
如图1所示，K个数据驱动电路12中的一个数据驱动电路12与K个时序控制器11中对应的一个时序控制器11连接，每个数据驱动电路12被配置为接收来自对应的时序控制器11的一组像素数据，并根据该组像素数据，输出一组数据电压。
示例的，第1个数据驱动电路12与第1个时序控制器11连接，第1个数据驱动电路12接收来自第1个时序控制器11的第1组像素数据，并根据该组像素数据，输出第1组数据电压。第2个数据驱动电路12与第2个时序控制器11连接，第2个数据驱动电路12接收来自第2个时序控制器11的第2组像素数据，并根据该组像素数据，输出第2组数据电压。依次类推，第K个数据驱动电路12与第K个时序控制器11连接，第K个数据驱动电路12接收来自第K个时序控制器11的第K组像素数据，并根据该组像素数据，输出第K组数据电压。
示例的，除了接收对应的一组像素数据，每个时序控制器11还接收垂直同步信号VS、水平同步信号HS和数据使能信号DE。时序控制器11根据垂直同步信号VS、水平同步信号HS和数据使能信号DE控制对应的数据驱动电路12，以使数据驱动电路12根据来自对应的时序控制器11的一组像素数据，输出一组数据电压。
如图1所示，显示面板14与K个数据驱动电路电连接。该显示面板14被配置为接收K个数据驱动电路12输出的K组数据电压并进行显示。这里，显示面板14包括多行像素，在显示面板14显示一帧图像数据的情况下，显示面板14的第i行像素显示上述的一帧图像数据中的第i行像素数据。
本公开实施例提供的显示组件10包括K个时序控制器11，K个数据驱动电路12和显示面板14。通过多个时序控制器11分别接收由一帧图像数据中第i行像素数据分成的K组像素数据中的一组像素数据，从而可以在传输技术中带宽受限的情况下，传输高带宽的像素数据。
在一些实施例中，如图2A-图2C所示，显示组件10还包括栅极驱动电路13。栅极驱动电路13与K个时序控制器中的一个时序控制器11和显示面板14电连接。时序控制器11还被配置为向该栅极驱动电路13传输控制信号，该栅极驱动电路13被配置为根据接收的来自与该栅极驱动电路13连接的时序控制器11的控制信号，向显示面板14输出栅极扫描信号，以使在显示面 板14中的与第i行像素连接的栅线接收到该栅极扫描信号时，显示面板14的第i行像素接收来自K个数据驱动电路的K组数据电压并进行显示。
这里，来自与该栅极驱动电路13连接的时序控制器11的控制信号为：与该栅极驱动电路13连接的时序控制器11根据K个时序控制器11中的除该时序控制器11以外的其他K-1个时序控制器11的状态所输出。
在一些示例中，如图2A所示，显示组件10包括两个时序控制器11(分别记为TCON1和TCON2)、两个数据驱动电路12(分别记为DDRV1和DDRV2)。TCON1与DDRV1相连接，TCON2与DDRV2相连接；栅极驱动电路13与TCON1相连接。TCON1根据TCON2的状态输出控制信号，控制栅极驱动电路13，即栅极驱动电路13根据该控制信号，向显示面板14输出栅极扫描信号。
当然，栅极驱动电路13也可以与TCON2相连接。基于此，与上述栅极驱动电路13与TCON1相连接类似，TCON2根据TCON1的状态输出控制信号，控制栅极驱动电路13。
示例的，TCON1包括两个端口，TCON2包括两个端口，TCON1和TCON2的端口两两相连接，形成两条连接线路L 12和L 21，L 12被配置为向TCON2传输表明TCON1状态的信号，L 21被配置为向TCON1传输表明TCON2状态的信号。这里，端口例如为时序控制器11的引脚。
以下以将第i行像素数据分成2组像素数据，TCON1接收第1组像素数据，TCON2接收第2组像素数据；且栅极驱动电路13与TCON1连接为例，提供S11-S14，以清楚说明TCON1根据TCON2的状态控制栅极驱动电路(SDRV)的过程。
S11、TCON2将接收的第2组像素数据全部输出至DDRV2后，TCON2通过L 21向TCON1发送高电平信号；
S12、TCON1响应于接收到的来自TCON2的高电平信号，以及确定已经将第1组像素数据全部输出至DDRV1，输出控制信号至SDRV，以使SDRV响应于接收到该控制信号，向显示面板14输出栅极扫描信号；以使在显示面板14中的与第i行像素连接的栅线接收到该栅极扫描信号时，第i行像素接收来自DDRV1的第1组数据电压和来自DDRV2的第2组数据电压；也就是说，第i行像素数据已经被传输至显示面板14。
S13、在输出控制信号至SDRV的同时，TCON1通过L 12向TCON2发送持续一段时长的高电平信号，再发送低电平信号，以告知TCON2第i行像素数据已经送出。
S14、TCON2响应于接收到的来自TCON1的高电平信号时，通过L 21向TCON1发送低电平信号。在TCON2向DDRV2输出由第i+1行像素数据分成的第2组像素数据后，再通过L 21向TCON1发送高电平信号，依次类推。
示例的，S13中，TCON1通过L 12向TCON2发送持续一段时长的高电平信号，这里，高电平信号持续的时长为TCON1向DDRV1传输由第i行像素数据分成的第1组像素数据的时长的一半。这样，可以防止高电平信号持续时长太短，TCON2侦测不到。需要说明的是，在栅极驱动电路13与TCON2连接的情况下，TCON2根据TCON1的状态输出控制信号控制栅极驱动电路13的过程与上述S11-S14类似，在此不再赘述。
在另一些示例中，如图2B所示，显示组件10包括三个时序控制器11(分别记为TCON1、TCON2和TCON3)、三个数据驱动电路(分别记为DDRV1、DDRV2和DDRV3)。TCON1与DDRV1相连接，TCON2与DDRV2相连接，TCON3与DDRV3相连接；栅极驱动电路13与TCON1相连接。TCON1根据TCON2和TCON3的状态输出控制信号，控制栅极驱动电路13，即栅极驱动电路13根据该控制信号，向显示面板14输出栅极扫描信号。
当然，栅极驱动电路13也可以与TCON2或TCON3相连接，本公开实施例对此不进行限制。例如，栅极驱动电路13与TCON3相连接，基于此，与上述栅极驱动电路13与TCON1相连接类似，TCON3根据TCON1和TCON2的状态输出控制信号，控制栅极驱动电路13。又例如，栅极驱动电路13与TCON2相连接，基于此，与上述栅极驱动电路13与TCON1相连接类似，TCON2根据TCON1和TCON3的状态输出控制信号，控制栅极驱动电路13。
示例的，TCON1包括两个端口，TCON2包括4个端口，TCON3包括两个端口。TCON1和TCON2的端口两两相连接，形成两条连接线路L 12和L 21，L 12被配置为向TCON2传输表明TCON1状态的信号，L 21被配置为向TCON1传输表明TCON2状态的信号。TCON2和TCON3的端口两两相连接，形成两条连接线路L 23和L 32，L 23被配置为向TCON3传输表明TCON2状态的信号，L 32被配置为向TCON2传输表明TCON3状态的信号。这里，各端口例如为各时序控制器11的引脚。
以下以将第i行像素数据分成3组像素数据，TCON1接收第1组像素数据，TCON2接收第2组像素数据，TCON3接收第3组像素数据；且栅极驱动电路13与TCON1连接为例，提供S21-S26，以清楚说明TCON1根据TCON2和TCON3的状态控制SDRV的过程。
S21、TCON3将接收的第3组像素数据全部输出至DDRV3后，TCON3通过L 32向TCON2发送高电平信号。
S22、TCON2将接收的第2组像素数据全部输出至DDRV2后，并响应于接收到的来自TCON3的高电平信号，通过L 21向TCON1发送高电平信号。
S23、TCON1响应于接收到的来自TCON2的高电平信号，以及确定已经将第1组像素数据全部输出至DDRV1，输出控制信号至SDRV，以使SDRV响应于接收到该控制信号，向显示面板14输出栅极扫描信号；以使在显示面板14中的与第i行像素连接的栅线接收到该栅极扫描信号时，第i行像素接收来自DDRV1的第1组数据电压、来自DDRV2的第2组数据电压和来自DDRV3的第3组数据电压；也就是说，第i行像素数据已经被传输至显示面板14。
S24、在输出控制信号至SDRV的同时，TCON1通过L 12向TCON2发送持续一段时长的高电平信号，再发送低电平信号，以告知TCON2第i行像素数据已经送出。
S25、TCON2响应于接收的来自TCON1的高电平信号，通过L 23向TCON3发送持续一段时长的高电平信号，再发送低电平信号，以告知TCON3第i行像素数据已经送出；同时，通过L 21向TCON1发送低电平信号。
S26、TCON3响应于接收到的来自TCON2的高电平信号，通过L 32向TCON2发送低电平信号。TCON3向DDRV3输出由第i+1行像素数据分成的第3组像素数据后，再通过L 32向TCON2发送高电平信号，依次类推。
示例的，S23中的TCON1通过L 12向TCON2发送持续一段时长的高电平信号，这里，高电平信号持续的时长为TCON1向DDRV1传输由第i行像素数据分成的第1组像素数据的时长的一半。S25中的TCON2通过L 23向TCON3发送持续一段时长的高电平信号，这里，高电平信号持续的时长为TCON2向DDRV2传输由第i行像素数据分成的第2组像素数据的时长的一半；这样，可以防止高电平信号持续时长太短，TCON2和TCON3侦测不到。
需要说明的是，在栅极驱动电路13与TCON3连接的情况下，TCON3根据TCON1和TCON2的状态输出控制信号控制栅极驱动电路13的过程与上述S21-S26类似，在此不再赘述。
在又一些示例中，如图2C所示，显示组件10包括K个时序控制器11(分别记为TCON1、TCON2、…、TCONK)和K个数据驱动电路(分别记为DDRV1、DDRV2、…、DDRVK)。TCON1与DDRV1相连接，TCON2与DDRV2相连接，TCONK与DDRVK相连接；栅极驱动电路13与TCON1相连接。TCON1根据TCON2至TCONK的状态输出控制信号，控制栅极驱动电路13，即栅极驱动电路13根据该控制信号，向显示面板14输出栅极扫描信号。
在一些实施例中，如图3所示，每个时序控制器11包括第一eDp(Embedded Display Port)接口102。每个第一eDp接口102被配置为接收由一帧图像数据中第i行像素数据分成的K组像素数据中的一组像素数据。示例的，第1个时序控制器11的第一eDp接口102接收由一帧图像数据中第i行像素数据分成的K组像素数据中的第1组像素数据，第2个时序控制器11的第一eDp接口102接收由一帧图像数据中第i行像素数据分成的K组像素数据中的第2组像素数据。
示例的，第一eDP接口102包括4条信道(Lane)，每条Lane中的传输速率为1.62Gbps、2.7Gbps和5.4Gbps中的一个，Lane中的传输速率是通过时钟信号来控制的，例如，当时钟信号的频率为A时，相应的一条Lane中的传输速率为1.62Gbps。
通常，在传输过程中，可以根据实际需求来选择1条信道、2条信道或者4条信道(采用多条信道进行传输时，每条信道中的传输速率相同)来进行数据传输，以支持相应的分辨率。例如，本公开实施例中的每个时序控制器11的第一eDP接口102均选择4条信道，并且，每条信道的传输速率为5.4Gbps，以满足传输一帧图像数据的带宽的需要。
在一些示例中，如图4所示，每个时序控制器11还包括第一缓存器(如图4中B1所示)。每个第一缓存器101被配置为存储对应的时序控制器11所接收的一组像素数据。即，每个第一缓存器101被配置为存储对应的时序控制器11的第一eDp接口102所接收的一组像素数据。
示例的，第1个时序控制器11的第一缓存器被配置存储为第1个时序控制器11的第一eDp接口102所接收的由一帧图像数据中第i行像素数据分成的K组像素数据中的第1组像素数据，第2个时序控制器11的第一缓存器被 配置存储为第2个时序控制器11的第一eDp接口102所接收的由一帧图像数据中第i行像素数据分成的K组像素数据中的第2组像素数据。
在一些示例中，如图1-图4所示，显示面板14包括显示区，显示区沿显示面板14中像素的行方向划分成K个子区104，每个子区104中的所有像素与K个数据驱动电路中的一个数据驱动电路12电连接。
示例的，K个数据驱动电路12连接K组数据线15，每组数据线15对应连接K个子区104中的一个子区104的多列像素；1个数据驱动电路12将一组数据电压通过其连接的一组数据线15传输至显示面板14的第i行像素中对应的多列像素中，以使该多列像素显示与该组数据电压对应的一组像素数据，这样，K组像素数据在第i行像素的不同位置处一一显示。
基于此，每个时序控制器11还包括存储器，存储器被配置为存储与该时序控制器11相对应的一个子区104中的第i行像素的数量。
示例的，K个子区104中每个子区104中的第i行像素的数量相等。
又示例的，K个子区104中每个子区104中的第i行像素的数量不完全相等。这里，不完全相等可以被理解为：部分子区104中的第i行像素的数量相等，部分子区104中的第i行像素的数量不相等。例如，第1个子区104至第K-1个子区104中的第i行像素的数量相等，第K个子区104中的第i行像素的数量与第1个子区104中的第i行像素的数量不相等。
在一些示例中，每个时序控制器中的存储器还被配置为存储该时序控制器的显示配置数据(Display Port Configuration Data,DPCD)，显示配置数据包括第一eDp接口的信道的数量以及每个信道的传输速率。
本公开一些实施例提供一种显示装置2，如图5所示，该显示装置2包括：主控芯片20和如上述任一实施例的显示组件10。
主控芯片20包括处理器。处理器被配置为接收上述的一帧图像数据，将一帧图像数据中的第i行像素数据分成K组像素数据，并将K组像素数据同时传输至显示组件10中的K个时序控制器。
示例的，处理器接收一帧图像数据是先接收第1行像素数据，接着接收第2行像素数据，以此类推，直至接收完该帧图像数据中的最后一行像素数据。在接收一帧图像数据中的第i行像素数据时，处理器先接收该行像素数据中的第1个像素数据，接着接收该行像素数据中的第2个像素数，以此类推，直至接收完该行像素数据中的最后一个像素数据。因此，处理器是在接收第i行像素数据的同时，将第i行像素数据分成K组像素数据。例如，将接收到 的第1个像素数据至第S个像素数据划分为第1组像素数据，将接收到的第S+1个像素数据至第2S个像素数据划分为第2组像素数据。也就是说，处理器在接收完第i行像素数据的同时，即完成了将第i行像素数据分成K组像素数据的过程，然后，将K组像素数据同时输出至显示组件10中对应的时序控制器11。
本公开实施例提供的显示装置2将第i行像素数据分成K组像素数据，并向显示组件10同时发送该K组像素数据，从而可以在传输技术中带宽受限的情况下，传输较高带宽的像素数据。
在一些实施例中，如图6所示，主控芯片20包括K个第二缓存器201(如图6中B2所示)。假设所述第i行像素数据包括M个像素数据。
处理器还被配置为：将第i行像素数据中由第1个像素数据至第M个像素数据的每S个像素数据依次分别存入第1个第二缓存器201至第K-1个第二缓存器201中；(K-1)×S＜M≤K×S；S和M均为正整数。也就是说，第1个第二缓存器至所述第K-1个第二缓存器中每个缓存器中的S个像素数据构成一组像素数据，即，第1个第二缓存器中的S个像素数据为上述的由第i行像素数据分成的第1组像素数据，第2个第二缓存器中的S个像素数据为上述的由第i行像素数据分成的第2组像素数据，依此类推，第K-1个第二缓存器中的S个像素数据为上述的由第i行像素数据分成的第K-1组像素数据。
处理器还被配置为：将第i行像素数据中的第M-(K-1)×S个像素数据至第M个像素数据存入第K个第二缓存器201中。
在一些示例中，处理器还被配置为：生成S-[M-(K-1)×S]个虚拟像素数据，并将S-[M-(K-1)×S]个虚拟像素数据存入第K个第二缓存器201中。也就是说，第K个第二缓存器中的第M-(K-1)×S个像素数据至第M个像素数据以及S-[M-(K-1)×S]个虚拟像素数据构成一组像素数据，即为上述的由第i行像素数据分成的第K组像素数据。
示例的，处理器根据将第i行像素数据分成K组像素数据的情况，生成上述S-[M-(K-1)×S]个虚拟像素数据。这里，存入第K个第二缓存器201中的S-[M-(K-1)×S]个虚拟像素数据并不用于显示。
例如，如图7所示，显示面板14的分辨率为3440×1440，显示面板14的显示区分为两个子区。基于此，显示组件10中包括两个时序控制器11，若两个时序控制器11所控制的显示面板的子区(如图7中所示的L区域和R区域)的宽度均为1720，即，每个子区中第i行像素的数量为1720。此时，处理 器将第i行像素数据平均分割后存储于对应的第二缓存器201即可，即，将第i行像素数据中的第1个像素数据至第1720个像素数据存入第1个第二缓存器201中，将第1721个像素数据至第3440个像素数据存入第2个第二缓存器201中。
又例如，显示面板14的显示区分为两个子区，两个时序控制器11所控制的显示面板的子区的宽度均为1728，但不等于显示面板14的带宽的一半。此时，处理器将第i行像素数据分割为两组像素数据，第1组像素数据包括1728个像素数据，第2组像素数据包括1712个像素数据。这种情况下，在处理器将两组像素数据传输至时序控制器11的过程中，两组像素数据的传输时长不相同，会出现像素数据丢失的问题。因此，处理器生成16个虚拟像素数据，并将该16个虚拟像素数据存入第2个第二缓存器201中第2组像素数据的末尾，使两组像素数据所包括的像素数据的个数相同，传输时长相等，避免了传输过程中像素数据丢失的问题。
在一些示例中，如图8所示，主控芯片20还包括K个第二eDp接口202。K个第二eDp接口202中的一个第二eDp接口202与K个时序控制器11中的一个时序控制器11的第一eDp接口102相连接。示例的，主控芯片20中的第1个第二eDp接口202与显示组件10中第1个时序控制器11的第一eDp接口102相连接。又示例的，主控芯片20中的第2个第二eDp接口202与显示组件10中第2个时序控制器11的第一eDp接口102相连接。
处理器还被配置为：将由第i行像素数据分成的K组像素数据中的一组像素数据通过K个第二eDp接口202中的一个第二eDp接口输出至对应的时序控制器11。
在一些实施例中，处理器还被配置为通过辅助通道(Auxiliary,AUX)读取每个时序控制器11中存储的与该时序控制器11相对应的一个子区104中的第i行像素的数量，以使处理器根据该第i行像素的数量，将与第i行像素对应的第i行像素数据分成K组像素数据。
此外，处理器还被配置为通过AUX读取显示面板14的扩展显示识别数据(Extended Display Identification Data，EDID)，EDID包括各显示组件10的性能的基本参数，例如制造商识别码、产品识别码、制造时间、最大显示尺寸、色彩设置、频率限制和支持的分辨率等信息。通过获取扩展显示识别数据以获取显示面板14的显示能力，以使主控芯片20将与该扩展显示识别数据匹配的数据输出至显示组件10，以使其得以正常显示。
需要说明的是，若主控芯片20与显示组件10中的时序控制器11已经提前约定好每个时序控制器11对应的显示面板14的子区104中第i行像素的数量以及与每个子区104的对应关系，则处理器可以不读取每个时序控制器11中存储的与该时序控制器11相对应的一个子区104中的第i行像素的数量，主控芯片20可以直接按照约定信息，将第i行像素数据对应分割后传输至显示组件10中对应的时序控制器11。这样，可以加快显示面板显示第i行像素数据的显示速度。
在一些示例中，处理器还被配置为通过AUX读取每个时序控制器的DPCD，并根据所读取的DPCD获取该时序控制器11的第一eDp接口102的状态。
这里，获取时序控制器11的第一eDp接口102的状态指确认第一eDp接口102的传输参数，如信道的数目，每个信道的传输速率、电压摆幅、预加重、均衡，以及时钟恢复等。
基于此，处理器由读取到的信道数目乘以每个信道的传输速率，计算得到时序控制器11当前所支持的总带宽；通常的，每个信道的传输速率相等。
需要说明的是，处理器可以多次通过AUX读取DPCD，以起到防呆的作用。
在一些示例中，处理器还被配置为接收来自显示组件10中的K个时序控制器11中的每个时序控制器11的热插拔检测信号(Hot-Plug Detect,HPD)，以确认每个时序控制器11与主控芯片20是否连接。
示例的，处理器接收来自每个时序控制器11的热插拔检测信号，为：处理器通过第二eDp接口202接收来自每个时序控制器11的第一eDp接口102的热插拔检测信号。
其中，对于来自一个时序控制器11的热插拔检测信号，若处理器响应于接收到的该热插拔检测信号一直为低电平信号，则确认对应的时序控制器11与主控芯片20未连接，此时，主控芯片20与该时序控制器11的握手过程将不进行。若处理器响应于接收到的该热插拔检测信号为高电平信号，并且在接收到该高电平信号之前，接收到的低电平信号持续了100ms及以上，则确认对应的时序控制器11与主控芯片20相连接，可以进行上述第i行像素数据的传输。
示例的，在处理器接收到的热插拔检测信号为高电平信号期间，出现了持续2ms以内的低电平信号的情况，将该情况作为处理器通过辅助通道读取 显示配置数据的触发条件。即，当处理器响应于接收到的来自时序控制器11的热插拔检测信号为高电平信号，接着接收到的来自时序控制器11的热插拔检测信号为持续2ms以内的低电平信号，然后接收到的来自时序控制器11的热插拔检测信号又为高电平信号，则重新读取一次显示配置数据。
基于此，处理器根据K个第二eDp接口202与每个时序控制器11相对应的第一eDp接口102的握手过程(Training)的结果，将第i行像素数据通过第二eDp接口202传输至对应的时序控制器11的第一eDp接口102。
这里，握手过程包括上述的处理器通过辅助通道读取扩展显示识别数据、通过辅助通道读取显示配置数据、以及接收热插拔检测信号。
本公开的一些实施例提供一种数据信号显示方法，包括S10。
S10、显示面板接收K个数据驱动电路12的输出的K组数据电压并进行显示。其中，所述K组数据电压中的每组数据电压为K个数据驱动电路12中的每个数据驱动电路12根据接收的来自对应的时序控制器11的一组像素数据所输出，该组像素数据为所述K组像素数据中的一组像素数据。
本公开实施例提供的数据信号显示方法与上述提供的显示组件10具有相同的有益效果，在此不再赘述。
在一些实施例中，还包括：
S20、显示面板14中的与第i行像素连接的栅线接收来自栅极驱动电路13的栅极扫描信号，以使在与第i行像素连接的栅线接收到该栅极扫描信号时，第i行像素接收K组数据电压并进行显示。
其中，栅极扫描信号为栅极驱动电路13根据接收的来自与栅极驱动电路13连接的时序控制器11的控制信号所输出；时序控制器11的控制信号根据K个时序控制器11中除该时序控制器11外的其他K-1个时序控制器11的状态所输出。
本公开一些实施例提供一种数据信号传输方法，如图9所示，包括S100-S200。
S100、处理器接收一帧图像数据的第i行像素数据，将第i行像素数据分成K组像素数据。
示例的，一帧图像数据包括1440行像素数据，每行像素数据包括3440个像素数据，则，处理器先接收第1行中的第1个至第3440个像素数据，再接收第2行中的第1个至第3440个像素数据，依此类推。
又示例的，在接收第1行像素数据时，先接收第1行像素数据中的第1个像素数据，再接收第2个像素数据，依此类推，直至接收第3440个像素数据。
S200、处理器将K组像素数据同时传输至显示组件10中的K个时序控制器11。
本公开实施例提供的数据信号传输方法与上述提供的显示装置2具有相同的有益效果，在此不再赘述。
在一些实施例中，如图10所示，上述方法还包括S101-S102。
S101、处理器将第i行像素数据中由第1个像素数据至第M个像素数据的每S个像素数据依次分别存入第1个第二缓存器201至第K-1个第二缓存器201中；所述第1个第二缓存器至所述第K-1个第二缓存器中每个缓存器中的S个像素数据构成一组像素数据。
S102、处理器将第i行像素数据中的第M-(K-1)×S个像素数据至第M个像素数据存入第K个第二缓存器201中。
在一些示例中，如图10所示，上述方法还包括S103和S104。
S103、处理器生成S-[M-(K-1)×S]个虚拟像素数据。
S104、处理器将生成的S-[M-(K-1)×S]个虚拟像素数据存入第K个第二缓存器201中。
在一些示例中，上述S200，包括：
处理器通过K个第二eDp接口202，将K个第二缓存器201中存储的K组像素数据，同时输出至显示组件10中的K个时序控制器11中对应的时序控制器11的第一eDp接口。
示例的，处理器接收了1440行像素数据，每行像素数据包括3440个像素数据。
在主控芯片20包括2个第二缓存器201的情况下，每个第二缓存器201存储1728个像素数据，则处理器从第1行像素数据中的第1个像素数据开始接收并将其存储至一个第二缓存器201中，直至接收到第1728个像素数据并将其存储至一个第二缓存器201中；这里，存储至一个第二缓存器201中的第1个像素数据至第1728个像素数据即为处理器将第1行像素数据划分的第1组像素数据；然后接收第1729个像素数据并将其存储至另一个第二缓存器201中，直至接收到第3440个像素数据并将其存储至该另一个第二缓存器201中并且，再将16个虚拟像素数据继续存储至该第二缓存器201中；这里，存 储至该另一个第二缓存器201中的第1729个像素数据至第3440个像素数据以及16个虚拟像素数据即为处理器将第1行像素数据划分的第2组像素数据。
在将第1行像素数据全部存储完成后，在等待接收第2行像素数据并将其存储至第二缓存器201的同时，处理器通过2个第二eDp接口202分别开始将第1行的存储于两个第二缓存器201中的两组像素数据同时发送至对应的时序控制器11的第一eDp接口102；依此类推。
在一些示例中，在S100之前，数据信号传输方法还包括S003。
S003、处理器读取每个时序控制器11中存储的与该时序控制器11相对应的一个子区104中的一行像素的数量，以使处理器根据所读取的与每个时序控制器11相对应的一个子区104中的第i行像素的数量，将与第i行像素对应的所述第i行像素数据分成K组像素数据。
在一些示例中，上述S103在上述S003之后执行，且上述S103可与上述S100同时执行。
在一些示例中，在上述S100之前，数据信号传输方法还包括S002。
S002、处理器通过辅助通道读取上述的显示配置数据，并根据显示配置数据获取时序控制器11的第一eDp接口的状态。
在一些示例中，在S002之前，数据信号传输方法还包括S001。
S001、处理器接收来自显示组件10中的K个时序控制器11中的每个时序控制器11的热插拔检测信号，并根据来自每个时序控制器11的热插拔检测信号确认对应的时序控制器11与主控芯片20是否连接。
本公开的一些实施例提供一种显示系统1，如图11所示，包括：主机3、与所述主机3相连接的上述任一实施例的显示装置2。
主机3被配置为向显示装置2发送图像数据中的第i行像素数据。
示例的，主机3将一帧图像数据传输至显示装置2中的主控芯片20，该帧图像数据包括1440行像素数据，每行像素数据包括3440个像素数据。
在传输过程中，主机3先将第1行像素数据传输至主控芯片20，待主控芯片20接收完成后，再继续将第2行像素数据传输至主控芯片20，依此类推。
本公开的一些实施例提供一种计算机可读存储介质(例如，非暂态计算机可读存储介质)，该计算机可读存储介质中存储有计算机程序指令，计算机程序指令在处理器上运行时，使处理器执行如上述实施例中任一实施例所述的像素数据的显示方法中的一个或多个步骤或上述实施例中任一实施例所述的像素数据的传输方法中的一个或多个步骤。
示例性的，上述计算机可读存储介质可以包括，但不限于：磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，CD(Compact Disk，压缩盘)、DVD(Digital Versatile Disk，数字通用盘)等)，智能卡和闪存器件(例如，EPROM(Erasable Programmable Read-Only Memory，可擦写可编程只读存储器)、卡、棒或钥匙驱动器等)。本公开描述的各种计算机可读存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读存储介质。术语“机器可读存储介质”可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示组件，包括：
    K个时序控制器，所述K个时序控制器中的每个时序控制器被配置为接收由一帧图像数据中第i行像素数据分成的K组像素数据中的一组像素数据，且不同时序控制器接收不同组像素数据；K为大于等于2的正整数，i∈{1,2,3,···,n}，n为大于等于1的正整数；
    K个数据驱动电路，所述K个数据驱动电路中的一个数据驱动电路与所述K个时序控制器中对应的一个时序控制器连接；所述数据驱动电路被配置为接收来自对应的时序控制器的一组像素数据，并输出一组数据电压；
    显示面板，与所述K个数据驱动电路电连接，所述显示面板被配置为接收所述K个数据驱动电路输出的K组数据电压并进行显示。
  2. 根据权利要求1所述的显示组件，还包括：
    栅极驱动电路，与所述K个时序控制器中的一个时序控制器和所述显示面板电连接；该时序控制器还被配置为向所述栅极驱动电路传输控制信号，所述栅极驱动电路被配置为根据接收的来自所述时序控制器的控制信号，向所述显示面板输出栅极扫描信号，以使在所述显示面板中的与第i行像素连接的栅线接收到该栅极扫描信号时，第i行像素接收所述K组数据电压并进行显示。
  3. 根据权利要求1或2所述的显示组件，其中，所述时序控制器包括第一eDp接口，所述第一eDp接口被配置为接收所述由一帧图像数据中第i行像素数据分成的K组像素数据中的一组像素数据。
  4. 根据权利要求3所述的显示组件，其中，所述时序控制器还包括第一缓存器；所述第一缓存器被配置为存储该时序控制器所接收的一组像素数据。
  5. 根据权利要求4所述的显示组件，其中，所述显示面板包括显示区，所述显示区沿所述显示面板中像素的行方向划分成K个子区，每个子区中的所有像素与所述K个数据驱动电路中的一个数据驱动电路电连接；
    所述时序控制器还包括存储器，所述存储器被配置为存储与该时序控制器相对应的一个子区中的第i行像素的数量。
  6. 一种显示装置，包括：
    如权利要求1所述的显示组件；
    主控芯片，包括：
    处理器；所述处理器被配置为接收所述图像数据，将所述第i行像素数据分成K组像素数据，并将所述K组像素数据同时传输至所述显示组件中的所述K个时序控制器。
  7. 根据权利要求6所述的显示装置，其中，所述主控芯片包括K个第二缓存器；所述第i行像素数据包括M个像素数据；所述处理器还被配置为：将所述第i行像素数据中由第1个像素数据至第M个像素数据的每S个像素数据依次分别存入所述第1个第二缓存器至第K-1个第二缓存器中；(K-1)×S＜M≤K×S；S和M均为正整数；所述第1个第二缓存器至所述第K-1个第二缓存器中每个缓存器中的S个像素数据构成一组像素数据；以及
    将所述第i行像素数据中的第M-(K-1)×S个像素数据至第M个像素数据存入第K个第二缓存器中。
  8. 根据权利要求7所述的显示装置，其中，所述处理器还被配置为生成S-[M-(K-1)×S]个虚拟像素数据，并将所述S-[M-(K-1)×S]个虚拟像素数据存入所述第K个第二缓存器中；所述第K个第二缓存器中的第M-(K-1)×S个像素数据至第M个像素数据以及S-[M-(K-1)×S]个虚拟像素数据构成一组像素数据。
  9. 根据权利要求8所述的显示装置，其中，所述主控芯片还包括K个第二eDp接口，所述K个时序控制器中的每个时序控制器包括第一eDp接口；
    所述K个第二eDp接口中的一个第二eDp接口与所述K个时序控制器中的一个时序控制器的第一eDp接口相连接；
    所述处理器还被配置为将所述K组像素数据中的一组像素数据通过所述K个第二eDp接口中的一个第二eDp接口输出至对应的时序控制器的第一eDp接口。
  10. 根据权利要求6-9所述的显示装置，其中，所述显示面板包括显示区，所述显示区沿所述显示面板中像素的行方向划分成K个子区，每个子区中的所有像素与所述K个数据驱动电路中的一个数据驱动电路电连接；
    所述时序控制器包括存储器，所述存储器被配置为存储与该时序控制器相对应的一个子区中的第i行像素的数量；
    所述处理器还被配置为读取每个时序控制器中存储的与该时序控制器相对应的一个子区中的第i行像素的数量，以使所述处理器根据所述第i行像素的数量，将与所述第i行像素对应的所述第i行像素数据分成K组像素数据。
  11. 根据权利要求10所述的显示装置，其中，所述存储器还被配置为存储所述时序控制器的显示配置数据，所述显示配置数据为信道的数量以及每个信道的传输速率；
    所述处理器还被配置为读取所述显示配置数据，并根据所述显示配置数据获取所述时序控制器的第一eDp接口的状态。
  12. 根据权利要求11所述的显示装置，其中，所述处理器还被配置为接收来自所述K个时序控制器中的每个时序控制器的热插拔检测信号，以确认每个所述时序控制器与所述主控芯片是否连接。
  13. 一种如权利要求1所述的显示组件的数据信号显示方法，包括：
    显示面板接收所述K个数据驱动电路输出的K组数据电压并进行显示；其中，所述K组数据电压中的每组数据电压为所述K个数据驱动电路中的每个数据驱动电路根据接收的来自对应的时序控制器的一组像素数据所输出，该组像素数据为所述K组像素数据中的一组像素数据。
  14. 根据权利要求13所述的数据信号显示方法，其中，所述显示组件还包括栅极驱动电路，所述栅极驱动电路与所述K个时序控制器中的一个时序控制器和所述显示面板电连接；
    所述方法还包括：
    所述显示面板中的与第i行像素连接的栅线接收来自栅极驱动电路的栅极扫描信号，以使在与所述第i行像素连接的栅线接收到该栅极扫描信号时，第i行像素接收所述K组数据电压并进行显示；其中，所述栅极扫描信号为所述栅极驱动电路根据接收的来自与所述栅极驱动电路连接的时序控制器的控制信号所输出，所述时序控制器的控制信号根据所述K个时序控制器中除该时序控制器外的其他K-1个时序控制器的状态所输出。
  15. 一种如权利要求7所述的显示装置的数据信号传输方法，包括：
    所述处理器接收所述图像数据，将所述第i行像素数据分成K组像素数据，并将所述K组像素数据同时传输至所述显示组件中的所述K个时序控制器。
  16. 根据权利要求15所述的数据信号传输方法，其中，所述主控芯片包括K个第二缓存器；所述第i行像素数据包括M个像素数据；
    所述方法还包括：
    所述处理器将所述第i行像素数据中由第1个像素数据至第M个像素数据的每S个像素数据依次分别存入所述第1个第二缓存器至第K-1个第二缓 存器中；所述第1个第二缓存器至所述第K-1个第二缓存器中每个第二缓存器中的S个像素数据构成一组像素数据；
    所述处理器将所述第i行像素数据中的第M-(K-1)×S个像素数据至第M个像素数据存入第K个第二缓存器中。
  17. 根据权利要求15所述的数据信号传输方法，所述方法还包括：
    所述处理器生成S-[M-(K-1)×S]个虚拟像素数据，并将所述S-[M-(K-1)×S]个虚拟像素数据存入所述第K个第二缓存器中。
  18. 根据权利要求15所述的数据信号传输方法，所述显示面板包括显示区，所述显示区沿所述显示面板中像素的行方向划分成K个子区，每个子区中的所有像素与所述K个数据驱动电路中的一个数据驱动电路电连接；所述时序控制器包括存储器，所述存储器被配置为存储与该时序控制器相对应的一个子区中的第i行像素的数量；
    所述方法还包括：
    所述处理器读取每个时序控制器中存储的与该时序控制器相对应的一个子区中的一行像素的数量，以使所述处理器根据所读取的与每个时序控制器相对应的一个子区中的第i行像素的数量，将与所述第i行像素对应的所述第i行像素数据分成K组像素数据。
  19. 根据权利要求15所述的数据信号传输方法，所述时序控制器包括存储器；所述存储器被配置为存储所述时序控制器的显示配置数据，所述显示配置数据为信道的数量以及每个信道的传输速率；
    所述方法还包括：
    所述处理器读取所述显示配置数据，并根据所述显示配置数据获取所述时序控制器的第一eDp接口的状态。
  20. 根据权利要求19所述的数据信号传输方法，还包括：
    所述处理器接收来自所述K个时序控制器中的每个时序控制器的热插拔检测信号，并根据所述热插拔检测信号确认所述时序控制器与所述主控芯片是否连接。
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