WO2021118627A1 - Dispositif mémoire en trois dimensions contenant plusieurs lignes de mot de fonction de travail et procédés de formation de celui-ci - Google Patents

Dispositif mémoire en trois dimensions contenant plusieurs lignes de mot de fonction de travail et procédés de formation de celui-ci Download PDF

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WO2021118627A1
WO2021118627A1 PCT/US2020/026160 US2020026160W WO2021118627A1 WO 2021118627 A1 WO2021118627 A1 WO 2021118627A1 US 2020026160 W US2020026160 W US 2020026160W WO 2021118627 A1 WO2021118627 A1 WO 2021118627A1
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Prior art keywords
conductive material
layer
conductive
layers
memory
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PCT/US2020/026160
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English (en)
Inventor
Yanli Zhang
Dong-il MOON
Raghuveer S. Makala
Peng Zhang
Wei Zhao
Ashish Baraskar
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Sandisk Technologies Llc
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Priority claimed from US16/710,572 external-priority patent/US11101288B2/en
Priority claimed from US16/710,481 external-priority patent/US11063063B2/en
Application filed by Sandisk Technologies Llc filed Critical Sandisk Technologies Llc
Priority to KR1020217020021A priority Critical patent/KR102618204B1/ko
Publication of WO2021118627A1 publication Critical patent/WO2021118627A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • a three-dimensional memory device comprises an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack.
  • Each of the memory stack structures comprises a memory film and a vertical semiconductor channel.
  • At least one of the electrically conductive layers comprises a layer stack including, from bottom to top, a lower conductive liner, a conductive material layer, and an upper conductive liner, wherein each of the lower conductive liner, the conductive material layer, and the upper conductive liner contacts the memory films, wherein the conductive material layer has a lower work function than the lower and upper conductive liners.
  • FIG. 4B is a top-down view of the first exemplary structure of FIG. 4A.
  • the vertical plane A - A’ is the plane of the cross-section for FIG. 4A.
  • FIG. 7A is a schematic vertical cross-sectional view of the first exemplary structure after formation of backside trenches according to the first embodiment of the present disclosure.
  • FIG. 7C is a schematic vertical cross-sectional view of a region of the first exemplary structure of FIG. 7A.
  • FIGS. 10A - IOC are sequential vertical cross-sectional views of a region of the first exemplary structure during formation of electrically conductive layers according to the first embodiment of the present disclosure.
  • FIG. 17 is a vertical cross-sectional view of the third exemplary structure after formation of stepped surfaces and a retro-stepped dielectric material portion according to the third embodiment of the present disclosure.
  • FIGS. 19A - 19H are sequential schematic vertical cross-sectional views of a memory opening within the third exemplary structure during formation of a memory opening fill structure therein according to the third embodiment of the present disclosure.
  • a “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0 x 10 5 S/m to 1.0 x 10 5 S/m.
  • An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants.
  • a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material.
  • a doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein.
  • a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
  • a dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer 770.
  • the planarized top surface of the planarization dielectric layer 770 can be coplanar with a top surface of the dielectric liners (761, 762).
  • the planarization dielectric layer 770 and the dielectric liners (761, 762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer 9.
  • a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).
  • the thicknesses of the insulating layers 32 and the sacrificial material layers 42 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer 32 and for each sacrificial material layer 42.
  • the number of repetitions of the pairs of an insulating layer 32 and a sacrificial material layer 42 (e.g., a control gate electrode or a sacrificial material layer) can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed.
  • the top and bottom gate electrodes in the stack may function as the select gate electrodes.
  • each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer 42.
  • the terrace region includes stepped surfaces of the alternating stack (32, 42) that continuously extend from a bottommost layer within the alternating stack (32, 42) to a topmost layer within the alternating stack (32, 42).
  • a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion 65.
  • a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may, or may not, be doped with dopants such as B, P, and/or F.
  • a lithographic material stack including at least a photoresist layer can be formed over the insulating cap layer 70 and the retro- stepped dielectric material portion 65, and can be lithographically patterned to form openings therein.
  • the openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the staircase region 300.
  • the pattern in the lithographic material stack can be transferred through the insulating cap layer 70 or the retro- stepped dielectric material portion 65, and through the alternating stack (32, 42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask.
  • the recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed.
  • the overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 can be coplanar with the topmost surface of the semiconductor material layer 10. [0074]
  • Each of the memory openings 49 and the support openings 19 may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate.
  • a two-dimensional array of memory openings 49 can be formed in the memory array region 100.
  • a two-dimensional array of support openings 19 can be formed in the staircase region 300.
  • FIGS. 5 A - 5J illustrate structural changes in a memory opening 49, which is one of the memory openings 49 in the first exemplary structure of FIGS. 4A and 4B. The same structural change occurs simultaneously in each of the other memory openings 49 and in each of the support openings 19.
  • a first conductive material portion 48 including a first conductive material having a first work function is formed in each lateral recess 49A.
  • the work function of a conductive material refers to the minimum quantity of energy which is required to remove an electron from the conductive material to a distance at infinity.
  • the first conductive material is selected such that a second conductive material having a second work function that is greater than the first work function can be subsequently formed outside the memory openings 49 by replacing the sacrificial material layers 42 with material portions including at least the second conductive material.
  • a pair of conductive materials having different work functions can be employed in embodiments of the present disclosure.
  • the first conductive material can be ruthenium
  • the second conductive material can be titanium nitride, tungsten nitride, tantalum nitride, or tungsten, which may, or may not be, doped with silicon and/or boron.
  • Excess portion of the deposited n-type doped semiconductor material that are located outside the volumes of the lateral recesses 49A can be removed by a reactive ion etch process.
  • Each remaining annular portion of the n-type doped semiconductor material filling a respective lateral recess 49A comprises a first conductive material portion 48.
  • a stack of layers including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional first semiconductor channel layer 601 can be sequentially deposited in the memory openings 49 over each vertical stack of first conductive material portions 48.
  • the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.
  • the blocking dielectric layer 52 can include silicon oxide.
  • the dielectric semiconductor compound of the blocking dielectric layer 52 can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof.
  • the thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed.
  • the tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions.
  • the charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three- dimensional NAND string memory device to be formed.
  • the tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof.
  • the optional first semiconductor channel layer 601 includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
  • the first semiconductor channel layer 601 includes amorphous silicon or polysilicon.
  • the first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD).
  • LPCVD low pressure chemical vapor deposition
  • the thickness of the first semiconductor channel layer 601 can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.
  • a memory cavity 49’ is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 601).
  • Excess portions of the deposited semiconductor material can be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP) or a recess etch. Each remaining portion of the semiconductor material having a doping of the second conductively type constitutes a drain region 63.
  • CMP chemical mechanical planarization
  • the horizontal portion of the second semiconductor channel layer 602 located above the top surface of the insulating cap layer 70 can be concurrently removed by a planarization process.
  • Each remaining portion of the second semiconductor channel layer 602 can be located entirety within a memory opening 49 or entirely within a support opening 19.
  • the continuous electrically conductive material layer 46L includes a continuous portion of the conductive material liner 46A and a continuous portion of the conductive fill material layer 46B that are located in the backside trenches 79 or above the contact- level dielectric layer 73.
  • Each sacrificial material layer 42 can be replaced with an electrically conductive layer 46.
  • a backside cavity 79’ is present in the portion of each backside trench 79 that is not filled with the continuous electrically conductive material layer 46L.
  • the electrically conductive layers 46 are formed between vertically neighboring pairs of the insulating layers 32.
  • Each of the electrically conductive layers 46 comprise a respective one of the first conductive material portions 48 and a respective one of the second conductive material portions (comprising a conductive material liner 46A), and may comprise a respective one of the third conductive material portion (comprising a conductive fill material layer 46B).
  • a conductive material liner 146A including a third conductive material can be deposited on the sidewalls of the second conductive material portions 47, on the horizontal surfaces of the insulating layers 32, on the sidewalls of the at least one the backside trench 79, and over the top surface of the contact-level dielectric layer 73.
  • the third conductive material can include conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof and/or a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof.
  • the third conductive material can include TiN.
  • a fourth conductive material is deposited over the conductive material liner 146A to form a conductive fill material layer 146B.
  • the fourth conductive material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof.
  • the conductive fill material layer 146B can consist essentially of at least one elemental metal.
  • the at least one elemental metal of the conductive fill material layer 146B can be selected, for example, from tungsten, cobalt, ruthenium, titanium, or tantalum.
  • the number of repetitions of the unit layer stack (32, 246L, 42, 246U) can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed.
  • each layer within the unit layer stack (32, 246L, 42, 246U) can have a uniform thickness throughout.
  • Each of the memory openings 49 and the support openings 19 may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate.
  • a two-dimensional array of memory openings 49 can be formed in the memory array region 100.
  • a two-dimensional array of support openings 19 can be formed in the staircase region 300.
  • the pattern of the memory openings 49 and the pattern of the support openings 19 may be the same as in the first exemplary structure.
  • the optional first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 are sequentially anisotropically etched employing at least one anisotropic etch process.
  • the portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 located above the top surface of the insulating cap layer 70 can be removed by the at least one anisotropic etch process.
  • the horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 at a bottom of each memory cavity 49’ can be removed to form openings in remaining portions thereof.
  • the processing steps of FIG. 8 can be performed to form source regions 61.
  • An isotropic etch process can be performed to remove the sacrificial material layers 42 selective to the insulating layers 32, the lower conductive liners 246L, and the upper conductive liners 246U.
  • an isotropic etchant that etches the sacrificial material layers 42 selective to the insulating layers 32, the lower conductive liners 246L, and the upper conductive liners 246U can be introduced into the backside trenches to isotropically etch the sacrificial material layers 42.
  • the conductive fill material layer 346B can be deposited employing a fluorine-containing precursor gas such as WFe. In one embodiment, the conductive fill material layer 346B can be a tungsten layer including a residual level of fluorine atoms as impurities.
  • the conductive fill material layer 346B is spaced from the memory stack structures 55 by the first conductive material portion comprising a tubular portion of the conductive material layer 346A. As discussed above, the first conductive material has the first work function that is lower than the second work function of the second conductive material of the lower conductive liners 246L and the upper conductive liners 246U.
  • the electrically conductive layers 46 are formed between vertically neighboring pairs of the insulating layers 32.
  • Each of the electrically conductive layers 46 comprise a respective one of the lower conductive liners 246L, a respective one of the conductive material layers 346A, a respective one of the upper conductive liners 246U, and a respective one of the conductive fill material layers 346B.
  • FIGS. 22A - 22C the processing steps of FIGS. 12 and 13A and 13B can be performed to form backside trench fill structures (74, 76) and various contact via structures (86, 88).
  • the third exemplary structure includes a three-dimensional memory device, which can comprise an alternating stack of insulating layers 32 and electrically conductive layers 46 located over a substrate (9, 10), memory openings 49 vertically extending through the alternating stack (32., 46), and memory stack structures 55 extending through the alternating stack (32, 46).
  • Each of the memory stack structures 55 comprises a memory film 50 and a vertical semiconductor channel 60.
  • At least one of the electrically conductive layers 46 comprises a layer stack including, from bottom to top, a lower conductive liner 246L, a conductive material layer (346A or 346B), and an upper conductive liner 246L.
  • Each of the lower conductive liner 246L, the conductive material layer (346A or 346B), and the upper conductive liner 246U contacts the memory films 50.
  • the conductive material layer has a lower work function than the lower and upper conductive liners.
  • a backside trench fill structure (74, 76) contacts sidewalls of the alternating stack (32, 46).

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

Un dispositif mémoire en trois dimensions comprend un empilement alterné de couches isolantes et de couches électroconductrices situées sur un substrat, des ouvertures de mémoire s'étendant verticalement à travers l'empilement alterné, et des structures d'empilement de mémoire s'étendant à travers l'empilement alterné. Chacune des structures d'empilement de mémoire comprend un film de mémoire et un canal semi-conducteur vertical. Au moins une des couches électroconductrices contient une première partie en matériau conducteur ayant une paroi latérale interne respective qui est en contact avec un film de mémoire respectif parmi les films de mémoire au niveau d'une interface verticale, et une seconde partie en matériau conducteur qui a une composition différente de la première partie en matériau conducteur, et qui est en contact avec la première partie en matériau électroconducteur. La première partie en matériau conducteur a une fonction de travail inférieure à celle de la seconde partie en matériau conducteur.
PCT/US2020/026160 2019-12-11 2020-04-01 Dispositif mémoire en trois dimensions contenant plusieurs lignes de mot de fonction de travail et procédés de formation de celui-ci WO2021118627A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020217020021A KR102618204B1 (ko) 2019-12-11 2020-04-01 복수의 일함수 워드 라인들을 포함하는 3차원 메모리 디바이스 및 그 형성 방법

Applications Claiming Priority (4)

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US16/710,572 2019-12-11
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