WO2021114155A1 - 一种处理器及降低功耗的方法 - Google Patents

一种处理器及降低功耗的方法 Download PDF

Info

Publication number
WO2021114155A1
WO2021114155A1 PCT/CN2019/124706 CN2019124706W WO2021114155A1 WO 2021114155 A1 WO2021114155 A1 WO 2021114155A1 CN 2019124706 W CN2019124706 W CN 2019124706W WO 2021114155 A1 WO2021114155 A1 WO 2021114155A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
processor core
power consumption
processor
high power
Prior art date
Application number
PCT/CN2019/124706
Other languages
English (en)
French (fr)
Inventor
胡荻
刘臻
王哲
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980102277.6A priority Critical patent/CN114730263A/zh
Priority to PCT/CN2019/124706 priority patent/WO2021114155A1/zh
Publication of WO2021114155A1 publication Critical patent/WO2021114155A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Definitions

  • This application relates to the field of chip technology, and in particular to a processor and a method for reducing power consumption.
  • the types of instructions executed by the processor core are diverse.
  • the processor core will call more processor components (such as storage units, arithmetic units) in order to obtain higher execution efficiency when executing these types of instructions, resulting in excessive processor power consumption. , That is, in a high power consumption scene.
  • processor components such as storage units, arithmetic units
  • such instructions may be advanced vector extensions (AVX) instructions under the x86 architecture or scalable vector extensions (SVE) under the advanced RISC machine (ARM) architecture. )instruction.
  • AVX advanced vector extensions
  • SVE scalable vector extensions
  • ARM advanced RISC machine
  • the instantaneous power consumption of the processor may increase sharply, and the required current exceeds the limit power supply current of the system design, which in turn leads to chaos in the processor timing and even power-off operations.
  • the prior art processor chip has the problem of deterioration of processor performance under high power consumption scenarios.
  • the embodiments of the present application provide a processor and a method for reducing power consumption, so as to solve the problem of performance degradation of a processor chip in a high power consumption scenario.
  • an embodiment of the present application provides a processor, including: a processor core, used to determine whether the processor core is in a high power consumption scenario; when the processor core is in a high power consumption scenario, execute a first response strategy, The first response strategy is used to reduce the power consumption of the processor core in the current frequency period.
  • the high power consumption scenario is used to instruct the processor core to execute high power consumption instructions.
  • the frequency period is used to instruct the processor core to work based on a frequency. .
  • the high power consumption instruction may be an AVX instruction under the x86 architecture, an SVE instruction under the ARM architecture, or a single instruction multiple data (SIMD) instruction.
  • AVX AVX instruction under the x86 architecture
  • SVE single instruction multiple data
  • SIMD single instruction multiple data
  • the processor core executes the first response strategy, thereby reducing the power consumption of the processor core in the current frequency cycle, and is effective for high power consumption.
  • the scene responds instantly.
  • the processor provided in the first aspect further includes a frequency controller, and the processor core is further configured to: send a first system control signal to the frequency controller, and the first system control signal is used to instruct frequency control
  • the processor executes a second response strategy, and the second response strategy is used to reduce the power consumption of the processor core in the next frequency period of the current frequency period.
  • the frequency controller is used to receive the first system control signal and execute the second response strategy.
  • the processor core also sends the first system control signal to the frequency controller to instruct the frequency controller to execute the second response strategy, thereby reducing the power consumption of the processor core in the next frequency cycle, so that the frequency controller will operate at the next frequency. Respond to high power consumption scenarios within the cycle, so as to adjust the system for high power consumption scenarios.
  • the frequency controller is also used to: after executing the second response strategy, send a second system control signal to the processor core, the second system control signal is used to instruct the second response strategy to take effect; the processor core receives the second After the system responds to the signal, it stops executing the first response strategy.
  • the execution of the first response strategy can be stopped after the second response strategy executed by the frequency controller takes effect, and the immediate strategy can be replaced by system adjustment.
  • the processor core determines whether the processor core is in a high power consumption scene, it is specifically used to determine whether the processor core is in a high power consumption scene according to the density of high power consumption instructions in the instruction pipeline.
  • the processor core includes: an instruction comparison circuit for identifying high power consumption instructions in the instruction pipeline; a counter for counting high power consumption instructions identified by the instruction comparison circuit to obtain the first count value; When a count value exceeds the first threshold value per unit time, it is determined that the processor core is in a high power consumption scenario.
  • the density of high-power instructions in the instruction pipeline is used to determine whether the processor core is in a high-power scenario, instead of immediately determining that the processor core is in a high-power scenario after a high-power instruction occurs, so the determination can be improved.
  • the accuracy of the method of high power consumption scenarios avoids frequent response strategies to reduce the power consumption of the processor core.
  • the processor core determines whether the processor core is in a high power consumption scene, it is specifically used to determine whether the processor core is in a high power consumption scene according to the density of the characteristic signal of the high power consumption event.
  • the processor core includes: an accumulator, which is used to accumulate the number of occurrences of the characterizing signal of a high-power event to obtain the second count value; and a comparator, which is used to exceed the second count value within a unit time. In the case of the threshold, it is determined that the processor core is in a high power consumption scenario.
  • the processor core executes the first response strategy, it is specifically used to: reduce the transmission width of the instruction pipeline in the current frequency cycle.
  • reducing the issue width of the instruction pipeline can reduce the processing load of the processor core, thereby reducing the power consumption of the processor core.
  • the processor core may close at least one issue channel in the instruction pipeline when reducing the issue width of the instruction pipeline.
  • the first response strategy can be realized by reducing the emission width from the emission stage to the execution stage in the instruction pipeline. Closing part of the emission channels can reduce the flipping of subsequent execution unit circuits, thereby reducing the power consumption of the processor core.
  • the processor core may also include a phase-locked loop circuit for outputting a clock signal; when the processor core executes the first response strategy, it is specifically used to: divide the frequency of the clock signal output by the phase-locked loop circuit to obtain the divided frequency.
  • Frequency clock signal when the processor core executes the first response strategy, it is specifically used to: divide the frequency of the clock signal output by the phase-locked loop circuit to obtain the divided frequency.
  • Frequency clock signal when the processor core executes the first response strategy, it is specifically used to: divide the frequency of the clock signal output by the phase-locked loop circuit to obtain the divided frequency.
  • Frequency clock signal the frequency division clock signal is output in the current frequency period, and the frequency division clock signal is used to drive the processor core.
  • the frequency of the divided clock signal is less than the frequency of the clock signal output by the phase-locked loop circuit.
  • the power consumption of the processor core can be reduced by reducing the frequency of the clock signal of the processor core.
  • the frequency controller executes the second response strategy, it is specifically used to adjust the frequency sent to the processor core in the next frequency cycle of the current frequency cycle.
  • the frequency controller adjusts the frequency of the processor core, which can realize the adjustment of the power consumption of the processor core.
  • the frequency controller is specifically used to: send the frequency modulation frequency to the processor core, the effective time of the frequency modulation frequency is the start time of the next frequency cycle of the current frequency cycle, and the frequency modulation frequency is less than the next frequency cycle of the current frequency cycle.
  • the frequency controller is specifically used to: send the power budget and the maximum frequency to the processor core, the effective time of the power budget and the maximum frequency is the start time of the next frequency cycle of the current frequency cycle, The maximum frequency is used to indicate the maximum frequency at which the processor core works.
  • the power consumption budget is the same as the preset power budget of the next frequency cycle of the current frequency cycle, and the maximum frequency is less than the preset maximum frequency of the next frequency cycle of the current frequency cycle.
  • the frequency controller delivers frequencies to the processor core in different ways, the delivered frequency or the delivered maximum frequency can be adjusted respectively, thereby reducing the power consumption of the processor core.
  • the frequency controller is also used to query (for example, periodically query) whether the first system control signal from the processor core is received again after executing the second response strategy; If the first system control signal from the processor core is not received within the time period, the execution of the second response strategy is stopped.
  • the frequency controller frequently performs frequency up-down operations on the processor core. In order to avoid this phenomenon, using the above solution, the frequency controller can stop executing the second response strategy after the first system control signal indicating the high power consumption scenario has cooled down.
  • an embodiment of the present application provides a method for reducing power consumption, including: a processor core determines whether the processor core is in a high power consumption scene; when the processor core is in a high power consumption scene, executes the first Response strategy, the first response strategy is used to reduce the power consumption of the processor core in the current frequency cycle, high power consumption scenarios are used to instruct the processor core to execute high power consumption instructions, and the frequency cycle is used to instruct the processor core to perform based on a frequency The cycle of work.
  • the method further includes: the processor core sends a first system control signal to the frequency controller, the first system control signal is used to instruct the frequency controller to execute the second response strategy; the frequency controller receives the first system control signal; System control signal; the frequency controller executes a second response strategy, and the second response strategy is used to reduce the power consumption of the processor core in the next frequency period of the current frequency period.
  • the frequency controller may also send a second system control signal to the processor core, where the second system control signal is used to instruct the second response strategy to take effect.
  • the processor core After the processor core sends the first system control signal, the processor core receives the second system control signal; then, the processor core stops executing the first response strategy.
  • the processor core judging whether the processor core is in a high power consumption scenario includes: the processor core determines whether the processor core is in a high power consumption scenario according to the density of high power consumption instructions in the instruction pipeline.
  • the processor core judges whether the processor core is in a high power consumption scenario according to the density of high power consumption instructions in the instruction pipeline, which can be implemented in the following ways: the processor core recognizes the high power consumption instructions in the instruction pipeline; The high power consumption instructions are counted to obtain the first count value; when the first count value exceeds the first threshold, the processor core determines that the processor core is in a high power consumption scenario.
  • the processor core judging whether the processor core is in a high power consumption scene includes: the processor core judges whether the processor core is in a high power consumption scene according to the density of the characteristic signal of the high power consumption event,
  • the characteristic signal of a high power consumption event is a signal that appears in the control unit, arithmetic unit, or storage unit of the processor core when the processor core executes a high power consumption instruction.
  • the processor core judges whether the processor core is in a high power consumption scene according to the density of the characterization signal of the high power consumption event, which can be implemented in the following way: Two count value; when the second count value exceeds the second threshold, the processor core determines that the processor core is in a high power consumption scenario.
  • the processor core executes the first response strategy, including: the processor core reduces the transmission width of the instruction pipeline in the current frequency cycle.
  • reducing the emission width of the instruction pipeline by the processor core can be achieved in the following manner: the processor core closes at least one emission channel in the instruction pipeline.
  • the processor core executes the first response strategy, including: the processor core divides the frequency of the clock signal output by the phase-locked loop circuit to obtain a frequency-divided clock signal; the processor core is in the current frequency period The output frequency division clock signal, the frequency division clock signal is used to drive the processor core.
  • the frequency controller executes the second response strategy, including: the frequency controller adjusts the frequency sent to the processor core in the next frequency cycle of the current frequency cycle.
  • the frequency controller adjusts the frequency delivered to the processor core in the next frequency cycle of the current frequency cycle, which can be implemented in the following manner: the frequency controller delivers the frequency modulation frequency to the processor core, and the frequency modulation frequency takes effect The time is the start time of the next frequency cycle of the current frequency cycle, and the FM frequency is less than the preset FM frequency of the next frequency cycle of the current frequency cycle.
  • the frequency controller adjusts the frequency delivered to the processor core in the next frequency cycle of the current frequency cycle, which can be implemented in the following manner: the frequency controller delivers the power consumption budget and the maximum frequency to the processor core, The effective time of the power budget and the maximum frequency is the start time of the next frequency cycle of the current frequency cycle, the maximum frequency is used to indicate the maximum frequency of the processor core working, the power budget and the preset of the next frequency cycle of the current frequency cycle The power budget is the same, and the maximum frequency is less than the preset maximum frequency of the next frequency cycle of the current frequency cycle.
  • the method further includes: the frequency controller queries whether the first system control signal from the processor core is received again; In the case of the first system control signal of the device core, the execution of the second response strategy is stopped.
  • the method for reducing power consumption provided by the second aspect can be regarded as the method executed by the processor provided by the first aspect, and the specific implementation and corresponding technical effects in the method for reducing power consumption provided by the second aspect can be See the related description in the first aspect, which will not be repeated here.
  • an embodiment of the present application provides an apparatus for reducing power consumption, including: a processor and a power supply, the processor includes a plurality of processor cores, and the power supply is used to provide power to the plurality of processor cores, wherein: Each processor core is used for:
  • the processor core determines whether the processor core is in a high power consumption scenario; when the processor core is in a high power consumption scenario, execute the first response strategy, which is used to reduce the power consumption of the processor core in the current frequency period,
  • the high power consumption scenario is used to instruct the processor core to execute high power consumption instructions
  • the frequency period is used to instruct the processor core to work on a frequency based on a cycle.
  • each of the above-mentioned processor cores are the same as those of the processor cores in the first aspect or various implementation manners in the first aspect, and will not be repeated here; the above-mentioned processors may also include a frequency controller, The function of the frequency controller is the same as the function of the frequency controller in the various implementation manners in the first aspect, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an integrated chip provided by an embodiment of the application.
  • FIG. 2 is a schematic flowchart of a frequency controller judging to withdraw from a second response strategy according to an embodiment of the application
  • FIG. 3 is a schematic diagram of the response time of a first response strategy and a second response strategy provided by an embodiment of the application;
  • FIG. 4 is a schematic flowchart of a processor core provided by an embodiment of the application.
  • FIG. 5 is a schematic flowchart of a frequency controller provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a frequency controller issuing a frequency according to an embodiment of the application.
  • FIG. 7 is a flow chart of interaction between a processor core and a frequency controller provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of another integrated chip provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of a method for determining that a processor core is in a high power consumption scenario according to an embodiment of the application.
  • FIG. 10 is a schematic diagram of another method for determining that a processor core is in a high power consumption scenario according to an embodiment of the application;
  • FIG. 11 is a schematic structural diagram of a phase-locked loop frequency dividing circuit provided by an embodiment of the application.
  • FIG. 12 is a schematic flowchart of a method for reducing power consumption according to an embodiment of the application.
  • the processor 100 may be a system on chip (system on chip, SoC).
  • SoC system on chip
  • the processor 100 includes at least one processor core 101 and a frequency controller 102. If the processor 100 includes one processor core 101, the processor 100 is a single-core processor, and if the processor includes multiple processor cores 101, the processor 100 is a multi-core processor.
  • the frequency controller 102 is coupled with all the processor cores 101 to control the operating frequency of the processor core 101; the processor core 101 is used to execute instructions.
  • the frequency controller can be implemented by a general-purpose processor (a processor different from the processor 100).
  • the frequency controller 102 when the frequency controller 102 controls the operating frequency of the processor core 101, it can determine the operating frequency of each processor core 101 according to a frequency adjustment instruction from the system or hardware. In addition, in the embodiment of the present application, the frequency controller 102 also determines the operating frequency of each processor core 101 according to the system control signal from each processor core 101. For example, if a system control signal sent by a certain processor core 101 indicates that the processor core 101 is in a high power consumption scenario, then the frequency controller 102 will consider this situation when determining the operating frequency of the processor core 101, The processor core 101 performs operations such as frequency reduction to reduce power consumption.
  • the high power consumption instruction can be understood as follows: when the number of arithmetic units or storage units called when the processor core executes the instruction exceeds a preset value, the instruction is considered to be a high power consumption instruction. For example, when more than four or six arithmetic logic units (ALU) are called by executing a certain instruction, the instruction can be considered as a high-power instruction.
  • the high-power instruction may be an AVX instruction under the x86 architecture, may be an SVE instruction under the ARM architecture, or may be a SIMD instruction.
  • the high power consumption scenario can be understood as follows: when the processor core 101 executes certain high power consumption instructions, it will call more processor components in order to obtain higher execution efficiency, resulting in the power consumption of the processor core 101. If it is too high, this scenario can be called a high power consumption scenario.
  • a power consumption threshold can be preset. When the power consumption of the processor core 101 exceeds the preset power consumption threshold, the processor core 101 is considered to be in a high power consumption scenario.
  • the frequency controller 102 controls the operating frequency of the processor core 101, it periodically controls the frequency period of the system frequency modulation, and the frequency period is used to instruct the processor core 101 to operate based on a frequency. . That is, before the arrival of each frequency cycle, the frequency controller 102 issues to each processor core 101 the operating frequency of the processor core 101 in the next frequency cycle; then, in the next frequency cycle, the processor core 101 Call the frequency indicated by the frequency controller 102 to work.
  • the meaning of the frequency period is different from the clock period in which the processor core 101 works, and one frequency period usually includes multiple clock periods. In addition, in different frequency cycles, the operating frequency of the processor core 101 may be different.
  • the frequency controller 102 When the frequency controller 102 sends a frequency to the processor core 101, there are two implementation modes. In the first type, the frequency controller 102 can directly issue the operating frequency of the processor core 101, and then the processor core 101 will work at this frequency in the next frequency cycle; in the second type, the frequency controller 102 will send the processor core 101 to the processor core 101.
  • the power consumption budget and the maximum frequency at which the processor core 101 works are issued, so the processor core 101 can work at any frequency less than the maximum frequency in the next frequency cycle, and the power consumption does not exceed the power consumption budget.
  • each processor core 101 is equipped with a clock generation circuit for generating a clock signal that drives the processor core 101 to work.
  • the clock generation circuit may be a phase locked loop (PLL).
  • PLL phase locked loop
  • the processor 100 may include a processor core 101, and the processor core 101 is used to determine whether the processor core 101 is in a high power consumption scene; when the processor core 101 is in a high power consumption scene, execute the first One response strategy.
  • the first response strategy is used to reduce the power consumption of the processor core 101 in the current frequency cycle
  • the high power consumption scenario is used to indicate that the processor core 101 is executing high power consumption instructions
  • the frequency cycle is used to instruct the processor core 101 based on A cycle of frequency for work.
  • the processor core 101 executes the first response strategy, thereby reducing the power consumption of the processor core 101 in the current frequency period. That is to say, in the processor 100, the processor core 101 can be used to reduce the power consumption of the processor in the current frequency cycle, so as to achieve instant response to high power consumption scenarios.
  • the processor 100 may also include a frequency controller 102, and the processor core 101 is also used to send a first system control signal to the frequency controller 102, and the first system control signal is used to instruct the frequency controller 101 to perform a second response.
  • the frequency controller 102 is used to receive the first system control signal and execute the second response strategy, which is used to reduce the power consumption of the processor core 101 in the next frequency period of the current frequency period.
  • the processor core 101 can also send the first system control signal to the frequency controller 102 to instruct the frequency controller 102 to execute the second response strategy. Then, in this solution, the frequency controller 102 can also be used in the next Reduce the power consumption of the processor within the frequency period, and realize the system response of high power consumption scenarios.
  • the power consumption of the processor can be reduced in the current frequency period, and the response time can be reduced.
  • the frequency controller 102 can respond to the high power consumption scenario in the next frequency cycle, so as to perform system adjustment for the high power consumption scenario. Combining these two adjustment methods can not only make instant response to high power consumption scenarios, but also realize system-level adjustment and realize a two-layer response mechanism.
  • the frequency controller 102 may also send a second system control signal to the processor core 101, where the second system control signal is used to instruct the second response strategy to take effect. Then, the processor core 101 may stop executing the first response strategy after receiving the second system control signal.
  • the system control signal may be referred to as a Flag signal.
  • the first system control signal may be referred to as Flag signal 1
  • the second system control signal may be referred to as Flag signal 2.
  • the processor core 101 can execute the first response strategy in the current frequency period, thereby reducing the power consumption of the processor core 101 in a short time, and at the same time sending the first response strategy to the frequency controller 102 A system control signal to instruct the frequency controller 102 to execute the second response strategy.
  • the second response strategy executed by the frequency controller 102 takes effect, and the frequency controller 102 may send a second system control signal to the processor core 101 to instruct the processor core 101 to exit the first In response to the strategy, at this time, only the frequency controller 102 performs the system adjustment of the processor power consumption.
  • the processor core 101 and the frequency controller 102 adjusting the power consumption of the processor core 101 in different time periods, instant response to high power consumption scenarios and system adjustment can be realized.
  • the frequency controller 102 can also query (for example, periodically query) whether the first system control signal from the processor core 101 is received again; if the frequency controller 102 If the first system control signal from the processor core 101 is not received within the preset time period, the execution of the second response strategy is stopped.
  • the effective duration of the second response strategy is configurable. That is to say, the frequency controller 102 can start timing after receiving the first system control signal, if the first system control sent from the same processor core 101 is not received within the preset time length (the specific time length is configurable) Signal, you can stop executing the second response strategy. If the first system control signal sent by the same processor core 101 is received again within the preset time period, the timing is restarted.
  • the foregoing solution for determining when to stop executing the second response strategy can be referred to as the cooling exit mechanism of the second response strategy.
  • the cooling exit mechanism can be implemented by a timer or a counter in the frequency controller 102.
  • the frequency controller 102 may start a timer for the processor core 101, and when the timer reaches a preset duration and the frequency controller 102 is at the preset duration If the first system control signal sent by the processor core 101 is not received again, the execution of the second response strategy for the processor core 101 may be stopped.
  • the frequency controller 102 may turn on a counter for the processor core 101, and a counting threshold is set in the counter. Every time a frequency period passes, the counter responds to the The count threshold is decremented by one. When the count threshold is zero, the frequency controller 102 stops executing the second response strategy.
  • the processor core 101 can be regarded as any processor core in the processor 100, and the frequency controller 102 can set a timer for each processor core.
  • the determination process may be as shown in FIG. 2.
  • the frequency controller 102 receives and saves the first system control signal.
  • a counting device timer or scoreboard.
  • the frequency controller 102 repeatedly queries whether the first system control signal from the processor core 101 is received again according to a certain period (for example, a clock period or a frequency period). Once the first system control signal from the processor core 101 is found during a certain query, the corresponding counting device is cleared; otherwise, the value of the counting device is increased. Each time the value of the counting device increases, it is compared with a preset threshold. If the threshold is reached or exceeded, the corresponding storage signal is cleared and the second response strategy is stopped. Otherwise, continue to monitor and count.
  • the method in which the counting device increases the count is taken as an example.
  • a preset threshold can also be set in the counting device, and the counting device will be counted every time the first system control signal is received. Set to the threshold, if the first system control signal is not received within a period, the count value of the counting device is reduced by one until the count value is zero, and the second response strategy is stopped.
  • the reason for adopting the above cooling exit mechanism is that once a high-power consumption instruction is called for compilation, it may be called for compilation repeatedly. Then, if the effective time of the second response strategy is relatively short (for example, the effective time is one frequency cycle), after stopping the execution of the second response strategy, if the high power consumption instruction is repeatedly invoked and compiled, the frequency controller 102 will frequently occur. A phenomenon in which the frequency up and down operation of the processor core 101 is performed. In order to avoid this phenomenon, the frequency controller 102 may adopt the aforementioned cooling exit mechanism, and stop executing the second response strategy after the first system control signal indicating the high power consumption scene has cooled down (for example, the count value is 0).
  • the above examples all illustrate that the cooling exit mechanism is executed by the frequency controller 102 as an example.
  • the processor core 101 can also determine the exit timing of the second response strategy (that is, the time to stop the execution), and then the processing The core 101 notifies the frequency controller 102 to stop executing the second response strategy.
  • FIG. 3 shows a schematic diagram of the response time of the first response strategy and the second response strategy, where the X axis represents the time axis of the system operation.
  • the counter of the frequency controller 102 for the processor core 101 has never reached the threshold, so the second response strategy is always in effect during these M-1 frequency cycles.
  • the counter reaches the threshold, then at the beginning of the N+M+1th frequency cycle, the frequency controller 102 stops executing the second response strategy.
  • the specific flow of operations performed by the processor core 101 may be as shown in FIG. 4.
  • the processor core 101 sends a first system control signal to the frequency controller 102 after determining that a high power consumption scenario occurs. Then, the processor core 101 determines whether the second response strategy executed by the frequency controller 102 is effective, and if it is effective, the process ends; if it does not take effect, the first response strategy is executed. After the first response strategy takes effect, the processor core 101 determines whether the second response strategy executed by the frequency controller 102 is effective, and once the second response strategy takes effect or the high power consumption scenario ends, it stops executing the first response strategy and ends the process.
  • the frequency controller 102 executes the frequency adjustment process according to the frequency cycle (for example, it may be 1 ms). Specifically, at the beginning of a frequency cycle, the frequency controller 102 receives the first system control signal sent by the processor core 101. After the frequency controller 102 receives and saves this signal, it activates the second response strategy and sends it to the processor The core 101 sends a second system control signal to indicate that the second response strategy has taken effect. Then, end the frequency adjustment of the current frequency period.
  • the frequency controller 102 executes the frequency adjustment process according to the frequency cycle (for example, it may be 1 ms). Specifically, at the beginning of a frequency cycle, the frequency controller 102 receives the first system control signal sent by the processor core 101. After the frequency controller 102 receives and saves this signal, it activates the second response strategy and sends it to the processor The core 101 sends a second system control signal to indicate that the second response strategy has taken effect. Then, end the frequency adjustment of the current frequency period.
  • the frequency controller 102 receives the first system control signal sent from M processor cores out of the N processor cores, then the frequency controller 102 executes the process shown in FIG. 5 for each of the M processor cores.
  • the frequency controller 102 when the frequency controller 102 executes the second response strategy for the M processor cores, it usually achieves the purpose of reducing power consumption by reducing the frequency.
  • the frequency controller 102 controls the operating frequency of the processor core, it can determine the frequency of each processor core according to the frequency adjustment instruction from the system or hardware and whether it receives the first system control signal from the processor core. working frequency. Then, for M processor cores, the frequency controller 102 can issue to M processor cores after downscaling on the basis of the frequency indicated by the frequency adjustment instruction, and for N processor cores, except for M processing The NM processor cores outside the processor cores directly issue the frequency indicated by the frequency adjustment instruction, as shown in Figure 6.
  • the frequency controller 102 may also send a second system control signal to the M processor cores to instruct the second response strategy to take effect.
  • the interaction flow chart of the processor core 101 and the frequency controller 102 may be as shown in FIG. 7. It can be seen from FIG. 7 that the processor core 101 sends the first system control signal to the frequency controller 102 after detecting the high power consumption scene, and the frequency controller 102 sends the first system control signal to the processor core 101 after the second response strategy takes effect. For the second system control signal, the processor core 101 determines whether the second response strategy is effective according to the second system control signal, thereby determining whether to continue executing the first response strategy or stop executing the first response strategy.
  • the processor core 101 has the functions of high power consumption scene judgment, frequency adjustment, and frequency selection. Then, the processor core 101 can be composed of a high power consumption scene judgment module, a frequency adjustment circuit, and frequency selection. Circuit composition. Taking the processor 100 including four processor cores 101 as an example, a schematic diagram of a possible structure of the processor 100 may be as shown in FIG. 8. In the processor shown in FIG. 8, each processor core includes a high power consumption scene judgment module, a frequency adjustment circuit, and a frequency selection circuit.
  • the high power consumption scene judgment module is used to determine that the processor core is in a high power consumption scene; the frequency adjustment circuit is used to adjust the frequency of the processor core 101, and the frequency selection circuit is used to select the processor according to the judgment of the high power consumption scene judgment module.
  • the output frequency of the core 101 can be collectively referred to as the core control circuit.
  • the high power consumption scenario is used to indicate that the processor core 101 is executing high power consumption instructions, but it does not mean that as long as the processor core 101 is executing high power consumption instructions, the processor core 101 must be in high power. Consuming scene.
  • the processor core 101 can determine that the processor core 101 is in a high power consumption scenario in various ways.
  • the processor core 101 may determine that the processor core 101 is in a high power consumption scenario according to the density of high power consumption instructions in the instruction pipeline.
  • the instructions executed by the processor core 101 are fetched from the instruction cache during the instruction fetch (IF) stage. After the decoding is completed, they will be stored in a certain queue, waiting to be selected and sent to the execution (EX) stage to be executed. . Depending on the type of instruction, some instructions also access storage devices (such as memory) in the memory access (MEM) phase. Finally, the result obtained after the instruction is executed is written back to the register in the write-back (WB) stage, and stored in the form of a queue again, and the final completion confirmation is completed in sequence.
  • IF instruction fetch
  • EX execution
  • MEM memory access
  • the processor core 101 can make a determination based on the density of high-power instructions at a certain point in the pipeline (for example, after decoding). When the density reaches or exceeds a preset threshold, it is determined that the processor core 101 is in High power consumption scenarios.
  • the decoded instruction will be identified by the instruction comparison circuit. Once it is determined to be a high power consumption instruction, the value of the counter will increase. In a certain period, once the value of the counter exceeds a certain preset threshold, it is determined that the processor core 101 is in a high power consumption scenario.
  • the processor core 101 may determine that the processor core 101 is in a high power consumption scene according to the density of the characteristic signal of the high power consumption event.
  • the characteristic signal of a high power consumption event is a signal that appears in the control unit, arithmetic unit, or storage unit of the processor core 101 when the processor core 101 executes a high power consumption instruction.
  • LSU load store unit
  • FSU floating-point SIMD unit
  • ALU ALU
  • counters can be set in different execution units in the processor core 101, and by counting the number of times the characteristic signal of a high power consumption event occurs in a unit time, it can be judged whether the processor core 101 is in a high power consumption scene.
  • four high-power event characterization signals can be selected in each of the LSU and FSU. The occurrence of these characteristic signals will be counted through the accumulator, and then compared with the preset threshold through the comparator. When the count of the accumulator exceeds the preset threshold in the preset period, it is determined that the processor core 101 is in high power. Power consumption scene (output high power consumption scene indication signal).
  • the processor core 101 may execute the first response strategy in multiple ways.
  • the processor core 101 can reduce the issue width of the instruction pipeline in the current frequency cycle. That is, the processor core 101 can execute the first response strategy by reducing the transmission width from any stage to the next stage in the instruction pipeline. For example, for the instruction pipeline shown in FIG. 9, the processor core 101 can execute the first response strategy by reducing the transmission width from the instruction fetch stage to the decoding stage; or, the processor core 101 can also execute the first response strategy by reducing the execution stage to The first response strategy is executed by storing the emission width of the access phase.
  • the processor core 101 may close at least one transmission channel in the instruction pipeline when executing the first response strategy.
  • the first response strategy is executed by blocking the execution frequency of the high power consumption instruction.
  • the maximum number of instructions issued in the same clock cycle is six (that is, six instructions can be issued to the execution unit at the same time in the same clock cycle), then when the first response strategy is executed, It is possible to limit the maximum number of commands issued in the same clock cycle to a value less than six, that is, to close some transmission channels. Closing part of the transmitting channels can reduce the flipping of subsequent execution unit circuits, thereby reducing the power consumption of the processor core 101.
  • the processor core 101 includes a PLL circuit for outputting a clock signal; when the processor core 101 executes the first response strategy, it can divide the frequency of the clock signal output by the phase-locked loop circuit to obtain The frequency-divided clock signal; then, the frequency-divided clock signal is output in the current frequency period, and the frequency-divided clock signal is used to drive the processor core 101.
  • the frequency of the divided clock signal is less than the frequency of the clock signal output by the phase-locked loop circuit.
  • the purpose of reducing power consumption is achieved by reducing the operating frequency of the processor core 101.
  • the processor core 101 includes a PLL circuit for outputting the above-mentioned clock signal; the processor core 101 can divide the clock signal through a frequency divider circuit, and then perform a clock switching circuit. Clock switching, that is, select the output clock signal in the high power consumption scene, and select the output frequency division clock signal in the non-high power consumption scene.
  • the PLL can be regarded as a part of the frequency adjustment circuit in the processor shown in FIG. 8, and the frequency dividing circuit and the selection circuit can be regarded as a part of the frequency selection circuit in the processor shown in FIG. 8.
  • the processor core 101 can also execute the first response strategy through other ways of reducing the frequency of the clock signal or changing the phase shift of the clock signal.
  • This application implements The example does not make specific restrictions on this.
  • the first implementation manner and the second implementation manner may also be combined to implement the first response strategy.
  • the density of high-power instructions or high-power event signals exceeds 20%, some transmission channels can be closed; when the density of high-power instructions or high-power event signals exceeds 40% , PLL can be used to output the divided clock signal by dividing by two (that is, the divided clock frequency is 1/2 of the clock frequency output by the PLL); when the density of the characteristic signal of the high power consumption instruction or the high power consumption event exceeds
  • the divided clock signal can be output by PLL divided by three (that is, the divided clock frequency is 1/3 of the clock frequency output by the PLL), as shown in Table 1.
  • the frequency delivered to the processor core 101 may be adjusted in the next frequency cycle to reduce the power consumption of the processor core 101.
  • the frequency delivered to the processor core 101 multiple implementation manners can be adopted.
  • the frequency controller 102 can directly issue the frequency modulation frequency to the processor core 101, the effective time of the frequency modulation frequency is the start time of the next frequency cycle of the current frequency cycle, and the frequency modulation frequency is less than the preset of the next frequency cycle of the current frequency cycle. FM frequency.
  • the signal flow of the frequency issued by the frequency controller 102 shows that when the frequency controller 102 issues the frequency to each processor core in the processor 100, it is performed according to the frequency adjustment instruction. That is, when the first system control signal sent by the processor core 101 is not received, the frequency controller 102 can determine the operating frequency of the processor core 101 in the next frequency cycle according to the frequency adjustment instruction. For ease of understanding, this The working frequency is called frequency 1 (that is, the aforementioned preset FM frequency); and when the first system control signal is received, the frequency controller 102 can add an offset to frequency 1 to obtain frequency 2 (that is, the aforementioned frequency Frequency modulation frequency) and sent to the processor core 101, the frequency value of frequency 2 is less than the frequency value of frequency 1.
  • frequency 1 that is, the aforementioned preset FM frequency
  • the frequency controller 102 can add an offset to frequency 1 to obtain frequency 2 (that is, the aforementioned frequency Frequency modulation frequency) and sent to the processor core 101, the frequency value of frequency 2 is less than the frequency value of frequency 1.
  • the frequency controller 102 calculates according to the frequency adjustment instruction that the frequency of Core M in the next frequency cycle is 3 GHz.
  • the frequency controller 102 receives the first system control signal sent by Core M, it is finally sent to Core
  • the frequency of M is 2.5 GHz, that is, the offset added by the frequency controller 102 to the preset FM frequency is -0.5 GHz.
  • the intensity of the high power consumption scene can also be indicated through the first system control signal, so when the frequency controller 102 adds an offset to the preset frequency modulation frequency, it can be based on the different intensity of the high power consumption scene.
  • the first system control signal is a 2-bit indicator signal.
  • the indicator signal is "11"; when the next level is severe, the indicator signal is "10”; when the next level is severe, the indicator is The signal is "01”; when there is no high power consumption, the indicator signal is "00".
  • the absolute value of the frequency offset set by the frequency controller 102 to the processor core 101 may gradually increase as the severity of the high power consumption scenario becomes more severe.
  • the frequency controller 102 can issue a power consumption budget and a maximum frequency to the processor core 101.
  • the effective time of the power consumption budget and the maximum frequency is the start time of the next frequency cycle of the current frequency cycle, and the maximum frequency is used to indicate processing.
  • the maximum frequency at which the device core 101 works, and the power budget is the same as the preset power budget of the next frequency cycle, and the maximum frequency is less than the preset maximum frequency of the next frequency cycle.
  • the frequency controller 102 issues frequencies for each processor core, it is issued in the form of maximum frequency + power consumption budget.
  • the processor core 101 receives the maximum frequency + power consumption.
  • power consumption is controlled through a local proportional-integral-differential (PID) control system, so that the operating frequency of the processor core 101 is less than the maximum frequency, and the power consumption of the processor core 101 is less than the power budget.
  • PID proportional-integral-differential
  • the frequency controller 102 may determine the preset maximum frequency and the preset power consumption budget of the processor core 101 in the next frequency cycle according to the frequency adjustment instruction ; In the case of receiving the first system control signal, the maximum frequency issued by the frequency controller 102 to the processor core 101 is less than the preset maximum frequency, the power budget and the preset power budget issued to the processor core 101 The same, so that under the same power budget, the operating frequency of the processor core 101 is reduced to achieve the purpose of reducing the power consumption of the processor core 101.
  • the processor core 101 executes the first response strategy, thereby reducing the power consumption of the processor core 101 in the current frequency period, Realize the immediate response strategy for high power consumption scenarios; in addition, the processor core 101 can also send the first system control signal to the frequency controller 102 to instruct the frequency controller 102 to execute the second response strategy, thereby reducing the processor in the next frequency cycle
  • the power consumption of the core can be used to reduce the power consumption of the processor in the current frequency cycle to achieve instant response to high power consumption scenarios, or the frequency controller 102 can be used to reduce the processor power consumption in the next frequency cycle. Power consumption, to achieve system response to high power consumption scenarios.
  • the power consumption of the processor core 101 can be reduced in the current frequency cycle, and the response time can be reduced.
  • the frequency controller 102 can respond to the high power consumption scenario in the next frequency period, so as to perform system adjustment for the high power consumption scenario. Combining these two adjustment methods can not only make instant response to high power consumption scenarios, but also realize system-level adjustment and realize a two-layer response mechanism.
  • An embodiment of the present application provides a device for reducing power consumption, including: a processor and a power supply.
  • the processor includes a plurality of processor cores, and the power supply is used to provide power to the plurality of processor cores, wherein each processor Nuclear is used for:
  • the first response strategy is executed.
  • the first response strategy is used to reduce the power consumption of the processor core in the current frequency period.
  • the high power consumption scenario is used to instruct the processor core to execute High-power instruction
  • the frequency cycle is used to instruct the processor core to work on a frequency based on the cycle.
  • each of the above-mentioned processor cores is the same as the function of the processor core in the preceding embodiment, and will not be repeated here; the above-mentioned processor may also include a frequency controller, the function of the frequency controller and the aforementioned embodiment The function of the middle frequency controller is the same, so I won't repeat it here.
  • an embodiment of the present application provides a method for reducing power consumption. Referring to FIG. 12, the method includes the following steps.
  • S1201 The processor core judges whether the processor core is in a high power consumption scenario.
  • the processor core executes the first response strategy when the processor core is in a high power consumption scenario.
  • the first response strategy is used to reduce the power consumption of the processor core in the current frequency cycle
  • the high power consumption scenario is used to indicate that the processor core is executing high power consumption instructions
  • the frequency cycle is used to instruct the processor core to perform based on a frequency. The cycle of work.
  • the method further includes: the processor core sends a first system control signal to the frequency controller, where the first system control signal is used to instruct the frequency controller to execute a second response strategy; the frequency controller receives the first system control signal; The frequency controller executes a second response strategy, and the second response strategy is used to reduce the power consumption of the processor core in the next frequency period of the current frequency period.
  • the frequency controller may also send a second system control signal to the processor core, where the second system control signal is used to instruct the second response strategy to take effect.
  • the processor core After the processor core sends the first system control signal, the processor core receives the second system control signal; then, the processor core stops executing the first response strategy.
  • the method further includes: the frequency controller queries whether the first system control signal from the processor core is received again; In the case of the first system control signal of the device core, the execution of the second response strategy is stopped.
  • the method for reducing power consumption shown in FIG. 12 is a method executed by the processor core 101 and the frequency controller 102 in the processor 100, and the implementation mode and technology thereof that are not described in detail in the method shown in FIG. 12 For the effect, please refer to the relevant description in the processor 100, which will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Power Sources (AREA)

Abstract

一种处理器及降低功耗的方法，用以在解决处理器芯片在高功耗场景下性能恶化的问题。处理器中包括处理器核，处理器核用于判断处理器核是否处于高功耗场景；以及，在处理器核处于高功耗场景时，执行第一响应策略。其中，第一响应策略用于在当前频率周期内降低处理器核的功耗，高功耗场景用于指示处理器核执行高功耗指令，频率周期用于指示处理器核基于一个频率进行工作的周期。

Description

一种处理器及降低功耗的方法 技术领域
本申请涉及芯片技术领域，尤其涉及一种处理器及降低功耗的方法。
背景技术
在处理器芯片中，处理器核执行的指令的类型多种多样。对于某些类型的指令，处理器核在执行这类指令时会为了获得更高的执行效率而调用较多的处理器部件(例如存储单元、运算单元)，从而导致处理器的功耗过高，即处于高功耗场景。示例性地，这类指令可以是x86架构下的高级向量扩展(advanced vector extensions，AVX)指令或高级精简指令集机器(advanced RISC machine，ARM)架构下的可伸缩矢量扩展(scalable vector extension，SVE)指令。
处理器核在处于高功耗场景时有可能导致处理器瞬时功耗陡增，所需电流超过系统设计的极限供电电流，进而导致处理器时序出现混乱，甚至发生下电操作。
因此，现有技术的处理器芯片存在高功耗场景下处理器性能恶化的问题。
发明内容
本申请实施例提供了一种处理器及降低功耗的方法，用以在解决处理器芯片在高功耗场景下性能恶化的问题。
第一方面，本申请实施例提供一种处理器，包括：处理器核，用于判断处理器核是否处于高功耗场景；在处理器核处于高功耗场景时，执行第一响应策略，第一响应策略用于在当前频率周期内降低处理器核的功耗，高功耗场景用于指示处理器核执行高功耗指令，频率周期用于指示处理器核基于一个频率进行工作的周期。
示例性地，高功耗指令可以是x86架构下的AVX指令，可以是ARM架构下的SVE指令，也可以是单指令流多数据流(single instruction multiple data，SIMD)指令。
采用第一方面提供的处理器核，在确定处理器核处于高功耗场景的情况下，处理器核执行第一响应策略，从而在当前频率周期降低处理器核的功耗，对高功耗场景做出即时响应。
在一种可能的设计中，第一方面提供的处理器还包括频率控制器，该处理器核还用于：向频率控制器发送第一系统控制信号，第一系统控制信号用于指示频率控制器执行第二响应策略，第二响应策略用于在当前频率周期的下一个频率周期内降低处理器核的功耗。频率控制器用于接收所述第一系统控制信号，执行所述第二响应策略。
采用上述方案，处理器核还向频率控制器发送第一系统控制信号，以指示频率控制器执行第二响应策略，从而在下一个频率周期降低处理器核的功耗，使得频率控制器在下一频率周期内对高功耗场景进行响应，从而针对高功耗场景进行系统调节。
此外，频率控制器还用于：在执行第二响应策略之后，向处理器核发送第二系统控制信号，第二系统控制信号用于指示第二响应策略生效；处理器核在接收到第二系统响应信号后，停止执行第一响应策略。
采用上述方案，可以在频率控制器执行的第二响应策略生效后停止执行第一响应策略， 由系统调节代替即时策略。
在一种可能的设计中，处理器核在判断处理器核是否处于高功耗场景时，具体用于：根据指令流水线中高功耗指令的密度判断处理器核是否处于高功耗场景。
具体地，处理器核包括：指令比较电路，用于识别指令流水线中的高功耗指令；计数器，用于对指令比较电路识别出的高功耗指令进行计数，得到第一计数值；在第一计数值在单位时间内超过第一阈值的情况下，确定处理器核处于高功耗场景。
采用上述方案，根据高功耗指令在指令流水线中的密度确定处理器核是否处于高功耗场景，而并非在出现高功耗指令后立即确定处理器核处于高功耗场景，因而可以提高确定高功耗场景的方式的准确性，避免频繁采取响应策略来降低处理器核的功耗。
在一种可能的设计中，处理器核在判断处理器核是否处于高功耗场景时，具体用于：根据高功耗事件的表征信号的密度判断处理器核是否处于高功耗场景。
具体地，处理器核包括：累加器，用于对高功耗事件的表征信号的出现次数进行累加，得到第二计数值；比较器，用于在第二计数值在单位时间内超过第二阈值的情况下，确定处理器核处于高功耗场景。
采用上述方案，根据高功耗事件的表征信号的密度确定处理器核是否处于高功耗场景，而并非在出现高功耗指令后立即确定处理器核处于高功耗场景，因而可以提高确定高功耗场景的方式的准确性，避免频繁采取响应策略来降低处理器核的功耗。
在一种可能的设计中，处理器核在执行第一响应策略时，具体用于：在当前频率周期内降低指令流水线的发射宽度。
采用上述方案，降低指令流水线的发射宽度可以降低处理器核的处理负荷，从而降低处理器核的功耗。
具体地，处理器核在降低指令流水线的发射宽度时，可以关闭指令流水线中的至少一个发射通道。
也就是说，可以通过降低指令流水线中发射阶段到执行阶段的发射宽度来实现第一响应策略，关闭部分发射通道可以减少后续执行单元电路的翻转，从而降低处理器核的功耗。
此外，处理器核中还可以包括锁相环电路，用于输出时钟信号；处理器核在执行第一响应策略时，具体用于：对锁相环电路输出的时钟信号进行分频，得到分频时钟信号；在当前频率周期内输出分频时钟信号，分频时钟信号用于驱动处理器核。其中，分频时钟信号的频率小于锁相环电路输出的时钟信号的频率。
采用上述方案，可以通过降低处理器核的时钟信号频率来降低处理器核的功耗。
在一种可能的设计中，频率控制器在执行第二响应策略时，具体用于：在当前频率周期的下一个频率周期对下发至处理器核的频率进行调整。
采用上述方案，频率控制器对处理器核的频率进行调整，可以实现对处理器核的功耗的调整。
在第一种实现方式中，频率控制器具体用于：向处理器核下发调频频率，调频频率的生效时间为当前频率周期的下一个频率周期的开始时刻，调频频率小于当前频率周期的下一个频率周期的预设调频频率。
在第二种实现方式中，频率控制器具体用于：向处理器核下发功耗预算以及最大频率，功耗预算和最大频率的生效时间为当前频率周期的下一个频率周期的开始时刻，最大频率用于指示处理器核工作的最大频率，功耗预算与当前频率周期的下一个频率周期的预设功 耗预算相同，最大频率小于当前频率周期的下一个频率周期的预设最大频率。
采用上述两种实现方式，当频率控制器向处理器核下发频率的方式不同时，可以分别对下发的频率或者下发的最大频率进行调节，从而降低处理器核的功耗。
在一种可能的设计中，频率控制器还用于：在执行第二响应策略之后，查询(例如可以周期性查询)是否再次接收到来自处理器核的第一系统控制信号；若在预设时长内未接收到来自处理器核的第一系统控制信号，则停止执行第二响应策略。
高功耗指令存在一旦被调用编译，就有可能被反复调用编译的特点。那么，如果第二响应策略的生效时间较短(例如生效时间为一个频率周期)，会出现频率控制器频繁对处理器核进行升降频操作的现象。为了避免出现这种现象，采用上述方案，频率控制器可以在指示高功耗场景的第一系统控制信号冷却后，才停止执行第二响应策略。
第二方面，本申请实施例提供一种降低功耗的方法，包括：处理器核判断处理器核是否处于高功耗场景；处理器核在处理器核处于高功耗场景时，执行第一响应策略，第一响应策略用于在当前频率周期内降低处理器核的功耗，高功耗场景用于指示处理器核执行高功耗指令，频率周期用于指示处理器核基于一个频率进行工作的周期。
在一种可能的设计中，该方法还包括：处理器核向频率控制器发送第一系统控制信号，第一系统控制信号用于指示频率控制器执行第二响应策略；频率控制器接收第一系统控制信号；频率控制器执行第二响应策略，第二响应策略用于在当前频率周期的下一个频率周期内降低处理器核的功耗。
此外，在频率控制器执行第二响应策略之后，频率控制器还可以向处理器核发送第二系统控制信号，第二系统控制信号用于指示第二响应策略生效。
进一步地，在处理器核发送第一系统控制信号之后，处理器核接收第二系统控制信号；然后，处理器核停止执行第一响应策略。
在一种可能的实现方式中，处理器核判断处理器核是否处于高功耗场景，包括：处理器核根据指令流水线中高功耗指令的密度判断处理器核是否处于高功耗场景。
其中，处理器核根据指令流水线中高功耗指令的密度判断处理器核是否处于高功耗场景，可以通过如下方式实现：处理器核识别指令流水线中的高功耗指令；处理器核对识别出的高功耗指令进行计数，得到第一计数值；处理器核在第一计数值超过第一阈值的情况下，确定处理器核处于高功耗场景。
在另一种可能的实现方式中，处理器核判断处理器核是否处于高功耗场景，包括：处理器核根据高功耗事件的表征信号的密度判断处理器核是否处于高功耗场景，高功耗事件的表征信号为处理器核执行高功耗指令时在处理器核的控制单元、运算单元或存储单元中出现的信号。
其中，处理器核根据高功耗事件的表征信号的密度判断处理器核是否处于高功耗场景，可以通过如下方式实现：处理器核对高功耗事件的表征信号的出现次数进行累加，得到第二计数值；处理器核在第二计数值超过第二阈值的情况下，确定处理器核处于高功耗场景。
在一种可能的实现方式中，处理器核执行第一响应策略，包括：处理器核在当前频率周期内降低指令流水线的发射宽度。
具体地，处理器核降低指令流水线的发射宽度，可以通过如下方式实现：处理器核关闭指令流水线中的至少一个发射通道。
在另一种可能的实现方式中，处理器核执行第一响应策略，包括：处理器核对锁相环 电路输出的时钟信号进行分频，得到分频时钟信号；处理器核在当前频率周期内输出分频时钟信号，分频时钟信号用于驱动处理器核。
在一种可能的设计中，频率控制器执行第二响应策略，包括：频率控制器在当前频率周期的下一个频率周期对下发至处理器核的频率进行调整。
示例性地，频率控制器在当前频率周期的下一个频率周期对下发至处理器核的频率进行调整，可以通过如下方式实现：频率控制器向处理器核下发调频频率，调频频率的生效时间为当前频率周期的下一个频率周期的开始时刻，调频频率小于当前频率周期的下一个频率周期的预设调频频率。
示例性地，频率控制器在当前频率周期的下一个频率周期对下发至处理器核的频率进行调整，可以通过如下方式实现：频率控制器向处理器核下发功耗预算以及最大频率，功耗预算和最大频率的生效时间为当前频率周期的下一个频率周期的开始时刻，最大频率用于指示处理器核工作的最大频率，功耗预算与当前频率周期的下一个频率周期的预设功耗预算相同，最大频率小于当前频率周期的下一个频率周期的预设最大频率。
此外，在频率控制器执行第二响应策略之后，该方法还包括：频率控制器查询是否再次接收到来自处理器核的第一系统控制信号；频率控制器在预设时长内未接收到来自处理器核的第一系统控制信号的情况下，停止执行第二响应策略。
需要说明的是，第二方面提供的降低功耗的方法可以视为第一方面提供的处理器所执行的方法，第二方面提供的降低功耗的方法中的具体实现方式及相应技术效果可以参见第一方面中的相关描述，此处不再赘述。
第三方面，本申请实施例提供一种降低功耗的装置，包括：处理器和电源，该处理器包括多个处理器核，该电源用于向该多个处理器核提供电源，其中，每一个处理器核用于：
判断该处理器核是否处于高功耗场景；在该处理器核处于高功耗场景时，执行第一响应策略，第一响应策略用于在当前频率周期内降低该处理器核的功耗，高功耗场景用于指示该处理器核执行高功耗指令，频率周期用于指示该处理器核基于一个频率进行工作的周期。
需要说明的是，上述每一个处理器核的功能和第一方面或者第一方面中各种实现方式中处理器核的功能相同，此处不再赘述；上述处理器还可以包括频率控制器，频率控制器的功能和第一方面中各种实现方式中频率控制器的功能相同，此处不再赘述。
附图说明
图1为本申请实施例提供的一种集成芯片的结构示意图；
图2为本申请实施例提供的一种频率控制器判断退出第二响应策略的流程示意图；
图3为本申请实施例提供的一种第一响应策略和第二响应策略的响应时间示意图；
图4为本申请实施例提供的一种处理器核的流程示意图；
图5为本申请实施例提供的一种频率控制器的流程示意图；
图6为本申请实施例提供的一种频率控制器下发频率的示意图；
图7为本申请实施例提供的一种处理器核和频率控制器的交互流程图；
图8为本申请实施例提供的另一种集成芯片的结构示意图；
图9为本申请实施例提供的一种确定处理器核处于高功耗场景的方法示意图；
图10为本申请实施例提供的另一种确定处理器核处于高功耗场景的方法示意图；
图11为本申请实施例提供的一种锁相环分频电路的结构示意图；
图12为本申请实施例提供的一种降低功耗的方法的流程示意图。
具体实施方式
下面，首先对本申请实施例的应用场景加以介绍。
本申请实施例可以应用于图1所示的处理器100，示例性地，处理器100可以是片上系统(system on chip，SoC)。如图1所示，该处理器100包括至少一个处理器核101以及频率控制器102。若该处理器100包括一个处理器核101，则该处理器100为单核处理器，若该处理器包括多个处理器核101，则该处理器100为多核处理器。
其中，频率控制器102与所有处理器核101耦合，用于对处理器核101的工作频率进行控制；处理器核101用于执行指令。
一般地，频率控制器可以由一个通用处理器(与处理器100不同的处理器)来实现。
现有技术中，频率控制器102在对处理器核101的工作频率进行控制时，可以根据来自系统或硬件的频率调节指令来确定每个处理器核101的工作频率。此外，本申请实施例中，频率控制器102还根据来自每个处理器核101的系统控制信号来确定该处理器核101的工作频率。例如，某个处理器核101发送的系统控制信号指示该处理器核101处于高功耗场景，那么，频率控制器102在确定该处理器核101的工作频率时会考虑这一情况，对该处理器核101进行降频等降低功耗的操作。
其中，关于高功耗指令可以有如下理解：当处理器核执行指令时调用的运算单元或存储单元的数量超过预设值时，则认为该指令为高功耗指令。例如，当执行某个指令所调用的算术逻辑单元(arithmetic&logical unit，ALU)超过四个或六个时，可以认为该指令为高功耗指令。示例性地，高功耗指令可以是x86架构下的AVX指令，可以是ARM架构下的SVE指令，也可以是SIMD指令。
其中，关于高功耗场景可以有如下理解：处理器核101在执行某些高功耗指令时会为了获得更高的执行效率而调用较多的处理器部件，导致处理器核101的功耗过高，这一场景可以称为高功耗场景。实际应用中，可以预先设定功耗阈值，当处理器核101的功耗超过预设的功耗阈值，则认为处理器核101处于高功耗场景。
具体地，频率控制器102在对处理器核101的工作频率进行控制时，是以系统调频的频率周期进行周期性控制的，该频率周期用于指示处理器核101基于一个频率进行工作的周期。即，在每个频率周期到来之前，频率控制器102向每个处理器核101下发该处理器核101在下一个频率周期中的工作频率；那么，在下一个频率周期中，该处理器核101调用频率控制器102所指示的频率进行工作。
值得注意的是，频率周期与处理器核101工作的时钟周期的含义不同，一个频率周期通常包括多个时钟周期。此外，在不同的频率周期内，处理器核101的工作频率可能不同。
频率控制器102在向处理器核101下发频率时，有两种实现方式。第一种，频率控制器102可以直接下发处理器核101的工作频率，那么处理器核101在下一个频率周期内则工作在该频率上；第二种，频率控制器102向处理器核101下发功耗预算以及处理器核101工作的最大频率，那么处理器核101在下一个频率周期内可以工作在小于最大频率的任一频率上，且功耗不超过功耗预算即可。
具体实现时，每个处理器核101中均配置有时钟产生电路，用于产生驱动处理器核101 工作的时钟信号。示例性地，时钟产生电路可以是锁相环(phase locked loop，PLL)。在每个频率周期到来之前，处理器核101可以调整PLL，以使得处理器核工作在频率控制器102所指示的频率上。
具体地，本申请实施例中，处理器100可以包括处理器核101，处理器核101用于判断处理器核101是否处于高功耗场景；在处理器核101处于高功耗场景时执行第一响应策略。其中，第一响应策略用于在当前频率周期内降低处理器核101的功耗，高功耗场景用于指示处理器核101正在执行高功耗指令，频率周期用于指示处理器核101基于一个频率进行工作的周期。
在处理器100中，在确定处理器核101处于高功耗场景的情况下，处理器核101执行第一响应策略，从而在当前频率周期降低处理器核101的功耗。也就是说，在处理器100中，可以通过处理器核101在当前频率周期内降低处理器功耗，实现高功耗场景的即时响应
此外，处理器100中还可以包括频率控制器102，处理器核101还用于向频率控制器102发送第一系统控制信号，该第一系统控制信号用于指示频率控制器101执行第二响应策略；频率控制器102用于接收第一系统控制信号，执行第二响应策略，第二响应策略用于在当前频率周期的下一个频率周期内降低处理器核101的功耗。
也就是说，处理器核101还可以向频率控制器102发送第一系统控制信号，以指示频率控制器102执行第二响应策略，那么，在该方案中，也可以通过频率控制器102在下一个频率周期内降低处理器功耗，实现高功耗场景的系统响应。
采用本申请实施例提供的处理器100，可以在当前频率周期内降低处理器的功耗，减少响应时间。此外，频率控制器102可以在下一频率周期对高功耗场景进行响应，从而针对高功耗场景进行系统调节。将这两种调节方式结合起来，既可以针对高功耗场景做出即时响应，又可以实现系统级调节，实现双层响应机制。
此外，在处理器100中，频率控制器102在执行第二响应策略之后，还可以向处理器核101发送第二系统控制信号，第二系统控制信号用于指示第二响应策略生效。那么，处理器核101在接收到第二系统控制信号后，可以停止执行第一响应策略。
本申请实施例中，系统控制信号可以称为Flag信号，例如第一系统控制信号可以称为Flag信号1，第二系统控制信号可以称为Flag信号2。
不难看出，第一响应策略和第二响应策略是分时实施的。在确定处理器核101处于高功耗场景之后，处理器核101可以在当前频率周期执行第一响应策略，从而在短时间内降低处理器核101的功耗，同时向频率控制器102发送第一系统控制信号，以指示频率控制器102执行第二响应策略。在当前频率周期的下一个频率周期开始时，频率控制器102执行的第二响应策略生效，频率控制器102可以向处理器核101发送第二系统控制信号，以指示处理器核101退出第一响应策略，此时仅由频率控制器102进行处理器功耗的系统调节即可。通过处理器核101和频率控制器102在不同时段对处理器核101的功耗进行调节，可以实现对高功耗场景的即时响应和系统调节。
进一步地，在频率控制器102执行第二响应策略之后，频率控制器102还可以查询(例如可以周期性查询)是否再次接收到来自处理器核101的第一系统控制信号；若频率控制器102在预设时长内未接收到来自处理器核101的第一系统控制信号，则停止执行第二响应策略。
不难看出，在本申请实施例中，第二响应策略的生效时长是可配置的。也就是说，频率控制器102可以在接收到第一系统控制信号后开始计时，若在预设时长(具体时长可配置)内均未收到来自同一个处理器核101发送的第一系统控制信号，则可以停止执行第二响应策略。若在预设时长内再次接收到同一处理器核101发送的第一系统控制信号，则重新开始计时。
上述确定何时停止执行第二响应策略的方案可以称为第二响应策略的冷却退出机制，具体实现时，可以通过频率控制器102中的计时器或者计数器来实现该冷却退出机制。
示例性地，在接收到处理器核101发送的第一系统控制信号后，频率控制器102可以针对处理器核101开启计时器，当计时器达到预设时长且频率控制器102在预设时长内未再次接收处理器核101发送的第一系统控制信号，则可以停止对处理器核101执行第二响应策略。
示例性地，在接收到处理器核101发送的第一系统控制信号后，频率控制器102可以针对处理器核101开启计数器，计数器中设置有一个计数阈值，每经过一个频率周期，计数器对该计数阈值进行减一操作，当计数阈值为零时，频率控制器102停止执行第二响应策略。
需要理解的是，若处理器100中包括多个处理器核，处理器核101可以视为处理器100中的任一个处理器核，频率控制器102可以针对每个处理器核均设置一个计时器或计数器，从而对每个处理器核进行适配的频率调节策略。
在一个具体的示例中，频率控制器102在判断是否停止执行第二响应策略时，判断流程可以如图2所示。频率控制器102接收第一系统控制信号并保存。与该被保存的信号相对应的，存在一个计数装置(计时器或记分牌)。每次频率控制器102收到一个来自处理器核101的第一系统控制信号，对应的计时器或记分牌即会被清零。频率控制器102按照一定的周期(例如可以是时钟周期或频率周期)反复查询是否再次收到来自处理器核101的第一系统控制信号。一旦在某次查询时发现来自处理器核101的第一系统控制信号，即清空对应的计数装置；否则，则增加计数装置的数值。每次计数装置的数值增加后，即和一个预先设定的阈值进行对比。如果达到或超过了该阈值，则清空对应的存储信号并停止执行第二响应策略。否则，则继续监测、计数。
在上述示例中，是以计数装置增加计数的方式为例进行说明的，实际应用中，也可以在计数装置中设置一个预先设定的阈值，每次接收到第一系统控制信号时即将计数装置置为该阈值，若在一个周期内未接收到第一系统控制信号则将计数装置的计数值减一，直至计数值为零，停止执行第二响应策略。
应理解，采用上述冷却退出机制的原因是：高功耗指令存在一旦被调用编译，就有可能被反复调用编译的特点。那么，如果第二响应策略的生效时间较短(例如生效时间为一个频率周期)，那么在停止执行第二响应策略后，若高功耗指令被反复调用编译，则会出现频率控制器102频繁对处理器核101进行升降频操作的现象。为了避免出现这种现象，频率控制器102可以采取上述冷却退出机制，在指示高功耗场景的第一系统控制信号冷却(例如计数值为0)后，才停止执行第二响应策略。
此外，上述示例均以冷却退出机制由频率控制器102执行为例进行示意，实际应用中，也可以由处理器核101判断第二响应策略的退出时机(即停止执行的时间)，然后由处理器核101通知频率控制器102停止执行第二响应策略。
结合以上描述，图3示出了第一响应策略和第二响应策略的响应时间示意图，其中，X轴表示系统运行的时间轴。从图3可以看出，在系统调频的第N-1个频率周期内的某个时间点，处理器核101发生了高功耗场景，第一响应策略生效。在第N个频率周期开始时，第二响应策略生效，处理器核101停止执行第一响应策略。在频率控制器102中设置有计数器，从第N个频率周期开始，在每个频率周期中，若频率控制器102未接收到处理器核101发送的第一系统控制信号，则计数器的计数值加一。在此后的M-1个频率周期内，频率控制器102针对处理器核101的计数器始终未达阈值，故在这M-1个频率周期内第二响应策略始终处于生效状态。在第N+M个频率周期内的某个时间点，计数器达到阈值，那么在第N+M+1个频率周期开始时，频率控制器102停止执行第二响应策略。
具体地，本申请实施例中，处理器核101所执行操作的具体流程可以如图4所示。如图4所示，处理器核101在判断高功耗场景发生后，向频率控制器102发送第一系统控制信号。然后，处理器核101判断频率控制器102执行的第二响应策略是否生效，如果已生效，则结束流程；如果未生效，则执行第一响应策略。第一响应策略生效后，处理器核101判断频率控制器102执行的第二响应策略是否生效，一旦第二响应策略生效或者高功耗场景结束，则停止执行第一响应策略，结束流程。
具体地，本申请实施例中，在一个频率周期内，频率控制器102所执行操作的具体流程可以如图5所示。如图5所示，频率控制器102按照频率周期(例如可以是1ms)执行频率调节流程。具体地，在一个频率周期的开始时刻，频率控制器102接收到处理器核101发送的第一系统控制信号，频率控制器102接收并保存此信号后，激活第二响应策略，并向处理器核101发送第二系统控制信号，以指示第二响应策略已生效。然后，结束当前频率周期的频率调节。
假设处理器100中包括N个处理器核，在频率周期的开始时刻，频率控制器102接收到来自N个处理器核中的M个处理器核发送的第一系统控制信号，那么频率控制器102针对M个处理器核中的每个处理器核均执行图5所示的流程。
其中，频率控制器102在对M个处理器核执行第二响应策略时，通常是以降低频率的方式来达到降低功耗的目的。频率控制器102在对处理器核的工作频率进行控制时，可以根据来自系统或硬件的频率调节指令以及是否接受到来自处理器核的第一系统控制信号的情况来确定每个处理器核的工作频率。那么，对于M个处理器核来说，频率控制器102可以在频率调节指令指示的频率的基础上降频后下发给M个处理器核，而对于N个处理器核中除M个处理器核之外的N-M个处理器核，则直接下发频率调节指令指示的频率，如图6所示。此外，频率控制器102还可以向M个处理器核发送第二系统控制信号，以指示第二响应策略生效。
结合图4和图5，处理器核101和频率控制器102的交互流程图可以如图7所示。从图7可以看出，处理器核101在检测到高功耗场景后即向频率控制器102发送第一系统控制信号，频率控制器102在第二响应策略生效后即向处理器核101发送第二系统控制信号，处理器核101根据第二系统控制信号来判断第二响应策略是否生效，从而确定继续执行第一响应策略还是停止执行第一响应策略。
不难看出，本申请实施例中，处理器核101具有高功耗场景判断、频率调节和频率选择的功能，那么，处理器核101可以由高功耗场景判断模块、频率调节电路和频率选择电路组成。以处理器100包括四个处理器核101为例，处理器100的一种可能的结构示意图 可以如图8所示。在图8所示的处理器中，每个处理器核中包括高功耗场景判断模块、频率调节电路和频率选择电路。高功耗场景判断模块用于确定处理器核处于高功耗场景；频率调节电路用于对处理器核101的频率进行调节，频率选择电路用于根据高功耗场景判断模块的判断选择处理器核101输出的频率。其中，频率选择电路和频率调节电路可以统称为核内控制电路。
以上是针对处理器100中的处理器核101和频率控制器102执行响应策略的时机以及二者的交互过程进行的介绍。下面对处理器100中处理器核101和频率控制器102内部的具体流程及实现方式进行介绍。
一、确定处理器核101处于高功耗场景的实现方式
本申请实施例中，高功耗场景用于指示处理器核101正在执行高功耗指令，但是，并不表示只要处理器核101正在执行高功耗指令，处理器核101就一定处于高功耗场景。处理器核101可以通过多种方式判断处理器核101处于高功耗场景。
比如，处理器核101可以根据指令流水线中高功耗指令的密度确定处理器核101处于高功耗场景。
以图9所示的六解码六发射五级(即取指、解码、执行、存储访问、写回)乱序发射流水线微架构为例。处理器核101所执行的指令在取指(IF)阶段被从指令缓存取出，在解码完成后，会以某种队列的形式被存储起来，等待被选中并发往执行(EX)阶段被执行。根据指令类型的不同，有些指令还会在存储访问(MEM)阶段访问存储装置(如内存)。最后，指令执行后得到的结果在写回(WB)阶段写回寄存器中，并再次以队列的形式存储起来，依序完成最后的完成确认。
如上所示，在指令流水线的各个阶段，指令以不同的形式存在于微架构的各级流水线中。因此，处理器核101可以根据高功耗指令在流水线中某一处的密度(如解码结束后)进行判定，当密度达到或超过某一预先设定的阈值时，即判断处理器核101处于高功耗场景。
在一个具体的示例中，当指令被解码后，解码后的指令会通过指令比较电路被识别，一旦被确定为是高功耗指令，计数器的值即会增加。在一定周期内，一旦计数器的值超过了某一预设的阈值，即判断处理器核101处于高功耗场景。
再比如，处理器核101可以根据高功耗事件的表征信号的密度确定处理器核101处于高功耗场景。其中，高功耗事件的表征信号为处理器核101执行高功耗指令时在处理器核101的控制单元、运算单元或存储单元中出现的信号。例如，当处理器核101执行高功耗指令时，在读取存储单元(load store unit，LSU)、浮点运算单元(floating-point SIMD unit，FSU)或ALU中会出现一些表征信号。通过这些表征信号的密度可以确定处理器核101是否处于高功耗场景。
具体实现时，可以在处理器核101中的不同执行单元中设置计数器，通过计算高功耗事件的表征信号在单位时间内出现的次数，来判断处理器核101是否处于高功耗场景。当然，也可以通过记分牌的形式来判断是否处于高功耗场景，例如将每一种高功耗事件的表征信号设置一个固定的分数，当出现高功耗事件的表征信号时即在记分牌中增加相应分数，当记分牌中记录的分数达到预设值时确定处理器核101处于高功耗场景。
在一个具体的示例中，如图10所示，可以在LSU和FSU中各选择四个高功耗事件的 表征信号。这些表征信号的出现会通过累加器进行计数，然后通过比较器与预设的阈值进行比较，当累加器的计数在预设周期内超过预设的阈值时，即确定处理器核101处于高功耗场景(输出高功耗场景指示信号)。
二、处理器核101执行第一响应策略的实现方式
本申请实施例中，处理器核101可以通过多种方式执行第一响应策略。
在第一种实现方式中，处理器核101可以在当前频率周期内降低指令流水线的发射宽度。即，处理器核101可以通过降低指令流水线中任一阶段到下一阶段的发射宽度的方式来执行第一响应策略。例如，对于图9所示的指令流水线，处理器核101可以通过降低取指阶段到解码阶段的发射宽度的方式，来执行第一响应策略；或者，处理器核101也可以通过降低执行阶段到存储访问阶段的发射宽度的方式，来执行第一响应策略。
在一个具体的示例中，处理器核101在执行第一响应策略时，可以关闭指令流水线中的至少一个发射通道。
不难理解，在第一种实现方式中，是通过阻塞高功耗指令的执行频率来执行第一响应策略。比如，在图9所示的指令流水线中，同一时钟周期内发射指令的最大数目为六(即在同一时钟周期内，可以同时发射六条指令到执行单元)，那么在执行第一响应策略时，可以限制同一时钟周期内发射指令的最大数目为小于六的数值，即关闭部分发射通道。关闭部分发射通道可以减少后续执行单元电路的翻转，从而降低处理器核101的功耗。
在第二种实现方式中，处理器核101中包括PLL电路，用于输出时钟信号；处理器核101在执行第一响应策略时，可以对锁相环电路输出的时钟信号进行分频，得到分频时钟信号；然后，在当前频率周期内输出分频时钟信号，分频时钟信号用于驱动处理器核101。其中，分频时钟信号的频率小于锁相环电路输出的时钟信号的频率。
不难理解，在第二种实现方式中，是通过降低处理器核101的工作频率来实现降低功耗的目的。
在一个具体示例中，如图11所示，处理器核101中包括PLL电路，用于输出上述时钟信号；处理器核101可以通过分频电路对时钟信号进行分频，然后通过时钟切换电路进行时钟切换，即在高功耗场景下选择输出时钟信号，在非高功耗场景下选择输出分频时钟信号。其中，PLL可以视为图8所示的处理器中的频率调节电路的一部分，分频电路和选择电路可以视为图8所示的处理器中的频率选择电路的一部分。
当然，除了上述通过PLL和分频电路来执行第一响应策略的方式之外，处理器核101还可以通过其他降低时钟信号频率或改变时钟信号相移的方式执行第一响应策略，本申请实施例对此不做具体限定。
此外，本申请实施例中，还可以将第一种实现方式与第二种实现方式相结合来实现第一响应策略。例如，当高功耗指令或高功耗事件的表征信号的密度超过20％时，可以采取关闭部分发射通道的方式；当高功耗指令或高功耗事件的表征信号的密度超过40％时，可以采取PLL二分频的方式输出分频时钟信号(即分频后的时钟频率为PLL输出的时钟频率的1/2)；当高功耗指令或高功耗事件的表征信号的密度超过80％时，可以采取PLL三分频的方式输出分频时钟信号(即分频后的时钟频率为PLL输出的时钟频率的1/3)，如表1所示。
表1
高功耗指令或高功耗事件的表征信号的密度 对应第一响应策略
20％ 关闭部分发射通道
40％ PLL二分频
80％ PLL三分频
三、频率控制器102执行第二响应策略的实现方式
在本申请实施例中，频率控制器102执行第二响应策略时，可以在下一个频率周期对下发至处理器核101的频率进行调整，以降低处理器核101的功耗。具体地，对下发至处理器核101的频率进行调整时可以采用多种实现方式。
比如，频率控制器102可以直接向处理器核101下发调频频率，调频频率的生效时间为当前频率周期的下一个频率周期的开始时刻，调频频率小于当前频率周期的下一个频率周期的预设调频频率。
如图6所示的频率控制器102下发频率的信号流向可知，频率控制器102在向处理器100中的每个处理器核下发频率时，是根据频率调节指令进行的。即，在未接收到处理器核101发送的第一系统控制信号的情况下，频率控制器102可以根据频率调节指令确定处理器核101在下一个频率周期的工作频率，为了便于理解，将这一工作频率称为频率1(即前述预设调频频率)；而在接收到第一系统控制信号的情况下，频率控制器102可以在频率1的基础上添加偏移量，得到频率2(即前述调频频率)并下发给处理器核101，频率2的频率值小于频率1的频率值。
示例性地，频率控制器102根据频率调节指令计算得到Core M在下一个频率周期的频率为3GHz，在频率控制器102接收到Core M发送的第一系统控制信号的情况下，最终下发至Core M的频率为2.5GHz，即频率控制器102对预设调频频率添加的偏移量为-0.5GHz。
此外，本申请实施例中，还可以通过第一系统控制信号指示高功耗场景的强度，那么频率控制器102在对预设调频频率添加偏移量的时候可以根据高功耗场景的不同强度选择不同的偏移量。例如，第一系统控制信号为2比特的指示信号，当高功耗程度最严重时，指示信号为“11”；次一级严重时，指示信号为“10”；再次一级严重时，指示信号为“01”；没有高功耗情况时，指示信号为“00”。相应的，频率控制器102对处理器核101设置的频率偏移量的绝对值可以随着高功耗场景的严重程度加剧而逐渐增加。
再比如，频率控制器102可以向处理器核101下发功耗预算以及最大频率，功耗预算和最大频率的生效时间为当前频率周期的下一个频率周期的开始时刻，最大频率用于指示处理器核101工作的最大频率，功耗预算与下一个频率周期的预设功耗预算相同，最大频率小于下一个频率周期的预设最大频率。
在这种实现方式中，频率控制器102在为每个处理器核下发频率时，均是以最大频率+功耗预算的形式下发的，处理器核101在接收到最大频率+功耗预算后，通过本地的比例-积分-微分(proportion integral differential，PID)控制系统进行功耗控制，使得处理器核101的工作频率小于最大频率，且处理器核101的功耗小于功耗预算。
那么，在未接收到处理器核101发送的第一系统控制信号的情况下，频率控制器102可以根据频率调节指令确定处理器核101在下一个频率周期的预设最大频率和预设功耗预算；在接收到第一系统控制信号的情况下，频率控制器102下发至处理器核101的最大频率小于预设最大频率，下发至处理器核101的功耗预算与预设功耗预算相同，从而在功耗 预算相同的情况下，降低处理器核101的工作频率，达到降低处理器核101的功耗的目的。
采用本申请实施例提供的处理器100，在确定处理器核101处于高功耗场景的情况下，处理器核101执行第一响应策略，从而在当前频率周期降低处理器核101的功耗，实现高功耗场景的即时响应策略；此外，处理器核101还可以向频率控制器102发送第一系统控制信号，以指示频率控制器102执行第二响应策略，从而在下一个频率周期降低处理器核的功耗。也就是说，在处理器100中，既可以通过处理器核在当前频率周期内降低处理器功耗，实现高功耗场景的即时响应，也可以通过频率控制器102在下一个频率周期降低处理器功耗，实现高功耗场景的系统响应。
采用本申请实施例提供的处理器100，可以在当前频率周期内降低处理器核101的功耗，减少响应时间。此外，频率控制器102可以在下一频率周期内对高功耗场景进行响应，从而针对高功耗场景进行系统调节。将这两种调节方式结合起来，既可以针对高功耗场景做出即时响应，又可以实现系统级调节，实现双层响应机制。
本申请实施例提供一种降低功耗的装置，包括：处理器和电源，该处理器包括多个处理器核，该电源用于向该多个处理器核提供电源，其中，每一个处理器核用于：
判断该处理器核是否处于高功耗场景；
在该处理器核处于高功耗场景时，执行第一响应策略，第一响应策略用于在当前频率周期内降低该处理器核的功耗，高功耗场景用于指示该处理器核执行高功耗指令，频率周期用于指示该处理器核基于一个频率进行工作的周期。
需要说明的是，上述每一个处理器核的功能和前述实施例中处理器核的功能相同，此处不再赘述；上述处理器还可以包括频率控制器，频率控制器的功能和前述实施例中频率控制器的功能相同，此处不再赘述。
基于同一发明构思，本申请实施例提供一种降低功耗的方法，参见图12，该方法包括如下步骤。
S1201：处理器核判断处理器核是否处于高功耗场景。
S1202：处理器核在处理器核处于高功耗场景时，执行第一响应策略。
其中，第一响应策略用于在当前频率周期内降低处理器核的功耗，高功耗场景用于指示处理器核正在执行高功耗指令，频率周期用于指示处理器核基于一个频率进行工作的周期。
可选地，该方法还包括：处理器核向频率控制器发送第一系统控制信号，第一系统控制信号用于指示频率控制器执行第二响应策略；频率控制器接收第一系统控制信号；频率控制器执行第二响应策略，第二响应策略用于在当前频率周期的下一个频率周期内降低处理器核的功耗。
此外，在频率控制器执行第二响应策略之后，频率控制器还可以向处理器核发送第二系统控制信号，第二系统控制信号用于指示第二响应策略生效。
进一步地，在处理器核发送第一系统控制信号之后，处理器核接收第二系统控制信号；然后，处理器核停止执行第一响应策略。
此外，在频率控制器执行第二响应策略之后，该方法还包括：频率控制器查询是否再次接收到来自处理器核的第一系统控制信号；频率控制器在预设时长内未接收到来自处理器核的第一系统控制信号的情况下，停止执行第二响应策略。
需要说明的是，图12所示的降低功耗的方法为处理器100中处理器核101以及频率控制器102所执行的方法，图12所示的方法中未详尽描述的实现方式及其技术效果可以参见处理器100中的相关描述，此处不再赘述。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (20)

  1. 一种处理器，其特征在于，包括：
    处理器核，用于判断所述处理器核是否处于高功耗场景；在所述处理器核处于所述高功耗场景时，执行第一响应策略，所述第一响应策略用于在当前频率周期内降低所述处理器核的功耗，所述高功耗场景用于指示所述处理器核执行高功耗指令，频率周期用于指示所述处理器核基于一个频率进行工作的周期。
  2. 如权利要求1所述的处理器，其特征在于，所述处理器还包括频率控制器；所述处理器核，还用于：向所述频率控制器发送第一系统控制信号，所述第一系统控制信号用于指示所述频率控制器执行第二响应策略；
    所述频率控制器，用于接收所述第一系统控制信号，执行所述第二响应策略，所述第二响应策略用于在当前频率周期的下一个频率周期内降低所述处理器核的功耗。
  3. 如权利要求2所述的处理器，其特征在于，所述频率控制器还用于：
    在执行所述第二响应策略之后，向所述处理器核发送第二系统控制信号，所述第二系统控制信号用于指示所述第二响应策略生效。
  4. 如权利要求3所述的处理器，其特征在于，所述处理器核还用于：
    在发送所述第一系统控制信号之后，接收所述第二系统控制信号；
    停止执行所述第一响应策略。
  5. 如权利要求1～4任一项所述的处理器，其特征在于，所述处理器核判断所述处理器核是否处于高功耗场景时，具体用于：
    根据指令流水线中高功耗指令的密度判断所述处理器核是否处于高功耗场景。
  6. 如权利要求5所述的处理器，其特征在于，所述处理器核包括：
    指令比较电路，用于识别所述指令流水线中的所述高功耗指令；
    计数器，用于对所述指令比较电路识别出的所述高功耗指令进行计数，得到第一计数值；在所述第一计数值超过第一阈值的情况下，确定所述处理器核处于高功耗场景。
  7. 如权利要求1～4任一项所述的处理器，其特征在于，所述处理器核在判断所述处理器核是否处于高功耗场景时，具体用于：
    根据高功耗事件的表征信号的密度判断所述处理器核是否处于高功耗场景，所述高功耗事件的表征信号为所述处理器核执行高功耗指令时在所述处理器核的控制单元、运算单元或存储单元中出现的信号。
  8. 如权利要求7所述的处理器，其特征在于，所述处理器核包括：
    累加器，用于对所述高功耗事件的表征信号的出现次数进行累加，得到第二计数值；
    比较器，用于在所述第二计数值超过第二阈值的情况下，确定所述处理器核处于高功 耗场景。
  9. 如权利要求1～8任一项所述的处理器，其特征在于，所述处理器核在执行第一响应策略时，具体用于：
    在当前频率周期内降低所述指令流水线的发射宽度。
  10. 如权利要求9所述的处理器，其特征在于，所述处理器核在降低所述指令流水线的发射宽度时，具体用于：
    关闭所述指令流水线中的至少一个发射通道。
  11. 如权利要求1～8任一项所述的处理器，其特征在于，所述处理器核包括锁相环电路，用于输出时钟信号；
    所述处理器核在执行第一响应策略时，具体用于：
    对所述锁相环电路输出的所述时钟信号进行分频，得到分频时钟信号；
    在当前频率周期内输出所述分频时钟信号，所述分频时钟信号用于驱动所述处理器核。
  12. 如权利要求2～11任一项所述的处理器，其特征在于，所述频率控制器在执行所述第二响应策略时，具体用于：
    在当前频率周期的下一个频率周期对下发至所述处理器核的频率进行调整。
  13. 如权利要求12所述的处理器，其特征在于，所述频率控制器在当前频率周期的下一个频率周期对下发至所述处理器核的频率进行调整时，具体用于：
    向所述处理器核下发调频频率，所述调频频率的生效时间为当前频率周期的下一个频率周期的开始时刻，所述调频频率小于当前频率周期的下一个频率周期的预设调频频率。
  14. 如权利要求12所述的处理器，其特征在于，所述频率控制器在当前频率周期的下一个频率周期对下发至所述处理器核的频率进行调整时，具体用于：
    向所述处理器核下发功耗预算以及最大频率，所述功耗预算和所述最大频率的生效时间为当前频率周期的下一个频率周期的开始时刻，所述最大频率用于指示所述处理器核工作的最大频率，所述功耗预算与当前频率周期的下一个频率周期的预设功耗预算相同，所述最大频率小于当前频率周期的下一个频率周期的预设最大频率。
  15. 如权利要求2～14任一项所述的处理器，其特征在于，所述频率控制器还用于：
    在执行所述第二响应策略之后，查询是否再次接收到来自所述处理器核的第一系统控制信号；
    若在预设时长内未接收到来自所述处理器核的第一系统控制信号，则停止执行所述第二响应策略。
  16. 一种降低功耗的方法，其特征在于，包括：
    处理器核判断所述处理器核是否处于高功耗场景；
    所述处理器核在所述处理器核处于所述高功耗场景时，执行第一响应策略，所述第一响应策略用于在当前频率周期内降低所述处理器核的功耗，所述高功耗场景用于指示所述处理器核执行高功耗指令，频率周期用于指示所述处理器核基于一个频率进行工作的周期。
  17. 如权利要求16所述的方法，其特征在于，还包括：
    所述处理器核向频率控制器发送第一系统控制信号，所述第一系统控制信号用于指示所述频率控制器执行第二响应策略；
    所述频率控制器接收所述第一系统控制信号；
    所述频率控制器执行所述第二响应策略，所述第二响应策略用于在当前频率周期的下一个频率周期内降低所述处理器核的功耗。
  18. 如权利要求17所述的方法，其特征在于，在所述频率控制器执行所述第二响应策略之后，还包括：
    所述频率控制器向所述处理器核发送第二系统控制信号，所述第二系统控制信号用于指示所述第二响应策略生效。
  19. 如权利要求18所述的方法，其特征在于，在所述处理器核发送所述第一系统控制信号之后，还包括：
    所述处理器核接收所述第二系统控制信号；
    所述处理器核停止执行所述第一响应策略。
  20. 如权利要求17～19任一项所述的方法，其特征在于，在所述频率控制器执行所述第二响应策略之后，还包括：
    所述频率控制器查询是否再次接收到来自所述处理器核的第一系统控制信号；
    所述频率控制器在预设时长内未接收到来自所述处理器核的第一系统控制信号的情况下，停止执行所述第二响应策略。
PCT/CN2019/124706 2019-12-11 2019-12-11 一种处理器及降低功耗的方法 WO2021114155A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980102277.6A CN114730263A (zh) 2019-12-11 2019-12-11 一种处理器及降低功耗的方法
PCT/CN2019/124706 WO2021114155A1 (zh) 2019-12-11 2019-12-11 一种处理器及降低功耗的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/124706 WO2021114155A1 (zh) 2019-12-11 2019-12-11 一种处理器及降低功耗的方法

Publications (1)

Publication Number Publication Date
WO2021114155A1 true WO2021114155A1 (zh) 2021-06-17

Family

ID=76329257

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/124706 WO2021114155A1 (zh) 2019-12-11 2019-12-11 一种处理器及降低功耗的方法

Country Status (2)

Country Link
CN (1) CN114730263A (zh)
WO (1) WO2021114155A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023202305A1 (zh) * 2022-04-18 2023-10-26 华为技术有限公司 芯片和电压噪声抑制方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116881090B (zh) * 2023-09-06 2024-01-26 北京壁仞科技开发有限公司 计算装置以及控制计算装置中的计算核的能耗的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1434934A (zh) * 1999-12-23 2003-08-06 英特尔公司 具有数字能量调节的微处理器
CN1608240A (zh) * 2001-12-28 2005-04-20 英特尔公司 多模式功率节制机制
US20150160714A1 (en) * 2013-12-10 2015-06-11 Electronics And Telecommunications Research Institute Method of dynamically contolling power in multicore environment
CN105765957A (zh) * 2014-03-28 2016-07-13 联发科技股份有限公司 在电子装置中进行系统功率控制的方法和相关设备
US20170177046A1 (en) * 2015-12-16 2017-06-22 Intel Corporation Controlling Telemetry Data Communication In A Processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1434934A (zh) * 1999-12-23 2003-08-06 英特尔公司 具有数字能量调节的微处理器
CN1608240A (zh) * 2001-12-28 2005-04-20 英特尔公司 多模式功率节制机制
US20150160714A1 (en) * 2013-12-10 2015-06-11 Electronics And Telecommunications Research Institute Method of dynamically contolling power in multicore environment
CN105765957A (zh) * 2014-03-28 2016-07-13 联发科技股份有限公司 在电子装置中进行系统功率控制的方法和相关设备
US20170177046A1 (en) * 2015-12-16 2017-06-22 Intel Corporation Controlling Telemetry Data Communication In A Processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023202305A1 (zh) * 2022-04-18 2023-10-26 华为技术有限公司 芯片和电压噪声抑制方法

Also Published As

Publication number Publication date
CN114730263A (zh) 2022-07-08

Similar Documents

Publication Publication Date Title
WO2021114155A1 (zh) 一种处理器及降低功耗的方法
KR102049952B1 (ko) 전력 분배 네트워크(pdn) 드룹/오버슈트 완화
CN111837110B (zh) 一种用于减少存储器系统的存储器访问等待时间的方法和装置
US8006076B2 (en) Processor and program execution method capable of efficient program execution
US8214662B2 (en) Multiprocessor control unit, control method performed by the same, and integrated circuit
US7334143B2 (en) Computer power conservation apparatus and method that enables less speculative execution during light processor load based on a branch confidence threshold value
US20080235364A1 (en) Method and apparatus for using dynamic workload characteristics to control CPU frequency and voltage scaling
US20150121106A1 (en) Dynamic and Adaptive Sleep State Management
US10209998B2 (en) Multi-threading processor and a scheduling method thereof
TW200305074A (en) Multiple mode power throttle mechanism
CN108885486B (zh) 增强型动态时钟和电压缩放(dcvs)方案
EP4086776A1 (en) Syncronization of interrupt processing to reduce power consumption
JP6418056B2 (ja) 演算処理装置及び演算処理装置の制御方法
TWM252999U (en) Processing apparatus
US9317096B2 (en) Performance aware idle power management
US9218048B2 (en) Individually activating or deactivating functional units in a processor system based on decoded instruction to achieve power saving
JP2017021513A (ja) マルチコアプロセッサ、マルチコアプロセッサのクロック制御方法およびクロック制御プログラム
JP2003271267A (ja) プロセッサの電力制御方法
JP2012003691A (ja) 情報処理装置、情報処理方法、情報処理プログラム、情報処理プログラムを記録したコンピュータ読み取り可能な記録媒体及び集積回路
US10270434B2 (en) Power saving with dynamic pulse insertion
JP2014038502A (ja) 情報処理装置、情報処理方法、およびプログラム
JPH0581042A (ja) プライオリテイ制御回路
US20150234449A1 (en) Fast power gating of vector processors
KR102157326B1 (ko) 컴퓨팅 장치, 컴퓨팅 장치의 메모리 대역폭 조정 방법 및 메모리 대역폭 조정기
JP2008243220A (ja) 情報処理通信装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19955762

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19955762

Country of ref document: EP

Kind code of ref document: A1