WO2021104093A1

WO2021104093A1 - Output adjustable nanosecond pulse source based on avalanche transistor cascade circuit

Info

Publication number: WO2021104093A1
Application number: PCT/CN2020/129203
Authority: WO
Inventors: 谈宇光; 鲁远甫; 陈良培; 焦国华; 章逸舟; 刘鹏
Original assignee: 深圳先进技术研究院
Priority date: 2019-11-29
Filing date: 2020-11-16
Publication date: 2021-06-03
Also published as: CN110880884B; CN110880884A

Abstract

A control circuit and a control method for a pulse output source, and a corresponding pulse source system. The control circuit comprises a trigger part, a cascade charging and discharging part, and a load part. The cascade charging and discharging part comprises a plurality of units cascaded in sequence. Each of the units comprises an avalanche transistor (Qm), a controllable transistor (QCm), a current limiting resistor (Rm1, Rm2), and a charging capacitor (Cm). A base of the controllable transistor (QCm) of each unit is used for receiving a control signal (Pm), so that the charging capacitor (Cm) in the unit can be selected to exclude from a charging capacitor group to adjust the output power of a pulse output source. The pulse source system can selectively collect electricity from the energy source, is low in cost, is easy to manufacture, and can meet requirements of more application scenes while improving the control flexibility.

Description

Output adjustable nanosecond pulse source based on avalanche triode cascade circuit

Technical field

The present invention relates to the technical field of control circuits, in particular to a control circuit, a control method and a pulse source system of a pulse source.

Background technique

With the increasing innovation of electronic products, in many fields such as ground penetrating radar, sterilization, industrial processing, laser strobe imaging, etc., the demand for high-voltage, high-power, and repetitive frequency nanosecond-level narrow pulse signal sources is also increasing. more. Taking laser devices that are more and more widely used as an example, the power of commonly used small lasers is about ten milliwatts to one hundred milliwatts, and even some of them reach the watt level. Under normal circumstances, too much power supply will cause damage to the laser. However, the instant high power will not cause damage to the laser. Therefore, the application of instantaneous triggering of the laser also emerges, and then the method of instantaneously triggering the laser to light up, such as general output Q-switching technology in which the continuous laser energy is compressed into extremely narrow pulses has also been developed. Although the peak power of Q-switched lasers can be increased by several orders of magnitude, this method of triggering lasers has the disadvantage of frequency limitation. Not all lasers can do this. In comparison, high peak power and narrow pulses can also be obtained. The avalanche cascade circuit control method has better frequency band universality.

In practical applications, the higher the voltage or power is not always the better, and sometimes it is necessary to switch between multiple voltages or powers in order to apply different output results according to different application scenarios. For example, in the application of driving a laser tube, in order to make the brightness of the laser automatically adjust with the application scene, it is necessary to adjust the driving power to achieve this. Although the existing avalanche cascade circuits are of various styles, they are basically based on the Mark cascade circuit, and the output power is fixed, which has great limitations for devices that require a variety of outputs.

technical problem

The main purpose of the present invention is to provide a control circuit for a high-voltage narrow pulse output source, which improves the structure of the multi-level Mark cascade circuit, adds a specific switch control module, and combines software to realize the control of some units in the cascade circuit. Selective cascading to achieve the purpose of controllable output.

Technical solutions

Specifically, a pulse output source control circuit includes a trigger part, a cascade charging and discharging part, and a load part. The cascaded charging and discharging part includes a plurality of sequentially cascaded units, each of the above-mentioned units includes an avalanche transistor, a controllable transistor, a current-limiting resistor, and a charging capacitor; wherein the DC power supply is added to the avalanche through the current-limiting resistor The collector of the transistor, when the avalanche transistor is in the off state, the DC power supply can charge the charging capacitor through a current limiting resistor; the emitter of the avalanche transistor is grounded; the base of the avalanche transistor in each of the above-mentioned units The pole is connected to the charging capacitor in the previous unit immediately adjacent to the current unit or the trigger part immediately adjacent to the current unit. The base of the controllable transistor in each of the above-mentioned units is used to receive control signals, the emitter of the controllable transistor is connected to the base of the avalanche transistor in the current unit, and the collector of the controllable transistor is connected to the current unit. The collector of the avalanche transistor in the next cell next to the cell.

Preferably, the controllable transistor and the avalanche transistor are transistors of the same model. For example, the controllable transistor is of NPN type.

Further, the trigger mode of the avalanche transistor is triggered turn-on, over-voltage turn-on, or rapid rising edge turn-on. When the trigger mode of the controllable transistor is hardware trigger or software trigger.

In addition, in order to achieve the above-mentioned object, the present invention also provides a method for controlling a high-voltage narrow pulse output source, which uses the control circuit of the above-mentioned pulse output source. When the trigger part does not receive a trigger signal, the DC power supply is The charging capacitor is charged; when the triggering part receives the trigger signal, the capacitor group including a plurality of charging capacitors starts to discharge to achieve power output; in order to achieve output power adjustment, one, two or more The base of the controllable transistor in each of the units provides a trigger signal to exclude the charging capacitor in the unit where the controllable transistor is located from the capacitor bank, thereby realizing the adjustment of the output power.

Preferably, providing a trigger signal to the base of the controllable transistor is specifically providing a trigger signal to the bases of the controllable transistors of two or more units spaced apart from each other. At the same time, the trigger signal provided to the trigger part and the trigger signal provided to the base of the controllable transistor may also be the same

Further, a trigger signal is provided to the base of the controllable transistor before the trigger signal is provided to the trigger part.

In addition, in order to achieve the above-mentioned object, the present invention also provides a high-voltage narrow pulse output source system, the control circuit of the system includes the above-mentioned pulse output source control circuit, and can use the above-mentioned pulse output source control method to adjust the The output power of the system.

Beneficial effect

The invention is based on the Mark avalanche cascade control circuit to produce a signal source with high peak value and narrow pulse, and combined with software control, realizes the adjustable voltage and power output. While increasing the control flexibility, the output source and corresponding control can meet more requirements. The needs of the application scenario. In addition, the present invention selectively collects the voltage from the energy source, does not have any restriction on the frequency band of the driving source, has low cost and is easy to manufacture.

Description of the drawings

Fig. 1 is a schematic diagram of a multi-tube Mark cascade circuit in the prior art, Fig. 1a is a multi-tube series circuit, Fig. 1b is a multi-stage Mark circuit, and Fig. 1c is a multi-tube parallel circuit;

2 is a schematic diagram of a cascade circuit of n-level Mark circuits in the prior art;

Fig. 3 is a schematic diagram of an improved n-level Mark circuit cascade circuit of the present invention;

4 is a schematic diagram of the combined circuit of the discharge capacitor when P0+P1 is triggered in the present invention;

Figure 5 is a schematic diagram of the output of the 6-level avalanche circuit under a 50 ohm load of the present invention;

Fig. 6 is a schematic diagram of the output of the 4-level avalanche circuit under a 50 ohm load of the present invention.

Embodiments of the present invention

The realization of the objectives, functional characteristics and advantages of the present invention will be further described in conjunction with the embodiments and with reference to the drawings.

It should be understood that the specific embodiments described here are only used to explain the present invention, but not used to limit the present invention.

The basic circuits are shown in Figures 1a to 1c. At present, the Mark cascade circuit mainly includes multi-tube series cascade and multi-tube parallel cascade. With the increase of applications, there are many ways to combine series and parallel. Multi-tube series can effectively reduce the breakdown risk of a single tube under high-voltage driving. The parallel connection of multiple tubes can realize parallel charging and serial discharging of the charging capacitors to achieve a higher output voltage. The combination of multi-tube series and parallel can absorb the advantages of the two methods, and can efficiently output instantaneous high-voltage and high-power pulses.

There are three avalanche trigger modes for avalanche transistors: trigger conduction, overvoltage conduction, and rapid rising edge conduction. In this embodiment, the trigger conduction mode is taken as an example, but the overall solution is not limited to this trigger mode. It is easy for those skilled in the art to understand that the other two trigger modes are also applicable, and depending on the trigger mode, the technology in the art Personnel know how to modify part of the circuit at the trigger source. Refer to Figure 2, which is a relatively complete schematic diagram of an n-level Mark cascade circuit, which mainly includes a trigger part, a cascade charge and discharge part, and a load part. In this embodiment, the avalanche transistor adopts a triggered turn-on method. Among them, the trigger part includes an avalanche transistor Q0, a current limiting resistor R01, a basic static resistance R02, a capacitor C00, and a capacitor C0. The trigger part belongs to a first-level avalanche, and C00 is a filter capacitor, which filters and blocks the trigger signal. The high-voltage direct current power source DC is added to the collector of the avalanche transistor Q0 through the current limiting resistor R01. Before the trigger pulse P0 comes, the avalanche transistor Q0 is in an off state, so the power source DC charges the capacitor C0 through R01. The trigger part is connected with the cascade charging and discharging part, and the cascading charging and discharging part includes n independent units, n>=1. Each of the above-mentioned units includes an avalanche transistor Qm, current-limiting resistors Rm1 and Rm2, and a capacitor Cm, where m=1, 2, 3...n. The current source DC is added to the collector of the avalanche transistor Qm through the current limiting resistor Rm1, the emitter of the avalanche transistor Qm is grounded through Rm2, and the base of the avalanche transistor Qm is connected to one end of the capacitor of the previous unit. When the avalanche transistor Qm is in the off state, The power supply DC charges the capacitor Cm through Rm1.

As shown in Figure 2, the cascaded charging and discharging part of the figure illustrates 4 cells. The first cell includes an avalanche transistor Q1, current-limiting resistors R11 and R12, and a capacitor C1, that is, for this cell m= 1. The current source DC is added to the collector of the avalanche transistor Q1 through the current limiting resistor R11, the emitter of the avalanche transistor Q1 is grounded through R12, and the base of the avalanche transistor Q1 is connected to one end of the capacitor of the previous unit. For the first unit, the front of the unit is the trigger part, so the base of the avalanche transistor Q1 is connected to one end of the capacitor C0 of the trigger part. When the avalanche transistor Q1 is in the off state, the power supply DC charges the capacitor C1 through R11. The circuit structure of each unit is the same. For example, the second unit includes an avalanche transistor Q2, current-limiting resistors R21 and R22, and a capacitor C2. The base of the avalanche transistor Q2 in this unit is connected to the previous unit, that is, the capacitor C1 in the first unit One end. By analogy, parallel charging of capacitors at all levels is realized. That is to say, when the trigger part does not receive the trigger signal pulse P0, the avalanche transistors Q0,..., Qm are all in the off state, and the energy storage capacitors at all levels are in the charging state. The last unit in the cascade charging and discharging section is connected to the load section. The load part is an electric equipment with variable impedance, which is represented by RLOAD here.

When the trigger pulse P0 is sent out, the avalanche transistor Q0 of the trigger part is turned on and the capacitor is discharged. Under its excitation, the avalanche transistor Qm of each unit in the cascaded charging and discharging part is also turned on in turn, realizing that the capacitors of all levels are connected in series. Discharge in series to output high power.

On the basis of the above-mentioned multi-level Mark circuit, the present invention adds multiple avalanche transistors for switch control, referred to as controllable transistors. In Figure 3, the upper dashed frame is shown to distinguish the original cascade circuit in the lower dashed frame. The various avalanche transistors in. Each controllable transistor can be independently controlled on or off, which is convenient for real-time controllability to adjust the output power. Each controllable transistor in the circuit is not limited to the NPN type. As shown in Figure 3, each unit in the cascade charging and discharging section adds a controllable transistor QCm, where m=1, 2, 3...n. In this embodiment, each controllable transistor is, for example, an avalanche transistor of the same model, and the base of each controllable transistor is controlled by a different signal, which are named P1, P2, P3, P4, etc., respectively. The base of each controllable transistor is connected to a control signal, which can be replaced. The control signal can also be an optical signal or be controlled by a hardware switch. The emitter and collector of the controllable transistor QCm are respectively connected to the base of the avalanche transistor Qm in the current cell and the collector of the avalanche transistor Qm+1 in the next cell.

In other embodiments, each avalanche transistor may not be limited to avalanche transistors of the same model. If there is only one avalanche power supply (VCC) used in the entire circuit, in order to achieve that the avalanche transistors in the entire chain can be avalanche at the same time, it is best to use the same type of avalanche transistors. But different types of avalanche transistors can also be used, but they need to be avalanche transistors with the same or similar parameters such as the avalanche critical point. Alternatively, several transistors with a low avalanche critical point can be combined in series, so that the combined avalanche critical point is the same or similar to other single or combined avalanche critical points. Of course, you can also choose to use multiple power supplies. No matter which method is adopted, the ultimate goal is to ensure that all avalanche transistors can be avalanche in time after the signal comes.

As shown in Figure 3, among the 4 cells in the example of the cascaded charge and discharge section, the first cell also includes a controllable transistor QC1. The base of the controllable transistor QC1 is controlled by the control signal P1, and the emitter of the controllable transistor QC1 is controlled by the control signal P1. The and collector are respectively connected to the base of the current cell avalanche transistor Q1 and the next cell, that is, the collector of the avalanche transistor Q2 in the second cell. The second unit includes a controllable transistor QC2, the base of the controllable transistor QC2 is controlled by the control signal P2, and its emitter and collector are respectively connected to the base of the current second unit avalanche transistor Q2 and the next unit, That is, the collector of the avalanche transistor Q3 in the third cell. And so on, until the collector of the controllable transistor QCn-1 of the penultimate cell in the cascade charge and discharge is connected to the collector of the controllable transistor Qn of the last cell. In the whole scheme, the control link is QC1-QCn, which can be controlled by software or by hardware. When using software control, the software control signal can be connected to the base of any avalanche transistor in QC1-QCn. For example, when the control signal Pm (m=1, 2, 3...n) is at high level, the connected NPN type (high level control NPN type, low level control PNP type) avalanche transistor QCm is controlled by an external signal. When an avalanche occurs in the link, the current avalanche transistor Qm is prevented from avalanche. When using hardware control, the base of QC1-QCn can be connected to the external high and low level through the switch button. According to needs, the base level state of the corresponding position QCm can also be manually switched, so as to control the corresponding avalanche transistor Qm to avoid an avalanche.

In fact, the pulse signal P0 is the trigger signal of the trigger stage of the entire cascade circuit. When the main avalanche transistors Q0 and Qm all have an avalanche, the instantaneous maximum output power generated by the avalanche is the maximum output power, assuming that the maximum output power is W. The pulse voltage intensity finally released by the entire circuit is approximately proportional to the number of capacitors in the discharge capacitor combination. The purpose of adding a controllable transistor in the present invention is to be able to software change the number of discharge capacitors in the discharge capacitor combination. When it is necessary to adjust the output instantaneous voltage and instantaneous power, it can be realized by giving P1, P2, P3, P4... and other signals. Preferably, signals such as P1, P2, P3, P4, etc. are the same as the P0 signal. For example, in the need to lower the output power, consider removing the capacitor C1 from the discharge capacitor combination, which can be achieved by making the avalanche transistors Q1 and Q2 non-conducting, while the other avalanche transistors Qm are normally avalanche. At this time, P0 and P1 in the P series control signals can simultaneously output trigger pulses, while other P series trigger signals are not input to the base of the controllable transistor. The P1 trigger signal is connected to the base of the controllable transistor QC1 to turn on the controllable transistor QC1. Therefore, the avalanche transistor Q1 is turned off, the capacitor C1 is not discharged, and the avalanche transistor Q2 is not avalanche either. However, due to the conduction of the controllable transistor QC1, C2 can still be in the discharge capacitor combination without affecting the conduction of the avalanche transistor Q3. Therefore, P0 and P1 simultaneously output trigger pulses to remove the capacitor C1 from the combined discharge capacitor. In the above method of use, it is also possible to make P1 as the switching signal occur one pulse before P0.

By analogy, if you continue to output the P3 trigger signal, the controllable transistor QC3 will be turned on, and the avalanche transistors Q3 and Q4 will be turned off, so the capacitor C3 will not be connected to the discharge circuit, and the discharge of other capacitors will not be affected. . In fact, in the P series trigger signal, if the Pm signal is input alone, the capacitance Cm of the unit will be removed from the discharge capacitance combination. According to the circuit shown in Figure 3, it is not difficult to judge, P0, P1, P3... will be triggered at the same time, C1 and C3 will be removed from the discharge capacitor combination, P0, P2, P4... will be triggered at the same time, C2 and C4 will be removed from the discharge capacitor combination In this way, the avalanche of two or more main circuit avalanche transistors can be avoided, thereby avoiding the corresponding charging capacitors from being added to the series discharging capacitor combination.

However, it should be noted that due to the circuit structure, the selection of trigger signal except P0 needs to be sent at intervals. If adjacent trigger signals are to be selected for triggering at the same time, then the signal corresponding to the controllable transistor of the following unit does not play a role in removing the capacitance. For example, if the trigger signal is selected as P0, P1, P3..., or P0, P2, P4..., or P0, P1, P4..., etc., the capacitance Cm of the unit corresponding to the Pm signal can be eliminated. But if it is not sent at intervals, the effect of sending every two adjacent signals at the same time will be equivalent to sending a front-end signal. For example, the trigger signal selection P0, P1, P2 is equivalent to the selection of P0, P1. For another example, the trigger signal selection P0, P2, P3 is equivalent to the selection of P0, P2. The reason why the latter trigger signal in the above continuous Pm signal does not work is because the access of the former trigger signal has made the capacitance of the unit corresponding to the latter trigger signal in a connected state. Furthermore, if more Pm trigger signals are input continuously, for example, the trigger signal selection P0, P1, P2, P3 is equivalent to the selection of P0, P1, P3, because P1 and P2 are adjacent, and P2 does not play a role. Although P2 and P3 are adjacent to each other, since P2 does not play a role, it does not affect the effectiveness of P3.

By controlling the P series trigger signal as described above, those skilled in the art can control and adjust the output power. Assuming that the capacitances of all charging point capacitors are equal, then if x effective signals are triggered at the same time with P0, it is equivalent to the instantaneous maximum output power of W·(kx)/k. In the formula, k=n+1 means all The number of charging capacitors. n represents the number of cells in the cascade charging and discharging part, and k is the total number of all charging capacitors including capacitors C0 and Cm. Since the above two consecutive Pm trigger signals will cause the second trigger signal to fail, the number of valid Pm signals is at most (n-1)/2.

Before the trigger signal P0 comes, all the energy storage capacitors can be in a charged state at the same time. Only when P0 is added, and other Pm (m=0,1,2,3,4,... generally refers to the controllable transistor base trigger signal) signal is not added, the circuit function is the same as that in Figure 2, but only a multi-level Mark Cascade circuit. At this time, the avalanche transistors such as Q1, Q2, Q3, Q4,... will be avalanche breakdown in turn. At this time, the discharge capacitor combination is: C0+C1+C2+C3+C4+C5+..., the number of discharge capacitors is the largest, and the instantaneous voltage is output. The highest, the instantaneous output power is also the highest. The total output instant power value varies with the number of stages of DC and avalanche transistors and the parameters of avalanche transistors. Only when the trigger signals P0 and P1 are added, the first avalanche breakdown is Q0 and QC1. Then Q3, Q4, Q5... breakdown. The avalanche breakdown of QC1 causes the voltage difference between the collector and emitter of Q1 to be insufficient for avalanche conditions, which indirectly makes C1 unable to connect to the discharge capacitor combination in series through Q1. At this time, the discharge capacitor combination is: C0+C2+C3+C4+..., C1 is missing, so the discharge path is shown as the thick solid line in Figure 4, and the instantaneous output power at this time is W·(k-1)/k, that is x=1.

Only when P0+P1+P2+P3 is added, the first avalanche breakdown is Q0, QC1, QC2, and QC3. Then Q5, Q6, etc... breakdown. The avalanche breakdown of QC1 causes the voltage difference between the collector and emitter of Q1 to be insufficient for avalanche conditions, thereby indirectly causing C1 to fail to connect in series with the discharge capacitor combination through Q1. Because P2 has no effect on the charging and discharging of the circuit at this time, C2 is normally involved in charging and discharging. In the same way, C3 cannot be connected in series with the discharge capacitor combination. At this time, the discharge capacitor combination is: C0+C2+C4+..., lack of C1, C3. The instantaneous power output at this time is W·(k-2)/k, that is, x=2.

With reference to the above control method, the number of discharge capacitors can be combined at will. The types that can be combined also vary with the number of cascades. The more cascades, the more combinations and the more points that can be adjusted.

Based on the application of the present invention to the laser drive of the camera's strobe imaging front end, it has been possible to realize a high voltage pulse with a falling edge of 3 ns (nanoseconds), and the amplitude can be adjusted. Figures 5 and 6 of the specification are the test pictures of the 6-level avalanche and the 4-level avalanche under a load of 50 ohms. It can be seen from Fig. 5 that the maximum pulse amplitude during the 6-level avalanche is 272V and the load is 50 ohms. It can be concluded that the instantaneous maximum output power can reach 1479 watts. Figure 6 is based on Figure 5 and turned off the two-stage avalanche. It can be seen that the maximum pulse amplitude in the four-stage avalanche is 234V and the load is 50 ohms. The instantaneous maximum output power can reach 1095 watts.

It should be noted that in this article, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, It also includes other elements that are not explicitly listed, or elements inherent to the process, method, article, or system. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, article, or system that includes the element.

The sequence numbers of the foregoing embodiments of the present invention are only for description, and do not represent the superiority or inferiority of the embodiments.

The above are only preferred embodiments of the present invention, and do not limit the scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied to other related technical fields , The same reason is included in the scope of patent protection of the present invention.

Claims

A pulse output source control circuit, the circuit includes a trigger part, a cascade charging and discharging part and a load part, characterized in that:

The cascaded charging and discharging part includes a plurality of sequentially cascaded units, each of the above-mentioned units includes an avalanche transistor, a controllable transistor, a current-limiting resistor, and a charging capacitor; wherein the DC power supply is added to the avalanche through the current-limiting resistor The collector of the transistor, when the avalanche transistor is in the off state, the DC power supply can charge the charging capacitor through a current limiting resistor; the emitter of the avalanche transistor is grounded; the base of the avalanche transistor in each of the above-mentioned units Pole connected to the charging capacitor in the previous unit immediately adjacent to the current unit or the trigger part immediately adjacent to the current unit;

The base of the controllable transistor in each of the above-mentioned units is used to receive control signals, the emitter of the controllable transistor is connected to the base of the avalanche transistor in the current unit, and the collector of the controllable transistor is connected to the current unit. The collector of the avalanche transistor of the next cell next to the cell.
The pulse output source control circuit according to claim 1, wherein the controllable transistor is of NPN type.
The pulse output source control circuit according to claim 1, wherein the controllable transistor and the avalanche transistor are transistors of the same model or transistors meeting the same avalanche condition.
The pulse output source control circuit according to claim 1, wherein the trigger mode of the controllable transistor is software trigger or hardware trigger.
A pulse output source control method using the pulse output source control circuit of any one of claims 1 to 4, characterized in that:

When the trigger part does not receive a trigger signal (P0), the DC power supply charges the charging capacitor;

When the trigger part receives the trigger signal (P0), the capacitor group including the plurality of charging capacitors starts to discharge to achieve power output;

Provide a trigger signal to the base of the controllable transistor in one, two or more of the units to exclude the charging capacitor in the unit where the controllable transistor is located from the capacitor group, thereby realizing the output power adjust.
The pulse output source control method according to claim 5, wherein providing a trigger signal to the base of the controllable transistor is specifically providing a trigger to the bases of the controllable transistors of two or more units spaced apart from each other. signal.
The pulse output source control method according to claim 5, wherein the trigger signal is provided to the base of the controllable transistor before the trigger signal is provided to the trigger part.
The pulse output source control method according to claim 5, wherein the trigger signal provided to the trigger part is the same as the trigger signal provided to the base of the controllable transistor.
A pulse output source system, characterized in that the control circuit of the system comprises the pulse output source control circuit according to any one of claims 1-4.