WO2021101532A1

WO2021101532A1 - Port circuits

Info

Publication number: WO2021101532A1
Application number: PCT/US2019/062331
Authority: WO
Inventors: Charles Shaver
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2019-11-20
Filing date: 2019-11-20
Publication date: 2021-05-27

Abstract

Example implementations relate to port circuits. For example, a circuit can include a tristate buffer that includes: a first data input coupled to a transceiver, a second data input coupled to an output of a connector, a first data output to transfer data from the first data input to an input/output mechanism when activated by a first signal, and a second data output to transfer data from the second data input to the input/output mechanism when activated by a second signal.

Description

PORT CIRCUITS

Background

[0001] Computing devices can utilize a plurality of peripheral devices through communication ports (e.g., universal serial bus (USB) port, etc.). In some examples, the different peripheral devices can utilize different communication protocols. In some examples, the different communication protocols can utilize different devices to convert the communication protocol to a different communication protocol to be utilized by the computing device.

Brief Description of the Drawings

[0002] Figure 1 illustrates an example of a circuit diagram for port circuits, in accordance with the present disclosure.

[0003] Figure 2 illustrates an example of a circuit diagram for port circuits, in accordance with the present disclosure.

[0004] Figure 3 illustrates an example of a circuit diagram for port circuits, in accordance with the present disclosure.

[0005] Figure 4 illustrates an example of a circuit diagram for port circuits, in accordance with the present disclosure.

Detailed Description

[0006] Computing devices can utilize peripheral devices to receive inputs and/or provide outputs. For example, peripheral devices can include, but are not limited to: a computer mouse, a microphone, a display, a keyboard, a barcode scanner, among other devices that can be coupled to a computing device. In some examples, peripheral devices can utilize different communication protocols to communicate with the computing device. As used herein, a communication protocol can include a system of rules that allow two entities to transmit information.

[0007] In some examples, particular communication protocols can utilize a transceiver or similar device to convert the communication protocol of a peripheral device into a different communication protocol that can be utilized by the computing device. For example, a first peripheral device can utilize Recommended Standard 232 (RS-232) and a second peripheral device can utilize Transistor-transistor logic (TTL). In this example, the RS-232 communication protocol can utilize a transceiver or similar device to convert the RS-232 communication packets to TTL communication packets. In addition, the TTL communication may not utilize a transceiver and may be directly provided to the computing device or input/output (I/O) device of the computing device. [0008] In some examples, a manual switch can be utilized to switch between communication protocols that utilize a transceiver and communication protocols that do not utilize a transceiver. However, manual switches can create technical issues for users. For example, manual switches may be positioned within an enclosure of the computing device, which may be removed in order to switch between communication protocols. This can result in the computing device having to be restarted or deactivated in order to operate the manual switch.

[0009] The present disclosure relates to port circuits that are capable of switching between different communication protocols, even when the communication protocols utilize different hardware (e.g., transceiver, etc.). In some examples, a firmware interface (e.g., basic input/output system (BIOS) interface, extensible firmware interface (EFI), unified extensible firmware interface (UEFI), etc.) can be utilized to select a particular communication protocol from a plurality of communication protocols. As used herein, a firmware interface can include displayed selections that can be utilized to alter functions of the firmware (e.g., BIOS, EFI, UEFI, etc.). When the communication protocol is selected, the port circuit described herein can receive a corresponding signal or voltage from the firmware and an enable input of a tristate buffer or similar device can activate or deactivate a particular data input such that a data input corresponding to the selected communication protocol is activated while other data inputs corresponding to non-selected communication protocols can be deactivated. In this way, the firmware interface can be utilized to switch between different communication protocols that utilize different hardware without having to remove the enclosure or portion of the enclosure of the computing device.

[0010] Figure 1 illustrates an example of a circuit diagram 100 for port circuits, in accordance with the present disclosure. In some examples, the circuit diagram 100 can illustrate an example circuit for selecting a particular communication protocol to be utilized by a particular port of a computing device. For example, the circuit illustrated by the circuit diagram 100 can be positioned within a computing device that can be coupled to a plurality of different peripheral devices utilizing ports (e.g., communication ports, electrical ports, universal serial bus (USB) ports, etc.). In some examples, the circuit can be communicatively coupled to data inputs of a particular port to receive data inputs from peripheral devices coupled to the particular port.

[0011] In some examples, the circuit diagram 100 can include a tristate buffer 102. In some examples, the tristate buffer 102 can include a plurality of gates 112-1, 112-2. As used herein, a buffer, such as the tristate buffer 102, can include a device to receive an input and provide the input as an output. In some examples, a buffer can be utilized as a propagation delay. As used herein, a tristate buffer 102 can be a buffer with additional enable inputs 113-1 , 113-2 that can be utilized to allow or restrict communication through a corresponding gate 112-1, 112-2. As used herein, the gates 112-1, 112-2 can include separate buffers that can be separately controlled by corresponding enable inputs 113-1, 113-2. In some examples, gate 112-1 can be coupled to a first data input pin (e.g., pin 2 as illustrated in Figure 1 , etc.) and gate 112- 2 can be coupled to a second data input pin (e.g., pin 5 as illustrated in Figure 1, etc.).

In some examples, the enable input 113-1 can be utilized to activate or deactivate gate

112-1. In some examples, the enable input 113-1 can be coupled to a first enable input pin (e.g., pin 1 as illustrated in Figure 1, etc.). In these examples, the enable input 113-2 can be utilized to activate or deactivate gate 112-2. In these examples, the enable input

113-2 can be coupled to a second enable input pin (e.g., pin 7 as illustrated in Figure 1, etc.). [0012] As described herein, the enable inputs 113-1, 113-2 can be utilized to activate or deactivate a corresponding gate 112-1, 112-2. In some examples, the enable inputs 113-1 , 113-2 can activate a corresponding gate 112-1, 112-2 when a received signal through the corresponding input is below a threshold voltage and deactivate a corresponding gate 112-1, 112-2 when a received signal through the corresponding input is above a threshold voltage. In some examples, the gates 112-1, 112-2 can be inversely activated or deactivated. For example, when gate 112-1 is activated, gate 112- 2 is deactivated. In addition, when gate 112-2 is activated, gate 112-1 is deactivated. In this way, data can be transmitted through the tri state buffer 102 from a single input (e.g., from data input pin 2 or data input pin 5, etc.). As described herein, the tristate buffer 102 can include a plurality of pins (e.g., pin 1, pin2, pin 3, pin 4, etc.). In some examples, each of the plurality of pins can be utilized to receive or provide different signals. For example, pin 1 can be utilized as a first output enable input (10E) and pin 7 can be utilized as a second output enable input (20E). In another example, pin 2 can be utilized as a first data input (1A) and pin 5 can be utilized as a second data input (2A). Furthermore, in another example, pin 6 can be utilized as a first data output (1 Y) and pin 3 can be a second data output (2Y). In some examples, the tristate buffer 102 can include a pin 4 (not shown) that can be utilized as a ground pin (GND) and a pin 8 (not shown) that can be utilized as a supply voltage pin (Vcc).

[0013] In some examples, the circuit illustrated by the circuit diagram 100 can include firmware 106 coupled to the enable inputs 113-1, 113-2 to provide a signal to the enable inputs 113-1, 113-2 to activate or deactivate corresponding gates 112-1, 112-2. As used herein, the firmware 106 can include instructions associated with the computing device that controls input/output functions of the computing device. For example, the firmware 106 can include a BIOS, EFI, UEFI, or similar instructions for controlling input/output functions of a computing device. In some examples, the firmware 106 can be coupled to the first enable input 113-1 and/or the second enable input 113-2 through firmware mechanisms. As used herein, a firmware mechanism is a device or system that can communicatively or electrically couple the firmware 106 to other devices. For example, the firmware mechanisms can include electrical connections to allow the firmware 106 to provide a first voltage to the first enable input 113-1 and a second voltage to the second enable input 113-2.

[0014] As described further herein, the firmware 106 can utilize a firmware interface to allow changes to be made to the input/output functions provided by the firmware 106. As used herein, a firmware interface can include instructions to display a selectable menu that can alter the input/output functions provided by the firmware 106. For example, the firmware interface can be prompted utilizing an F10 key on a keyboard peripheral device coupled to the computing device. In this example, the firmware interface can include a plurality of selections that include a communication protocol selection for a plurality of ports. In this way, a particular communication protocol can be selected, and a corresponding signal or voltage can be provided to the enable inputs 113-1, 113-2.

[0015] In some examples, the circuit represented by the circuit diagram 100 can include additional hardware elements that can be utilized by different communication protocols. For example, the circuit diagram can include a transceiver 104. As used herein, a transceiver 104 can include a device that converts a first communication protocol to a second communication protocol. For example, the transceiver 104 can be communicatively coupled to a port of the computing device to receive communication from a peripheral device and convert the communication to a different communication protocol. In some examples, devices that utilize RS-232 can utilize a transceiver 104 to convert the RS-232 protocol to a different protocol (e.g., TTL protocol, etc.) that can be utilized by the I/O mechanism 110 or other hardware of the computing device. Although RS-232 and TTL protocols are described herein, the disclosure is not limited to these communication protocols. In some examples, the circuit diagram 100 can include a peripheral device 108. In these examples, the peripheral device 108 may not need additional hardware such as a transceiver to convert the communication protocol of the peripheral device 108 to a different communication protocol. In these examples, the data output of the peripheral device 108 can be directly coupled to the data input of pin 5 as illustrated in Figure 1.

[0016] As described herein, the firmware 106 can receive a selection from a firmware interface. In some examples, the selection can be a first communication protocol that utilizes the transceiver 104. In these examples, the firmware 106 or firmware mechanism can provide a first voltage to pin 1 to activate the enable input 113- 1 and/or activate the gate 112-1 and also provide a second voltage to pin 7 to deactivate the enable input 113-2 and/or deactivate the gate 112-2. In this way, communication can be provided through the gate 112-1 and through pin 6 to the I/O mechanism 110. In a similar example, the firmware 106 can receive a selection of a second communication protocol that does not utilize the transceiver 104. In this example, the firmware 106 or firmware mechanism can provide a first voltage to pin 7 to activate the enable input 113-2 and/or activate the gate 112-2 and also provide a first voltage to pin 1 to deactivate the enable input 113-1 and/or deactivate gate 112-1. In this way, communication can be provided directly from the peripheral device 108 to the I/O mechanism 110 through pin 3.

[0017] In some examples, the I/O mechanism 110 can be an I/O controller or similar device (e.g., super I/O, etc.) that can be utilized to interface with a plurality of devices and control input/output functions. In some examples, the I/O mechanism 110 can be coupled to pin 6 to receive outputs from the gate 112-1 when the enable input 113-1 is activated. In other examples, the I/O mechanism 110 can be coupled to pin 3 to receive outputs from the gate 112-2 when the enable input 113-2 is activated. To ensure that the I/O mechanism 110 is not receiving communication from pin 6 and pin 3 simultaneously, one enable input from the enable inputs 113-1, 113-2 may be activated at one time. That is, when the enable input 113-1 is activated, then enable input 113-2 is deactivated. In addition, when the enable input 113-2 is activated, then enable input 113-1 is deactivated.

[0018] As described herein, the circuit diagram 100 can illustrate a circuit that can be utilized to switch between communication protocols for devices without having to utilize a physical switch on a printed circuit board (PCB) of the computing device, which may be accessible when a cover or portion of an enclosure is removed from the computing device to reveal the PCB. In addition, the circuit does not tie inputs or outputs together, which can lead to failures.

[0019] Figure 2 illustrates an example of a circuit diagram 200 for port circuits, in accordance with the present disclosure. In some examples, the circuit diagram 200 can include the same or similar elements as the circuit diagram 100 as referenced in Figure 1. For example, the circuit diagram 200 can include a tristate buffer 202 that can utilize a first gate 212-1 with a corresponding first enable input 213-1 and a second gate 212-2 with a corresponding second enable input 213-2. In some examples, the circuit diagram 200 can illustrate a circuit that can be coupled to a port that can receive a connection from a peripheral device (e.g., a first peripheral device 208-1, a second peripheral device 208-2, etc.). In these examples, communication from a peripheral device can be received through a port and the communication can be altered from a first communication protocol to a second communication protocol utilizing a firmware interface 222.

[0020] As described herein, a firmware interface 222 can be a user interface that can be displayed to allow selections to be made that an alter the input/output functions of the firmware 206. As used herein, a user interface can include a selectable display that can allow interactions between a user and a computing device. In some examples, the firmware interface 222 can include a selectable interface that includes a plurality of different communication protocols for a number of ports associated with the computing device that includes the circuit illustrated by the circuit diagram 200. In some examples, the different communication protocols can utilize different hardware in order to convert the communication protocol to a different communication protocol. For example, a first peripheral device 208-1 can utilize a first communication protocol (e.g., RS-232, etc.) that can utilize a transceiver 204 to convert the first communication protocol to a second communication protocol (e.g., TTL, etc.). In this example, a second peripheral device 208-2 can utilize a second communication protocol that may not need a transceiver 204 or other device to convert the second communication protocol to a different communication protocol. Thus, the first peripheral device 208-1 and/or pin of the first peripheral device 208-1 can be coupled to an input of a transceiver 204 and the output of the transceiver 204 can be coupled to pin 2 of the tristate buffer 202. In addition, the second peripheral device 208-2 and/or a pin of the second peripheral device 208-2 can be coupled directly to pin 5 of the tristate buffer 202.

[0021] As described herein, the circuit can include an I/O mechanism 210 that can be coupled to pin 6 of the tristate buffer 202 and/or pin 3 of the tristate buffer 202 in order to receive either input data from pin 2 when the enable input 213-1 is activated or receive input data from pin 5 when the enable input 213-2 is activated. In this way, a selection from the firmware interface 222 can translate in the firmware 206 providing a first signal or voltage to pin 1 and a second signal or voltage to pin 7 to activate one of the enable inputs 213-1, 213-2 and deactivate on of the enable inputs 213-1, 213-2. [0022] In one example, a first communication protocol corresponding to the first peripheral device 208-1 can be selected utilizing the firmware interface 222. In this example, the firmware 206 can provide a first signal to pin 1 to activate the enable input 213-1 and provide a second signal to pin 7 to deactivate the enable input 213-2. In this example, the first peripheral device 208-1 can provide communication using the first communication protocol to the transceiver 204. In this example, the transceiver can convert the first communication protocol to a second communication protocol and provide the communication to pin 2, which can pass through the gate 212-1 since the enable input 213-1 is activated and be directed through pin 6 to the I/O mechanism 210. [0023] In a similar example, a second communication protocol corresponding to the second peripheral device 208-2 can be selected utilizing the firmware interface 222. In this example, the firmware 206 can provide a second signal to pin 1 to deactivate the enable input 213-1 and provide a first signal to pin 7 to activate the enable input 213-2.

In this example, the second peripheral device 208-2 can provide communication using the second communication protocol to pin 5, which can pass through the gate 212-2 since the enable input 213-2 is activated and be directed through pin 3 to the I/O mechanism 210.

[0024] As described herein, the circuit diagram 200 can illustrate a circuit that can be utilized to switch between communication protocols for peripheral devices 208-1 , 208-2 without having to utilize a physical switch on a printed circuit board (PCB) of the computing device, which may be accessible when a cover or portion of an enclosure is removed from the computing device to reveal the PCB. In addition, the circuit does not tie inputs or outputs together, which can lead to failures.

[0025] Figure 3 illustrates an example of a circuit diagram 300 for port circuits, in accordance with the present disclosure. In some examples, the circuit diagram 300 can include the same or similar elements as the circuit diagram 200 as referenced in Figure 2, and/or the circuit diagram 100 as referenced in Figure 1. For example, the circuit diagram 300 can include a tristate buffer 302 that can utilize a first gate 312-1 with a corresponding first enable input 313-1 and a second gate 312-2 with a corresponding enable input 313-2. In some examples, the circuit diagram 300 can illustrate a circuit that can be coupled to a port that can receive a connection from a peripheral device (e.g., a first peripheral device 308-1, a second peripheral device 308-2, etc.). In these examples, the port can be altered from a first communication protocol to a second communication protocol utilizing a firmware interface 322.

[0026] As described herein, a firmware interface 322 can be a user interface that can be displayed to allow selections to be made that can alter the input/output functions of the firmware 306. In some examples, the firmware interface 322 can include a selectable interface that includes a plurality of different communication protocols for a number of ports associated with the computing device that includes the circuit illustrated by the circuit diagram 300. In some examples, the different communication protocols can utilize different hardware in order to convert the communication protocol to a different communication protocol. For example, a first peripheral device 308-1 can utilize a first communication protocol (e.g., RS-232, etc.) that can utilize a transceiver 304 to convert the first communication protocol to a second communication protocol (e.g., TTL, etc.). In this example, a second peripheral device 308-2 can utilize a second communication protocol that may not need a transceiver 304 or other device to convert the second communication protocol to a different communication protocol. Thus, the first peripheral device 308-1 and/or pin of the first peripheral device 308-1 can be coupled to an input of a transceiver 304 and the output of the transceiver 304 can be coupled to pin 2 of the tristate buffer 302. In addition, the second peripheral device 308- 2 and/or a pin of the second peripheral device 308-2 can be coupled directly to pin 5 of the tristate buffer 302.

[0027] As described herein, the circuit can include an I/O mechanism 310 that can be coupled to pin 6 of the tristate buffer 302 and/or pin 3 of the tristate buffer 302 in order to receive either input data from pin 2 when the enable input 313-1 is activated or receive input data from pin 5 when the enable input 313-2 is activated. In this way, a selection from the firmware interface 322 can translate in the firmware 306 providing a first signal or voltage to pin 1 and a second signal or voltage to pin 7 to activate one of the enable inputs 313-1, 313-2 and deactivate on of the enable inputs 313-1, 313-2. [0028] In some examples, the circuit diagram 300 can include a field effect transistor 334 (FET). As used herein, a FET 334 can include a transistor where a voltage on one terminal (e.g., terminals 336-1 , 336-2, etc.) creates a field that allows or disallows conduction between the other terminals. In some examples, the firmware 306 or a mechanism of the firmware 306 (e.g., firmware mechanism, electrical connection coupled to the firmware 306, etc.) can be coupled to a first terminal 336-1 of the FET 334. In some examples, the first terminal 336-1 can be coupled to the firmware 306 and coupled to pin 1. In this way, the firmware 306 can apply a first voltage to the first terminal 336-1 and/or pin 1. In some examples, the FET 334 can be utilized to apply inverse signals or inverse voltages to pin 1 and pin 7. For example, the firmware 306 can provide a relatively high voltage to the first terminal 336-1 and pin 1 to activate the enable input 313-1. In this example, the FET 334 can utilize the second terminal 336-2 to provide a relatively low voltage to pin 7 in response to the relatively high voltage applied to the first terminal 336-1 to deactivate the enable input 313-2.

[0029] In some examples, the firmware 306 can provide a first signal to the first terminal 336-1 of the FET 334, which can result in the first signal being provided to pin 1 of the tristate buffer 302 when pin 1 is coupled to the first terminal 336-1 of the FET 334. In some examples, the FET 334 can be utilized to control a signal provided through the second terminal 336-2 based on the first signal provided to the first terminal 336-1. For example, the first signal can be a first voltage that is greater than a threshold voltage, which can activate the enable input 313-1. In this example, the FET 334 can be utilized to control a voltage at the second terminal 336-2 to remain below the threshold voltage, which an deactivate the enable input 313-2. In this way, the FET 334 can be utilized to ensure that one of the enable inputs 313-1, 313-2 is activated and one of the enable inputs 313-1, 313-2 is deactivated.

[0030] As described herein, the circuit diagram 300 can illustrate a circuit that can be utilized to switch between communication protocols for peripheral devices 308-1 , 308-2 without having to utilize a physical switch on a printed circuit board (PCB) of the computing device, which may be accessible when a cover or portion of an enclosure is removed from the computing device to reveal the PCB. In addition, the circuit does not tie inputs or outputs together, which can lead to failures.

[0031] Figure 4 illustrates an example of a circuit diagram 400 for port circuits, in accordance with the present disclosure. In some examples, the circuit diagram 400 can include the same or similar elements as the circuit diagram 300 as referenced in Figure 3, the circuit diagram 200 as referenced in Figure 2, and/or the circuit diagram 100 as referenced in Figure 1. For example, the circuit diagram 400 can include a tristate buffer 402 that can utilize a first gate with a corresponding first enable input and a second gate with a corresponding enable input. In some examples, the circuit diagram 400 can illustrate a circuit that can be coupled to a port that can receive a connection from a peripheral device (e.g., a first peripheral device 408-1 , a second peripheral device 408- 2, etc.). In these examples, the port can be altered from a first communication protocol to a second communication protocol utilizing a firmware interface.

[0032] In some examples, the circuit diagram 400 can include a tristate buffer 402. The tristate buffer 402 can be coupled to a power source 446 at pin 8 and a ground source 444 at pin 4. In some examples, the power source 446 can provide electrical energy to be utilized by the tristate buffer 402. In some examples, the ground source 444 can be an electrical ground for the tristate buffer 402. In some examples, pin 5 can be coupled to a transceiver 404 that is coupled to a first peripheral device 408-1 and pin 2 can be coupled to a second peripheral device 408-2. In some examples, pin 6 can be coupled to a connection 442. In some examples, pin 3 can be coupled to the connection 442 and/or connected to an I/O mechanism 410.

[0033] In some examples, the circuit diagram 400 can include a field effect transistor (FET) 434. As described herein, the FET 434 includes a first terminal 436-1 and a second terminal 436-2. In some examples, the first terminal 436-1 can be coupled to pin 1 of the tristate buffer 402 and/or coupled to a firmware mechanism 433. In some examples, the firmware mechanism 433 can be a device coupled to the firmware (e.g., BIOS, UEFI, etc.) of a computing device that can generate a particular signal or voltage. In some examples, the firmware mechanism 433 can generate a first signal or voltage that can be received by the first terminal 436-1 and/or pin 1 of the tristate buffer 402. [0034] As described herein, pin 1 can be coupled to an enable input and when a particular signal or voltage is applied can be activated to activate or open a corresponding gate. As described herein, the FET 434 can alter a voltage at the second terminal 436-2 to a second signal or voltage. In some examples, the second terminal 436-2 can be coupled to pin 7 and pin 7 can be coupled to an enable input that can be coupled to a corresponding gate. In some examples, the second terminal 436-2 can provide the second signal or voltage to pin 7 to activate or deactivate the enable input coupled to pin 7 based on the voltage applied to the first terminal 436-1.

[0035] As described herein, the circuit diagram 400 can include a first peripheral device 408-1 that can utilize a transceiver 404 to alter a communication protocol of the first peripheral device 408-1 from a first communication protocol to a second communication protocol. In some examples, communication packets from the first peripheral device 408-1 can be transmitted to the transceiver 404 and the transceiver can transfer the converted communication protocol to pin 5 of the tristate buffer 402. In some examples, the voltage applied at the second terminal 436-2 can be utilized to activate or deactivate a gate positioned between pin 5 and pin 3. In this way, communication packets from the transceiver 404 can be restricted or allowed to pass through the tristate buffer 402 based on the signal or voltage at the second terminal 436-2.

[0036] In some examples, the circuit diagram 400 can include a second peripheral device 408-2 that may not utilize additional hardware, such as a transceiver 404, to convert the communication protocol of the second peripheral device 408-2. For example, the second peripheral device 408-2 can be coupled to pin 2 or directly coupled to pin 2. In some examples, the second peripheral device 408-2 can transmit communication packets directly to pin 2 of the tristate buffer 402. In some examples, the signal or voltage applied by the firmware mechanism 433 can be received at pin 1 of the tristate buffer 402 and either activate or deactivate an enable input coupled to pin 1 and/or gate coupled to pin 2. In some examples, the voltage applied at the first terminal 436-1 can be utilized to activate or deactivate a gate positioned between pin 2 and pin 6. In this way, communication packets from the second peripheral device 408-2 can be restricted or allowed to pass through the tristate buffer 402 based on the signal or voltage at the first terminal 436-1.

[0037] As described herein, the circuit diagram 400 can illustrate a circuit that can be utilized to switch between communication protocols for peripheral devices 408-1 , 408-2 without having to utilize a physical switch on a printed circuit board (PCB) of the computing device, which may be accessible when a cover or portion of an enclosure is removed from the computing device to reveal the PCB. In addition, the circuit does not tie inputs or outputs together, which can lead to failures.

[0038] The figures herein follow a numbering convention in which the first digit corresponds to the drawing figure number and the remaining digits identify an element or component in the drawing. Elements shown in the various figures herein can be added, exchanged, and/or eliminated so as to provide a number of additional examples of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the examples of the present disclosure, and should not be taken in a limiting sense. As used herein, the designator “N”, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with examples of the present disclosure. The designators can represent the same or different numbers of the particular features. Further, as used herein, "a number of an element and/or feature can refer to one or more of such elements and/or features.

[0039] In the foregoing detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure, and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

Claims

What is claimed:

1. A circuit, comprising: a tristate buffer that includes: a first data input coupled to a transceiver; a second data input coupled to an output of a connector; a first data output to transfer data from the first data input to an input/output mechanism when activated by a first signal; and a second data output to transfer data from the second data input to the input/output mechanism when activated by a second signal.

2. The circuit of claim 1 , comprising a firmware mechanism to provide the first signal and the second signal by providing a voltage on a side of a field effect transistor (FET).

3. The circuit of claim 2, wherein the voltage is altered between a first voltage to activate the first data output and a second voltage to activate the second data output.

4. The circuit of claim 2, wherein the voltage is altered based on a selection from a firmware interface.

5. The circuit of claim 1 , comprising a first enable input coupled to the first data input to enable the first data input when the first enable input receives the first signal.

6. The circuit of claim 5, comprising a second enable input coupled to the second data input to enable the second data input when the second enable input receives the second signal.

7. The circuit of claim 6, wherein the first signal enables the first enable input and disables the second enable input and the second signal enables the second enable input and disables the first enable input.

8. A computing device, comprising: a firmware interface to select a communication type for a port; and a tristate buffer, including: a first data input to receive a first communication type; a first enable input to activate or deactivate the first data input based on a first signal from the firmware interface; a second data input to receive a second communication type; and a second enable input to activate or deactivate the second data input based on a second signal from the firmware interface.

9. The computing device of claim 8, wherein the first enable input is to deactivate the first data input when the second enable input is to activate the second data input.

10. The computing device of claim 9, wherein the second enable input is to deactivate the second data input when the first enable input is to activate the first data input.

11. The computing device of claim 8, wherein the first enable input is coupled to a first side of a field effect transistor (FET) and the second enable input is coupled to a second side of the FET.

12. The computing device of claim 11 , comprising a firmware mechanism to apply a first voltage to the first side of the FET to generate the first signal; and apply a second voltage to the first side of the FET to generate the second signal.

13. A system, comprising: a firmware mechanism communicatively coupled to a firmware interface, wherein a selection from the firmware interface generates a corresponding signal by the firmware mechanism; a tristate buffer, including: a first data input coupled to an output of a serial transceiver; a first enable input to activate the first data input when the firmware mechanism provides a first signal; a second data input to couple to an output of a communication pin coupled to a peripheral device; and a second enable input to activate the second data input when the firmware mechanism provides a second signal; and a field effect transistor (FET) coupled to: the firmware mechanism to receive the corresponding signal on a first end of the FET; the first enable input on the first end of the FET; and the second enable input on a second end of the FET.

14. The system of claim 13, wherein the first signal creates a first voltage on the first end of the FET and a second voltage on the second end of the FET and the second signal creates the second voltage on the first end of the FET and the first voltage on the second end of the FET.

15. The system of claim 14, wherein: the first enable input is activated in response to the first voltage and the second enable input is deactivated in response to the second voltage; and the second enable input is activated in response to the first voltage and the first enable input is deactivated in response to the second voltage.