WO2021100116A1 - Power conversion device - Google Patents

Power conversion device Download PDF

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Publication number
WO2021100116A1
WO2021100116A1 PCT/JP2019/045247 JP2019045247W WO2021100116A1 WO 2021100116 A1 WO2021100116 A1 WO 2021100116A1 JP 2019045247 W JP2019045247 W JP 2019045247W WO 2021100116 A1 WO2021100116 A1 WO 2021100116A1
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WO
WIPO (PCT)
Prior art keywords
output
comparison
inverter
phase inverters
phase
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PCT/JP2019/045247
Other languages
French (fr)
Japanese (ja)
Inventor
章太 渡辺
友一 坂下
聡士 小鹿
研吾 内山
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2019/045247 priority Critical patent/WO2021100116A1/en
Priority to JP2021558073A priority patent/JP7146115B2/en
Publication of WO2021100116A1 publication Critical patent/WO2021100116A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483Converters with outputs that each can have more than two voltages levels
    • H02M7/49Combination of the output voltage waveforms of a plurality of converters

Definitions

  • This application relates to a power conversion device.
  • a power conversion device capable of obtaining a desired output waveform by gradation control by combining a plurality of inverters has been put into practical use.
  • a control method has been proposed in which the voltage of the capacitor of each inverter is controlled to be constant by adjusting the charge / discharge current of each inverter at the same time as obtaining an arbitrary output voltage (for example, Patent Document 1).
  • the present application discloses a technique for solving the above-mentioned problems, and power conversion capable of keeping the capacitor voltage constant and outputting an arbitrary voltage even if the number of inverters constituting the power conversion device increases.
  • the purpose is to provide the device.
  • the power conversion device disclosed in the present application is one or more single-phase inverters selected from a plurality of single-phase inverters by connecting a plurality of AC sides of a single-phase inverter that converts DC power of a DC power source into AC power in series.
  • each of the plurality of single-phase inverters includes a power storage element that generates a DC power supply voltage, and at least one of the plurality of single-phase inverters.
  • a comparison unit that calculates a comparison standard value by dividing by the ratio of the DC power supply voltage of multiple single-phase inverters to the target value of each DC power supply voltage, and compares the calculated multiple comparison standard values, and the comparison unit.
  • the comparison unit includes an output pattern determination unit that determines an output pattern that is a combination of one or more single-phase inverters that should output a voltage among a plurality of single-phase inverters based on the result and predetermined selection conditions.
  • An average value comparison unit that compares at least some of the average values of multiple comparison standard values with each comparison standard value as a comparison process, and a standard that compares each comparison standard value with another comparison standard value as a comparison process. It includes at least one of the value comparison units.
  • the capacitor voltage can be kept constant and an arbitrary voltage can be output.
  • FIG. 1 It is a block diagram of the main circuit part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. It is a block diagram of the control part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. It is a block diagram of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. It is a block diagram of the modification part of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. It is a block diagram of an example of the main circuit part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. It is a block diagram of one example of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. 5 is an explanatory diagram of an example of the relationship between the number of gradations and the output pattern according to the power conversion device according to the first embodiment. It is a block diagram of the modification of the main circuit part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. It is a block diagram of another example of the main circuit part which concerns on the power conversion apparatus by Embodiment 1.
  • FIG. It is a block diagram of the control part which concerns on the power conversion apparatus by Embodiment 2.
  • It is a block diagram of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 2.
  • FIG. 3 It is a block diagram of the control part which concerns on the power conversion apparatus by Embodiment 3.
  • FIG. It is a block diagram of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 3.
  • FIG. It is a block diagram of the modification part of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 3.
  • FIG. It is a block diagram of one example of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 3.
  • the plurality of single-phase inverters are composed of a main inverter group composed of one or a plurality of single-phase inverters to which DC power is supplied from the outside, and a sub-inverter group composed of a plurality of other single-phase inverters.
  • the voltage ratio of each DC power supply of the main and sub-inverter groups is substantially constant, and the total DC power supply voltage of the main inverter group is set to be larger than the total DC power supply voltage of the sub-inverter group by a predetermined ratio, and the voltage is detected.
  • a comparison unit that calculates a comparison standard value by dividing by the ratio of the DC power supply voltage of a plurality of single-phase inverters detected by the means and the target value of each DC power supply voltage, and performs comparison processing of the calculated multiple comparison standard values.
  • the comparison unit includes an average value comparison unit that compares at least a part of the average values of a plurality of comparison standard values with each comparison standard value.
  • the output pattern determination unit selects the output combination of each single-phase inverter so that each DC voltage of the sub-inverter group becomes substantially constant by charging / discharging via each single-phase inverter using the output result of the comparison unit. It relates to a power converter.
  • FIG. 1 which is a configuration diagram of a main circuit unit of the power conversion device
  • FIG. 2 which is a configuration diagram of a control unit
  • a configuration diagram of a comparison unit of the control unit
  • FIG. 3 which is a configuration diagram of a modified example of the comparison unit of the control unit
  • FIG. 5 which is a configuration diagram of an example of the main circuit unit
  • FIG. 6 which is a configuration diagram of an example of the comparison unit of the control unit.
  • FIG. 7 which is an explanatory diagram of an example of the relationship between the number of gradations and an output pattern
  • FIG. 8 which is a configuration diagram of a modified example of the main circuit unit
  • FIG. 9 which is a configuration diagram of another example of the main circuit unit. Will be explained.
  • the power conversion device includes the main circuit unit 1 of FIG. 1 and the control unit 20 of FIG.
  • the main circuit unit 1 includes a sub-inverter group 2 which is a second inverter group, a main inverter group 3 which is a first inverter group, a changeover switch 4, a charging resistor 5, an output filter 6, an inverter voltage detection circuit 7D, and an inverter voltage detection circuit 7D.
  • the output voltage detection circuit 8 is provided.
  • a load 11 is connected to the output of the main circuit unit 1.
  • the entire sub-inverter group 2 and main inverter group 3 are referred to as an inverter unit.
  • the sub-inverter group 2 is composed of single-phase inverters 2I1, 2I2, ..., 2Im (m is an integer of 2 or more). When the single-phase inverter of the sub-inverter group 2 is described as a representative, it is described as the single-phase inverter 2I. Further, the main inverter group 3 is composed of single-phase inverters 3Im + 1, ..., 3Im + n (n is an integer of 1 or more). When the single-phase inverter of the main inverter group 3 is described as a representative, it is described as the single-phase inverter 3I.
  • inverter voltage detection circuits 7D1, 7D2, ..., 7Dm, 7Dm + 1, which are voltage detecting means for detecting the output voltage of each single-phase inverter 2I and 3I
  • the inverter voltage detection is performed. Described as circuit 7D.
  • Each single-phase inverter 2I, 3I is a self-extinguishing semiconductor switching element (g11, g12, g21, g22) such as a plurality of IGBTs (Insulated Gate Bipolar transformers) in which a plurality of diodes are connected in antiparallel and a power storage element. It consists of a full bridge circuit with a capacitor. In FIG. 1, the reference numerals of the diode and the capacitor are omitted for simplification.
  • the capacitors of the single-phase inverters 2I and 3I are DC power supplies of the single-phase inverters 2I and 3I.
  • the voltage ratio (V1: V2: ...: Vm + n) is controlled to be substantially constant for the voltages Vm + 1 to Vm + n.
  • the voltage of the capacitor which is the DC power supply of the single-phase inverters 3Im + 1 to 3Im + n of the main inverter group 3 only the voltage of the capacitor of the single-phase inverter 3Im + 1 is detected.
  • the voltage of the capacitor which is a DC power supply will be appropriately referred to as a DC power supply voltage or a capacitor voltage.
  • the total DC power supply voltage of the main inverter group 3 (Vm + 1 + Vm + 2 + ... + Vm + n) is controlled to be larger than the total DC power supply voltage of the sub-inverter group 2 (V1 + V2 + ... + Vm) at a predetermined ratio.
  • V1: V2: ...: Vm + n is controlled to 1: 2: ...: 2 ⁇ (m + n-1). The details of the control will be described later.
  • the single-phase inverters 3Im + 1 ..., 3Im + n of the main inverter group 3 are supplied with electric power by the external power supplies 10S1, ..., 10Sn. When it is not necessary to distinguish each external power supply 10S1, ..., 10Sn, it is described as an external power supply 10S.
  • Each single-phase inverter 2I, 3I can generate positive and negative and zero voltages as outputs.
  • the semiconductor switching elements g11 and g22 when the output is positive, the semiconductor switching elements g11 and g22 are turned on, and when the output is negative, the semiconductor switching elements g12 and g21 are turned on.
  • the semiconductor switching elements g11 and g21 When the output is 0, the semiconductor switching elements g11 and g21 (or g12 and g22) are turned on.
  • the inverter unit includes a sub-inverter group 2 and a main inverter group 3, and the AC side of each single-phase inverter 2I1 to 2Im, 3Im + 1 to 3Im + n is connected in series.
  • a predetermined voltage is output as the total by gradation control.
  • the inverter unit supplies power to the load 11 via the output filter 6 with a predetermined voltage whose gradation is controlled.
  • V1 grade number 1
  • V2 grade number 0
  • a charging resistor 5 and a changeover switch 4 are installed at the output end of the inverter unit.
  • the changeover switch 4 connects the AC output end of the sub-inverter group 2 to the charging resistor 5 when the power conversion device is started to initially charge each DC power source of the sub-inverter group 2.
  • the changeover switch 4 is connected to the output filter 5 side at the time of normal output. This initial charge is performed by the control described later.
  • the changeover switch 4 is connected to the AC output of the sub-inverter group 2, but may be connected to the output side of the main inverter group 3. Further, the changeover switch 4 and the charging resistor 5 may be installed on the output side of the output filter 6.
  • each DC power source of the sub-inverter group 2 may be performed by passing a charging current through the load 11. In this case, since the charging current is passed through the load 11, the charging resistor 5 and the changeover switch 4 are unnecessary. Further, the initial charge of each DC power source of the sub-inverter group 2 may be performed by connecting an external power source to the sub-inverter group 2 only at the time of the initial charge. In this case, since the DC power supply of each single-phase inverter 2I1 of the sub-inverter group 2 is directly charged, the charging resistor 5 and the changeover switch 4 are unnecessary.
  • FIG. 1 shows an example of detecting only the capacitor voltage, which is the DC power supply voltage of the single-phase inverter 3Im + 1, which has the smallest voltage in the main inverter group 3.
  • a case where only the capacitor voltage, which is the DC power supply voltage of the single-phase inverter 3Im + 1, which has the smallest voltage in the main inverter group 3, is detected will be described.
  • the same method can be applied even if a capacitor voltage, which is a DC power supply voltage other than the single-phase inverter having the smallest voltage in the main inverter group 3, is detected.
  • the voltage output to the load 11 is detected by the output voltage detection circuit 8.
  • the installation position of the output voltage detection circuit 8 may be any position as long as it can detect the output voltage of the inverter unit, and may be, for example, the front stage of the output filter 6 or the front stage of the changeover switch 4.
  • the control unit 20 includes a gradation number determination unit 21, a comparison unit 22, an output pattern determination unit 23, and a gate signal generation unit 24.
  • the gradation number determination unit 21 determines the gradation number in order to control the output voltage Vo to the output voltage command value based on the output voltage Vo detected by the output voltage detection circuit 8 and the output voltage command value. Specifically, the difference between the output voltage detection value Vo and the output voltage command value is input to the PI (Proportional-Integral) controller, and the output result of the PI controller is used as the number of gradations.
  • the PI control may be any control such as P (Proportional) control and PID (Proportional-Integral-Differential) control that operates so as to bring the output voltage detection value Vo closer to the output voltage command value. Further, a rounding process or a limiter process for a value smaller than the number adopted for the number of gradations of the PI calculation result (the portion after the decimal point) may be added.
  • the comparison unit 22 includes a divider 22D, an average calculator 22H, and an average value comparator 22AC which is an average value comparison unit.
  • the OPD is an output pattern determination unit.
  • the dividers have different inputs and outputs, but have the same functions, so the divider 22D is used.
  • the functions are the same, so the average value comparator 22AC is used.
  • the code numbers of each arithmetic unit are not distinguished.
  • the capacitor voltages V1 to Vm + 1 of the single-phase inverters 2I and 3I detected by the inverter voltage detection circuit 7D are input to the comparison unit 22.
  • the input capacitor voltages V1 to Vm + 1 are converted, that is, standardized, into signals V1 * to Vm + 1 * having uniform voltage levels by the divider 22D.
  • This standardized signal is referred to as a comparative standard value. That is, the comparative standard value is calculated by dividing by the ratio of the DC power supply voltage of the plurality of single-phase inverters detected by the voltage detecting means and the target value of each DC power supply voltage.
  • the capacitor voltage Vm of the single-phase inverter 2Im detected by the inverter voltage detection circuit 7Dm is divided by Km, which is the ratio of the target value of the capacitor voltage in the divider 22D.
  • the average value Wave is calculated by the average calculator 22H from the standardized signal, that is, the comparative standard values V1 * to Vm + 1 *.
  • the average value Wave is compared with the comparison standard value (V2 * to Vm + 1 *) by the average value comparator 22AC, and m average value comparison signals are output.
  • the comparison unit 22 in the first embodiment may output the comparison result using the calculated average value, and may change the calculation method of the average value as shown in FIG. 4, for example.
  • FIG. 4 is a configuration diagram of a modified example of the comparison unit, and is referred to as the comparison unit 22A in order to distinguish it from the comparison unit 22 of FIG.
  • the comparison unit 22A includes a divider 22AD, an average calculator 22AH, and an average value comparator 22AAC.
  • the OPD is an output pattern determination unit.
  • the average value Vave-1 is calculated from the comparative standard values V1 * to Vm + 1 * by the average calculator 22AH
  • the average value Vave-2 is calculated from the comparative standard values V1 * to Vm * by the average calculator 22AH.
  • the average value Wave-m is calculated from the comparative standard values V1 * and V2 * by the average calculator 22AH.
  • the average value Vave-1 is compared with the comparison standard value Vm + 1 * and the average value comparator 22AAC
  • the average value Vave-2 is compared with the comparison standard value Vm * and the average value comparator 22AAC
  • the average value Vave-m is the comparison standard.
  • the value V2 * is compared with the average value comparator 22AAC, and each average value comparison signal is output. That is, assuming that L is an integer in the range of (1 ⁇ L ⁇ m + 1), the comparison standard value from 1 to VL is used for the calculation of the average value to be compared with the comparison standard value VL *.
  • the comparison unit when the sub-inverter group is composed of Y single-phase inverters, the comparison unit includes Y or more average value comparison units.
  • the output pattern determination unit 23 determines the combination (output pattern) of the outputs of each single-phase inverter by the operation described later based on the gradation number determined by the gradation number determination unit 21 and the comparison result output from the comparison unit 22. ..
  • the control unit 20 controls the capacitor voltages of the single-phase inverters 2I and 3I to be substantially constant based on the output pattern and the number of gradations determined by the output pattern determination unit 23.
  • the gate signal generation unit 24 generates a gate signal for operating the single-phase inverters 2I and 3I based on the output result of the output pattern determination unit 23. Specifically, a gate drive signal for driving the semiconductor switching elements g11 to g22 of each single-phase inverter 2I and 3I is generated from the output pattern.
  • the output pattern determination unit 23 determines an output pattern from a plurality of output patterns that realize the number of gradations obtained from the gradation number determination unit 21 by using the output result of the comparison unit 22. At that time, the output pattern is determined according to the following rules. Determine the output pattern. (A) Determine the output from a single-phase inverter with a large capacitor voltage. (B) In a certain single-phase inverter, when the capacitor voltage is larger than the average value, the output is selected in the order of +, 0,-. If the capacitor voltage is smaller than the average value, the output is selected in the order of-, 0, +.
  • FIG. 5 is a configuration diagram of an example of the main circuit unit 1.
  • FIG. 5 shows an example in which the sub-inverter group 2 is composed of three single-phase inverters 2I1, 2I2, 2I3, and the main inverter group 3 is composed of one single-phase inverter 3I4.
  • the main circuit unit 1A is used.
  • the sub-inverter group 2A and the main inverter group 3A are used.
  • the output voltage of the single-phase inverter 2I1 is detected by the inverter voltage detection circuit 7D1
  • the output voltage of the single-phase inverter 2I2 is detected by the inverter voltage detection circuit 7D2
  • the output voltage of the single-phase inverter 2I3 is detected by the inverter voltage detection circuit 7D3.
  • the output voltage of the single-phase inverter 3I4 is detected by the inverter voltage detection circuit 7D4.
  • the changeover switch 4 and the charging resistor 5 are omitted.
  • the capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 2I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8. Further, the first single-phase inverter, the second single-phase inverter, the third single-phase inverter, and the fourth single-phase inverter will be described in order from the single-phase inverter having the smallest capacitor voltage.
  • the single-phase inverter 2I1 corresponds to the first single-phase inverter
  • the single-phase inverter 2I2 corresponds to the second single-phase inverter
  • the single-phase inverter 2I3 corresponds to the third single-phase inverter
  • FIG. 6 shows an example of a comparison unit corresponding to the main circuit unit 1A of FIG.
  • the comparison unit 22B is used to distinguish it from the comparison unit 22 in FIG. 3 and the comparison unit 22A in FIG.
  • the comparison unit 22B includes a divider 22BD, an average calculator 22BH, and an average value comparator 22BAC.
  • the OPD is an output pattern determination unit.
  • the average value Wave ⁇ 0.972 is calculated by the average calculator 22BH.
  • the comparison results V4 *> Vave, V3 *> Vave, and V2 * ⁇ Vave are output from the average value comparator 22BAC.
  • the output pattern is determined according to the following rules.
  • the output of the fourth single-phase inverter having the largest capacitor voltage is determined in order. Since the comparative standard value of the fourth single-phase inverter is larger than the average value (V4 *> Wave), the output of the fourth single-phase inverter is selected in the order of +, 0,-. Of the five patterns with the number of gradations 3, patterns D and E in which the fourth single-phase inverter has a + output are selected.
  • a third single-phase inverter with a large capacitor voltage Since the comparative standard value of the third single-phase inverter is larger than the average value (V3 *> Wave), the output of the third single-phase inverter is selected in the order of +, 0,-.
  • the method of determining the output from the single-phase inverter having a large capacitor voltage is shown by the output pattern determination unit 23, but the order of the single-phase inverters that determine the output can be freely changed. There is no problem.
  • the output may be determined from a single-phase inverter having a small capacitor voltage.
  • fluctuations in the capacitor voltage of a single-phase inverter with a large capacitor voltage appear more as fluctuations in the output voltage, so it is desirable to determine from the output of a single-phase inverter with a large capacitor voltage.
  • FIG. 8 shows a configuration diagram of a main circuit unit when the output current Io is controlled so as to approach the current command value.
  • the main circuit unit 1B is used to distinguish it from the main circuit unit 1 of FIG.
  • the output voltage detection circuit 8 of FIG. 1 may be changed to the output current detection circuit 12, and the control unit 20 may change the signal input to the gradation number determination unit 21 to the output current detection value and the output current command value.
  • FIG. 9 shows an example in which the sub-inverter group 2 is composed of two single-phase inverters 2I1 and 2I2, and the main inverter group 3 is composed of two single-phase inverters 3I3 and 3I4.
  • the external power supply 10S1 is connected to the single-phase inverter 3I3, and the external power supply 10S2 is connected to the single-phase inverter 3I4.
  • the changeover switch 4 and the charging resistor 5 are omitted.
  • the capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 3I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8. Further, the first single-phase inverter, the second single-phase inverter, the third single-phase inverter, and the fourth single-phase inverter will be described in order from the single-phase inverter having the smallest capacitor voltage.
  • the single-phase inverter 2I1 corresponds to the first single-phase inverter
  • the single-phase inverter 2I2 corresponds to the second single-phase inverter
  • the single-phase inverter 3I3 corresponds to the third single-phase inverter
  • the control method (selection procedure) described above with reference to FIGS. 5 to 7 can be applied to the main circuit unit 1C having the configuration shown in FIG. Specifically, as in the case where the sub-inverter group 2 has three single-phase inverters and the main inverter group 3 has one single-phase inverter, the third single-phase inverter is regarded as not connected to an external power source. Each single-phase inverter 2I1, 2I2, 3I3, 3I4 can be controlled by using the output pattern selection procedure. In this case, the power capacity of the external power supply 10S can be reduced.
  • the 4th single-phase inverter 3I4 is not used for constant capacitor voltage control, and is operated as + output when the number of gradations is 8 or more and 0 output when the number of gradations is 7 or less, and the total of the first to third single-phase inverters.
  • the three units may perform constant capacitor voltage control by the control method (selection procedure) described above.
  • the inverter voltage detection circuit 7D4 of the fourth single-phase inverter 3I4 and one stage of the single-phase inverter of the control unit 20 can be omitted.
  • the external power supply 10S may also be connected to the sub-inverter group 2. Even in this case, by applying the present embodiment, the power supply capacity required for the external power supply 10S is reduced as compared with the conventional power conversion device to which the gradation control is applied, and the device is compact and inexpensive. be able to.
  • the ratio (comparative standard value) between the capacitor voltage of each single-phase inverter and the target value of the capacitor voltage of each single-phase inverter is calculated and compared with the average value of the calculated comparative standard values.
  • the output pattern is selected using the comparison result with the standard value.
  • the charge / discharge current of each single-phase inverter of the sub-inverter group 2 is adjusted, and a desired output voltage is output while keeping the voltage ratio of each single-phase inverter (2I1 to 2Im, 3Im + 1 to 3Im + n) substantially constant. It becomes possible. Therefore, it is possible to eliminate the need for a power source for supplying electric power to the sub-inverter group 2, so that the device is small and inexpensive.
  • the output pattern determination unit of the first embodiment by selecting the output code in order from the inverter having the largest capacitor voltage, the capacitor voltage fluctuation of the single-phase inverter having the largest capacitor voltage is suppressed, and the output voltage fluctuates greatly. Can be suppressed.
  • the output pattern determination unit 23 (A) the output is determined from the single-phase inverter having a large capacitor voltage, and (B) in a certain single-phase inverter, when the comparison standard value is larger than the average value, +, 0,-.
  • the output pattern can be determined by a simple rule that the output is selected in the order of priority, and if the comparison standard value is smaller than the average value, the output is selected in the order of priority of-, 0, +. Since this rule can be applied even when the number of single-phase inverters increases, it is possible to control each capacitor voltage substantially constantly while outputting an arbitrary output voltage even when the number of single-phase inverters increases.
  • the sub-inverter group 2 and the main inverter group 3 have been described separately.
  • the whole may be treated as one single-phase inverter group, at least one of the single-phase inverters may be connected to an external power supply, and the voltage ratio of the DC power supply voltage of each single-phase inverter may be controlled to be constant.
  • the plurality of single-phase inverters are a main inverter group composed of one or a plurality of single-phase inverters to which DC power is supplied from the outside, and a plurality of other single-phase inverters. It is composed of a sub-inverter group consisting of inverters, and the voltage ratio of each DC power supply of the main and sub-inverter groups is almost constant. A plurality of comparisons calculated by dividing by the ratio of the DC power supply voltage of a plurality of single-phase inverters detected by the voltage detecting means and the target value of each DC power supply voltage to calculate a comparison standard value, which is largely set by a predetermined ratio.
  • a comparison unit that performs standard value comparison processing and an output pattern determination unit that determines the combination of outputs of each single-phase inverter are provided, and the comparison unit includes an average value of at least a part of a plurality of comparison standard values and each comparison standard value.
  • the output pattern determination unit uses the output result of the comparison unit to make each DC voltage of the sub-inverter group substantially constant by charging / discharging via each single-phase inverter. The combination of outputs of the single-phase inverter is selected. Therefore, the power conversion device of the first embodiment can keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.
  • the power conversion device of the second embodiment includes a standard value comparison unit that compares a comparison standard value with another comparison standard value as a comparison unit.
  • FIG. 10 is a configuration diagram of a control unit
  • FIG. 11 is a configuration diagram of a comparison unit of the control unit
  • FIG. 12 is a configuration diagram of an example of the comparison unit of the control unit.
  • the difference from the first embodiment will be mainly described.
  • the drawings of the first embodiment will be referred to as appropriate.
  • the same or corresponding parts as those of the first embodiment are designated by the same reference numerals.
  • the configuration of the control unit 30 will be described with reference to FIG.
  • the control unit 30 includes a gradation number determination unit 21, a comparison unit 32, an output pattern determination unit 33, and a gate signal generation unit 24.
  • the difference from the control unit 20 of the first embodiment is the comparison unit 32 and the output pattern determination unit 33.
  • the comparison unit 32 includes a divider 32D and a standard value comparator 32SC which is a standard value comparison unit.
  • the OPD is an output pattern determination unit.
  • the capacitor voltages V1 to Vm + 1 of each single-phase inverter 2I and 3I detected by the inverter voltage detection circuit 7D are input.
  • the input capacitor voltages V1 to Vm + 1 are standardized by the divider 32D to the comparative standard values V1 * to Vm + 1 * whose voltage levels are aligned.
  • the comparison unit 32 compares the standardized comparison standard values V1 * to Vm + 1 * with the standard value comparator 32SC to clarify the magnitude relationship of the comparison standard values V1 * to Vm + 1 *, and determines the output pattern as a result. Output to unit 33.
  • the comparison unit 32 in the second embodiment is different from the first embodiment in that the sum calculation is not performed, that is, the averaging calculation is not performed.
  • m + 1 voltage is detected by the inverter voltage detection circuit 7D, the magnitude relationship of all comparison standard values can be calculated if there are (m + 1) ⁇ m / 2 or more standard value comparators.
  • the comparison unit when the sub-inverter group is composed of Y single-phase inverters, the comparison unit is composed of (Y + 1) ⁇ Y / 2 or more standard value comparison units. Will be done.
  • the output pattern determination unit 33 determines the combination of outputs (output pattern) of each single-phase inverter based on the number of gradations determined by the gradation number determination unit 21 and the comparison result output from the comparison unit 32.
  • the control unit 30 controls the capacitor voltages of the single-phase inverters 2I and 3I to be substantially constant based on the output pattern and the number of gradations determined by the output pattern determination unit 33.
  • the gate signal generation unit 24 generates a gate signal for operating each single-phase inverter 2I and 3I based on the output result of the output pattern determination unit 33.
  • the output pattern determination unit 33 determines an output pattern from a plurality of output patterns that realize the number of gradations obtained from the gradation number determination unit 21 by using the output result of the comparison unit 32. At that time, the output pattern is determined according to the following rules. Determine the output pattern.
  • the output is determined from a single-phase inverter having a large comparison standard value V1 * to Vm + 1 *.
  • the output of each single-phase inverter is selected in the order of +, 0,-.
  • FIG. 5 shows an example in which the sub-inverter group 2 is composed of three single-phase inverters 2I1, 2I2, 2I3, and the main inverter group 3 is composed of one single-phase inverter 3I4.
  • the capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 2I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8.
  • FIG. 12 shows an example of the comparison unit 32 of the second embodiment corresponding to the main circuit unit 1A of FIG.
  • the comparison unit 32A is used to distinguish it from the comparison unit 32 of FIG.
  • the comparison unit 32A includes a divider 32AD and a standard value comparator 32ASC.
  • the OPD is an output pattern determination unit.
  • V1 0.9V
  • V2 1.9V
  • V3 4.1V
  • V4 8.1V
  • the output of the gradation number determination unit 21 is 3.
  • V2 * 0.95V
  • V3 * 1.025V
  • V4 * 1.0125V.
  • the comparison result V3 *> V4 *> V2 *> V1 * is output from the standard value comparator 32ASC.
  • the output pattern determination unit 33 determines in order from the output of the third single-phase inverter having the largest comparison standard value. Since the outputs are selected in the order of priority of +, 0,-, patterns B and C in which the third single-phase inverter has a + output are selected. Next, the output of the fourth single-phase inverter with the larger comparative standard value is selected. The output is selected in the order of priority of +, 0,-, but since the output of the fourth single-phase inverter of patterns B and C is 0, it cannot be selected by the fourth single-phase inverter.
  • the output pattern determination unit 33 selects an output from a single-phase inverter having a large comparison standard value, but if the output pattern is determined using the magnitude relationship of the comparison standard value, the output is determined. There is no problem even if you change the order.
  • the output may be selected from a single-phase inverter having a smaller comparison standard value. In this case, the output of the single-phase inverter is selected in the order of-, 0, +.
  • the comparison standard value is calculated from the ratio of the target value of the capacitor voltage of each single-phase inverter and the capacitor voltage of each single-phase inverter, and the output pattern is used by using the comparison result of the calculated comparison standard value. Select.
  • the charge / discharge current of each single-phase inverter of the sub-inverter group 2 is adjusted, and a desired output voltage can be output while keeping the voltage ratio of each single-phase inverter 2I and 3I substantially constant. Therefore, it is possible to eliminate the need for a power source for supplying electric power to the sub-inverter group 2, so that the device is small and inexpensive.
  • the output pattern determination unit of the second embodiment selects the output code in order from the single-phase inverter having the larger comparative standard value, it is possible to prevent the capacitor voltage of the single-phase inverter from increasing significantly, and the voltage. It is possible to prevent the adverse effect on the capacitor due to the rise.
  • the output pattern determination unit 33 determines the output from the single-phase inverter having the larger comparison standard value V1 * to Vm + 1 *, and (B) the output of each single-phase inverter has priority in the order of +, 0,-.
  • the output pattern can be determined by a simple rule of selecting with. Since this rule can be applied even when the number of single-phase inverters increases, it is possible to control each capacitor voltage substantially constantly while outputting an arbitrary output voltage even when the number of single-phase inverters increases.
  • the power conversion device of the second embodiment includes a standard value comparison unit for comparing a comparison standard value with another comparison standard value as a comparison unit. Therefore, the power conversion device of the second embodiment can keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.
  • Embodiment 3 The power conversion device of the third embodiment has an average value comparison unit that compares at least a part of the average values of a plurality of comparison standard values with each comparison standard value as a comparison unit, and each comparison standard value and another comparison standard. It is equipped with both standard value comparison units that compare values.
  • FIG. 13 is a configuration diagram of a control unit
  • FIG. 14 is a configuration diagram of a comparison unit of the control unit
  • FIG. 15 is a configuration diagram of a modified example of the comparison unit of the control unit
  • the difference from the first embodiment will be mainly described with reference to FIG. 16, which is a configuration diagram of an example of the comparison unit of the control unit.
  • the drawings of the first embodiment will be referred to as appropriate.
  • the same or corresponding parts as those of the first embodiment are designated by the same reference numerals.
  • the configuration of the control unit 40 will be described with reference to FIG.
  • the control unit 40 includes a gradation number determination unit 21, a comparison unit 42, an output pattern determination unit 43, and a gate signal generation unit 24.
  • the difference from the control unit 20 of the first embodiment is the comparison unit 42 and the output pattern determination unit 43.
  • the comparison unit 42 includes a divider 42D, an average calculator 42H, an average value comparator 42AC which is an average value comparison unit, and a standard value comparator 42SC which is a standard value comparison unit.
  • the OPD is an output pattern determination unit.
  • the capacitor voltages V1 to Vm + 1 of each single-phase inverter 2I and 3I detected by the inverter voltage detection circuit 7D are input.
  • the input capacitor voltages V1 to Vm + 1 are standardized by the divider 42D to the comparative standard values V1 * to Vm + 1 * whose voltage levels are aligned.
  • the comparison unit 42 calculates the average value Wave from the standardized comparison standard values V1 * to Vm + 1 * with the average calculator 42H.
  • the average value Wave and the comparison standard values V4 * to Vm + 1 * are compared with the average value comparator 42AC.
  • the comparison standard values V3 * to V1 * are compared by the standard value comparator 42SC, respectively, and the magnitude relationship is clarified.
  • the difference between the average value Wave and the comparison standard values V4 * to Vm + 1 * and the magnitude relationship between the comparison standard values V1 * to V * 3 are the outputs of the comparison unit 42.
  • the comparison unit 42 in the third embodiment is different from the first and second embodiments in that both the comparison using the average value and the comparison not using the average value are used.
  • the comparison unit 42 may use both a comparison using the average value and a comparison not using the average value, and for example, the calculation method of the average value may be changed as shown in FIG. Further, the ratio of the comparison using the average value and the comparison not using the average value may be changed.
  • FIG. 15 will explain an example in which the comparison standard values V3 * to Vm + 1 * are compared with the average value, and only the comparison standard values V2 * and V1 * are compared in magnitude.
  • the comparison unit 42A includes a divider 42AD, an average calculator 42AH, an average value comparator 42AAC, and a standard value comparator 42ASC.
  • the OPD is an output pattern determination unit.
  • the average value Wave calculated by the average calculator 42AH and the comparison standard values V3 * to Vm + 1 * are compared by the average value comparator 42AAC. Further, the comparison standard values V1 * to V2 * are compared by the standard value comparator 42ASC, and the magnitude relationship thereof is clarified. Then, the difference between the average value Wave and the comparative standard values V3 * to Vm + 1 * and the magnitude relationship between the comparative standard values V1 * to V * 2 are the outputs of the comparison unit 42A.
  • the output pattern determination unit 43 in the third embodiment determines an output pattern to be used by using the output result of the comparison unit 42 from the output patterns that realize the number of gradations obtained from the gradation number determination unit 21.
  • the output pattern determination unit 43 in the third embodiment determines the output pattern according to the following rules.
  • A) Select the output in the order of the comparison result using the average value and the comparison result not using the average value.
  • B When using the comparison result using the average value, follow the following rules (same as the first embodiment).
  • (B1) Determine the output from a single-phase inverter with a large capacitor voltage.
  • (C) The comparison result without using the average value follows the following rule (same as the second embodiment).
  • (C1) The output is determined from a single-phase inverter having a large comparison standard value V1 * to Vm + 1 *.
  • (C2) The output of each single-phase inverter is selected in the order of priority of +, 0,-.
  • FIG. 5 shows an example in which the sub-inverter group 2 is composed of three single-phase inverters 2I1, 2I2, 2I3, and the main inverter group 3 is composed of one single-phase inverter 3I4.
  • the capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 2I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8.
  • FIG. 16 shows an example of the comparison unit 42 of the third embodiment corresponding to the main circuit unit 1A of FIG.
  • the comparison unit 42B is used to distinguish it from the comparison unit 42 in FIG.
  • the comparison unit 42B includes a divider 42BD, an average calculator 42BH, an average value comparator 42BAC, and a standard value comparator 42BSC.
  • the OPD is an output pattern determination unit.
  • V1 0.9V
  • V2 1.9V
  • V3 4.1V
  • V4 8.1V
  • the output of the gradation number determination unit 21 is 3.
  • V1 * 0.9V
  • V2 * 0.95V
  • V3 * 1.025V
  • V4 * 1.0125V
  • Wave ⁇ 0.972 is calculated by the average calculator 42BH.
  • V4 *> Wave is output from the average value comparator 42BAC
  • V3 *> V2 *> V1 * is output from the standard value comparator 42BSC.
  • the output pattern determination unit 43 first selects an output pattern based on the comparison result using the average value.
  • the 4th single-phase inverter is compared using the average value, and the comparison standard value of the 4th single-phase inverter is larger than the average value (V4 *> Wave), so + Select the output in the order of priority, 0,-.
  • the patterns D and E in which the output of the fourth single-phase inverter is + are selected.
  • the output pattern is then determined based on the comparison results that do not use the average value. Since V3 *> V2 *> V1 *, the output of the third single-phase inverter having the largest comparative standard value is determined in order. The output is selected in the order of priority of +, 0, and-, but patterns D and E cannot be selected because the third single-phase inverter is both-output. Next, a second single-phase inverter having a large comparative standard value will be examined. Since the output of the second single-phase inverters of patterns D and E is 0 for pattern D and ⁇ for pattern E, pattern D with 0 output is selected. By the above operation, the pattern D is selected under the above conditions and output to the gate signal generation unit 24.
  • the output is determined in the order of the comparison result using the average value and the comparison result not using the average value, but the comparison result not using the average value and the comparison result using the average value are used in this order. You may select the output. Further, a comparison using an average value for a single-phase inverter having a large capacitor voltage may be used, and a comparison using an average value may be used for a single-phase inverter having a small capacitor voltage. However, since a single-phase inverter with a small capacitor voltage is more likely to cause a voltage rise due to the charging current, it is desirable to use a comparison result that does not use an average value that can suppress the voltage rise for a single-phase inverter with a small capacitor voltage. ..
  • the comparison standard value is calculated from the ratio of the target value of the capacitor voltage of each single-phase inverter and the capacitor voltage of each single-phase inverter, and the comparison using the average value of the calculated comparison standard values is performed.
  • the output pattern is selected using the comparison result between the calculated comparison standard values.
  • the output pattern determination unit of the third embodiment it is possible to prevent the capacitor voltage of the single-phase inverter from rising significantly while preventing the output of the single-phase inverter for comparison using the average value from fluctuating from the target value. it can. Therefore, it is possible to prevent a large fluctuation in the capacitor voltage of the single-phase inverter and prevent an adverse effect on the capacitor due to the voltage rise.
  • the output pattern determination unit 43 can determine the output pattern by a simple rule. Since this rule can be applied even when the number of single-phase inverters increases, it is possible to control each capacitor voltage substantially constantly while outputting an arbitrary output voltage even when the number of single-phase inverters increases.
  • an average value comparison unit that compares at least a part of the average values of the plurality of comparison standard values with each comparison standard value, and each comparison standard. It is equipped with both a standard value comparison unit that compares a value with other comparison standard values. Therefore, the power conversion device of the third embodiment can keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.
  • This application can be widely applied to power conversion devices because it is possible to keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.

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Abstract

This power conversion device has a plurality of single-phase inverters (2I, 3I), at least one of which is connected to an external power supply (10S), wherein the voltage ratios between the DC power supply voltages of the respective single-phase inverters (2I, 3I) are constant, and is provided with: a comparison unit (22) for calculating comparison standard values by dividing the voltage ratios by the ratios between the detected voltage values of the DC power supply voltages of the single-phase inverters (2I, 3I) and the target values of the respective DC power supply voltages and performing comparison processing on the comparison standard values; and an output pattern determination unit (23) for determining, on the basis of the comparison results obtained by the comparison unit (22) and a predetermined selection condition, an output pattern that is a combination of the single-phase inverters (2I, 3I) from which voltages are to be output. The comparison unit (22) compares an average value of at least some of the plurality of comparison standard values with the respective comparison standard values.

Description

電力変換装置Power converter
 本願は、電力変換装置に関するものである。 This application relates to a power conversion device.
 複数のインバータを組み合わせて、階調制御により所望の出力波形を得ることが可能な電力変換装置が実用化されている。 A power conversion device capable of obtaining a desired output waveform by gradation control by combining a plurality of inverters has been put into practical use.
 任意の出力電圧を得ると同時に、各インバータの充放電電流を調整することで各インバータのコンデンサの電圧を一定に制御する制御法が提案されている(例えば、特許文献1)。 A control method has been proposed in which the voltage of the capacitor of each inverter is controlled to be constant by adjusting the charge / discharge current of each inverter at the same time as obtaining an arbitrary output voltage (for example, Patent Document 1).
特許第4490309公報(段落[0006]-[0008]および図1)Japanese Patent No. 4490309 (paragraphs [0006]-[0008] and FIG. 1)
 特許文献1の制御法では、インバータ数が増加すると、選択できる各インバータの出力の組合せおよび電圧を一定に保つ必要があるコンデンサ数が増加するため、コンデンサの電圧を一定に保つことが困難になる。その結果、コンデンサ電圧にばらつきが発生し、所望の出力電圧を実現できなくなる課題があった。 In the control method of Patent Document 1, as the number of inverters increases, the combination of outputs of each inverter that can be selected and the number of capacitors that need to be kept constant increase, so that it becomes difficult to keep the voltage of the capacitors constant. .. As a result, there is a problem that the capacitor voltage varies, and a desired output voltage cannot be realized.
 本願は、上記のような課題を解決するための技術を開示するものであり、電力変換装置を構成するインバータ数が増加しても、コンデンサ電圧を一定に保ち、任意の電圧を出力できる電力変換装置を提供することを目的とする。 The present application discloses a technique for solving the above-mentioned problems, and power conversion capable of keeping the capacitor voltage constant and outputting an arbitrary voltage even if the number of inverters constituting the power conversion device increases. The purpose is to provide the device.
 本願に開示される電力変換装置は、直流電源の直流電力を交流電力に変換する単相インバータの交流側を複数直列接続し、複数の単相インバータの中から選択された1以上の単相インバータの発生電圧の総和により全体出力電圧を制御して負荷に電力供給する電力変換装置において、複数の単相インバータの各々は直流電源電圧を発生する蓄電素子を含み、複数の単相インバータの少なくとも1つは外部電源と接続され、各単相インバータの直流電源電圧の目標値の比率は一定であり、複数の単相インバータの直流電源電圧を検出する電圧検出手段と、電圧検出手段により検出された複数の単相インバータの直流電源電圧と各直流電源電圧の目標値の比率で除算して比較標準値を算出し、算出した複数の比較標準値の比較処理を行う比較部と、比較部による比較結果および予め定められた選択条件に基づいて、複数の単相インバータのうち、電圧を出力すべき1以上の単相インバータの組合せである出力パターンを決定する出力パターン決定部を備え、比較部は、比較処理として複数の比較標準値のうち少なくとも一部の平均値と各比較標準値とを比較する平均値比較部、および比較処理として各比較標準値と他の比較標準値とを比較する標準値比較部の少なくとも一方を含むものである。 The power conversion device disclosed in the present application is one or more single-phase inverters selected from a plurality of single-phase inverters by connecting a plurality of AC sides of a single-phase inverter that converts DC power of a DC power source into AC power in series. In a power converter that controls the overall output voltage by the sum of the generated voltages to supply power to the load, each of the plurality of single-phase inverters includes a power storage element that generates a DC power supply voltage, and at least one of the plurality of single-phase inverters. One is connected to an external power supply, the ratio of the target value of the DC power supply voltage of each single-phase inverter is constant, and it is detected by the voltage detecting means for detecting the DC power supply voltage of a plurality of single-phase inverters and the voltage detecting means. A comparison unit that calculates a comparison standard value by dividing by the ratio of the DC power supply voltage of multiple single-phase inverters to the target value of each DC power supply voltage, and compares the calculated multiple comparison standard values, and the comparison unit. The comparison unit includes an output pattern determination unit that determines an output pattern that is a combination of one or more single-phase inverters that should output a voltage among a plurality of single-phase inverters based on the result and predetermined selection conditions. , An average value comparison unit that compares at least some of the average values of multiple comparison standard values with each comparison standard value as a comparison process, and a standard that compares each comparison standard value with another comparison standard value as a comparison process. It includes at least one of the value comparison units.
 本願に開示される電力変換装置によれば、インバータ数が増加しても、コンデンサ電圧を一定に保ち、任意の電圧を出力することが可能となる。 According to the power conversion device disclosed in the present application, even if the number of inverters increases, the capacitor voltage can be kept constant and an arbitrary voltage can be output.
実施の形態1による電力変換装置に係る主回路部の構成図である。It is a block diagram of the main circuit part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態1による電力変換装置に係る制御部の構成図である。It is a block diagram of the control part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態1による電力変換装置に係る制御部の比較部の構成図である。It is a block diagram of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態1による電力変換装置に係る制御部の比較部の変形例の構成図である。It is a block diagram of the modification part of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態1による電力変換装置に係る主回路部の1例の構成図である。It is a block diagram of an example of the main circuit part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態1による電力変換装置に係る制御部の比較部の1例の構成図である。It is a block diagram of one example of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態1による電力変換装置に係る階調数と出力パターンの関係の1例の説明図である。FIG. 5 is an explanatory diagram of an example of the relationship between the number of gradations and the output pattern according to the power conversion device according to the first embodiment. 実施の形態1による電力変換装置に係る主回路部の変形例の構成図である。It is a block diagram of the modification of the main circuit part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態1による電力変換装置に係る主回路部の別例の構成図である。It is a block diagram of another example of the main circuit part which concerns on the power conversion apparatus by Embodiment 1. FIG. 実施の形態2による電力変換装置に係る制御部の構成図である。It is a block diagram of the control part which concerns on the power conversion apparatus by Embodiment 2. 実施の形態2による電力変換装置に係る制御部の比較部の構成図である。It is a block diagram of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 2. 実施の形態2による電力変換装置に係る制御部の比較部の1例の構成図である。It is a block diagram of one example of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 2. 実施の形態3による電力変換装置に係る制御部の構成図である。It is a block diagram of the control part which concerns on the power conversion apparatus by Embodiment 3. FIG. 実施の形態3による電力変換装置に係る制御部の比較部の構成図である。It is a block diagram of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 3. FIG. 実施の形態3による電力変換装置に係る制御部の比較部の変形例の構成図である。It is a block diagram of the modification part of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 3. FIG. 実施の形態3による電力変換装置に係る制御部の比較部の1例の構成図である。It is a block diagram of one example of the comparison part of the control part which concerns on the power conversion apparatus by Embodiment 3. FIG.
実施の形態1.
 実施の形態1は、複数の単相インバータは直流電源が外部から供給される1あるいは複数の単相インバータから成る主インバータ群と、その他の複数の単相インバータから成る副インバータ群と、で構成され、主、副インバータ群の各直流電源の電圧比は略一定で、主インバータ群の直流電源電圧の総和は、副インバータ群の直流電源電圧の総和より所定の比率で大きく設定され、電圧検出手段により検出された複数の単相インバータの直流電源電圧と各直流電源電圧の目標値の比率で除算して比較標準値を算出し、算出した複数の比較標準値の比較処理を行う比較部と、各単相インバータの出力の組合せを決定する出力パターン決定部を備え、比較部は複数の比較標準値のうち少なくとも一部の平均値と各比較標準値とを比較する平均値比較部を備え、出力パターン決定部は比較部の出力結果を用いて副インバータ群の各直流電圧を、各単相インバータを介した充放電により略一定になるように各単相インバータの出力の組合せを選択する電力変換装置に関するものである。
Embodiment 1.
In the first embodiment, the plurality of single-phase inverters are composed of a main inverter group composed of one or a plurality of single-phase inverters to which DC power is supplied from the outside, and a sub-inverter group composed of a plurality of other single-phase inverters. The voltage ratio of each DC power supply of the main and sub-inverter groups is substantially constant, and the total DC power supply voltage of the main inverter group is set to be larger than the total DC power supply voltage of the sub-inverter group by a predetermined ratio, and the voltage is detected. A comparison unit that calculates a comparison standard value by dividing by the ratio of the DC power supply voltage of a plurality of single-phase inverters detected by the means and the target value of each DC power supply voltage, and performs comparison processing of the calculated multiple comparison standard values. , Equipped with an output pattern determination unit that determines the combination of outputs of each single-phase inverter, and the comparison unit includes an average value comparison unit that compares at least a part of the average values of a plurality of comparison standard values with each comparison standard value. , The output pattern determination unit selects the output combination of each single-phase inverter so that each DC voltage of the sub-inverter group becomes substantially constant by charging / discharging via each single-phase inverter using the output result of the comparison unit. It relates to a power converter.
 以下、実施の形態1に係る電力変換装置の構成および動作について、電力変換装置の主回路部の構成図である図1、制御部の構成図である図2、制御部の比較部の構成図である図3、制御部の比較部の変形例の構成図である図4、主回路部の1例の構成図である図5、制御部の比較部の1例の構成図である図6、階調数と出力パターンの関係の1例の説明図である図7、主回路部の変形例の構成図である図8、および主回路部の別例の構成図である図9に基づいて説明する。 Hereinafter, regarding the configuration and operation of the power conversion device according to the first embodiment, FIG. 1 which is a configuration diagram of a main circuit unit of the power conversion device, FIG. 2 which is a configuration diagram of a control unit, and a configuration diagram of a comparison unit of the control unit. FIG. 3, FIG. 4, which is a configuration diagram of a modified example of the comparison unit of the control unit, FIG. 5, which is a configuration diagram of an example of the main circuit unit, and FIG. 6 which is a configuration diagram of an example of the comparison unit of the control unit. Based on FIG. 7, which is an explanatory diagram of an example of the relationship between the number of gradations and an output pattern, FIG. 8 which is a configuration diagram of a modified example of the main circuit unit, and FIG. 9 which is a configuration diagram of another example of the main circuit unit. Will be explained.
 実施の形態1の電力変換装置の全体の構成および動作を図1、図2に基づいて説明する。
 電力変換装置は、図1の主回路部1と図2の制御部20を備える。
The overall configuration and operation of the power conversion device of the first embodiment will be described with reference to FIGS. 1 and 2.
The power conversion device includes the main circuit unit 1 of FIG. 1 and the control unit 20 of FIG.
 まず、図1に基づいて、電力変換装置の主回路部1の構成および動作を説明する。
 主回路部1は、第2のインバータ群である副インバータ群2、第1のインバータ群である主インバータ群3、切換スイッチ4、充電用抵抗5、出力フィルタ6、インバータ電圧検出回路7D、および出力電圧検出回路8を備える。
 主回路部1の出力には、負荷11が接続されている。
 なお、副インバータ群2および主インバータ群3の全体をインバータユニットと記載する。
First, the configuration and operation of the main circuit unit 1 of the power conversion device will be described with reference to FIG.
The main circuit unit 1 includes a sub-inverter group 2 which is a second inverter group, a main inverter group 3 which is a first inverter group, a changeover switch 4, a charging resistor 5, an output filter 6, an inverter voltage detection circuit 7D, and an inverter voltage detection circuit 7D. The output voltage detection circuit 8 is provided.
A load 11 is connected to the output of the main circuit unit 1.
The entire sub-inverter group 2 and main inverter group 3 are referred to as an inverter unit.
 副インバータ群2は、単相インバータ2I1、2I2、・・・、2Im(mは2以上の整数)から構成される。副インバータ群2の単相インバータを代表して記載する場合は、単相インバータ2Iと記載する。
 また、主インバータ群3は、単相インバータ3Im+1、・・・、3Im+n(nは1以上の整数)から構成される。主インバータ群3の単相インバータを代表して記載する場合は、単相インバータ3Iと記載する。
 また、各単相インバータ2I、3Iの出力電圧を検出する電圧検出手段であるインバータ電圧検出回路7D1、7D2、・・・、7Dm、7Dm+1について、特にそれぞれ区別する必要がない場合は、インバータ電圧検出回路7Dと記載する。
The sub-inverter group 2 is composed of single-phase inverters 2I1, 2I2, ..., 2Im (m is an integer of 2 or more). When the single-phase inverter of the sub-inverter group 2 is described as a representative, it is described as the single-phase inverter 2I.
Further, the main inverter group 3 is composed of single-phase inverters 3Im + 1, ..., 3Im + n (n is an integer of 1 or more). When the single-phase inverter of the main inverter group 3 is described as a representative, it is described as the single-phase inverter 3I.
Further, when it is not necessary to distinguish the inverter voltage detection circuits 7D1, 7D2, ..., 7Dm, 7Dm + 1, which are voltage detecting means for detecting the output voltage of each single-phase inverter 2I and 3I, the inverter voltage detection is performed. Described as circuit 7D.
 各単相インバータ2I、3Iは複数個のダイオードを逆並列に接続した複数個のIGBT(Insulated Gate Bipolar transistоr)等の自己消弧型半導体スイッチング素子(g11、g12、g21、g22)と蓄電素子であるコンデンサによるフルブリッジ回路で構成される。
 なお、図1において、簡素化のために、ダイオードおよびコンデンサの符番号を省略している。
Each single-phase inverter 2I, 3I is a self-extinguishing semiconductor switching element (g11, g12, g21, g22) such as a plurality of IGBTs (Insulated Gate Bipolar transformers) in which a plurality of diodes are connected in antiparallel and a power storage element. It consists of a full bridge circuit with a capacitor.
In FIG. 1, the reference numerals of the diode and the capacitor are omitted for simplification.
 各単相インバータ2I、3Iのコンデンサは、各単相インバータ2I、3Iの直流電源である。
 副インバータ群2の単相インバータ2I1~2Imの直流電源の電圧であるコンデンサ電圧V1、V2、・・・、Vm、および主インバータ群3の単相インバータ3Im+1~3Im+nの直流電源の電圧であるコンデンサ電圧Vm+1~Vm+nは電圧比(V1:V2:・・・:Vm+n)が略一定で制御される。
 なお、主インバータ群3の単相インバータ3Im+1~3Im+nの直流電源であるコンデンサの電圧は、単相インバータ3Im+1のコンデンサの電圧のみを検出している。
 以降、直流電源であるコンデンサの電圧を適宜、直流電源電圧またはコンデンサ電圧と記載する。
The capacitors of the single-phase inverters 2I and 3I are DC power supplies of the single-phase inverters 2I and 3I.
The voltage of the DC power supply of the single-phase inverters 2I1 to 2Im of the sub-inverter group 2 V1, V2, ..., Vm, and the voltage of the DC power supply of the single-phase inverter 3Im + 1 to 3Im + n of the main inverter group 3. The voltage ratio (V1: V2: ...: Vm + n) is controlled to be substantially constant for the voltages Vm + 1 to Vm + n.
As for the voltage of the capacitor which is the DC power supply of the single-phase inverters 3Im + 1 to 3Im + n of the main inverter group 3, only the voltage of the capacitor of the single-phase inverter 3Im + 1 is detected.
Hereinafter, the voltage of the capacitor which is a DC power supply will be appropriately referred to as a DC power supply voltage or a capacitor voltage.
 主インバータ群3の直流電源電圧の総和(Vm+1+Vm+2+・・・+Vm+n)は副インバータ群2の直流電源電圧の総和(V1+V2+・・・+Vm)よりも所定の比率で大きく制御される。
 実施の形態1の場合はV1:V2:・・・:Vm+nは1:2:・・・:2^(m+n-1)に制御される。制御の詳細については、後述する。
 主インバータ群3の各単相インバータ3Im+1・・・、3Im+nは外部電源10S1、・・・、10Snにより電力が供給される。
 なお、各外部電源10S1、・・・、10Snを特に区別する必要がない場合は、外部電源10Sと記載する。
The total DC power supply voltage of the main inverter group 3 (Vm + 1 + Vm + 2 + ... + Vm + n) is controlled to be larger than the total DC power supply voltage of the sub-inverter group 2 (V1 + V2 + ... + Vm) at a predetermined ratio.
In the case of the first embodiment, V1: V2: ...: Vm + n is controlled to 1: 2: ...: 2 ^ (m + n-1). The details of the control will be described later.
The single-phase inverters 3Im + 1 ..., 3Im + n of the main inverter group 3 are supplied with electric power by the external power supplies 10S1, ..., 10Sn.
When it is not necessary to distinguish each external power supply 10S1, ..., 10Sn, it is described as an external power supply 10S.
 各単相インバータ2I、3Iは、出力として正負およびゼロの電圧を発生することができる。
 例えば単相インバータ2I1において、出力が正の時には、半導体スイッチング素子g11およびg22がオンし、出力が負の時には半導体スイッチング素子g12およびg21がオンする。また出力が0の時には半導体スイッチング素子g11およびg21(あるいはg12およびg22)がオンする。
Each single-phase inverter 2I, 3I can generate positive and negative and zero voltages as outputs.
For example, in the single-phase inverter 2I1, when the output is positive, the semiconductor switching elements g11 and g22 are turned on, and when the output is negative, the semiconductor switching elements g12 and g21 are turned on. When the output is 0, the semiconductor switching elements g11 and g21 (or g12 and g22) are turned on.
 インバータユニットは、副インバータ群2および主インバータ群3を備え、各単相インバータ2I1~2Im、3Im+1~3Im+nの交流側を直列に接続されている。各単相インバータ2I1~2Im、3Im+1~3Im+nの発生電圧を組み合わせることで、その総和として所定の電圧を階調制御により出力する。
 インバータユニットは、階調制御された所定の電圧を出力フィルタ6を介して負荷11に電力供給する。
 各単相インバータ2I1~2Im、3Im+1~3Im+nの出力電圧比V1:V2:・・・:Vm+nが1:2:・・・:2^(m+n-1)と制御されている場合は、インバータユニットの出力電圧は0(階調数0)からV1×{2^(m+n-1)}(階調数2^(m+n-1)までV1(階調数1)の細かさで出力することができる。
The inverter unit includes a sub-inverter group 2 and a main inverter group 3, and the AC side of each single-phase inverter 2I1 to 2Im, 3Im + 1 to 3Im + n is connected in series. By combining the generated voltages of the single-phase inverters 2I1 to 2Im, 3Im + 1 to 3Im + n, a predetermined voltage is output as the total by gradation control.
The inverter unit supplies power to the load 11 via the output filter 6 with a predetermined voltage whose gradation is controlled.
When the output voltage ratio of each single-phase inverter 2I1 to 2Im, 3Im + 1 to 3Im + n is controlled as V1: V2: ...: Vm + n is 1: 2: ...: 2 ^ (m + n-1), the inverter unit The output voltage of is V1 (gradation number 1) from 0 (gradation number 0) to V1 × {2 ^ (m + n-1)} (gradation number 2 ^ (m + n-1)). it can.
 インバータユニットの出力端には、充電用抵抗5と切換スイッチ4とが設置されている。
 切換スイッチ4は、副インバータ群2の交流出力端を、電力変換装置の起動時に充電用抵抗5に接続して副インバータ群2の各直流電源を初期充電する。切換スイッチ4は、通常出力時には出力フィルタ5側に接続される。
 この初期充電は後述する制御により行う。図1では、切換スイッチ4は副インバータ群2の交流出力に接続しているが、主インバータ群3の出力側に接続しても良い。また、切換スイッチ4および充電用抵抗5は出力フィルタ6の出力側に設置しても良い。
A charging resistor 5 and a changeover switch 4 are installed at the output end of the inverter unit.
The changeover switch 4 connects the AC output end of the sub-inverter group 2 to the charging resistor 5 when the power conversion device is started to initially charge each DC power source of the sub-inverter group 2. The changeover switch 4 is connected to the output filter 5 side at the time of normal output.
This initial charge is performed by the control described later. In FIG. 1, the changeover switch 4 is connected to the AC output of the sub-inverter group 2, but may be connected to the output side of the main inverter group 3. Further, the changeover switch 4 and the charging resistor 5 may be installed on the output side of the output filter 6.
 また、負荷11に充電電流を流すことで、副インバータ群2の各直流電源の初期充電を行ってもよい。この場合は、負荷11に充電電流を流すため、充電用抵抗5と切換スイッチ4は不要となる。
 また、初期充電の時だけ副インバータ群2に外部電源を接続することで副インバータ群2の各直流電源の初期充電を行ってもよい。この場合は、副インバータ群2の各単相インバータ2I1の直流電源を直接充電するため、充電用抵抗5と切換スイッチ4は不要となる。
Further, the initial charge of each DC power source of the sub-inverter group 2 may be performed by passing a charging current through the load 11. In this case, since the charging current is passed through the load 11, the charging resistor 5 and the changeover switch 4 are unnecessary.
Further, the initial charge of each DC power source of the sub-inverter group 2 may be performed by connecting an external power source to the sub-inverter group 2 only at the time of the initial charge. In this case, since the DC power supply of each single-phase inverter 2I1 of the sub-inverter group 2 is directly charged, the charging resistor 5 and the changeover switch 4 are unnecessary.
 副インバータ群2の各単相インバータ2Iの直流電源電圧であるコンデンサ電圧と主インバータ群3の1つ以上の単相インバータ3Iの直流電源電圧であるコンデンサ電圧はインバータ電圧検出回路7Dにより検出される。
 図1では主インバータ群3の中で最も電圧が小さい単相インバータ3Im+1の直流電源電圧であるコンデンサ電圧だけを検出する例を示している。
 以降は主インバータ群3の中で最も電圧が小さい単相インバータ3Im+1の直流電源電圧であるコンデンサ電圧だけを検出する場合について説明する。
 主インバータ群3の中で最も電圧が小さい単相インバータ以外の直流電源電圧であるコンデンサ電圧を検出したとしても同様の手法が適用できる。
The capacitor voltage which is the DC power supply voltage of each single-phase inverter 2I of the sub-inverter group 2 and the capacitor voltage which is the DC power supply voltage of one or more single-phase inverters 3I of the main inverter group 3 are detected by the inverter voltage detection circuit 7D. ..
FIG. 1 shows an example of detecting only the capacitor voltage, which is the DC power supply voltage of the single-phase inverter 3Im + 1, which has the smallest voltage in the main inverter group 3.
Hereinafter, a case where only the capacitor voltage, which is the DC power supply voltage of the single-phase inverter 3Im + 1, which has the smallest voltage in the main inverter group 3, is detected will be described.
The same method can be applied even if a capacitor voltage, which is a DC power supply voltage other than the single-phase inverter having the smallest voltage in the main inverter group 3, is detected.
 負荷11に出力される電圧は出力電圧検出回路8によって検出される。なお、出力電圧検出回路8の設置位置はインバータユニットの出力電圧を検出できる位置であればよく、例えば出力フィルタ6の前段または切換スイッチ4の前段でもよい。 The voltage output to the load 11 is detected by the output voltage detection circuit 8. The installation position of the output voltage detection circuit 8 may be any position as long as it can detect the output voltage of the inverter unit, and may be, for example, the front stage of the output filter 6 or the front stage of the changeover switch 4.
 次に制御部20の構成および動作を図2に基づいて説明する。
 制御部20は階調数決定部21、比較部22、出力パターン決定部23、およびゲート信号生成部24を備える。
Next, the configuration and operation of the control unit 20 will be described with reference to FIG.
The control unit 20 includes a gradation number determination unit 21, a comparison unit 22, an output pattern determination unit 23, and a gate signal generation unit 24.
 階調数決定部21は出力電圧検出回路8で検出した出力電圧Voと出力電圧指令値とに基づいて、出力電圧Voを出力電圧指令値に制御すべく階調数を決定する。
 具体的には、出力電圧検出値Voと出力電圧指令値の差分を、PI(Proportional-Integral)制御器に入力し、PI制御器の出力結果を階調数として用いる。
 PI制御はP(Proportional)制御、PID(Proportional-Integral-Differential)制御など出力電圧検出値Voを出力電圧指令値に近づけるように動作する制御であればよい。
 また、PI演算結果の階調数に採用される位より小さな値(小数点以下部分)対する丸めこみ処理、あるいはリミッタ処理などを追加してもよい。
The gradation number determination unit 21 determines the gradation number in order to control the output voltage Vo to the output voltage command value based on the output voltage Vo detected by the output voltage detection circuit 8 and the output voltage command value.
Specifically, the difference between the output voltage detection value Vo and the output voltage command value is input to the PI (Proportional-Integral) controller, and the output result of the PI controller is used as the number of gradations.
The PI control may be any control such as P (Proportional) control and PID (Proportional-Integral-Differential) control that operates so as to bring the output voltage detection value Vo closer to the output voltage command value.
Further, a rounding process or a limiter process for a value smaller than the number adopted for the number of gradations of the PI calculation result (the portion after the decimal point) may be added.
 次に比較部22の構成と動作を図3に基づいて説明する。
 比較部22は、除算器22D、平均演算器22H、平均値比較部である平均値比較器22ACを備える。図において、OPDは出力パターン決定部である。
 例えば、除算器はそれぞれ入出力が異なるが、機能は同じであるため除算器22Dとしている。また、平均値比較器はそれぞれ入出力が異なるが、機能は同じであるため平均値比較器22ACとしている。以降の比較部の構成図においても同様に各演算器の符番号は区別していない。
Next, the configuration and operation of the comparison unit 22 will be described with reference to FIG.
The comparison unit 22 includes a divider 22D, an average calculator 22H, and an average value comparator 22AC which is an average value comparison unit. In the figure, the OPD is an output pattern determination unit.
For example, the dividers have different inputs and outputs, but have the same functions, so the divider 22D is used. Further, although the input and output of the average value comparator are different, the functions are the same, so the average value comparator 22AC is used. Similarly, in the subsequent configuration diagrams of the comparison section, the code numbers of each arithmetic unit are not distinguished.
 比較部22にはインバータ電圧検出回路7Dで検出した各単相インバータ2I、3Iのコンデンサ電圧V1~Vm+1が入力される。入力されたコンデンサ電圧V1~Vm+1は除算器22Dによって電圧レベルが揃えられた信号V1*~Vm+1*に変換、すなわち規格化される。この規格化された信号を比較標準値と記載する。
 すなわち、電圧検出手段により検出された複数の単相インバータの直流電源電圧と各直流電源電圧の目標値の比率で除算して比較標準値を算出する。
The capacitor voltages V1 to Vm + 1 of the single-phase inverters 2I and 3I detected by the inverter voltage detection circuit 7D are input to the comparison unit 22. The input capacitor voltages V1 to Vm + 1 are converted, that is, standardized, into signals V1 * to Vm + 1 * having uniform voltage levels by the divider 22D. This standardized signal is referred to as a comparative standard value.
That is, the comparative standard value is calculated by dividing by the ratio of the DC power supply voltage of the plurality of single-phase inverters detected by the voltage detecting means and the target value of each DC power supply voltage.
 具体的には、例えばインバータ電圧検出回路7Dmで検出された単相インバータ2Imのコンデンサ電圧Vmは、除算器22Dにおいてコンデンサ電圧の目標値の比率であるKmで除算される。
 ここで、K1~Km+1は、単相インバータ2I1~2Im、3Im+1のコンデンサ電圧の目標値の比率が(V1:V2:・・・:Vm+1)=(1:2:・・・:2^m)であれば、例えばK1=1、K2=2、・・・、Km+1=2^mとすればよい。
Specifically, for example, the capacitor voltage Vm of the single-phase inverter 2Im detected by the inverter voltage detection circuit 7Dm is divided by Km, which is the ratio of the target value of the capacitor voltage in the divider 22D.
Here, for K1 to Km + 1, the ratio of the target values of the capacitor voltages of the single-phase inverters 2I1 to 2Im and 3Im + 1 is (V1: V2: ...: Vm + 1) = (1: 2: ...: 2 ^ m). Then, for example, K1 = 1, K2 = 2, ..., Km + 1 = 2 ^ m may be set.
 規格化後の信号、すなわち比較標準値V1*~Vm+1*から平均演算器22Hで平均値Vaveを算出する。平均値Vaveは比較標準値(V2*~Vm+1*)と平均値比較器22ACで比較され、m個の平均値比較信号が出力される。 The average value Wave is calculated by the average calculator 22H from the standardized signal, that is, the comparative standard values V1 * to Vm + 1 *. The average value Wave is compared with the comparison standard value (V2 * to Vm + 1 *) by the average value comparator 22AC, and m average value comparison signals are output.
 なお、実施の形態1における比較部22は算出した平均値を用いて比較結果を出力すればよく、例えば図4に示すように平均値の演算法を変更してもよい。
 図4は比較部の変形例の構成図であり、図3の比較部22と区別するために比較部22Aとしている。
 比較部22Aは、除算器22AD、平均演算器22AH、平均値比較器22AACを備える。図において、OPDは出力パターン決定部である。
The comparison unit 22 in the first embodiment may output the comparison result using the calculated average value, and may change the calculation method of the average value as shown in FIG. 4, for example.
FIG. 4 is a configuration diagram of a modified example of the comparison unit, and is referred to as the comparison unit 22A in order to distinguish it from the comparison unit 22 of FIG.
The comparison unit 22A includes a divider 22AD, an average calculator 22AH, and an average value comparator 22AAC. In the figure, the OPD is an output pattern determination unit.
 図4において、比較標準値V1*~Vm+1*から平均演算器22AHで平均値Vave-1を算出し、比較標準値V1*~Vm*から平均演算器22AHで平均値Vave-2を算出する。また、比較標準値V1*、V2*から平均演算器22AHで平均値Vave-mを算出する。
 平均値Vave-1は比較標準値Vm+1*と平均値比較器22AACで比較され、平均値Vave-2は比較標準値Vm*と平均値比較器22AACで比較され、平均値Vave-mは比較標準値V2*と平均値比較器22AACで比較され、それぞれの平均値比較信号が出力される。
 すなわち、Lを(1<L≦m+1)の範囲の整数とすると、比較標準値VL*と比較する平均値の演算には1~VLまでの比較標準値を用いる。
In FIG. 4, the average value Vave-1 is calculated from the comparative standard values V1 * to Vm + 1 * by the average calculator 22AH, and the average value Vave-2 is calculated from the comparative standard values V1 * to Vm * by the average calculator 22AH. Further, the average value Wave-m is calculated from the comparative standard values V1 * and V2 * by the average calculator 22AH.
The average value Vave-1 is compared with the comparison standard value Vm + 1 * and the average value comparator 22AAC, the average value Vave-2 is compared with the comparison standard value Vm * and the average value comparator 22AAC, and the average value Vave-m is the comparison standard. The value V2 * is compared with the average value comparator 22AAC, and each average value comparison signal is output.
That is, assuming that L is an integer in the range of (1 <L ≦ m + 1), the comparison standard value from 1 to VL is used for the calculation of the average value to be compared with the comparison standard value VL *.
 実施の形態1の比較部の構成を一般化すると、副インバータ群がY個の単相インバータで構成されている場合、比較部はY個以上の平均値比較部を含む。 Generalizing the configuration of the comparison unit of the first embodiment, when the sub-inverter group is composed of Y single-phase inverters, the comparison unit includes Y or more average value comparison units.
 出力パターン決定部23の動作について説明する。
 出力パターン決定部23では階調数決定部21で決定した階調数と比較部22から出力される比較結果に基づいて後述する動作で各単相インバータの出力の組合せ(出力パターン)を決定する。
 制御部20は、出力パターン決定部23が決定した出力パターンおよび階調数に基づいて、各単相インバータ2I、3Iのコンデンサ電圧を略一定に制御する。
The operation of the output pattern determination unit 23 will be described.
The output pattern determination unit 23 determines the combination (output pattern) of the outputs of each single-phase inverter by the operation described later based on the gradation number determined by the gradation number determination unit 21 and the comparison result output from the comparison unit 22. ..
The control unit 20 controls the capacitor voltages of the single-phase inverters 2I and 3I to be substantially constant based on the output pattern and the number of gradations determined by the output pattern determination unit 23.
 ゲート信号生成部24は出力パターン決定部23の出力結果に基づいて各単相インバータ2I、3Iを動作させるゲート信号を生成する。
 具体的には、出力パターンから各単相インバータ2I、3Iの半導体スイッチング素子g11~g22を駆動するゲート駆動信号を生成する。
The gate signal generation unit 24 generates a gate signal for operating the single-phase inverters 2I and 3I based on the output result of the output pattern determination unit 23.
Specifically, a gate drive signal for driving the semiconductor switching elements g11 to g22 of each single-phase inverter 2I and 3I is generated from the output pattern.
 次に、出力パターン決定部23の動作の具体例を、図5~図7に基づいて説明する。
 出力パターン決定部23は、階調数決定部21から得られる階調数を実現する複数の出力パターンから比較部22の出力結果を用いて出力パターンを決定するが、その際、下記のルールに従い出力パターンを決定する。
(A)コンデンサ電圧が大きい単相インバータから出力を決める。
(B)ある単相インバータでは、コンデンサ電圧が平均値より大きい場合は+、0、-の順の優先度で出力を選択する。コンデンサ電圧が平均値より小さい場合は-、0、+の順の優先度で出力を選択する。
Next, a specific example of the operation of the output pattern determination unit 23 will be described with reference to FIGS. 5 to 7.
The output pattern determination unit 23 determines an output pattern from a plurality of output patterns that realize the number of gradations obtained from the gradation number determination unit 21 by using the output result of the comparison unit 22. At that time, the output pattern is determined according to the following rules. Determine the output pattern.
(A) Determine the output from a single-phase inverter with a large capacitor voltage.
(B) In a certain single-phase inverter, when the capacitor voltage is larger than the average value, the output is selected in the order of +, 0,-. If the capacitor voltage is smaller than the average value, the output is selected in the order of-, 0, +.
 出力パターン決定部23の動作を主回路部1の1例の構成図である図5に基づいて説明する。
 図5は副インバータ群2が3つの単相インバータ2I1、2I2、2I3、主インバータ群3が1つの単相インバータ3I4で構成された例である。
 図1の主回路部1と区別するために、主回路部1Aとしている。また、副インバータ群2A、主インバータ群3Aとしている。
 単相インバータ2I1の出力電圧をインバータ電圧検出回路7D1で検出し、単相インバータ2I2の出力電圧をインバータ電圧検出回路7D2で検出し、単相インバータ2I3の出力電圧をインバータ電圧検出回路7D3で検出している。また、単相インバータ3I4の出力電圧をインバータ電圧検出回路7D4で検出している。
 簡略化のため切換スイッチ4、充電用抵抗5は省略している。
The operation of the output pattern determination unit 23 will be described with reference to FIG. 5, which is a configuration diagram of an example of the main circuit unit 1.
FIG. 5 shows an example in which the sub-inverter group 2 is composed of three single-phase inverters 2I1, 2I2, 2I3, and the main inverter group 3 is composed of one single-phase inverter 3I4.
In order to distinguish it from the main circuit unit 1 in FIG. 1, the main circuit unit 1A is used. Further, the sub-inverter group 2A and the main inverter group 3A are used.
The output voltage of the single-phase inverter 2I1 is detected by the inverter voltage detection circuit 7D1, the output voltage of the single-phase inverter 2I2 is detected by the inverter voltage detection circuit 7D2, and the output voltage of the single-phase inverter 2I3 is detected by the inverter voltage detection circuit 7D3. ing. Further, the output voltage of the single-phase inverter 3I4 is detected by the inverter voltage detection circuit 7D4.
For the sake of simplicity, the changeover switch 4 and the charging resistor 5 are omitted.
 各単相インバータ2I1、2I2、2I3、3I4のコンデンサ電圧V1、V2、V3、V4は1:2:4:8で略一定になるように制御する。また、コンデンサ電圧が小さい単相インバータから順に第1単相インバータ、第2単相インバータ、第3単相インバータ、第4単相インバータと記載する。
 本例では、単相インバータ2I1が第1単相インバータに相当し、単相インバータ2I2が第2単相インバータに相当し、単相インバータ2I3が第3単相インバータに相当し、単相インバータ3I4が第4単相インバータに相当する。
The capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 2I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8. Further, the first single-phase inverter, the second single-phase inverter, the third single-phase inverter, and the fourth single-phase inverter will be described in order from the single-phase inverter having the smallest capacitor voltage.
In this example, the single-phase inverter 2I1 corresponds to the first single-phase inverter, the single-phase inverter 2I2 corresponds to the second single-phase inverter, the single-phase inverter 2I3 corresponds to the third single-phase inverter, and the single-phase inverter 3I4. Corresponds to the fourth single-phase inverter.
 図5の主回路部1Aに対応する比較部の1例を図6に示す。
 ここで、図6では、図3の比較部22、図4の比較部22Aと区別するために比較部22Bとしている。
 比較部22Bは、除算器22BD、平均演算器22BH、平均値比較器22BACを備える。図において、OPDは出力パターン決定部である。
FIG. 6 shows an example of a comparison unit corresponding to the main circuit unit 1A of FIG.
Here, in FIG. 6, the comparison unit 22B is used to distinguish it from the comparison unit 22 in FIG. 3 and the comparison unit 22A in FIG.
The comparison unit 22B includes a divider 22BD, an average calculator 22BH, and an average value comparator 22BAC. In the figure, the OPD is an output pattern determination unit.
 各単相インバータ2I1、2I2、2I3、3I4のコンデンサ電圧がV1=0.9V、V2=1.9V、V3=4.1V、V4=8.1V、階調数決定部21の出力が3であった場合を想定する。
 比較部22Bにおいて、除算器22BDで、V1*=0.9V、V2*=0.95V、V3*=1.025V、V4*=1.0125Vが算出される。
 平均演算器22BHで、平均値Vave≒0.972が算出される。
 平均値比較器22BACから比較結果V4*>Vave、V3*>Vave、V2*<Vaveが出力される。
The capacitor voltage of each single-phase inverter 2I1, 2I2, 2I3, 3I4 is V1 = 0.9V, V2 = 1.9V, V3 = 4.1V, V4 = 8.1V, and the output of the gradation number determination unit 21 is 3. Imagine if there was one.
In the comparison unit 22B, the divider 22BD calculates V1 * = 0.9V, V2 * = 0.95V, V3 * = 1.025V, and V4 * = 1.0125V.
The average value Wave≈0.972 is calculated by the average calculator 22BH.
The comparison results V4 *> Vave, V3 *> Vave, and V2 * <Vave are output from the average value comparator 22BAC.
 階調数3の時の出力パターンは図7に示す通り、パターンA~Eの5通り存在する。
 パターンAは第1単相インバータと第2単相インバータで+を出力(3=1+2)している。
 パターンBは第3単相インバータで+、第1単相インバータで-を出力(3=4-1)している。パターンCは第1、第3単相インバータで+、第2単相インバータで-を出力(3=4-2+1)している。
 パターンDは第4単相インバータで+、第1、第3単相インバータで-を出力(3=8-4-1)している。
 パターンEは第1、第4単相インバータで+、第2、第3単相インバータでーを出力(3=8-4-2+1)している。
As shown in FIG. 7, there are five output patterns, patterns A to E, when the number of gradations is 3.
In pattern A, + is output (3 = 1 + 2) by the first single-phase inverter and the second single-phase inverter.
In pattern B, the third single-phase inverter outputs + and the first single-phase inverter outputs − (3 = 4-1). In pattern C, + is output by the first and third single-phase inverters, and-is output by the second single-phase inverter (3 = 4-2 + 1).
In pattern D, + is output by the fourth single-phase inverter, and-is output by the first and third single-phase inverters (3 = 8-4-1).
In the pattern E, the first and fourth single-phase inverters output +, and the second and third single-phase inverters output − (3 = 8-4-2 + 1).
 出力パターン決定部23の動作の具体例を説明する。この例では、以下のルールに従い出力パターンを決定する。
(A)コンデンサ電圧V1~V4が大きい単相インバータから出力を決める。
(B)各単相インバータでは、比較標準値が平均値より大きい場合は、+、0、-の順の優先度で出力を選択する。比較標準値が平均値より小さい場合は、-、0、+の順の優先度で出力を選択する。
A specific example of the operation of the output pattern determination unit 23 will be described. In this example, the output pattern is determined according to the following rules.
(A) The output is determined from a single-phase inverter having a large capacitor voltage V1 to V4.
(B) In each single-phase inverter, when the comparison standard value is larger than the average value, the output is selected in the order of priority of +, 0,-. If the comparison standard value is smaller than the average value, the output is selected in the order of-, 0, +.
 具体的には、コンデンサ電圧の大きい第4単相インバータの出力から順に決定していく。
 第4単相インバータの比較標準値は平均値より大きい(V4*>Vave)ため、第4単相インバータの出力は+、0、-の順の優先度で選択される。階調数3の5つのパターンの内、第4単相インバータが+出力であるパターンD、Eが選択される。
 次にコンデンサ電圧が大きい第3単相インバータを検討する。第3単相インバータの比較標準値は平均値より大きい(V3*>Vave)ため、第3単相インバータの出力は+、0、-の順の優先度で選択される。パターンD、Eの第3単相インバータの出力はともに-であるため、パターンD、Eの一方のみを選択することはできないため、パターンD、Eの両方が選択される。
 次にコンデンサ電圧が大きい第2単相インバータを検討する。第2単相インバータの比較標準値は平均値より小さい(V2*<Vave)ため、第2単相インバータの出力は-、0、+の順の優先度で選択される。
 パターンDは0出力、パターンEは-出力であるため、第2単相インバータが-出力であるパターンEが選択される。以上の動作により上記条件ではパターンEが選択され、ゲート信号生成部24に出力される。
Specifically, the output of the fourth single-phase inverter having the largest capacitor voltage is determined in order.
Since the comparative standard value of the fourth single-phase inverter is larger than the average value (V4 *> Wave), the output of the fourth single-phase inverter is selected in the order of +, 0,-. Of the five patterns with the number of gradations 3, patterns D and E in which the fourth single-phase inverter has a + output are selected.
Next, consider a third single-phase inverter with a large capacitor voltage. Since the comparative standard value of the third single-phase inverter is larger than the average value (V3 *> Wave), the output of the third single-phase inverter is selected in the order of +, 0,-. Since the outputs of the third single-phase inverters of patterns D and E are both −, only one of patterns D and E cannot be selected, so both patterns D and E are selected.
Next, consider a second single-phase inverter with a large capacitor voltage. Since the comparative standard value of the second single-phase inverter is smaller than the average value (V2 * <Vave), the output of the second single-phase inverter is selected in the order of −, 0, +.
Since the pattern D has 0 output and the pattern E has-output, the pattern E in which the second single-phase inverter has-output is selected. By the above operation, the pattern E is selected under the above conditions and output to the gate signal generation unit 24.
 以上の実施の形態1の説明では、出力パターン決定部23にてコンデンサ電圧が大きい単相インバータから出力を決定していく方法を示したが、出力を決める単相インバータの順は自由に変更しても問題ない。
 例えば、コンデンサ電圧が小さい単相インバータから出力を決定してもよい。ただし、コンデンサ電圧の大きな単相インバータのコンデンサ電圧が変動した方が、出力電圧の変動として大きく表れるため、コンデンサ電圧の大きな単相インバータの出力から決めていくことが望ましい。
In the above description of the first embodiment, the method of determining the output from the single-phase inverter having a large capacitor voltage is shown by the output pattern determination unit 23, but the order of the single-phase inverters that determine the output can be freely changed. There is no problem.
For example, the output may be determined from a single-phase inverter having a small capacitor voltage. However, fluctuations in the capacitor voltage of a single-phase inverter with a large capacitor voltage appear more as fluctuations in the output voltage, so it is desirable to determine from the output of a single-phase inverter with a large capacitor voltage.
 以上の実施の形態1の説明では、主回路部1の出力電圧Voを検出し、出力電圧Voを電圧指令値に近づける構成について説明した。
 主回路部1の出力電流Ioを検出し、出力電流Ioを電流指令値に近づける構成としてもよい。この出力電流Ioを電流指令値に近づけるように制御する場合の主回路部の構成図を図8に示す。図8では、図1の主回路部1と区別するために、主回路部1Bとしている。
 図1の出力電圧検出回路8を出力電流検出回路12に変更し、また制御部20において、階調数決定部21に入力する信号を出力電流検出値と出力電流指令値に変更すればよい。
In the above description of the first embodiment, the configuration in which the output voltage Vo of the main circuit unit 1 is detected and the output voltage Vo is brought close to the voltage command value has been described.
The output current Io of the main circuit unit 1 may be detected and the output current Io may be brought close to the current command value. FIG. 8 shows a configuration diagram of a main circuit unit when the output current Io is controlled so as to approach the current command value. In FIG. 8, the main circuit unit 1B is used to distinguish it from the main circuit unit 1 of FIG.
The output voltage detection circuit 8 of FIG. 1 may be changed to the output current detection circuit 12, and the control unit 20 may change the signal input to the gradation number determination unit 21 to the output current detection value and the output current command value.
 次に、主インバータ群3の複数の単相インバータのコンデンサ電圧を検出するインバータ電圧検出回路を設ける例を図9に基づいて説明する。
 図5の主回路部1Aと区別するために、主回路部1Cとしている。また、副インバータ群2C、主インバータ群3Cとしている。
 図9は副インバータ群2が2つの単相インバータ2I1、2I2、主インバータ群3が2つの単相インバータ3I3、3I4で構成された例である。
 単相インバータ3I3に外部電源10S1が接続され、単相インバータ3I4に外部電源10S2が接続されている。
 簡単化のため切換スイッチ4、充電用抵抗5は省略している。
Next, an example of providing an inverter voltage detection circuit for detecting the capacitor voltage of a plurality of single-phase inverters of the main inverter group 3 will be described with reference to FIG.
In order to distinguish it from the main circuit unit 1A in FIG. 5, the main circuit unit 1C is used. Further, the sub-inverter group 2C and the main inverter group 3C are used.
FIG. 9 shows an example in which the sub-inverter group 2 is composed of two single-phase inverters 2I1 and 2I2, and the main inverter group 3 is composed of two single-phase inverters 3I3 and 3I4.
The external power supply 10S1 is connected to the single-phase inverter 3I3, and the external power supply 10S2 is connected to the single-phase inverter 3I4.
For the sake of simplicity, the changeover switch 4 and the charging resistor 5 are omitted.
 各単相インバータ2I1、2I2、3I3、3I4のコンデンサ電圧V1、V2、V3、V4は1:2:4:8で略一定になるように制御する。また、コンデンサ電圧が小さい単相インバータから順に第1単相インバータ、第2単相インバータ、第3単相インバータ、第4単相インバータと記載する。
 本例では、単相インバータ2I1が第1単相インバータに相当し、単相インバータ2I2が第2単相インバータに相当し、単相インバータ3I3が第3単相インバータに相当し、単相インバータ3I4が第4単相インバータに相当する。
The capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 3I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8. Further, the first single-phase inverter, the second single-phase inverter, the third single-phase inverter, and the fourth single-phase inverter will be described in order from the single-phase inverter having the smallest capacitor voltage.
In this example, the single-phase inverter 2I1 corresponds to the first single-phase inverter, the single-phase inverter 2I2 corresponds to the second single-phase inverter, the single-phase inverter 3I3 corresponds to the third single-phase inverter, and the single-phase inverter 3I4. Corresponds to the fourth single-phase inverter.
 図9の構成の主回路部1Cに対して、先に図5から図7で説明した制御方法(選択手順)を適用できる。
 具体的には、副インバータ群2は単相インバータ3台、主インバータ群3は単相インバータが1台のときと同様に、第3単相インバータは外部電源が接続していないとみなして、出力パターンの選択手順を用いて各単相インバータ2I1、2I2、3I3、3I4を制御することができる。この場合は、外部電源10Sの電源容量を低減できる。
The control method (selection procedure) described above with reference to FIGS. 5 to 7 can be applied to the main circuit unit 1C having the configuration shown in FIG.
Specifically, as in the case where the sub-inverter group 2 has three single-phase inverters and the main inverter group 3 has one single-phase inverter, the third single-phase inverter is regarded as not connected to an external power source. Each single-phase inverter 2I1, 2I2, 3I3, 3I4 can be controlled by using the output pattern selection procedure. In this case, the power capacity of the external power supply 10S can be reduced.
 また、第4単相インバータ3I4はコンデンサ電圧一定制御に用いず、階調数が8以上の場合は+出力、7以下の場合は0出力と動作させ、第1から第3単相インバータの合計3台で、先に説明した制御方法(選択手順)でコンデンサ電圧一定制御を行ってもよい。
 この場合は第4単相インバータ3I4のインバータ電圧検出回路7D4と制御部20の単相インバータ1段分が省略できる。
Further, the 4th single-phase inverter 3I4 is not used for constant capacitor voltage control, and is operated as + output when the number of gradations is 8 or more and 0 output when the number of gradations is 7 or less, and the total of the first to third single-phase inverters. The three units may perform constant capacitor voltage control by the control method (selection procedure) described above.
In this case, the inverter voltage detection circuit 7D4 of the fourth single-phase inverter 3I4 and one stage of the single-phase inverter of the control unit 20 can be omitted.
 以上の実施の形態1の説明では、副インバータ群2には外部電源10Sを接続しない構成について説明した。しかし、副インバータ群2のコンデンサ電圧の安定化を図るため副インバータ群2にも外部電源10Sを接続する構成としてもよい。
 この場合においても、本実施の形態を適用することで、従来の階調制御を適用した電力変換装置に比較して、外部電源10Sに必要な電源容量を低減し、装置を小型で安価とすることができる。
In the above description of the first embodiment, the configuration in which the external power supply 10S is not connected to the sub-inverter group 2 has been described. However, in order to stabilize the capacitor voltage of the sub-inverter group 2, the external power supply 10S may also be connected to the sub-inverter group 2.
Even in this case, by applying the present embodiment, the power supply capacity required for the external power supply 10S is reduced as compared with the conventional power conversion device to which the gradation control is applied, and the device is compact and inexpensive. be able to.
 実施の形態1の電力変換装置では、各単相インバータのコンデンサ電圧と各単相インバータのコンデンサ電圧の目標値との比率(比較標準値)を算出し、算出した比較標準値の平均値と比較標準値との比較結果を用いて出力パターンを選択する。これにより、副インバータ群2の各単相インバータの充放電電流は調整され、各単相インバータ(2I1~2Im、3Im+1~3Im+n)の電圧比を略一定に保ちつつ、所望の出力電圧を出力することが可能となる。このため、副インバータ群2への電力供給のための電源を不要にできるため、装置が小型で安価となる。 In the power conversion device of the first embodiment, the ratio (comparative standard value) between the capacitor voltage of each single-phase inverter and the target value of the capacitor voltage of each single-phase inverter is calculated and compared with the average value of the calculated comparative standard values. The output pattern is selected using the comparison result with the standard value. As a result, the charge / discharge current of each single-phase inverter of the sub-inverter group 2 is adjusted, and a desired output voltage is output while keeping the voltage ratio of each single-phase inverter (2I1 to 2Im, 3Im + 1 to 3Im + n) substantially constant. It becomes possible. Therefore, it is possible to eliminate the need for a power source for supplying electric power to the sub-inverter group 2, so that the device is small and inexpensive.
 また、実施の形態1の出力パターン決定部ではコンデンサ電圧の大きなインバータから順に出力符号を選択することで、コンデンサ電圧の大きな単相インバータのコンデンサ電圧変動を抑制し、出力電圧に大きな変動が発生することを抑制できる。 Further, in the output pattern determination unit of the first embodiment, by selecting the output code in order from the inverter having the largest capacitor voltage, the capacitor voltage fluctuation of the single-phase inverter having the largest capacitor voltage is suppressed, and the output voltage fluctuates greatly. Can be suppressed.
 また、出力パターン決定部23では、(A)コンデンサ電圧が大きい単相インバータから出力を決める、(B)ある単相インバータでは、比較標準値が平均値より大きい場合は、+、0、-の順の優先度で出力を選択し、比較標準値が平均値より小さい場合は、-、0、+の順の優先度で出力を選択する、という単純なルールで出力パターンを決定できる。このルールは単相インバータ数が増加した時でも適用できるため、単相インバータ数が増加した時でも任意の出力電圧を出力しつつ、各コンデンサ電圧を略一定に制御することができる。 Further, in the output pattern determination unit 23, (A) the output is determined from the single-phase inverter having a large capacitor voltage, and (B) in a certain single-phase inverter, when the comparison standard value is larger than the average value, +, 0,-. The output pattern can be determined by a simple rule that the output is selected in the order of priority, and if the comparison standard value is smaller than the average value, the output is selected in the order of priority of-, 0, +. Since this rule can be applied even when the number of single-phase inverters increases, it is possible to control each capacitor voltage substantially constantly while outputting an arbitrary output voltage even when the number of single-phase inverters increases.
 実施の形態1では、電力変換装置の全体の構成、動作の説明を分かり易くするために、副インバータ群2、主インバータ群3と分けて説明した。しかし、全体を1つの単相インバータ群として扱い、単相インバータの少なくとも1つは外部電源と接続され、各単相インバータの直流電源電圧の電圧比は一定となるように制御すればよい。 In the first embodiment, in order to make it easier to understand the overall configuration and operation of the power conversion device, the sub-inverter group 2 and the main inverter group 3 have been described separately. However, the whole may be treated as one single-phase inverter group, at least one of the single-phase inverters may be connected to an external power supply, and the voltage ratio of the DC power supply voltage of each single-phase inverter may be controlled to be constant.
 以上説明したように、実施の形態1の電力変換装置は、複数の単相インバータは直流電源が外部から供給される1あるいは複数の単相インバータから成る主インバータ群と、その他の複数の単相インバータから成る副インバータ群と、で構成され、主、副インバータ群の各直流電源の電圧比は略一定で、主インバータ群の直流電源電圧の総和は、副インバータ群の直流電源電圧の総和より所定の比率で大きく設定され、電圧検出手段により検出された複数の単相インバータの直流電源電圧と各直流電源電圧の目標値の比率で除算して比較標準値を算出し、算出した複数の比較標準値の比較処理を行う比較部と、各単相インバータの出力の組合せを決定する出力パターン決定部を備え、比較部は複数の比較標準値のうち少なくとも一部の平均値と各比較標準値とを比較する平均値比較部を備え、出力パターン決定部は比較部の出力結果を用いて副インバータ群の各直流電圧を、各単相インバータを介した充放電により略一定になるように各単相インバータの出力の組合せを選択するものである。
 したがって、実施の形態1の電力変換装置は、インバータ数が増加しても、コンデンサ電圧を一定に保ち、任意の電圧を出力することが可能となる。
As described above, in the power conversion device of the first embodiment, the plurality of single-phase inverters are a main inverter group composed of one or a plurality of single-phase inverters to which DC power is supplied from the outside, and a plurality of other single-phase inverters. It is composed of a sub-inverter group consisting of inverters, and the voltage ratio of each DC power supply of the main and sub-inverter groups is almost constant. A plurality of comparisons calculated by dividing by the ratio of the DC power supply voltage of a plurality of single-phase inverters detected by the voltage detecting means and the target value of each DC power supply voltage to calculate a comparison standard value, which is largely set by a predetermined ratio. A comparison unit that performs standard value comparison processing and an output pattern determination unit that determines the combination of outputs of each single-phase inverter are provided, and the comparison unit includes an average value of at least a part of a plurality of comparison standard values and each comparison standard value. The output pattern determination unit uses the output result of the comparison unit to make each DC voltage of the sub-inverter group substantially constant by charging / discharging via each single-phase inverter. The combination of outputs of the single-phase inverter is selected.
Therefore, the power conversion device of the first embodiment can keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.
実施の形態2.
 実施の形態2の電力変換装置は、比較部として比較標準値と他の比較標準値とを比較する標準値比較部を備えるものである。
Embodiment 2.
The power conversion device of the second embodiment includes a standard value comparison unit that compares a comparison standard value with another comparison standard value as a comparison unit.
 実施の形態2の電力変換装置について、制御部の構成図である図10、制御部の比較部の構成図である図11、および、制御部の比較部の1例の構成図である図12に基づいて、実施の形態1との差異を中心に説明する。なお、適宜実施の形態1の図面を参照する。
 実施の形態2の構成図において、実施の形態1と同一あるいは相当部分は、同一の符号を付している。
Regarding the power conversion device of the second embodiment, FIG. 10 is a configuration diagram of a control unit, FIG. 11 is a configuration diagram of a comparison unit of the control unit, and FIG. 12 is a configuration diagram of an example of the comparison unit of the control unit. The difference from the first embodiment will be mainly described. The drawings of the first embodiment will be referred to as appropriate.
In the configuration diagram of the second embodiment, the same or corresponding parts as those of the first embodiment are designated by the same reference numerals.
 制御部30の構成を図10に基づいて説明する。
 制御部30は階調数決定部21、比較部32、出力パターン決定部33、およびゲート信号生成部24を備える。実施の形態1の制御部20との違いは、比較部32および出力パターン決定部33である。
The configuration of the control unit 30 will be described with reference to FIG.
The control unit 30 includes a gradation number determination unit 21, a comparison unit 32, an output pattern determination unit 33, and a gate signal generation unit 24. The difference from the control unit 20 of the first embodiment is the comparison unit 32 and the output pattern determination unit 33.
 比較部32の構成と動作を図11に基づいて説明する。
 比較部32は、除算器32D、標準値比較部である標準値比較器32SCを備える。図において、OPDは出力パターン決定部である。
The configuration and operation of the comparison unit 32 will be described with reference to FIG.
The comparison unit 32 includes a divider 32D and a standard value comparator 32SC which is a standard value comparison unit. In the figure, the OPD is an output pattern determination unit.
 比較部32ではインバータ電圧検出回路7Dで検出した各単相インバータ2I、3Iのコンデンサ電圧V1~Vm+1が入力される。入力されたコンデンサ電圧V1~Vm+1は除算器32Dによって電圧レベルが揃えられた比較標準値V1*~Vm+1*に規格化される。 In the comparison unit 32, the capacitor voltages V1 to Vm + 1 of each single-phase inverter 2I and 3I detected by the inverter voltage detection circuit 7D are input. The input capacitor voltages V1 to Vm + 1 are standardized by the divider 32D to the comparative standard values V1 * to Vm + 1 * whose voltage levels are aligned.
 比較部32では規格化後の比較標準値V1*~Vm+1*を標準値比較器32SCでそれぞれ比較することで、比較標準値V1*~Vm+1*の大小関係を明らかにし、その結果を出力パターン決定部33に出力する。
 実施の形態2における比較部32は、和演算をしない、すなわち平均演算をしない点で実施の形態1と異なる。インバータ電圧検出回路7Dでm+1個の電圧を検出した場合、全比較標準値の大小関係は(m+1)×m/2個以上の標準値比較器があれば算出できる。
The comparison unit 32 compares the standardized comparison standard values V1 * to Vm + 1 * with the standard value comparator 32SC to clarify the magnitude relationship of the comparison standard values V1 * to Vm + 1 *, and determines the output pattern as a result. Output to unit 33.
The comparison unit 32 in the second embodiment is different from the first embodiment in that the sum calculation is not performed, that is, the averaging calculation is not performed. When m + 1 voltage is detected by the inverter voltage detection circuit 7D, the magnitude relationship of all comparison standard values can be calculated if there are (m + 1) × m / 2 or more standard value comparators.
 実施の形態2の比較部の構成を一般化すると、副インバータ群がY個の単相インバータで構成されている場合、比較部は(Y+1)×Y/2個以上の標準値比較部で構成される。 Generalizing the configuration of the comparison unit of the second embodiment, when the sub-inverter group is composed of Y single-phase inverters, the comparison unit is composed of (Y + 1) × Y / 2 or more standard value comparison units. Will be done.
 出力パターン決定部33の動作について説明する。
 出力パターン決定部33では階調数決定部21で決定した階調数と比較部32から出力される比較結果に基づいて、各単相インバータの出力の組合せ(出力パターン)を決定する。
 制御部30は、出力パターン決定部33が決定した出力パターンおよび階調数に基づいて、各単相インバータ2I、3Iのコンデンサ電圧を略一定に制御する。
The operation of the output pattern determination unit 33 will be described.
The output pattern determination unit 33 determines the combination of outputs (output pattern) of each single-phase inverter based on the number of gradations determined by the gradation number determination unit 21 and the comparison result output from the comparison unit 32.
The control unit 30 controls the capacitor voltages of the single-phase inverters 2I and 3I to be substantially constant based on the output pattern and the number of gradations determined by the output pattern determination unit 33.
 ゲート信号生成部24は出力パターン決定部33の出力結果に基づいて各単相インバータ2I、3Iを動作させるゲート信号を生成する。 The gate signal generation unit 24 generates a gate signal for operating each single-phase inverter 2I and 3I based on the output result of the output pattern determination unit 33.
 出力パターン決定部33は、階調数決定部21から得られる階調数を実現する複数の出力パターンから比較部32の出力結果を用いて出力パターンを決定するが、その際、下記のルールに従い出力パターンを決定する。
(A)比較標準値V1*~Vm+1*の大きい単相インバータから出力を決める。
(B)各単相インバータの出力は、+、0、-の順の優先度で選択する。
The output pattern determination unit 33 determines an output pattern from a plurality of output patterns that realize the number of gradations obtained from the gradation number determination unit 21 by using the output result of the comparison unit 32. At that time, the output pattern is determined according to the following rules. Determine the output pattern.
(A) The output is determined from a single-phase inverter having a large comparison standard value V1 * to Vm + 1 *.
(B) The output of each single-phase inverter is selected in the order of +, 0,-.
 出力パターン決定部33の動作を、実施の形態1の図5に示した例を用いて説明する。
 図5は副インバータ群2が3つの単相インバータ2I1、2I2、2I3、主インバータ群3が1つの単相インバータ3I4で構成された例である。
 各単相インバータ2I1、2I2、2I3、3I4のコンデンサ電圧V1、V2、V3、V4は1:2:4:8で略一定になるように制御する。
The operation of the output pattern determination unit 33 will be described with reference to the example shown in FIG. 5 of the first embodiment.
FIG. 5 shows an example in which the sub-inverter group 2 is composed of three single-phase inverters 2I1, 2I2, 2I3, and the main inverter group 3 is composed of one single-phase inverter 3I4.
The capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 2I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8.
 図5の主回路部1Aに対応する実施の形態2の比較部32の1例を図12に示す。
 ここで、図12では、図11の比較部32と区別するために比較部32Aとしている。
 比較部32Aは、除算器32AD、標準値比較器32ASCを備える。図において、OPDは出力パターン決定部である。
FIG. 12 shows an example of the comparison unit 32 of the second embodiment corresponding to the main circuit unit 1A of FIG.
Here, in FIG. 12, the comparison unit 32A is used to distinguish it from the comparison unit 32 of FIG.
The comparison unit 32A includes a divider 32AD and a standard value comparator 32ASC. In the figure, the OPD is an output pattern determination unit.
 各単相インバータのコンデンサ電圧がV1=0.9V、V2=1.9V、V3=4.1V、V4=8.1V、階調数決定部21の出力が3であった場合を想定する。
 比較部32Aにおいて、除算器32ADで、V1*=0.9V、V2*=0.95V、V3*=1.025V、V4*=1.0125Vが算出される。
 標準値比較器32ASCから比較結果V3*>V4*>V2*>V1*が出力される。
It is assumed that the capacitor voltage of each single-phase inverter is V1 = 0.9V, V2 = 1.9V, V3 = 4.1V, V4 = 8.1V, and the output of the gradation number determination unit 21 is 3.
In the comparison unit 32A, the divider 32AD calculates V1 * = 0.9V, V2 * = 0.95V, V3 * = 1.025V, and V4 * = 1.0125V.
The comparison result V3 *> V4 *> V2 *> V1 * is output from the standard value comparator 32ASC.
 出力パターン決定部33の具体的な動作を説明する。
 階調数3の時の出力パターンは図7に示した通り、パターンA~Eの5パターン存在する。
 出力パターン決定部33では比較標準値が最も大きい第3単相インバータの出力から順に決定していく。出力は+、0、-の順の優先度で選択されるため、第3単相インバータが+出力であるパターンB、Cが選択される。
 次に比較標準値の大きい第4単相インバータの出力が選択される。出力は+、0、-の順の優先度で選択されるが、パターンB、Cの第4単相インバータの出力はともに0であるため、第4単相インバータでは選択することができない。
 次に比較標準値が大きい第2単相インバータを検討する。パターンB、Cの第2単相インバータの出力はパターンBが0、パターンCが-であるため、0出力のパターンBが選択される。
 以上の動作により上記条件ではパターンEが選択され、ゲート信号生成部24に出力される。
The specific operation of the output pattern determination unit 33 will be described.
As shown in FIG. 7, there are five output patterns, patterns A to E, when the number of gradations is 3.
The output pattern determination unit 33 determines in order from the output of the third single-phase inverter having the largest comparison standard value. Since the outputs are selected in the order of priority of +, 0,-, patterns B and C in which the third single-phase inverter has a + output are selected.
Next, the output of the fourth single-phase inverter with the larger comparative standard value is selected. The output is selected in the order of priority of +, 0,-, but since the output of the fourth single-phase inverter of patterns B and C is 0, it cannot be selected by the fourth single-phase inverter.
Next, a second single-phase inverter having a large comparative standard value will be examined. Since the output of the second single-phase inverters of patterns B and C is 0 for pattern B and − for pattern C, pattern B with 0 output is selected.
By the above operation, the pattern E is selected under the above conditions and output to the gate signal generation unit 24.
 なお、ここでは出力パターン決定部33において比較標準値の大きい単相インバータから出力を選択していく例を示したが、比較標準値の大小関係を使って出力パターンを決定すれば、出力の決定順序を変更しても問題ない。
 例えば、比較標準値の小さい単相インバータから出力を選択してもよい。この場合、単相インバータの出力は-、0、+の順の優先度で選択する。
Here, an example is shown in which the output pattern determination unit 33 selects an output from a single-phase inverter having a large comparison standard value, but if the output pattern is determined using the magnitude relationship of the comparison standard value, the output is determined. There is no problem even if you change the order.
For example, the output may be selected from a single-phase inverter having a smaller comparison standard value. In this case, the output of the single-phase inverter is selected in the order of-, 0, +.
 この実施の形態2によれば、各単相インバータのコンデンサ電圧と各単相インバータのコンデンサ電圧の目標値の比率から比較標準値を算出し、算出した比較標準値の比較結果を用いて出力パターンを選択する。これにより、副インバータ群2の各単相インバータの充放電電流は調整され、各単相インバータ2I、3Iの電圧比を略一定に保ちつつ、所望の出力電圧を出力することができる。このため、副インバータ群2への電力供給のための電源を不要にできるため、装置が小型で安価となる。 According to the second embodiment, the comparison standard value is calculated from the ratio of the target value of the capacitor voltage of each single-phase inverter and the capacitor voltage of each single-phase inverter, and the output pattern is used by using the comparison result of the calculated comparison standard value. Select. As a result, the charge / discharge current of each single-phase inverter of the sub-inverter group 2 is adjusted, and a desired output voltage can be output while keeping the voltage ratio of each single-phase inverter 2I and 3I substantially constant. Therefore, it is possible to eliminate the need for a power source for supplying electric power to the sub-inverter group 2, so that the device is small and inexpensive.
 また、実施の形態2の出力パターン決定部では上記比較標準値の大きな単相インバータから順に出力符号を選択していくため、単相インバータのコンデンサ電圧が大きく上昇することを防ぐことができ、電圧上昇によるコンデンサへの悪影響を防ぐことができる。 Further, since the output pattern determination unit of the second embodiment selects the output code in order from the single-phase inverter having the larger comparative standard value, it is possible to prevent the capacitor voltage of the single-phase inverter from increasing significantly, and the voltage. It is possible to prevent the adverse effect on the capacitor due to the rise.
 また、出力パターン決定部33では(A)比較標準値V1*~Vm+1*の大きい単相インバータから出力を決める、(B)各単相インバータの出力は、+、0、-の順の優先度で選択する、という単純なル-ルで出力パターンを決定できる。このルールは、単相インバータ数が増加した時でも適用できるため、単相インバータ数が増加した時でも任意の出力電圧を出力しつつ、各コンデンサ電圧を略一定に制御することができる。 Further, the output pattern determination unit 33 determines the output from the single-phase inverter having the larger comparison standard value V1 * to Vm + 1 *, and (B) the output of each single-phase inverter has priority in the order of +, 0,-. The output pattern can be determined by a simple rule of selecting with. Since this rule can be applied even when the number of single-phase inverters increases, it is possible to control each capacitor voltage substantially constantly while outputting an arbitrary output voltage even when the number of single-phase inverters increases.
 以上説明したように、実施の形態2の電力変換装置は、比較部として比較標準値と他の比較標準値とを比較する標準値比較部を備えるものである。
 したがって、実施の形態2の電力変換装置は、インバータ数が増加しても、コンデンサ電圧を一定に保ち、任意の電圧を出力することが可能となる。
As described above, the power conversion device of the second embodiment includes a standard value comparison unit for comparing a comparison standard value with another comparison standard value as a comparison unit.
Therefore, the power conversion device of the second embodiment can keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.
実施の形態3.
 実施の形態3の電力変換装置は、比較部として複数の比較標準値のうち少なくとも一部の平均値と各比較標準値とを比較する平均値比較部、および各比較標準値と他の比較標準値とを比較する標準値比較部の両方を備えたものである。
Embodiment 3.
The power conversion device of the third embodiment has an average value comparison unit that compares at least a part of the average values of a plurality of comparison standard values with each comparison standard value as a comparison unit, and each comparison standard value and another comparison standard. It is equipped with both standard value comparison units that compare values.
 実施の形態3の電力変換装置について、制御部の構成図である図13、制御部の比較部の構成図である図14、制御部の比較部の変形例の構成図である図15、および制御部の比較部の1例の構成図である図16に基づいて、実施の形態1との差異を中心に説明する。なお、適宜実施の形態1の図面を参照する。
 実施の形態3の構成図において、実施の形態1と同一あるいは相当部分は、同一の符号を付している。
Regarding the power conversion device of the third embodiment, FIG. 13 is a configuration diagram of a control unit, FIG. 14 is a configuration diagram of a comparison unit of the control unit, FIG. 15 is a configuration diagram of a modified example of the comparison unit of the control unit, and The difference from the first embodiment will be mainly described with reference to FIG. 16, which is a configuration diagram of an example of the comparison unit of the control unit. The drawings of the first embodiment will be referred to as appropriate.
In the configuration diagram of the third embodiment, the same or corresponding parts as those of the first embodiment are designated by the same reference numerals.
 制御部40の構成を図13に基づいて説明する。
 制御部40は階調数決定部21、比較部42、出力パターン決定部43、およびゲート信号生成部24を備える。実施の形態1の制御部20との違いは、比較部42および出力パターン決定部43である。
The configuration of the control unit 40 will be described with reference to FIG.
The control unit 40 includes a gradation number determination unit 21, a comparison unit 42, an output pattern determination unit 43, and a gate signal generation unit 24. The difference from the control unit 20 of the first embodiment is the comparison unit 42 and the output pattern determination unit 43.
 比較部42の構成と動作を図14に基づいて説明する。
 比較部42は、除算器42D、平均演算器42H、平均値比較部である平均値比較器42AC、標準値比較部である標準値比較器42SCを備える。図において、OPDは出力パターン決定部である。
The configuration and operation of the comparison unit 42 will be described with reference to FIG.
The comparison unit 42 includes a divider 42D, an average calculator 42H, an average value comparator 42AC which is an average value comparison unit, and a standard value comparator 42SC which is a standard value comparison unit. In the figure, the OPD is an output pattern determination unit.
 比較部42ではインバータ電圧検出回路7Dで検出した各単相インバータ2I、3Iのコンデンサ電圧V1~Vm+1が入力される。入力されたコンデンサ電圧V1~Vm+1は除算器42Dによって電圧レベルが揃えられた比較標準値V1*~Vm+1*に規格化される。 In the comparison unit 42, the capacitor voltages V1 to Vm + 1 of each single-phase inverter 2I and 3I detected by the inverter voltage detection circuit 7D are input. The input capacitor voltages V1 to Vm + 1 are standardized by the divider 42D to the comparative standard values V1 * to Vm + 1 * whose voltage levels are aligned.
 比較部42では規格化後の比較標準値V1*~Vm+1*から平均演算器42Hで平均値Vaveを算出する。平均値Vaveと比較標準値V4*~Vm+1*とを平均値比較器42ACで比較する。また、比較標準値V3*~V1*は、それぞれ標準値比較器42SCで比較され大小関係が明らかにされる。そして、平均値Vaveと比較標準値V4*~Vm+1*との差異、および比較標準値V1*~V*3の大小関係が比較部42の出力となる。
 実施の形態3における比較部42は、平均値を用いた比較と平均値を使用しない比較の両方を用いる点で実施の形態1、2と異なる。
The comparison unit 42 calculates the average value Wave from the standardized comparison standard values V1 * to Vm + 1 * with the average calculator 42H. The average value Wave and the comparison standard values V4 * to Vm + 1 * are compared with the average value comparator 42AC. Further, the comparison standard values V3 * to V1 * are compared by the standard value comparator 42SC, respectively, and the magnitude relationship is clarified. Then, the difference between the average value Wave and the comparison standard values V4 * to Vm + 1 * and the magnitude relationship between the comparison standard values V1 * to V * 3 are the outputs of the comparison unit 42.
The comparison unit 42 in the third embodiment is different from the first and second embodiments in that both the comparison using the average value and the comparison not using the average value are used.
 なお、比較部42は平均値を用いた比較と平均値を使用しない比較の両方を用いればよく、例えば図4で示したように平均値の演算方法を変更してもよい。また、平均値を用いた比較と平均値を使用しない比較の割合を変更してもよい。 Note that the comparison unit 42 may use both a comparison using the average value and a comparison not using the average value, and for example, the calculation method of the average value may be changed as shown in FIG. Further, the ratio of the comparison using the average value and the comparison not using the average value may be changed.
 例えば、比較標準値V3*~Vm+1*までを平均値と比較し、比較標準値V2*とV1*だけを大小比較した場合の例を図15で説明する。
 比較部42Aは、除算器42AD、平均演算器42AH、平均値比較器42AAC、標準値比較器42ASCを備える。図において、OPDは出力パターン決定部である。
For example, FIG. 15 will explain an example in which the comparison standard values V3 * to Vm + 1 * are compared with the average value, and only the comparison standard values V2 * and V1 * are compared in magnitude.
The comparison unit 42A includes a divider 42AD, an average calculator 42AH, an average value comparator 42AAC, and a standard value comparator 42ASC. In the figure, the OPD is an output pattern determination unit.
 平均演算器42AHで算出された平均値Vaveと比較標準値V3*~Vm+1*とを平均値比較器42AACで比較する。また、比較標準値V1*~V2*が標準値比較器42ASCで比較され、その大小関係が明らかにされる。そして、平均値Vaveと比較標準値V3*~Vm+1*との差異、および比較標準値V1*~V*2の大小関係が比較部42Aの出力となる。 The average value Wave calculated by the average calculator 42AH and the comparison standard values V3 * to Vm + 1 * are compared by the average value comparator 42AAC. Further, the comparison standard values V1 * to V2 * are compared by the standard value comparator 42ASC, and the magnitude relationship thereof is clarified. Then, the difference between the average value Wave and the comparative standard values V3 * to Vm + 1 * and the magnitude relationship between the comparative standard values V1 * to V * 2 are the outputs of the comparison unit 42A.
 実施の形態3の比較部の構成を一般化すると、副インバータ群がY個の単相インバータで構成されている場合、Xは(0<X<Y)の条件で、比較部は(X+1)×X/2個以上の平均値比較部とY-X個以上の標準値比較部を含む。 Generalizing the configuration of the comparison unit of the third embodiment, when the sub-inverter group is composed of Y single-phase inverters, X is a condition of (0 <X <Y), and the comparison unit is (X + 1). Includes × X / 2 or more average value comparison units and YX / 2 or more standard value comparison units.
 出力パターン決定部43の動作について説明する。
 実施の形態3における出力パターン決定部43は階調数決定部21から得られる階調数を実現する出力パターンの中から比較部42の出力結果を用いて使用する出力パターンを決定する。実施の形態3における出力パターン決定部43は下記のルールに従い出力パターンを決定する。
(A)平均値を用いた比較結果、平均値を使用しない比較結果の順で出力を選択する。
(B)平均値を用いた比較結果を使用時は以下のルールに従う(実施の形態1と同じ)。
(b1)コンデンサ電圧が大きい単相インバータから出力を決める。
(b2)ある単相インバータでは、比較標準値が平均値より大きい場合は、+、0、-の順の優先度で出力を選択し、比較標準値が平均値より小さい場合は、-、0、+の順の優先度で出力を選択する。
The operation of the output pattern determination unit 43 will be described.
The output pattern determination unit 43 in the third embodiment determines an output pattern to be used by using the output result of the comparison unit 42 from the output patterns that realize the number of gradations obtained from the gradation number determination unit 21. The output pattern determination unit 43 in the third embodiment determines the output pattern according to the following rules.
(A) Select the output in the order of the comparison result using the average value and the comparison result not using the average value.
(B) When using the comparison result using the average value, follow the following rules (same as the first embodiment).
(B1) Determine the output from a single-phase inverter with a large capacitor voltage.
(B2) In a single-phase inverter, if the comparison standard value is larger than the average value, the output is selected in the order of +, 0,-, and if the comparison standard value is smaller than the average value,-, 0. Select the output in the order of priority, +.
(C)平均値を使用しない比較結果は以下のルールに従う(実施の形態2と同じ)。
(c1)比較標準値V1*~Vm+1*の大きい単相インバータから出力を決める。
(c2)各単相インバータの出力は、+、0、-の順の優先度で選択する。
(C) The comparison result without using the average value follows the following rule (same as the second embodiment).
(C1) The output is determined from a single-phase inverter having a large comparison standard value V1 * to Vm + 1 *.
(C2) The output of each single-phase inverter is selected in the order of priority of +, 0,-.
 出力パターン決定部43の動作を実施の形態1の図5に示した例を用いて説明する。
 図5は副インバータ群2が3つの単相インバータ2I1、2I2、2I3、主インバータ群3が1つの単相インバータ3I4で構成された例である。
 各単相インバータ2I1、2I2、2I3、3I4のコンデンサ電圧V1、V2、V3、V4は1:2:4:8で略一定になるように制御する。
The operation of the output pattern determination unit 43 will be described with reference to the example shown in FIG. 5 of the first embodiment.
FIG. 5 shows an example in which the sub-inverter group 2 is composed of three single-phase inverters 2I1, 2I2, 2I3, and the main inverter group 3 is composed of one single-phase inverter 3I4.
The capacitor voltages V1, V2, V3, and V4 of the single-phase inverters 2I1, 2I2, 2I3, and 3I4 are controlled to be substantially constant at 1: 2: 4: 8.
 図5の主回路部1Aに対応する実施の形態3の比較部42の1例を図16に示す。
 ここで、図16では、図14の比較部42と区別するために比較部42Bとしている。
 比較部42Bは、除算器42BD、平均演算器42BH、平均値比較器42BAC、標準値比較器42BSCを備える。図において、OPDは出力パターン決定部である。
FIG. 16 shows an example of the comparison unit 42 of the third embodiment corresponding to the main circuit unit 1A of FIG.
Here, in FIG. 16, the comparison unit 42B is used to distinguish it from the comparison unit 42 in FIG.
The comparison unit 42B includes a divider 42BD, an average calculator 42BH, an average value comparator 42BAC, and a standard value comparator 42BSC. In the figure, the OPD is an output pattern determination unit.
 各単相インバータのコンデンサ電圧がV1=0.9V、V2=1.9V、V3=4.1V、V4=8.1V、階調数決定部21の出力が3であった場合を想定する。
 比較部42Bにおいて、除算器42BDでV1*=0.9V、V2*=0.95V、V3*=1.025V、V4*=1.0125Vが算出される。平均演算器42BHでVave≒0.972が算出される。また、平均値比較器42BACからV4*>Vaveが、標準値比較器42BSCからV3*>V2*>V1*が出力される。
It is assumed that the capacitor voltage of each single-phase inverter is V1 = 0.9V, V2 = 1.9V, V3 = 4.1V, V4 = 8.1V, and the output of the gradation number determination unit 21 is 3.
In the comparison unit 42B, V1 * = 0.9V, V2 * = 0.95V, V3 * = 1.025V, and V4 * = 1.0125V are calculated by the divider 42BD. Wave ≈ 0.972 is calculated by the average calculator 42BH. Further, V4 *> Wave is output from the average value comparator 42BAC, and V3 *> V2 *> V1 * is output from the standard value comparator 42BSC.
 出力パターン決定部43の具体的動作を説明する。
 階調数3の時の出力パターンは図7に示した通り、パターンA~Eの5パターン存在する。
 出力パターン決定部43では、始めに平均値を用いた比較結果に基づいて出力パターンを選択していく。
 今回の例では平均値を用いた比較を行っているのは第4単相インバータだけであり、また、第4単相インバータの比較標準値は平均値より大きい(V4*>Vave)ため、+、0、-の順の優先度で出力を選択する。
 この結果、パターンA~Eの5パターンの内、第4単相インバータの出力が+であるパターンD、Eが選択される。
The specific operation of the output pattern determination unit 43 will be described.
As shown in FIG. 7, there are five output patterns, patterns A to E, when the number of gradations is 3.
The output pattern determination unit 43 first selects an output pattern based on the comparison result using the average value.
In this example, only the 4th single-phase inverter is compared using the average value, and the comparison standard value of the 4th single-phase inverter is larger than the average value (V4 *> Wave), so + Select the output in the order of priority, 0,-.
As a result, among the five patterns A to E, the patterns D and E in which the output of the fourth single-phase inverter is + are selected.
 平均値を用いた比較を行っている単相インバータは第4単相インバータのみであるため、次に平均値を使用しない比較結果を基に出力パターンを決定していく。
 V3*>V2*>V1*であるため、最も比較標準値が大きい第3単相インバータの出力から順に決定していく。
 出力は+、0、-の順の優先度で選択されるが、パターンD、Eは第3単相インバータが共に-出力であるため選択することができない。
 次に比較標準値が大きい第2単相インバータを検討する。
 パターンD、Eの第2単相インバータの出力はパターンDが0、パターンEが-であるため、0出力のパターンDが選択される。
 以上の動作により上記条件ではパターンDが選択され、ゲート信号生成部24に出力される。
Since the only single-phase inverter that makes comparisons using the average value is the fourth single-phase inverter, the output pattern is then determined based on the comparison results that do not use the average value.
Since V3 *> V2 *> V1 *, the output of the third single-phase inverter having the largest comparative standard value is determined in order.
The output is selected in the order of priority of +, 0, and-, but patterns D and E cannot be selected because the third single-phase inverter is both-output.
Next, a second single-phase inverter having a large comparative standard value will be examined.
Since the output of the second single-phase inverters of patterns D and E is 0 for pattern D and − for pattern E, pattern D with 0 output is selected.
By the above operation, the pattern D is selected under the above conditions and output to the gate signal generation unit 24.
 なお、ここでは平均値を用いた比較結果、平均値を使用しない比較結果の順で出力を決定する例を示したが、平均値を使用しない比較結果、平均値を用いた比較結果の順で出力を選択してもよい。
 また、コンデンサ電圧の大きな単相インバータに平均値を使用しない比較を用いて、コンデンサ電圧の小さな単相インバータに平均値を用いた比較を用いてもよい。
 ただし、コンデンサ電圧が小さい単相インバータの方が充電電流により電圧上昇が発生し易いため、コンデンサ電圧が小さい単相インバータには電圧上昇抑制が可能な平均値を使用しない比較結果を用いる方が望ましい。
Here, an example is shown in which the output is determined in the order of the comparison result using the average value and the comparison result not using the average value, but the comparison result not using the average value and the comparison result using the average value are used in this order. You may select the output.
Further, a comparison using an average value for a single-phase inverter having a large capacitor voltage may be used, and a comparison using an average value may be used for a single-phase inverter having a small capacitor voltage.
However, since a single-phase inverter with a small capacitor voltage is more likely to cause a voltage rise due to the charging current, it is desirable to use a comparison result that does not use an average value that can suppress the voltage rise for a single-phase inverter with a small capacitor voltage. ..
 この実施の形態3によれば、各単相インバータのコンデンサ電圧と各単相インバータのコンデンサ電圧の目標値の比率から比較標準値を算出し、算出した比較標準値の平均値を用いた比較と算出した比較標準値間の比較結果を用いて出力パターンを選択する。
 これにより、副インバータ群2の各単相インバータの充放電電流は調整され、各単相インバータ2I、3Iの電圧比を略一定に保ちつつ、所望の出力電圧を出力することができる。これにより、副インバータ群2への電力供給のための電源を不要にできるため、装置が小型で安価となる。
According to the third embodiment, the comparison standard value is calculated from the ratio of the target value of the capacitor voltage of each single-phase inverter and the capacitor voltage of each single-phase inverter, and the comparison using the average value of the calculated comparison standard values is performed. The output pattern is selected using the comparison result between the calculated comparison standard values.
As a result, the charge / discharge current of each single-phase inverter of the sub-inverter group 2 is adjusted, and a desired output voltage can be output while keeping the voltage ratio of each single-phase inverter 2I and 3I substantially constant. As a result, it is possible to eliminate the need for a power source for supplying electric power to the sub-inverter group 2, so that the device is compact and inexpensive.
 また、実施の形態3の出力パターン決定部では平均値を用いた比較を行う単相インバータの出力が目標値から変動しないようにしつつ、単相インバータのコンデンサ電圧が大きく上昇することを防ぐことができる。このため、単相インバータのコンデンサ電圧の大きな変動を防止しつつ、電圧上昇によるコンデンサへの悪影響を防止することができる。 Further, in the output pattern determination unit of the third embodiment, it is possible to prevent the capacitor voltage of the single-phase inverter from rising significantly while preventing the output of the single-phase inverter for comparison using the average value from fluctuating from the target value. it can. Therefore, it is possible to prevent a large fluctuation in the capacitor voltage of the single-phase inverter and prevent an adverse effect on the capacitor due to the voltage rise.
 また、出力パターン決定部43は単純なルールで出力パターンを決定できる。このルールは、単相インバータ数が増加した時でも適用できるため、単相インバータ数が増加した時でも任意の出力電圧を出力しつつ、各コンデンサ電圧を略一定に制御することができる。 Further, the output pattern determination unit 43 can determine the output pattern by a simple rule. Since this rule can be applied even when the number of single-phase inverters increases, it is possible to control each capacitor voltage substantially constantly while outputting an arbitrary output voltage even when the number of single-phase inverters increases.
 以上説明したように、実施の形態3の電力変換装置は、比較部として複数の比較標準値のうち少なくとも一部の平均値と各比較標準値とを比較する平均値比較部、および各比較標準値と他の比較標準値とを比較する標準値比較部の両方を備えたものである。
 したがって、実施の形態3の電力変換装置は、インバータ数が増加しても、コンデンサ電圧を一定に保ち、任意の電圧を出力することが可能となる。
As described above, in the power conversion device of the third embodiment, as a comparison unit, an average value comparison unit that compares at least a part of the average values of the plurality of comparison standard values with each comparison standard value, and each comparison standard. It is equipped with both a standard value comparison unit that compares a value with other comparison standard values.
Therefore, the power conversion device of the third embodiment can keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.
 本願は、様々な例示的な実施の形態及び実施例が記載されているが、1つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるものではなく、単独で、または様々な組合せで実施の形態に適用可能である。
 従って、例示されていない無数の変形例が、本願に開示される技術の範囲内において想定される。例えば、少なくとも1つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも1つの構成要素を抽出し、他の実施の形態の構成要素と組合せる場合が含まれるものとする。
Although the present application describes various exemplary embodiments and examples, the various features, embodiments, and functions described in one or more embodiments are applications of a particular embodiment. It is not limited to the above, and can be applied to the embodiment alone or in various combinations.
Therefore, innumerable variations not illustrated are envisioned within the scope of the techniques disclosed in the present application. For example, it is assumed that at least one component is modified, added or omitted, and further, at least one component is extracted and combined with the components of other embodiments. ..
 本願は、インバータ数が増加しても、コンデンサ電圧を一定に保ち、任意の電圧を出力することが可能となるため、電力変換装置に広く適用できる。 This application can be widely applied to power conversion devices because it is possible to keep the capacitor voltage constant and output an arbitrary voltage even if the number of inverters increases.
1,1A,1B,1C 主回路部、2,2A,2C 副インバータ群、2I1,2I2,2I3,2Im,3I3,3I4,3Im+1,3Im+n 単相インバータ、3,3A,3C 主インバータ群、4 切換スイッチ、5 充電用抵抗、6 出力フィルタ、7D1,7D2,7D3,7D4,7Dm,7Dm+1 インバータ電圧検出回路、8 出力電圧検出回路、10S1,10S2,10Sn 外部電源、11 負荷、12 出力電流検出回路、20 制御部、21 階調数決定部、22,22A,22B,32,32A,42,42A,42B 比較部、23,33,43 出力パターン決定部、24 ゲート信号生成部、22D,22AD,22BD,32D,32AD,42D,42AD,42BD 除算器、22H,22AH,22BH,42H,42AH,42BH 平均演算器、22AC,22AAC,22BAC,42AC,42AAC,42BAC 平均値比較器、32SC,32ASC,42SC,42ASC,42BSC 標準値比較器、g11,g12,g21,g22 半導体スイッチング素子。 1,1A, 1B, 1C main circuit section, 2,2A, 2C sub-inverter group, 2I1,2I2,2I3,2Im, 3I3,3I4,3Im + 1,3Im + n single-phase inverter, 3,3A, 3C main inverter group, 4 switching Switch, 5 Charging resistor, 6 Output filter, 7D1, 7D2, 7D3, 7D4, 7Dm, 7Dm + 1 Inverter voltage detection circuit, 8 Output voltage detection circuit, 10S1,10S2, 10Sn External power supply, 11 Load, 12 Output current detection circuit, 20 Control unit, 21 Gradation number determination unit, 22, 22A, 22B, 32, 32A, 42, 42A, 42B Comparison unit, 23, 33, 43 Output pattern determination unit, 24 Gate signal generation unit, 22D, 22AD, 22BD , 32D, 32AD, 42D, 42AD, 42BD Divider, 22H, 22AH, 22BH, 42H, 42AH, 42BH Average calculator, 22AC, 22AAC, 22BAC, 42AC, 42AAC, 42BAC Average value comparator, 32SC, 32ASC, 42SC, 42ASC, 42BSC standard value comparator, g11, g12, g21, g22 semiconductor switching element.

Claims (8)

  1. 直流電源の直流電力を交流電力に変換する単相インバータの交流側を複数直列接続し、複数の前記単相インバータの中から選択された1以上の前記単相インバータの発生電圧の総和により全体出力電圧を制御して負荷に電力供給する電力変換装置において、
    前記複数の単相インバータの各々は直流電源電圧を発生する蓄電素子を含み、前記複数の単相インバータの少なくとも1つは外部電源と接続され、各前記単相インバータの前記直流電源電圧の目標値の比率は一定であり、
    前記複数の単相インバータの前記直流電源電圧を検出する電圧検出手段と、
    前記電圧検出手段により検出された前記複数の単相インバータの前記直流電源電圧と各前記直流電源電圧の前記目標値の比率で除算して比較標準値を算出し、算出した複数の前記比較標準値の比較処理を行う比較部と、
    前記比較部による比較結果および予め定められた選択条件に基づいて、前記複数の単相インバータのうち、電圧を出力すべき1以上の前記単相インバータの組合せである出力パターンを決定する出力パターン決定部を備え、
    前記比較部は、前記比較処理として複数の前記比較標準値のうち少なくとも一部の平均値と各前記比較標準値とを比較する平均値比較部、および前記比較処理として各前記比較標準値と他の前記比較標準値とを比較する標準値比較部の少なくとも一方を含む電力変換装置。
    Multiple AC sides of a single-phase inverter that converts DC power of a DC power supply to AC power are connected in series, and the total output is calculated by summing the generated voltages of one or more of the single-phase inverters selected from the plurality of single-phase inverters. In a power converter that controls voltage and supplies power to a load
    Each of the plurality of single-phase inverters includes a power storage element that generates a DC power supply voltage, and at least one of the plurality of single-phase inverters is connected to an external power supply, and a target value of the DC power supply voltage of each of the single-phase inverters is provided. The ratio of
    A voltage detecting means for detecting the DC power supply voltage of the plurality of single-phase inverters, and
    A comparative standard value is calculated by dividing by the ratio of the DC power supply voltage of the plurality of single-phase inverters detected by the voltage detecting means to the target value of each of the DC power supply voltages, and the calculated comparative standard values are obtained. And the comparison part that performs the comparison processing of
    Output pattern determination that determines an output pattern that is a combination of one or more of the single-phase inverters for which a voltage should be output among the plurality of single-phase inverters based on the comparison result by the comparison unit and predetermined selection conditions. With a part
    The comparison unit is an average value comparison unit that compares at least a part of the average values of the plurality of comparison standard values with each of the comparison standard values as the comparison process, and each of the comparison standard values and others as the comparison process. A power conversion device including at least one of the standard value comparison units for comparing with the comparison standard value of the above.
  2. 前記複数の単相インバータは、前記直流電源が外部から供給される1あるいは複数の前記単相インバータから成る第1のインバータ群と、前記第1のインバータ群以外の複数の前記単相インバータから成る第2のインバータ群とで構成され、
    前記第2のインバータ群がY個の前記単相インバータで構成されている場合、前記比較部はY個以上の前記平均値比較部を含む請求項1に記載の電力変換装置。
    The plurality of single-phase inverters include a first inverter group including one or a plurality of the single-phase inverters to which the DC power supply is supplied from the outside, and a plurality of the single-phase inverters other than the first inverter group. Consists of a second group of inverters
    The power conversion device according to claim 1, wherein when the second inverter group is composed of Y single-phase inverters, the comparison unit includes Y or more average value comparison units.
  3. 各前記単相インバータは、前記直流電源電圧により+、0、-の電圧を出力可能に構成され、
    前記選択条件は、「前記直流電源電圧が大きい前記単相インバータから出力を決める」、「前記比較標準値が平均値より大きい場合は+、0、-の順の優先度で出力を選択し、前記比較標準値が平均値より小さい場合は-、0、+の順の優先度で出力を選択する」を含む、請求項2に記載の電力変換装置。
    Each of the single-phase inverters is configured to be able to output +, 0, and-voltages by the DC power supply voltage.
    The selection conditions are "determine the output from the single-phase inverter having a large DC power supply voltage" and "select the output in the order of +, 0,-if the comparative standard value is larger than the average value". The power conversion device according to claim 2, further comprising "selecting the output in the order of priority of-, 0, + when the comparative standard value is smaller than the average value".
  4. 前記複数の単相インバータは、前記直流電源が外部から供給される1あるいは複数の前記単相インバータから成る第1のインバータ群と、前記第1のインバータ群以外の複数の前記単相インバータから成る第2のインバータ群とで構成され、
    前記第2のインバータ群がY個の前記単相インバータで構成されている場合、前記比較部は(Y+1)×Y/2個以上の前記標準値比較部で構成される請求項1に記載の電力変換装置。
    The plurality of single-phase inverters include a first inverter group including one or a plurality of the single-phase inverters to which the DC power supply is supplied from the outside, and a plurality of the single-phase inverters other than the first inverter group. Consists of a second group of inverters
    The first aspect of claim 1, wherein when the second inverter group is composed of Y single-phase inverters, the comparison unit is composed of (Y + 1) × Y / 2 or more standard value comparison units. Power converter.
  5. 各前記単相インバータは、前記直流電源電圧により+、0、-の電圧を出力可能に構成され、
    前記選択条件は、「前記比較標準値が大きい前記単相インバータから出力を決める」、「各前記単相インバータの出力は、+、0、-の順の優先度で選択する」を含む、請求項4に記載の電力変換装置。
    Each of the single-phase inverters is configured to be able to output +, 0, and-voltages by the DC power supply voltage.
    The selection condition includes "determining the output from the single-phase inverter having the larger comparative standard value" and "selecting the output of each of the single-phase inverters in the order of priority of +, 0,-". Item 4. The power conversion device according to item 4.
  6. 前記複数の単相インバータは、前記直流電源が外部から供給される1あるいは複数の前記単相インバータから成る第1のインバータ群と、前記第1のインバータ群以外の複数の前記単相インバータから成る第2のインバータ群とで構成され、
    前記第2のインバータ群はY個の前記単相インバータで構成されている場合、Xは(0<X<Y)の条件で、前記比較部は(X+1)×X/2個以上の前記標準値比較部とY-X個以上の前記平均値比較部を含む請求項1に記載の電力変換装置。
    The plurality of single-phase inverters include a first inverter group including one or a plurality of the single-phase inverters to which the DC power supply is supplied from the outside, and a plurality of the single-phase inverters other than the first inverter group. Consists of a second group of inverters
    When the second inverter group is composed of Y single-phase inverters, X is a condition of (0 <X <Y), and the comparison unit is (X + 1) × X / 2 or more of the standard. The power conversion device according to claim 1, further comprising a value comparison unit and YX or more of the average value comparison units.
  7. 各前記単相インバータは、前記直流電源電圧により+、0、-の電圧を出力可能に構成され、
    前記選択条件は、前記平均値比較部を用いる場合、「前記直流電源電圧が大きい前記単相インバータから出力を決める」、「前記比較標準値が前記平均値より大きい場合は+、0、-の順の優先度で出力を選択し、前記比較標準値が平均値より小さい場合は-、0、+の順の優先度で出力を選択する」を含み、
    前記標準値比較部を用いる場合、「前記比較標準値が大きい前記単相インバータから出力を決める」、「各前記単相インバータの出力は、+、0、-の順の優先度で選択する」を含む、請求項6に記載の電力変換装置。
    Each of the single-phase inverters is configured to be able to output +, 0, and-voltages by the DC power supply voltage.
    When the average value comparison unit is used, the selection conditions are "determine the output from the single-phase inverter having a large DC power supply voltage" and "+, 0,-when the comparison standard value is larger than the average value". "Select the output in the order of priority, and if the comparison standard value is smaller than the average value, select the output in the order of-, 0, +".
    When the standard value comparison unit is used, "the output is determined from the single-phase inverter having the larger comparison standard value" and "the output of each of the single-phase inverters is selected in the order of priority of +, 0,-". 6. The power conversion device according to claim 6.
  8. 前記第2のインバータ群の少なくとも1つの前記直流電源が外部から供給される、請求項2から請求項7のいずれか1項に記載の電力変換装置。 The power conversion device according to any one of claims 2 to 7, wherein at least one DC power source of the second inverter group is supplied from the outside.
PCT/JP2019/045247 2019-11-19 2019-11-19 Power conversion device WO2021100116A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006238616A (en) * 2005-02-25 2006-09-07 Mitsubishi Electric Corp Power converter
WO2010086929A1 (en) * 2009-01-29 2010-08-05 三菱電機株式会社 Power conversion device
JP2012522477A (en) * 2009-03-27 2012-09-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Power supply, method and computer program for supplying power to a load

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006238616A (en) * 2005-02-25 2006-09-07 Mitsubishi Electric Corp Power converter
WO2010086929A1 (en) * 2009-01-29 2010-08-05 三菱電機株式会社 Power conversion device
JP2012522477A (en) * 2009-03-27 2012-09-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Power supply, method and computer program for supplying power to a load

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