WO2021091616A1

WO2021091616A1 - Dual 3-phase harmonic rejection transceiver

Info

Publication number: WO2021091616A1
Application number: PCT/US2020/050691
Authority: WO
Inventors: Hong Jiang; Wael Al-Qaq; Jamil Mark FORRESTER
Original assignee: Futurewei Technologies, Inc.
Priority date: 2020-05-30
Filing date: 2020-09-14
Publication date: 2021-05-14
Also published as: CN115769488A

Abstract

Architectures are presented for dual 3-phase transmitters and receivers that can achieve similar harmonics performance as N-phase systems having a higher N value, while using a lower VCO frequency. A first 3-phase clock signal is generated, along with a second, shifted 3-phase clock signal. The components of the first of these clock signals are each mixed with the component of a 3-phase input signal of the same phase, with the resultant three signals mixed to form a first intermediate signal. The components of the second 3-phase clock signals are each mixed with the inverse component of three 3-phase input signal of the same phase, with the three signals mixed to form a second intermediate signal. The intermediate signals can be individually amplified and combined to provide the output. In a differential embodiment, a n-side output can similarly be generated by switching the roles of the 3-phase input and its inverses.

Description

DUAL 3-PHASE HARMONIC REJECTION TRANSCEIVER

[0001] This application claims priority to U.S. Provisional Patent Application No. 63/032,591 , entitled, “DUAL 3-PHASE HARMONIC REJECTION TRANSCEIVER,” filed May 30, 2020 by Jiang et al. , which is incorporated by reference in its entirety.

FIELD

[0002] This disclosure generally relates to architectures for reducing unwanted harmonic content in transceivers.

BACKGROUND

[0003] In a wireless terminal, such as a cellular phone, it is common to have the undesired local oscillator clock generated harmonic signals (harmonics) that may interfere with signal processing. On the transmitter side, these harmonics can be mixed back to near to the carrier frequency of the desired signal through non-linearity and create near channel distortion and may impact other wireless terminals nearby using carrier frequencies that are the same or close to the same. On the receiver side, a blocker signal that is near the desired signal’s clock harmonics’ frequency can, when mixed back to baseband frequency, fall on top of the desired signal frequency through the down-conversion process to degrade the signal-to-noise and distortion ratio for the received signal. It is desirable to reduce the impact of these clock harmonics as much as possible. SUMMARY

[0004] According to one aspect of the present disclosure, a transmitter having a 3- phase signal source is configured to provide three input signals forming a 3-phase input signal and an inverse input signal for each of the three input signals, and to include a frequency synthesizer, and a harmonic rejection mixer. The frequency synthesizer is configured to generate a first 3-phase clock signal having three clock signals, each of the three clock signals having a phase corresponding to one of the input signals of the 3-phase input signal, and to generate a second 3-phase clock signal having three clock signals, each of the three clock signals having a phase corresponding to one of the inverse input signals of the 3-phase input signal. The harmonic rejection mixer includes: a first set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal with the one of the input signals of the corresponding phase; and a second set of three mixers, each configured to receive and mix one of the clock signals of the second 3-phase clock signal with the one of the inverse input signals of the corresponding phase. The harmonic rejection mixer is further configured to: form a first intermediate signal by combining an output of the first set of three mixers, form a second intermediate signal by combining an output of the second set of three mixers, and combine the first and second intermediate signals to form a first output signal for the harmonic rejection mixer.

[0005] Optionally, in the preceding aspect, the transmitter also includes a first variable gain amplifier and a second variable gain amplifier. The first variable gain amplifier is configured to: receive the first intermediate signal; and amplify the first intermediate signal prior to combining the first and second intermediate signals to form the first output signal for the harmonic rejection mixer. The second variable gain amplifier is configured to: receive the second intermediate signal; and amplify the second intermediate signal prior to combining the first and second intermediate signals to form the first output signal for the harmonic rejection mixer.

[0006] Optionally, in any of the preceding aspects, the harmonic rejection mixer further comprises a second mixing section, including: a third set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal with the inverse input signal of the one of the input signals of the corresponding phase; and a fourth set of three mixers, each configured to receive and mix one of the clock signals of the second 3-phase clock signal with the input signal of which the one of the inverse input signals of the corresponding phase is the inverse. The harmonic rejection mixer is configured to: form a third intermediate signal by combining an output of the third set of three mixers, form a fourth intermediate signal by combining an output of the fourth set of three mixers, and combine the third and fourth intermediate signals to form a second output signal for the harmonic rejection mixer.

[0007] Optionally, in the preceding aspect, the transmitter also includes an inductive coupler, comprising: a first coil configured to receive the first output signal for the harmonic rejection mixer at a first terminal and the second output signal for the harmonic rejection mixer at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single ended output for the transmitter and a second terminal connected to ground.

[0008] Optionally, in the preceding aspect, the transmitter also includes a power amplifier configured to receive and amplify the single ended output.

[0009] Optionally, in the preceding aspect, the transmitter also includes an antenna configured to receive and transmit the single ended output.

[0010] Optionally, in any of the preceding aspects, the 3-phase signal source is configured to receive an input signal in in-phase/quadrature format and generate therefrom the three input signals forming an 3-phase input signal and the inverse input signal for each signal of the three input signals.

[0011] Optionally, in any of the preceding aspects, the frequency synthesizer comprises: a voltage controlled oscillator configured to generate an oscillator signal; a first 3-phase generator configured to generate the first 3-phase clock signal from the oscillator signal; a delay circuit configured to receive and delay the oscillator signal; and a second 3-phase generator connected to the delay circuit and configured to generate the second 3-phase clock signal from the delayed oscillator signal. [0012] Optionally, in the preceding aspect, the frequency synthesizer includes a phase locked loop including the voltage controlled oscillator.

[0013] Optionally, in any of the preceding two aspects, the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

[0014] Optionally, in the preceding aspect, the delay circuit introduces 90° phase shift into the oscillator signal.

[0015] Optionally, in any of the preceding two aspects, the frequency synthesizer is configured to generate the 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.

[0016] According to another aspect of the present disclosure, there is provided a method of transmitting a signal includes: receiving three input signals forming a 3- phase input signal and an inverse input signal for each signal of the three input signals; receiving a first 3-phase clock signal having three clock signals and a second 3-phase clock signal having three clock signals, each of the three clock signals of the first 3- phase clock signal having a phase corresponding to one of the input signals of the 3- phase input signal and each of the three clock signals of the second 3-phase clock signal having a phase corresponding to one of the inverse input signals of the 3-phase input signal; and generating a first output signal from three input signals forming a 3- phase input signal and an inverse input signal for each signal of the three input signals and from the first 3-phase clock signal and the second 3-phase clock signal. The first output signal is generated by: for each of the three clock signals of the first 3-phase clock signal, mixing the clock signal with the input signal of the corresponding phase; combining the mixed clocked signals and input signals for the three clock signals of the first 3-phase clock signal to form a first intermediate signal; for each of the three clock signals of the second 3-phase clock signal, mixing the clock signal with the inverse input signal of the corresponding phase; combining the mixed clocked signals and inverse input signals for the three clock signals of the second 3-phase clock signal to form a second intermediate signal; and combining the first intermediate signal and the second intermediate signal to generate the first output signal. [0017] Optionally, in the preceding aspect, the method also includes individually amplifying the first intermediate signal and the second intermediate signal prior to combining the first intermediate signal and the second intermediate signal to generate the first output signal.

[0018] Optionally, in any of the two preceding aspects, the method further includes: generating a second output signal from three input signals forming a 3-phase input signal and an inverse input signal for each signal of the three input signals and from the first 3-phase clock signal and the second 3-phase clock signal, by: for each of the three clock signals of the first 3-phase clock signal, mixing the clock signal with the inverse input signal of the corresponding phase; combining the mixed clocked signals and inverse input signals for the three clock signals of the first 3-phase clock signal to form a third intermediate signal; for each of the three clock signals of the second 3- phase clock signal, mixing the clock signal with the input signal of which the one of the inverse input signals of the corresponding phase is the inverse; combining the mixed clocked signals and input signals for the three clock signals of the second 3-phase clock signal to form a fourth intermediate signal; and combining the third intermediate signal and the fourth intermediate signal to generate the first output signal.

[0019] Optionally, in the preceding aspect, the method further comprises: applying the first output signal and the second output signal to a first terminal and a second terminal, respectively, of a first coil of an inductive coupler; receiving and amplifying an output from a second coil of the inductive coupler that is inductively coupled to the first coil; and transmitting the amplified output.

[0020] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises: receiving an input signal in in-phase/quadrature format; and generating the three input signals forming a 3-phase input signal and the inverse input signal for each signal of the three input signals from the input signal.

[0021] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises: generating an oscillator signal by a voltage controlled oscillator; generating the first 3-phase clock signal from the oscillator signal; delaying the oscillator signal; and generating the second 3-phase clock signal from the delayed oscillator signal.

[0022] Optionally, in the preceding aspect, the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

[0023] Optionally, in the preceding aspect, delaying the oscillator signal includes introducing a 90° phase shift into the oscillator signal.

[0024] Optionally, in any of the preceding three aspects, the method also includes: generating the first 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3; and generating the second 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.

[0025] According to an additional aspect of the present disclosure, a receiver includes: a frequency synthesizer configured to generate a first 3-phase clock signal having three clock signals and to generate a second 3-phase clock signal having three clock signals, the three clock signals of the second 3-phase clock including a clock signal with a 180° phase shift from one of the three clock signals of the first 3-phase clock signal; and a harmonic rejection mixer. The harmonic rejection mixer includes a first mixing section that includes: a first set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal and an input signal to generate one of three signals of a 3-phase first output signal; and a second set of three mixers, each configured to receive and mix one of the clock signals of the second 3- phase clock signal and the input signal to generate one of three signals of a 3-phase second output signal, each of the signals of the second output signal being an inversion of a corresponding signal of the first 3-phase output signal.

[0026] Optionally, in the preceding aspect, the receiver also includes a differential 3-phase to quadrature converter configured to receive and convert the first 3-phase output signal and the second 3-phase output signal into in-phase/quadrature format.

[0027] Optionally, in any of the preceding aspects for a receiver, the receiver also includes: a first low noise amplifier configured to receive and amplify the input signal; and supply the amplified input signal to the first set of three mixers; and a second low noise amplifier configured to receive and amplify the input signal and supply the amplified input signal to the second set of three mixers.

[0028] Optionally, in the preceding aspect, the first and second low noise amplifiers are configured to provide the amplified input signal as a differential output, the first set of three mixers and the second set of three mixers respectively receiving a positive side output of the first and second low noise low noise amplifiers: the harmonic rejection mixer further comprising a second mixing section, including: a third set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal and a negative side output of the first low noise amplifier to generate one of three signals of a 3-phase negative side first output signal; and a fourth set of three mixers, each configured to receive and mix one of the clock signals of the second 3-phase clock signal and a negative side output of the low noise amplifier to generate one of three signals of a 3-phase negative side second output signal, each of the signals of the negative side second output signal being an inversion of a corresponding signal of the first negative side 3-phase output signal.

[0029] Optionally, in any of the preceding two aspects for a receiver, the receiver also includes an antenna configured to receive and supply the input signal to the first and second low noise amplifiers.

[0030] Optionally, in any of the preceding aspects for a receiver, the frequency synthesizer comprises: a voltage controlled oscillator configured to generate an oscillator signal; a first 3-phase generator configured to generate the first 3-phase clock signal from the oscillator signal; a delay circuit configured to receive and delay the oscillator signal; and a second 3-phase generator connected to the delay circuit and configured to generate the second 3-phase clock signal from the delayed oscillator signal.

[0031] Optionally, in the preceding aspect, the frequency synthesizer includes a phase locked loop including the voltage controlled oscillator. [0032] Optionally, in any of the preceding two aspects for a receiver, the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

[0033] Optionally, in the preceding aspect, the delay circuit introduces 90° phase shift into the oscillator signal.

[0034] Optionally, in any of the preceding two aspects for a receiver, the frequency synthesizer is configured to generate the 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.

[0035] According to another aspect of the present disclosure, there is provided a method of receiving a signal that includes: receiving an input signal; receiving a first 3-phase clock signal having three clock signals and a second 3-phase clock signal having three clock signals, each of the three clock signals of the first 3-phase clock signal having a phase corresponding to one of the input signals of the 3-phase input signal and each of the three clock signals of the second 3-phase clock signal having a phase corresponding to one of the inverse input signals of the 3-phase input signal; and generating three first output signals forming a 3-phase first output signal and an inverse output signal for each signal of the three first output signals from the input signal and from the first 3-phase clock signal and the second 3-phase clock signal, each of the 3 first output signals having a phase corresponding to one of the 3 clock signals. The three first output signals are generated by: for each of the three clock signals of the first 3-phase clock signal in a corresponding one of a first set of three mixers, mixing the clock signal with the input signal to generate the 3-phase first output signal; and for each of the three clock signals of the second 3-phase clock signal in a corresponding one of a second set of three mixers, mixing the clock signal with the input signal to generate the inverse output signal for each signal of the three first output signals.

[0036] Optionally, in the preceding aspect of a method of receiving a signal, the method also includes converting the 3-phase first output signal and the inverse output signal for each signal of the three first output signals into in-phase/quadrature format. [0037] Optionally, in any of the preceding aspects of a method of receiving a signal, the method also includes: individually amplifying the input signal in a first low noise amplifier and a second low noise amplifier; supplying the amplified input signal from the first low noise amplifier to be mixed with the corresponding first 3-phase clock signal to generate the 3-phase first output signal; and supplying the amplified input signal from the second low noise amplifier to be mixed with the corresponding second 3-phase clock signal to generate the inverse output signal for each signal of the three first output signals.

[0038] Optionally, in the preceding aspect, the first and second low noise amplifiers are configured to provide the amplified input signal as a differential output, the first set of three mixers and the second set of three mixers respectively receiving a positive side output of the first and second low noise low noise amplifiers, the method further comprising: for each of the three clock signals of the first 3-phase clock signal in a corresponding one of a third set of three mixers, mixing the clock signal with a negative side output of the first low noise amplifier to generate one of three signals of a 3-phase negative side first output signal; and for each of the three clock signals of the second 3-phase clock signal in a corresponding one of a fourth set of three mixers, mixing the clock signal with a negative side output of the low noise amplifier to generate one of three signals of a 3-phase negative side second output signal, each of the signals of the negative side second output signal being an inversion of a corresponding signal of the first negative side 3-phase output signal.

[0039] Optionally, in any of the preceding two aspects the method also includes receiving and supplying the input signal to the first and second low noise amplifiers from an antenna.

[0040] Optionally, in any of the preceding aspects of a method of receiving a signal, the method also includes: generating an oscillator signal by a voltage controlled oscillator; generating the first 3-phase clock signal from the oscillator signal; delaying the oscillator signal; and generating the second 3-phase clock signal from the delayed oscillator signal. [0041] Optionally, in the preceding aspect, the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

[0042] Optionally, in the preceding aspect, delaying the oscillator signal includes introducing a 90° phase shift into the oscillator signal.

[0043] Optionally, in any of the preceding three aspects of a method of receiving a signal, the method also includes: generating the first 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3; and generating the second 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.

[0044] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background.

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying figures for which like references indicate elements.

[0046] FIG. 1 illustrates a wireless network for communicating data.

[0047] FIG. 2 is block diagram of a wireless communication system that can be used in a network such as in FIG. 1.

[0048] FIG. 3 is a block diagram for a first embodiment of a dual 3-phase transmitter illustrating improved harmonic rejection.

[0049] FIG. 4 is a timing diagram showing each clock from the frequency synthesizer block of FIG. 3 and its duty ratio. [0050] FIG. 5 shows the results of a simulation for the performance of the power amplifier for the embodiment of FIG. 3.

[0051] FIG. 6 is a flowchart illustrating a first embodiment for the operation of a transceiver as in the embodiment of FIG. 3.

[0052] FIG. 7 is a block diagram for a first embodiment of a dual 3-phase receiver illustrating improved harmonic rejection.

[0053] FIG. 8A illustrates an example of a strong blocker frequency being present at the second harmonic of the carrier frequency of the desired receiver signal.

[0054] FIG. 8B illustrates the output for the receiver of FIG. 7 for the input of FIG. 8A.

[0055] FIG. 9 is a flowchart illustrating an embodiment for the operation of a receiver as in the embodiment of FIG. 7.

DETAILED DESCRIPTION

[0056] The present disclosure will now be described with reference to the figures, which in general relate to techniques for reducing unwanted harmonic content from transmitters and receivers. Embodiments are presented for dual 3-phase transmitters and receivers that can generate local oscillator clock signals from a voltage controller oscillator operating at a frequency of 3/2 the local oscillator frequency and that are able to reduce unwanted harmonics at a level that would typically require the voltage controller oscillator to run at twice (or higher) the local oscillator frequency. In the architectures described below, a first 3-phase clock signal is generated, along with a second, shifted 3-phase clock signal. The components of the first of these clock signals are each mixed with the component of a 3-phase input signal of the same phase, with the resultant three signals mixed to form a first intermediate signal. The components of the second 3-phase clock signals are each mixed with the inverse component of three 3-phase input signal of the same phase, with the resultant three signals mixed to form a second intermediate signal. The two intermediate signals can be individually amplified and combined to provide the output. In a differential embodiment, a n-side output can similarly be generated by switching the roles of the 3-phase input and its inverses.

[0057] It is understood that the present embodiments of the disclosure may be implemented in many different forms and that claims scopes should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive embodiment concepts to those skilled in the art. Indeed, the disclosure is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details.

[0058] FIG. 1 illustrates a wireless network for communicating data. The communication system 10 includes, for example, user equipment 11A-11 C, radio access networks (RANs) 12A-12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private and public data-packet networks including corporate intranets. While certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in the system 10.

[0059] In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station which employs orthogonal frequency- division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 millisecond (ms) (e.g., 100 or 200 microseconds), to communicate with the communication devices. In general, a reference to base station may refer any of the eNB and the 5G base stations (gNB). In addition, the network may further include a network server for processing information received from the communication devices via the at least one eNB or gNB base station. [0060] System 10 enables multiple wireless users to transmit and receive data and other content. The system 10 may implement one or more channel access methods, such as but not limited to code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0061] The user equipment (UE) 11A-11 C are configured to operate and/or communicate in the system 10. For example, the user equipment 11A-11C are configured to transmit and/or receive wireless signals or wired signals. Each user equipment 11A-11 C represents any suitable end user device and may include such devices (or may be referred to) as a user equipment/device, wireless transmit/receive unit (UE), mobile station, fixed or mobile subscriber unit, pager, cellular telephone, personal digital assistant (PDA), smartphone, laptop, computer, touchpad, wireless sensor, wearable devices or consumer electronics device.

[0062] In the depicted embodiment, the RANs 12A-12B include one or more base stations 17A, 17B (collectively, base stations 17), respectively. Each of the base stations 17 is configured to wirelessly interface with one or more of the UEs 11A, 11 B, 11 C to enable access to the core network 13, the PSTN 14, the Internet 15, and/or the other networks 16. For example, the base stations (BSs) 17 may include one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a Flome NodeB, a Flome eNodeB, a site controller, an access point (AP), or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network.

[0063] In one embodiment, the base station 17A forms part of the RAN 12A, which may include other base stations, elements, and/or devices. Similarly, the base station 17B forms part of the RAN 12B, which may include other base stations, elements, and/or devices. Each of the base stations 17 operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell.” In some embodiments, multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell. [0064] The base stations 17 communicate with one or more of the user equipment 11A-11 C over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology.

[0065] It is contemplated that the system 10 may use multiple channel access functionality, including for example schemes in which the base stations 17 and user equipment 11A-11 C are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base stations 17 and user equipment 11A-11 C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized.

[0066] The RANs 12A-12B are in communication with the core network 13 to provide the user equipment 11 A-11 C with voice, data, application, Voice over Internet Protocol (VoIP), or other services. As appreciated, the RANs 12A-12B and/or the core network 13 may be in direct or indirect communication with one or more other RANs (not shown). The core network 13 may also serve as a gateway access for other networks (such as PSTN 14, Internet 15, and other networks 16). In addition, some or all of the user equipment 11 A-11 C may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols.

[0067] The RANs 12A-12B may also include millimeter and/or microwave access points (APs). The APs may be part of the base stations 17 or may be located remote from the base stations 17. The APs may include, but are not limited to, a connection point (an mmW CP) or a base station 17 capable of mmW communication (e.g., a mmW base station). The mmW APs may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but are not required to operate throughout this range. As used herein, the term base station is used to refer to a base station and/or a wireless access point.

[0068] Although FIG. 1 illustrates one example of a communication system, various changes may be made to FIG. 1. For example, the communication system 10 could include any number of user equipment, base stations, networks, or other components in any suitable configuration. It is also appreciated that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are a target device, device-to-device (D2D) user equipment, machine type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDA, iPad, Tablet, mobile terminals, smart phones, laptop embedded equipped (LEE), laptop mounted equipment (LME) and USB dongles.

[0069] FIG. 2 is block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A-11 C or base station 17, showing some of the elements discussed in relation to the following figures. To transmit an output signal from the circuit elements of processor 111 , a transmitter (Tx) RF/analog section 101 up-converts the output signal from either a baseband or an intermediate frequency (IF) range, depending on the construction of Tx digital baseband block 107 to the radio frequency (RF) range, and also amplifies and filters an outgoing transmit signal before supplying the transmit signal to the antenna 105. The transmitter (Tx) RF/analog section 101 can also be configured to perform other processes to prepare the outgoing transmit signal. The output signal generated by Tx digital baseband block 107 is provided to the Tx RF/analog section 101 in in-phase/quadrature (l/Q) format as in- phase and quadrature signals IT_X and QT_X. Although Tx digital baseband block 107 is shown as a separate block from Tx RF/analog section 101 in FIG. 2, depending on the embodiment these elements can be variously combined as circuit elements and implemented in hardware, firmware, software, or a combination of these.

[0070] Signals are received by the antenna 105 and supplied to a receiver (Rx) RF/analog section 102. Rx section 102 performs any needed or wanted signal processing, such as down-conversion from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering, before passing the signal on to other elements on the device represented at processor 111. In the embodiment of FIG. 2, the output of the Rx RF/analog section 102 is in l/Q format and the Rx digital baseband section 117 converts this to the receive signal supplied to the processor. Although the Rx digital baseband section 117 is shown as a separate block from Rx RF/analog section 102 in FIG. 2, depending on the embodiment these elements can be variously combined as circuit elements and implemented in hardware, firmware, software, or a combination of these. Additionally, although FIG. 2 represents the Tx RF/analog section 101 and Rx section RF/analog 102 as separate elements, depending on the embodiment, the transmitter and receiver paths can share many elements or be embodied as a combined transceiver. In the following, “transceiver” may be used generally to refer a combined transmitter/receiver, separate transceiver and receiver sections, or an embodiment in which one or more components (e.g., local oscillators) are shared between the transmitter and receiver.

[0071] In a transceiver, such as a mobile telephone, it is common to have undesired clock harmonics generated from the local oscillator. On the transmitter side, these clock harmonics can be mixed back to near the frequency of the desired signal through non-linearities in and creates near channel distortion (e.g., CIM2, CIM3, CIM5, where CIMx is the x^th order counter inter-modulation) and also impact other wireless terminals nearby using near-by carrier frequencies. On the receiver side, a blocker signal near the desired signal’s clock harmonics frequency can fall on top of the desired signal frequency when mixed back to the baseband frequency when down-converted and degrade the received signal. Consequently, it is desirable to reduce these unwanted clock harmonics’ impact as much as possible.

[0072] Typically, some of these unwanted harmonics can be removed through multi-phase (N-phase) mixer design, with an appropriate choice of N, where the higher the value N, the more harmonics that will be removed. So, a high value of N is preferred for harmonic suppression. Flowever, for an N-phase mixer design, a high value of N requires the oscillator (e.g., a voltage controller oscillator, or VCO) to run at a high frequency. (Typically, the minimum VCO frequency is fi_o^*N/2, where fi_o is the local oscillator carrier frequency.) This results in high power consumption in the VCO and can make the VCO design challenging.

[0073] The following presents embodiments for a Flarmonic Rejection Mixer (FIRM) mixer that can run at a lower value of N=3, thus reducing the VCO frequency requirement, while rejecting more harmonics than a traditional 3-phase FIRM. To transmit a quadrature IQ signal (a signal in in-phase/quadrature, or IQ, format), a minimum of N=3, i.e. 3-phase system, is used. A 3-phase system is often preferred due to the small value of N. For a 5G cellular system, the carrier frequency (as currently defined) can be 7.15GHz. With a 3-phase system, the VCO can be run as low as fcarrier^*N/2 = 7.15GHz^*3/2=10.725GHz, which is not overly difficult to design. However, a conventional 3-phase system does not reject the 2^nd clock harmonic and 4^th harmonic, which will be converted to CIM2/CIM4 in the transmitter case by the single-ended power amplifier and may fail the specification of some standards. In addition, depending on the front-end configuration, the 2^nd harmonics themselves may cause a transmitter system to fail a spurious emission specification at the 2^nd harmonic frequency.

[0074] The following presents embodiments of transmitters and receivers that use a 3-phase system while rejecting more clock harmonics than a standard 3-phase system. Even though the standard 3-phase system has an advantage in terms of lowering the maximum operating frequency of the voltage controlled oscillator, the lack of rejection of the 2^nd and the 4^th harmonics is a serious concern and makes the standard 3-phase not very useful in a cellular system. Embodiments presented below use a dual 3-phase system, where the two 3-phase systems are offset from each other by 60 degrees. In this dual 3-Phase system, the VCO can run at a frequency of 3/2 the carrier frequency (fvco=fcarrier^*3/2) while rejecting the 2^nd, 3^rd and 4^th harmonics. This means this dual 3-phase system has the harmonics rejection property of a 6- phase system while only having the VCO’s maximum frequency to be that of a standard 3-phase system. FIG. 3 is a block diagram that shows the basic concept.

[0075] FIG. 3 is a block diagram for a first embodiment of a dual 3-phase transmitter exhibiting improved harmonic rejection. Considering FIG. 3 at a high level, an IQ source 107, which can be generated inside the Tx digital baseband block 107 of FIG. 2, provides the signal to be transmitted. The signal from IQ source 107 is in l/Q format, and, as described below, is converted into a differential 3-phase signal in the 3-phase signal source 241 , whose components provide the source signal in an analog 3-phase format to harmonic rejection block HRM 200. A frequency synthesizer 230 supplies the dual 3-phase clock signals to HRM 200. The output of HRM 200 is supplied to antenna 105 through a set of variable gain amplifiers VGA 221-/ and VGA 223-/, inductive coupler 251 , power amplifier PA 253, and filter 255.

[0076] In the IQ signal path, the IQ data from IQ source 107 is digitally converted to a set of 3-phase baseband signals (0, 120, 240) in conversion block 243. Then three digital to analog converters (DACs) DAC_0 245-1 , DAC_120 245-2, and DAC_240 245-3 convert the 3-Phase digital signals to analog signals, which are then filtered through low pass filters (LPFs) LPF_0 247-1 , LPF 20 247-2, and LPF_240 247-3 to remove unwanted distortions and noise. Typically, the DACs and LPFs are differential circuit to be relatively immune from other noise sources inside the transceiver. This means in addition to 0, 120 and 240 signals, the complementary signals (180, 300, 60) are also created and provided to HRM 200. Together, the elements 107, 243, 245-1 , 245-2, 245-3, 247-1 , 247-2, and 247-3 form a differential 3- phase signal source 241 .

[0077] In the block of frequency synthesizer 230, a VCO 231 can be part of a phase locked loop PLL 233. The VCO can run at a frequency fVCO=1 5^*fLO, where fLO is the local oscillator or carrier frequency. The VCO output is fed to a first 3-phase clock generation block 235 to generate clkO, clk120 and clk240. The VCO output is also fed a 90 degrees phase shift block 237 and then to a second 3-phase generation block 239. Since the 3-phase generation block 239 is basically a divide by 1.5 operation, the initial 90 degrees phase shift becomes 60 degrees at the final carrier frequency, which means the clk60, clk180 and clk300 will be generated in block 239. For all six clocks (clkO, clk120, clk240, clk60, clk180 and clk300), each clock has duty ratio of 33.33% in this embodiment, so that the three clock signals from each of the generation blocks 235 and 239 are non-overlapping and together add up to 100%, but the clocks form the different blocks overlap.

[0078] FIG. 4 is a timing diagram showing each clock from frequency synthesizer block 230 and its duty ratio. As shown in FIG. 4, elk 0, clk120 and clk240 form a first set of non-overlapping signals of 3-phase clock signal and clk60, clk180 and clk300 forms a second set of non-overlapping signals of a 3-phase clock signal. Combing all six clocks, they are overlapping clocks. [0079] Returning to FIG. 3, the two p side intermediate outputs of HRM 200 each go to a corresponding one of VGA 221-1 or VGA-2 221-2. The input of each of these VGAs is the combined output from a set of three mixers each receiving one the set of clock signals from either 3-phase generator block 235 or 3-phase clock generator block 239: the input of VGA 221-1 is the combined output of mixer 201 receiving clkO, mixer 202 receiving clk120, and mixer 203 receiving clk240 to produce a first p side intermediate output; and the input of VGA 221-2 is the combined output of mixer 204 receiving clk60, mixer 205 receiving clk300, and mixer 206 receiving clk180 to produce a second p side intermediate output. As noted above each of these clock signals has a duty cycle of 1/3, or 33%, and are non-overlapping, but together add up to 100%.

[0080] A similar arrangement is used for the n side intermediate outputs of HRM 200, each going to one of a corresponding VGA 223-1 or VGA-3 223-2. The input of each of these VGAs is the combined output from a set of three mixers each receiving one the set of clock signals from either 3-phase generator block 235 or 3-phase clock generator block 239: the input of VGA 223-1 is the combined output of mixer 211 receiving clkO, mixer 212 receiving clk120, and mixer 213 receiving clk240 to produce a first n side intermediate output; and the input of VGA 221-2 is the combined output of mixer 214 receiving clk60, mixer 215 receiving clk300, and mixer 216 receiving clk180 to produce a second n side intermediate output. As noted above each of these clock signals has a duty cycle of 1/3, or 33%, and are non-overlapping, but together add up to 100%.

[0081] The harmonic rejection mixer (HRM) 200 combines the LPFs’ outputs and the signal of the dual 3-pahse LO clocks to generate the RF output. As illustrated in FIG. 3, on the p side the signals of the 3-phase outputs 0, 120 and 240 from respective LPF 247-1 , 247-2, and 247-3 are each mixed with clock signal of the same phase of the first 3-phase clock signal in the corresponding one of the first set of mixers 201 , 202, and 203. Also on the p side, the inverse input signal of the 3-phase outputs 180, 300 and 60 from respective LPF 247-1 , 247-2, and 247-3 are each mixed with clock signal of the same phase of the second 3-phase clock signal in the corresponding one of the first set of mixers 206, 205, and 204. [0082] The n side of HRM 200 is arranged similarly to the p side, but with the outputs from each of the LPFs swapped so that the input signals are mixed with the clock signals of the opposite phase. In the first set of n side mixers, the inverse inputs 180, 300, and 60 of the 3-phase input signal are respectively mixed with clkO in mixer 211 , with clk120 in mixer 212, and with clk240 in mixer 213. In the second set of n side mixers, the inputs 0, 120, and 240 of the 3-phase input signal are respectively mixed with clock signal of the of the second 3-phase clock signal corresponding to the opposite phase of clk180 in mixer 216, with clk300 in mixer 215, and with clk60 in mixer 214.

[0083] The RF intermediate outputs from the p side mixers are amplified by the VGAs 221-1 and 221-2 and combined to provide a p side output signal from FIRM 200, with the RF intermediate outputs from the n side mixers similarly amplified by the VGAs 223-1 and 223-2 and combined to provide an n side output signal from FIRM 200. To convert the RF output from the VGAs to a single ended output, an inductive coupler 251 can be used, with the combined p side output and the combined n -side output connected across a first coil of inductive coupler 251 and the second coil of the inductive coupler 251 having one side set at ground and the other side providing a single-ended signal at the output. A power amplifier PA 253 amplifies the single-ended output and the PA output is filtered through a RF filter 255 to remove unwanted distortions. Finally, the filtered RF output is fed to the antenna 105 to be transmitted.

[0084] Typically, the mixers inside FIRM 200 are passive mixers in cellular applications, which means overlapping clock creates cross talk among different paths. To avoid this, segmented VGAs 221 -1 , 221-2, 223-1 , and 223-2 can be use as shown in FIG. 3 such that each individual path has non-overlapping clocks.

[0085] FIG. 5 shows the results of a simulation for the performance at the output of the power amplifier for the embodiment of FIG. 3. More specifically, the plot of FIG. 5 plots the output of the 3-Phase power amplifier output in decibels (dB), normalized so that the desired transmitter (Tx) signal is at OdB, as a function of frequency. In the plot of FIG. 5, the desired signal frequency (about 1 .2288x10⁸Hz) is chosen to be lower than an actual RF target frequency for fast simulation purpose. In the simulation, the 90 degrees phase shift block 237 is assumed to be non-ideal (85 degrees is used). In addition to the desired Tx signal, at a somewhat lower frequency are a peak due to LO leakage, down by about -60dB, and a peak due to image distortion, down by over -80dB. The CIM2n and CIM4p spikes are generated due to the non-perfect delay value. Overall, it shows the CIM distortions can be significantly reduced even with non ideal implementations if properly managed.

[0086] With respect to the harmonics, for the second order counter inter-modulation FIG. 5 shows a peak on the positive side CIM2p down by -80dB and the peak on the negative side CIM2n down by about -60dB, along with CIM4p down by about -90dB. If the phased shift in phase shift block 237 were closer to 90 degrees, these CIM values would be reduced further. There is no third order CIM3 peak and the only other significant spike is for CIM5, which is down about -100dB. Consequently, the simulation results of FIG. 5 illustrate that the performance at output of power amplifier PA 253 of the dual 3-Phase FIRM architecture of FIG. 3 can achieve harmonic rejection that is comparable to a standard 6-Phase FIRM. The spectrum of this system shows the levels of all CIM distortion are sufficiently low for cellular applications.

[0087] FIG. 6 is a flowchart illustrating a first embodiment for the operation of a transceiver as in the embodiment of FIG. 3. At 601 the FIRM receives the N components of the N-phase input signal and the inverse of these input signals from the 3-phase signal source 241. In the embodiment of FIG. 3, this includes the components (0, 120, 240) of the 3-Phase input signal and the inverses (180, 300, 60) of these input signals. In the embodiment of FIG.3, these signals are generated from the l/Q signal of IQ source 107 by the 3-phase conversion block, DACs 245-1 , 245-2, 245-3 and LPFs 247-1 , 247-2, 247-3.

[0088] At 603 the frequency synthesizer 230 generates, and FIRM 200 receives, the LO clock signals. The LO clock signals include the three components of the first 3-phase clock signal and the three components of the second 3-phase clock signal. In the embodiment of FIG. 3, the first 3-phase clock signal is the clock signals ClkO, Clk120, and Clk240 from generator block 235, all with a duty ratio of 1/3, and second 3-phase clock signal is shifted by 60 degrees from the first 3-phase signal and is the clock signals Clk60, Clk180, and Clk300 from generator block 239, all with a duty ratio of 1/3. Although the flowchart of FIG. 6 presents its elements is particular sequence, it will be understood that these can all be performed concurrently (i.e. , 601 , 603, and following elements are going at the same time during operation) to generate the output signal when the circuit of FIG. 3 is transmitting.

[0089] At 605, each clock signal of the first 3-phase clock signal is mixed with the input signal of the corresponding phase. For example, in the embodiment of FIG. 3, in the first set of mixers on the p-side of FIRM 200 the inputs signal components (0, 120, 240) are respectively mixed with the components of the 3-Phase (clkO, clk120, clk240) in mixers 201 , 202 and 203. At 607 the outputs of the mixers are combined to form a first intermediate signal for the p side, which is then amplified in VGA 221-1 .

[0090] Concurrently with 605 and 607, 609 and 611 are performed. At 609, each clock signal of the second 3-phase clock signal is mixed with the inverse input signal of the corresponding phase. For example, in the embodiment of FIG. 3, in the second set of mixers on the p-side of FIRM 200 the shifted inputs signal components (60, 300, 180) are respectively mixed with the components of the second 3-Phase (clk60, clk300, clk180) in mixers 204, 205 and 206. At 611 the outputs of these mixers are combined to form a second intermediate signal for the p side, which is then amplified in VGA 221-2. In a two sided embodiment as in FIG. 3, the two n side intermediate outputs are generated as described above to complement 605-611

[0091] At 613, the first and second intermediate signals are combined to generate the output signal for, in the two sided embodiment of FIG. 3, the p side of FIRM 200. The outputs of the VGA 221-1 and 221-2 are combined to provide the output signal for the p side of FIRM 200. In the two sided embodiment of FIG. 3, on the n side intermediate outputs are similarly combined to provide the output signal for the n side of FIRM 200.

[0092] The output signals are then transmitted in 615. In a two sided embodiment like FIG. 3, the p side and n side outputs are converted to a single sided output at the coils of inductive coupler 251. The single sided output is then amplified in power amplifier PA 253, filtered at filter 255, and then transmitted from antenna 105.

[0093] As described, the techniques described here use a dual 3-Phase transmitter system for better harmonic rejection compared to a standard 3-Phase transmitter system. The dual 3-phase transmitter system can achieve similar performance in terms of harmonics rejection as a standard 6-phase transmitter system. Additionally, the dual 3-phase system only requires the VCO to run at 1 .5 times the carrier or local oscillator frequency, instead of three times the carrier frequency needed for a standard 6-phase system, which reduces the VCO design complexity and power consumption.

[0094] FIG. 7 is a block diagram of an embodiment for a dual 3-Phase receiver system which rejects blockers that are located at or near 2^nd, 3^rd and 4^th clock harmonics. The overall structure of the receiver embodiment of FIG. 7 is similar to the transmitter embodiment of FIG. 3, except, roughly speaking, with the signal paths reversed. In the receiver embodiments presented here, a segmented low noise amplifier (LNA) is used to avoid overlapping cross-talk.

[0095] More specifically, the frequency synthesizer 730 can be of the same or a similar structure to frequency synthesizer 230 of FIG. 3, where VCO 731 , PLL 733, first 3-phase generation block 735, delay block 737, and second 3-phase generation block 739 can operate as described above with respect to the corresponding elements 231 , 233, 235, 237, and 239.

[0096] Rather than receiving a 3-phase input signal and inverse signals of its components, FIRM 700 now generates a 3-phase output signal (0, 120, 240) and, as FIG. 7 is again a two sided embodiment, the inverse values (180, 300, 60) of the 3- phase output. The complimentary output signal pairs act as the differential inputs to a set of low pass filters and analog to digital converters. More specifically, the (0, 180) pair are the differential input to LPF_0 747-1 , whose output then goes to ADC_0 745-

1 to give the (single ended) first (0 degree phase) component of the 3-phase output. Similarly, the (120, 300) pair are the differential input to LPF_120747-2, whose output then goes to ADC_120 745-2 to give the (single ended) second (120 degree phase) component of the 3-phase output; and the (240, 60) pair are the differential input to LPF_240747-3, whose output then goes to ADC_240745-3 to give the (single ended) third (240 degree phase) component of the 3-phase output.

[0097] The inputs to FIRM 700 are from a segmented LNA of LNA 721-1 and LNA-

2 721-2, each connected to receive a signal from the antenna 105 by way of RF filter 755. The output of each of LNAs 721-1 and 721-2 is differential, with the p side output of each going to a corresponding set of p side mixers in HRM 700 and the n side output of each going to the corresponding set of n side mixers in HRM 700.

[0098] Within HRM 700, the p side output from LNA 921-1 goes to the first set of p side mixers 701 , 702, and 703 to be respectively mixed with clkO, clk120 and clk240 to generate the output components 0, 120, and 240. The n side output from LNA 921- 1 goes to the first set of p side set of mixers pair 711 , 712, and 713 to be respectively mixed with clkO, clk120 and clk240 to generate the output components 180, 300, and 60 to generate the reversed differential output component 180, 300, and 60.

[0099] Similarly, the p side output from LNA 921-2 goes to the second first set of n side mixers 711 , 712, and 713 to be respectively mixed with clkO, clk120 and clk240 to generate the output components 60, 300, and 180. The n side output from LNA 921-1 goes to the second set of n side set of mixers pair 714, 715, and 716 to be respectively mixed with clk60, clk300, and clk180 to generate the output components 60, 300, and 180 to generate the reversed differential output component 240, 300, and 180.

[00100] For receivers, an issue to be solved is when there is a strong blocker (i.e. , an interfering signal such as another near-by cellular telephone) presented at the antenna near a harmonic frequency of desired receiver signal frequency, e.g. at the 2^nd harmonic, with the requirement of the receiver’s maximum VCO frequency at 1.5 the carrier frequency. This is illustrated by FIG. 8A.

[00101] FIG. 8A illustrates an example of a strong blocker frequency being present at the second harmonic of the carrier frequency of the desired receiver signal. FIG. 8A is a plot of frequency versus level for signals seen at antenna 105 of the receiver of FIG. 7. The signal at fcarrier is the desired receiver signal, where fcarrier corresponds to the local oscillator frequency of the clock signals from frequency synthesizer block 730. The signal at fcarrier^*2 is an example of a strong blocker signal at near the second harmonic of the desired signal, and is of a higher level that the desired signal. With a 1 5X clock, the receiver will be a 3-phase system, which means that the strong blocker near 2^nd harmonic will be converted to baseband signal through the down conversion process and falls into desired channel and, in a standard 3-phase receiver system, will degrade the signal to noise ratio of the receiver. Depending on the blocker signal level, this clock generated distortion level can be significantly larger than the targeted/desired signal level, which means that such a typical 3-phase system may fail a standard’s required blocker test case.

[00102] In a dual 3-phase embodiment as illustrated in FIG. 7, the second harmonics to baseband conversion can be minimized. In the arrangement of FIG. 7, the single- ended signal from the antenna 105 is converted to a differential form by the LNA block 721-1 , 721-2 and fed to the FIRM 700 and then propagates through the signal path similarly to as in the transmitter of FIG. 3. FIG. 8B illustrates the resultant output from the 3-phase to IQ conversion block 743 is represented in FIG. 8B.

[00103] FIG. 8B illustrates the output for the receiver of FIG. 7 for the input of FIG. 8A. The receiver channel runs from a baseband frequency of -Fc to Fc. The unwanted blocker near 2^nd harmonic may be converted to baseband within the targeted RX channel which will degrade the signal to noise ratio; however, using the dual 3-phase receiver architecture this blocker conversion will be minimized as illustrated in FIG. 8B to be of a lower level, thus improving the signal to noise ratio.

[00104] FIG. 9 is a flowchart illustrating an embodiment for the operation of a receiver as in the embodiment of FIG. 7. At 901 , an input signal is received. Referring to the embodiment of FIG. 7, the input signal is received by the antenna 105 and then goes to the segmented LNA 721-1 and 721-2, with the differential outputs supplied to the p side and n side of HRM 700.

[00105] At 903 the frequency synthesizer 730 generates, and HRM 700 receives, the LO clock signals. The LO clock signals include the three components of the first 3-phase clock signal and the three components of the shifted, second 3-phase clock signal. In the embodiment of FIG. 7, these are the clock signals ClkO, Clk120, and Clk240 and the shifted signal Clk60, Clk180, and Clk300, all of which have a duty cycle ratio of 1/3 (33%).

[00106] At 905, for each component of the first 3-phase clock signals, the p side input signal from the LNA 721-1 is mixed with the clock signal to generate to the corresponding 3-phase output signal. In the embodiment of FIG. 7, on the p side the output of LNA 721-1 goes to the mixers 701 , 702, and 703, where it is respectively mixed with ClkO, Clk120, and Clk240 to provide first 3-phase output signal of the 0, 120, and 240 components.

[00107] At 907, for each component of the second 3-phase clock signals, the p side input signal from the LNA 721-2 is mixed with the clock signal to generate to the corresponding second 3-phase output signal, whose component will be the inverses of the components of the first 3-phase output signal of 905. In the embodiment of FIG. 9, on the p side the output of LNA 721-2 goes to the mixers 704, 705, and 706, where it is respectively mixed with Clk60, Clk300, and Clk180 to provide second 3-phase output signal of the 60, 300, and 180 components. Together, the first 3-phase output from 905 and the second 3-phase output from 907 generate a differential 3-phase output. The differential 3-phase output can then go the LPFs 747-1 , 747-2, and 747- 3, followed ADCs 745-1 , 745-2, and 745-3 and the 3-phase to IQ converter 745 to provide the output data in IQ format.

[00108] For a two sided embodiment as in FIG. 7, the n side outputs of the LNAs 721-1 and 721-2 respectively go to the first set of n side mixers (711 , 712, 713) to be mixed with the first 3-phase clock signal and to the second set of n side mixers (714, 715, 716) to be mixed with the second 3-phase clock signal. These respectively generate another copy of the second, inverse output signal and the first output signal that can similarly be used in generating the IQ output.

[00109] As described above, for the receiver embodiments as well as the transmitter embodiments, the described dual 3-phase architecture allows for the use of a lower VCO frequency to achieve similar harmonics performance as for traditional 6-phase systems. This lowers the requirement of VCO’s maximum operating frequency to be 1 5X instead standard 6-phase system’s 3X VCO frequency requirement.

[00110] The technology described herein can be implemented using hardware, firmware, software, or a combination of these. The software or firmware used can be stored on one or more processor readable storage devices to program one or more of the blocks of FIGs. 3-9 to perform the functions described herein. The processor readable storage devices can include computer readable media such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information, and which can be accessed by the components described above. A computer readable medium or media does (do) not include propagated, modulated or transitory signals.

[00111] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

[00112] In alternative embodiments, some or all of the software or firmware can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media/ storage devices, peripherals and/or communication interfaces.

[00113] It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.

[00114] Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

[00115] The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated.

[00116] For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device.

[00117] Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

CLAIMS What is claimed is:

1. A transmitter, comprising: a 3-phase signal source configured to provide three input signals forming a 3- phase input signal and an inverse input signal for each signal of the three input signals; a frequency synthesizer configured to: generate a first 3-phase clock signal having three clock signals, each of the three clock signals having a phase corresponding to one of the input signals of the 3-phase input signal, and generate a second 3-phase clock signal having three clock signals, each of the three clock signals having a phase corresponding to one of the inverse input signals of the 3-phase input signal; and a harmonic rejection mixer, comprising: a first mixing section, including: a first set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal with the one of the input signals of the corresponding phase; and a second set of three mixers, each configured to receive and mix one of the clock signals of the second 3-phase clock signal with the one of the inverse input signals of the corresponding phase, wherein the harmonic rejection mixer is further configured to: form a first intermediate signal by combining an output of the first set of three mixers, form a second intermediate signal by combining an output of the second set of three mixers, and combine the first and second intermediate signals to form a first output signal for the harmonic rejection mixer.

2. The transmitter of claim 1 , further comprising: a first variable gain amplifier configured to: receive the first intermediate signal; and amplify the first intermediate signal prior to combining the first and second intermediate signals to form the first output signal for the harmonic rejection mixer; and a second variable gain amplifier configured to: receive the second intermediate signal; and amplify the second intermediate signal prior to combining the first and second intermediate signals to form the first output signal for the harmonic rejection mixer.

3. The transmitter of any of claims 1-2, the harmonic rejection mixer further comprising: a second mixing section, including: a third set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal with the inverse input signal of the one of the input signals of the corresponding phase; and a fourth set of three mixers, each configured to receive and mix one of the clock signals of the second 3-phase clock signal with the input signal of which the one of the inverse input signals of the corresponding phase is the inverse, wherein the harmonic rejection mixer is configured to: form a third intermediate signal by combining an output of the third set of three mixers, form a fourth intermediate signal by combining an output of the fourth set of three mixers, and combine the third and fourth intermediate signals to form a second output signal for the harmonic rejection mixer.

4. The transmitter of claim 3, further comprising: an inductive coupler, comprising: a first coil configured to receive the first output signal for the harmonic rejection mixer at a first terminal and the second output signal for the harmonic rejection mixer at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single ended output for the transmitter and a second terminal connected to ground.

5. The transmitter of claim 4, further comprising: a power amplifier configured to receive and amplify the single ended output.

6. The transmitter of claim 5, further comprising: an antenna configured to receive and transmit the single ended output.

7. The transmitter of any of claims 1-6, wherein: the 3-phase signal source is configured to receive an input signal in in phase/quadrature format and generate therefrom the three input signals forming an 3- phase input signal and the inverse input signal for each signal of the three input signals.

8. The transmitter of any of claims 1-7, wherein the frequency synthesizer comprises: a voltage controlled oscillator configured to generate an oscillator signal; a first 3-phase generator configured to generate the first 3-phase clock signal from the oscillator signal; a delay circuit configured to receive and delay the oscillator signal; and a second 3-phase generator connected to the delay circuit and configured to generate the second 3-phase clock signal from the delayed oscillator signal.

9. The transmitter of claim 8, wherein the frequency synthesizer includes a phase locked loop including the voltage controlled oscillator.

10. The transmitter of any of claims 8-9, wherein the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

11 . The transmitter of claim 10, wherein the delay circuit introduces 90° phase shift into the oscillator signal.

12. The transmitter of any of claims 10-11 , wherein the frequency synthesizer is configured to generate the 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.

13. A method of transmitting a signal, comprising: receiving three input signals forming a 3-phase input signal and an inverse input signal for each signal of the three input signals; receiving a first 3-phase clock signal having three clock signals and a second 3-phase clock signal having three clock signals, each of the three clock signals of the first 3-phase clock signal having a phase corresponding to one of the input signals of the 3-phase input signal and each of the three clock signals of the second 3-phase clock signal having a phase corresponding to one of the inverse input signals of the 3- phase input signal; and generating a first output signal from three input signals forming a 3-phase input signal and an inverse input signal for each signal of the three input signals and from the first 3-phase clock signal and the second 3-phase clock signal, by: for each of the three clock signals of the first 3-phase clock signal, mixing the clock signal with the input signal of the corresponding phase; combining the mixed clocked signals and input signals for the three clock signals of the first 3-phase clock signal to form a first intermediate signal; for each of the three clock signals of the second 3-phase clock signal, mixing the clock signal with the inverse input signal of the corresponding phase; combining the mixed clocked signals and inverse input signals for the three clock signals of the second 3-phase clock signal to form a second intermediate signal; and combining the first intermediate signal and the second intermediate signal to generate the first output signal.

14. The method of claim 13, further comprising: individually amplifying the first intermediate signal and the second intermediate signal prior to combining the first intermediate signal and the second intermediate signal to generate the first output signal.

15. The method of any of claims 13-14, further comprising: generating a second output signal from three input signals forming a 3-phase input signal and an inverse input signal for each signal of the three input signals and from the first 3-phase clock signal and the second 3-phase clock signal, by: for each of the three clock signals of the first 3-phase clock signal, mixing the clock signal with the inverse input signal of the corresponding phase; combining the mixed clocked signals and inverse input signals for the three clock signals of the first 3-phase clock signal to form a third intermediate signal; for each of the three clock signals of the second 3-phase clock signal, mixing the clock signal with the input signal of which the one of the inverse input signals of the corresponding phase is the inverse; combining the mixed clocked signals and input signals for the three clock signals of the second 3-phase clock signal to form a fourth intermediate signal; and combining the third intermediate signal and the fourth intermediate signal to generate the first output signal.

16. The method of claim 15, further comprising: applying the first output signal and the second output signal to a first terminal and a second terminal, respectively, of a first coil of an inductive coupler; receiving and amplifying an output from a second coil of the inductive coupler that is inductively coupled to the first coil; and transmitting the amplified output.

17. The method of any of claims 13-16, further comprising: receiving an input signal in in-phase/quadrature format; and generating the three input signals forming a 3-phase input signal and the inverse input signal for each signal of the three input signals from the input signal.

18. The method of any of claims 13-17, further comprising: generating an oscillator signal by a voltage controlled oscillator; generating the first 3-phase clock signal from the oscillator signal; delaying the oscillator signal; and generating the second 3-phase clock signal from the delayed oscillator signal.

19. The method of claim 18, wherein the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

20. The method of claim 19, wherein delaying the oscillator signal includes introducing a 90° phase shift into the oscillator signal.

21. The method of any of claims 18-20, further comprising: generating the first 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3; and generating the second 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.

22. A receiver, comprising: a frequency synthesizer configured to: generate a first 3-phase clock signal having three clock signals; and generate a second 3-phase clock signal of three clock signals, the three clock signals of the second 3-phase clock including a clock signal with a 180° phase shift from one of the three clock signals of the first 3-phase clock signal; and a harmonic rejection mixer, comprising: a first mixing section, including: a first set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal and an input signal to generate one of three signals of a 3-phase first output signal; and a second set of three mixers, each configured to receive and mix one of the clock signals of the second 3-phase clock signal and the input signal to generate one of three signals of a 3-phase second output signal, each of the signals of the second output signal being an inversion of a corresponding signal of the first 3-phase output signal.

23. The receiver of claim 22, further comprising: a differential 3-phase to quadrature converter configured to receive and convert the first 3-phase output signal and the second 3-phase output signal into in phase/quadrature format.

24. The receiver of any of claims 22-23, further comprising: a first low noise amplifier configured to: receive and amplify the input signal; and supply the amplified input signal to the first set of three mixers; and a second low noise amplifier configured to: receive and amplify the input signal; and supply the amplified input signal to the second set of three mixers.

25. The receiver of claim 24, wherein the first and second low noise amplifiers are configured to provide the amplified input signal as a differential output, the first set of three mixers and the second set of three mixers respectively receiving a positive side output of the first and second low noise low noise amplifiers: the harmonic rejection mixer further comprising: a second mixing section, including: a third set of three mixers, each configured to receive and mix one of the clock signals of the first 3-phase clock signal and a negative side output of the first low noise amplifier to generate one of three signals of a 3-phase negative side first output signal; and a fourth set of three mixers, each configured to receive and mix one of the clock signals of the second 3-phase clock signal and a negative side output of the low noise amplifier to generate one of three signals of a 3-phase negative side second output signal, each of the signals of the negative side second output signal being an inversion of a corresponding signal of the first negative side 3-phase output signal.

26. The receiver of any of claims 24-25, further comprising: an antenna configured to receive and supply the input signal to the first and second low noise amplifiers.

27. The receiver of any of claims 22-26, wherein the frequency synthesizer comprises: a voltage controlled oscillator configured to generate an oscillator signal; a first 3-phase generator configured to generate the first 3-phase clock signal from the oscillator signal; a delay circuit configured to receive and delay the oscillator signal; and a second 3-phase generator connected to the delay circuit and configured to generate the second 3-phase clock signal from the delayed oscillator signal.

28. The receiver of claim 27, wherein the frequency synthesizer includes a phase locked loop including the voltage controlled oscillator.

29. The receiver of any of claims 27-28, wherein the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

30. The receiver of claim 29, wherein the delay circuit introduces 90° phase shift into the oscillator signal.

31 . The receiver of any of claims 29-30, wherein the frequency synthesizer is configured to generate the 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.

32. A method of receiving a signal, comprising: receiving an input signal; receiving a first 3-phase clock signal having three clock signals and a second 3-phase clock signal having three clock signals, each of the three clock signals of the first 3-phase clock signal having a phase corresponding to one of the input signals of the 3-phase input signal and each of the three clock signals of the second 3-phase clock signal having a phase corresponding to one of the inverse input signals of the 3- phase input signal; and generating three first output signals forming a 3-phase first output signal and an inverse output signal for each signal of the three first output signals from the input signal and from the first 3-phase clock signal and the second 3-phase clock signal, each of the 3 first output signals having a phase corresponding to one of the 3 clock signals, by: for each of the three clock signals of the first 3-phase clock signal in a corresponding one of a first set of three mixers, mixing the clock signal with the input signal to generate the 3-phase first output signal; and for each of the three clock signals of the second 3-phase clock signal in a corresponding one of a second set of three mixers, mixing the clock signal with the input signal to generate the inverse output signal for each signal of the three first output signals.

33. The method of claim 32, further comprising: converting the 3-phase first output signal and the inverse output signal for each signal of the three first output signals into in-phase/quadrature format.

34. The method of any of claims 32-33, further comprising: individually amplifying the input signal in a first low noise amplifier and a second low noise amplifier; supplying the amplified input signal from the first low noise amplifier to be mixed with the corresponding first 3-phase clock signal to generate the 3-phase first output signal; and supplying the amplified input signal from the second low noise amplifier to be mixed with the corresponding second 3-phase clock signal to generate the inverse output signal for each signal of the three first output signals.

35. The method of claim 34, wherein the first and second low noise amplifiers are configured to provide the amplified input signal as a differential output, the first set of three mixers and the second set of three mixers respectively receiving a positive side output of the first and second low noise low noise amplifiers, the method further comprising: for each of the three clock signals of the first 3-phase clock signal in a corresponding one of a third set of three mixers, mixing the clock signal with a negative side output of the first low noise amplifier to generate one of three signals of a 3-phase negative side first output signal; and for each of the three clock signals of the second 3-phase clock signal in a corresponding one of a fourth set of three mixers, mixing the clock signal with a negative side output of the low noise amplifier to generate one of three signals of a 3-phase negative side second output signal, each of the signals of the negative side second output signal being an inversion of a corresponding signal of the first negative side 3-phase output signal.

36. The method of any of claims 34-35, further comprising: receiving and supplying the input signal to the first and second low noise amplifiers from an antenna.

37. The method of any of claims 32-36, further comprising: generating an oscillator signal by a voltage controlled oscillator; generating the first 3-phase clock signal from the oscillator signal; delaying the oscillator signal; and generating the second 3-phase clock signal from the delayed oscillator signal.

38. The method of claim 37, wherein the voltage controller oscillator is configured to generate the oscillator signal with a frequency of 3/2 the frequency of the 3-phase clock signal.

39. The method of claim 38, wherein delaying the oscillator signal includes introducing a 90° phase shift into the oscillator signal.

40. The method of any of claims 37-39, further comprising: generating the first 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3; and generating the second 3-phase clock signal with each of the three clocks signals having a duty cycle ratio of 1/3.