CN115336183A

CN115336183A - Transceiver phase shifting for beamforming

Info

Publication number: CN115336183A
Application number: CN202080099088.0A
Authority: CN
Inventors: 姜宏; 张志航; 瓦埃勒·阿尔-卡克
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-04-01
Filing date: 2020-04-01
Publication date: 2022-11-11
Also published as: WO2020226793A2; WO2020226793A3

Abstract

In a beamforming transmitter, a signal is constructed from a plurality of paths having a defined phase shift relationship between the paths. A set of intermediate frequency beamformed signals is generated by introducing a phase shift based on a number of cycles of a higher frequency local oscillator signal used to up-convert the set of intermediate frequency signals. The set of intermediate frequency signals having the defined phase shift relationship is then mixed with data signals, such as in-phase/quadrature (I/Q) data signals, and subsequently upconverted to generate a set of beamformed signals that are provided to an antenna array. Receivers that use the same technique to generate a set of local oscillator signals are also proposed.

Description

Transceiver phase shifting for beamforming

Technical Field

The present disclosure relates generally to an architecture of a beamforming transceiver.

Background

With increasing demand for mobile network data throughput, mobile networks may move to higher frequencies for higher bandwidths, such as using the 5G (fifth generation) frequency range 2 (fr2) from 24,250mhz to 52,600mhz or the 30GHz to 300GHz or millimeter wave (mmWave) frequency band with wavelengths from 1 millimeter to 10 millimeters. Atmospheric attenuation is high compared to lower frequency bands because radio waves in these very high frequency radio bands are absorbed by gases in the atmosphere. Therefore, their distance is relatively short, resulting in high communication path loss in mmWave 5G mobile networks.

Disclosure of Invention

According to one aspect of the present disclosure, a transmitter includes one or more frequency synthesizers, a plurality of Intermediate Frequency (IF) local oscillators, a plurality of first data signal mixers, and a plurality of up-conversion mixers. Each frequency synthesizer is configured to generate a corresponding Radio Frequency (RF) local oscillator signal. Each IF local oscillator is configured to: receiving a first RF local oscillator signal of the one or more RF local oscillator signals; receiving a corresponding delay value of a plurality of delay values, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; and generating a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value. Each data signal mixer is configured to receive a first base data signal and a corresponding one of a plurality of first IF local oscillator signals and generate therefrom a corresponding one of a first plurality of IF data signals. Each up-conversion mixer is configured to receive a second one of the one or more RF local oscillator signals and a corresponding one of the plurality of first IF data signals and generate therefrom a beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

Optionally, in the foregoing aspect, each of the plurality of IF local oscillators is further configured to generate a second IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and offsetting the corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair. The transmitter may further include: a plurality of second data signal mixers, each second data signal mixer configured to receive a second base data signal and a corresponding second IF local oscillator signal of the plurality of second IF local oscillator signals and generate a corresponding second IF data signal of the plurality of second IF data signals therefrom. The first and second fundamental data signals are in-phase/quadrature pairs and the plurality of first IF data signals and the plurality of second IF data signals are a plurality of in-phase/quadrature IF data signal pairs. The plurality of up-conversion mixers are each further configured to receive a corresponding second signal of the plurality of first IF data signals, and the plurality of beamformed RF antenna signals are formed from a combined in-phase/quadrature IF data signal pair.

Optionally, in any preceding aspect, the transmitter further comprises: one or more control circuits configured to provide a plurality of delay values to the IF local oscillator.

Optionally, in any preceding aspect, the transmitter further comprises: a plurality of amplifiers connected to receive and amplify corresponding ones of the plurality of beamformed RF antenna signals.

Optionally, in the foregoing aspect, the transmitter further includes: the one or more control circuits are further configured to provide a plurality of delay values to the IF local oscillator and a corresponding gain factor to each amplifier of the plurality of amplifiers. Each amplifier is configured to amplify a received beamformed RF antenna signal of the plurality of beamformed RF antenna signals according to a corresponding gain factor.

Optionally, in any preceding aspect, the transmitter further comprises: a plurality of RF filters, each RF filter configured to receive and filter a corresponding beamformed RF antenna signal from the plurality of beamformed RF antenna signals.

Optionally, in any preceding aspect, the transmitter further comprises: an array of multiple antennas, each antenna configured to receive and transmit a corresponding beamformed RF antenna signal of the multiple beamformed RF antenna signals.

Optionally, in any preceding aspect, the number of frequency synthesizers is one, and the first RF local oscillator signal is the same as the second RF local oscillator signal.

Optionally, in any preceding aspect, the one or more frequency synthesizers comprise a first frequency synthesizer configured to provide a first RF local oscillator signal and a second frequency synthesizer configured to provide a second RF local oscillator signal.

Optionally, in any of the preceding aspects, each delay value specifies a delay of an integer number of cycles.

Optionally, in any preceding aspect, each delay value specifies a delay of a half integer number of cycles.

According to another aspect of the present disclosure, a method of transmitting a beamformed signal is provided. The method comprises the following steps: receiving, at each of a plurality of Intermediate Frequency (IF) local oscillators, a first Radio Frequency (RF) local oscillator signal and a corresponding delay value of a plurality of delay values, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; generating, at each IF local oscillator, a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and offsetting the first IF local oscillator signal by a corresponding delay value; at each of the plurality of first data signal mixers, a first base data signal and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals are received. Each first data signal mixer generates a first IF data signal from the first base data signal and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals. The second RF local oscillator signal and a corresponding first IF data signal of the plurality of first IF data signals are received at each of the plurality of up-conversion mixers. Each up-conversion mixer generates a corresponding beamformed RF antenna signal from the second RF local oscillator signal and a corresponding first IF data signal of the plurality of first IF data signals.

Optionally, in the foregoing aspect, the method further comprises: exchanging signals between a transmitter controller and a receiver one or more control signals; determining, by the transmitter controller, a delay value from the exchanged control signals; and providing the determined delay value from the transmitter controller to the IF local oscillator.

Optionally, in the foregoing aspect, the determining of the delay value comprises calculating, by the transmitter controller, the delay value from the exchanged control signals.

Optionally, in both of the foregoing aspects, the determining of the delay value comprises receiving the delay value from the receiver in an exchanged control signal.

Optionally, in the foregoing three aspects, the method further comprises: receiving, at each amplifier of a plurality of amplifiers, a corresponding beamformed RF antenna signal of a plurality of beamformed RF antenna signals and a corresponding gain factor; amplifying, at each amplifier, a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals according to a gain factor; determining, by the transmitter controller, a gain factor from the exchanged control signals; and providing the determined gain factor from the transmitter controller to the IF local oscillator.

Optionally, in any preceding aspect of the method of transmitting a beamformed signal, the method further comprises: generating a second IF local oscillator signal at each IF local oscillator by dividing the second RF local oscillator signal by an integer divide ratio and shifting the second IF local oscillator signal by a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair; receiving the second base data signal and a corresponding second IF local oscillator signal of the plurality of second IF local oscillator signals at each of a plurality of second data signal mixers; each second data signal mixer generating a second IF data signal from a second fundamental data signal and a corresponding second IF local oscillator signal of the plurality of second IF local oscillator signals, wherein the first fundamental data signal and the second fundamental data signal are in-phase/quadrature pairs and the plurality of first IF data signals and the plurality of second IF data signals are a plurality of in-phase/quadrature IF data signal pairs; and forming a combined in-phase/quadrature IF data signal pair, wherein generating, by each up-conversion mixer, a corresponding beamformed RF antenna signal from the second RF local oscillator signal and a corresponding first IF data signal of the plurality of first IF data signals comprises generating a corresponding beamformed RF antenna signal from a corresponding combined in-phase/quadrature IF data signal pair of the combined in-phase/quadrature IF data signal pair.

Optionally, in any preceding aspect of the method of transmitting beamformed signals, the method further comprises: each RF filter of the plurality of RF filters a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

Optionally, in any preceding aspect of the method of transmitting beamformed signals, the method further comprises: each antenna of the plurality of antennas transmits a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

Optionally, in any preceding aspect of the method of transmitting a beamformed signal, the RF local oscillator signal is the same as the second RF local oscillator signal.

According to additional aspects of the disclosure, a receiver comprises: one or more frequency synthesizers; a plurality of Intermediate Frequency (IF) local oscillators; a plurality of down-conversion mixers; and a plurality of first data signal mixers. The frequency synthesizers are each configured to generate a corresponding Radio Frequency (RF) local oscillator signal. Each IF local oscillator is configured to: receiving a first RF local oscillator signal of the one or more RF local oscillator signals; receiving a corresponding delay value of a plurality of delay values, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; and generating a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and offsetting the first RF local oscillator signal by a corresponding delay value. Each down conversion mixer is configured to receive a second one of the one or more RF local oscillator signals and an RF antenna signal of the plurality of RF antenna signals and to generate therefrom a corresponding first one of a plurality of first IF data signals; and each first data signal mixer is configured to receive a corresponding first IF data signal of the plurality of first IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals and to generate a first base data signal therefrom.

Optionally, in the aforementioned aspect, each IF local oscillator is further configured to generate a second IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and offsetting the corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair. The receiver further comprises: a plurality of second data signal mixers, each second data signal mixer configured to receive a corresponding second IF data signal of the plurality of second IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals and generate a second fundamental data signal therefrom, the first fundamental data signal and the second fundamental data signal forming a plurality of in-phase/quadrature fundamental data signal pairs.

Optionally, in any preceding aspect of the receiver, the receiver further comprises: one or more control circuits configured to provide a plurality of delay values to the IF local oscillator.

Optionally, in any preceding aspect of the receiver, the receiver further comprises: a plurality of amplifiers coupled to receive and amplify corresponding ones of the plurality of RF antenna signals and to provide each amplified RF antenna signal to a corresponding one of the plurality of down-conversion mixers.

Optionally, in the foregoing aspect, the one or more control circuits are further configured to provide the plurality of delay values to the IF local oscillator and to provide a corresponding gain factor to each amplifier of the plurality of amplifiers, wherein each amplifier is configured to amplify a received RF antenna signal of the plurality of RF antenna signals according to the corresponding gain factor.

Optionally, in any preceding aspect of the receiver, the receiver further comprises: a plurality of RF filters, each RF filter configured to receive and filter a corresponding RF antenna signal of the plurality of RF antenna signals.

Optionally, in any preceding aspect of the receiver, the receiver further comprises: an array of multiple antennas, each antenna configured to receive an RF signal and provide the RF signal to multiple down-conversion mixers.

Optionally, in any preceding aspect of the receiver, the number of frequency synthesizers is one, and the first RF local oscillator signal is the same as the second RF local oscillator signal.

Optionally, in any preceding aspect of the receiver, the one or more frequency synthesizers comprise a first frequency synthesizer configured to provide a first RF local oscillator signal and a second frequency synthesizer configured to provide a second RF local oscillator signal.

Optionally, in any preceding aspect of the receiver, each delay value specifies a delay of an integer number of cycles.

Optionally, in any preceding aspect of the receiver, each delay value specifies a delay of half an integer number of cycles.

According to another aspect of the present disclosure, there is provided a method of receiving a Radio Frequency (RF) signal, including: receiving, at each of a plurality of Intermediate Frequency (IF) local oscillators, a first RF local oscillator signal and a corresponding delay value of a plurality of delay values, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; generating, by each IF local oscillator, a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and shifting the first IF local oscillator signal by a corresponding delay value; receiving, at each of a plurality of down-conversion mixers, a second RF local oscillator signal and a corresponding RF antenna signal of a plurality of RF antenna signals; generating, at each of a plurality of down-conversion mixers, a corresponding first IF data signal of a plurality of first IF data signals from a second RF local oscillator signal and a corresponding RF antenna signal; receiving, at each of a plurality of first data signal mixers, a corresponding first IF data signal of a plurality of first IF data signals and a corresponding first IF local oscillator signal of a plurality of first IF local oscillator signals; and generating, at each of the plurality of first data signal mixers, a first base data signal from a corresponding first IF data signal of the plurality of first IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals.

Optionally, in the foregoing aspect of the method of receiving an RF signal, the method further comprises: exchanging signals between a receiver controller and a transmitter one or more control signals; determining, by the receiver controller, a delay value from the exchanged control signals; and providing the determined delay value from the receiver controller to the IF local oscillator.

Optionally, in the aforementioned aspect of the method of receiving RF signals, the determining of the delay value comprises calculating, by the receiver controller, the delay value from an exchanged control signal.

Optionally, in any of the preceding two aspects of the method of receiving RF signals, the determining of the delay value comprises receiving the delay value from the transmitter in an exchanged control signal.

Optionally, in any of the preceding three aspects of the method of receiving RF signals, the method further comprises: receiving, at each amplifier of a plurality of amplifiers, a corresponding RF antenna signal of a plurality of RF antenna signals and a corresponding gain factor; amplifying, at each amplifier, a corresponding RF antenna signal of the plurality of RF antenna signals according to a gain factor; the receiver controller determines a gain factor based on the exchanged control signals; and providing the determined gain factor from the receiver controller to the IF local oscillator.

Optionally, in any of the preceding aspects of the method of receiving RF signals, the method further comprises: each IF local oscillator generating a second IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and offsetting the corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair; receiving, at each of a plurality of second data signal mixers, a corresponding second IF data signal of the plurality of second IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals; and generating at each second data signal mixer a corresponding second base data signal from a corresponding second IF data signal of the plurality of second IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals, the first base data signal and the second base data signal forming a plurality of in-phase/quadrature base data signal pairs.

Optionally, in any of the preceding aspects of the method of receiving RF signals, the method further comprises: filtering is performed at each of the plurality of RF filters, filtering a corresponding RF antenna signal of the plurality of RF antenna signals.

Optionally, in any of the preceding aspects of the method of receiving RF signals, the number of frequency synthesizers is one, and the first RF local oscillator signal is the same as the second RF local oscillator signal.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the background.

Drawings

Aspects of the present disclosure are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate elements.

Fig. 1 illustrates a wireless network for communicating data.

Fig. 2 is a block diagram of a wireless communication system that may be used in a network such as that of fig. 1.

Fig. 3 is a block diagram of one embodiment of a beamforming transmitter that uses a high frequency local oscillator clock edge to introduce a delay value on an intermediate frequency local oscillator path.

Fig. 4 shows an Intermediate Frequency Local Oscillator (IFLO) in the N paths of the intermediate frequency local oscillator generation block 210.

Fig. 5 is a block diagram of an embodiment of a beamforming transmitter using quadrature Radio Frequency Local Oscillator (RFLO) upconversion and a high frequency local oscillator clock edge to introduce a delay value on an intermediate frequency local oscillator path.

Fig. 6A and 6B show the outputs of the non-image reject superheterodyne embodiment of fig. 3 and the image reject superheterodyne embodiment of fig. 5, respectively.

Fig. 7 is a block diagram of an embodiment of a beamforming transmitter including a dedicated frequency synthesizer for generating an intermediate frequency local oscillator signal.

Fig. 8 is a flow diagram of an embodiment for forming a set of beamformed signals, wherein phase shifts/delays for forming the beams are introduced in the IFLO generation block.

Figure 9 is a block diagram of an embodiment of a receiver that uses high frequency local oscillator clock edges to control various intermediate frequency local oscillator clock generation blocks to introduce delay values on the intermediate frequency local oscillator path.

FIG. 10 is a block diagram of an embodiment of a receiver that uses quadrature RFLO down conversion and introduces a predefined delay value on an intermediate frequency local oscillator path using a high frequency local oscillator clock edge.

Fig. 11 is a block diagram of an embodiment of a transmitter including a dedicated frequency synthesizer for generating an intermediate frequency local oscillator signal in an IFLO generation block.

Fig. 12 is a flow diagram of an embodiment for receiving a set of antenna signals and applying the phase shift/delay introduced in the IFLO generation block to extract the data content based on the embodiments of fig. 9-11.

Detailed Description

The present disclosure will now be described with reference to the accompanying drawings, which generally relate to techniques for improving communication signal transmission as networks advance to higher frequency ranges. As the demand for mobile network data throughput increases, mobile networks can use higher frequencies to achieve high bandwidth. For example, the mobile network may start communicating in the 5G frequency range 2 (FR 2) from 24250MHz to 52600MHz and the 5G millimeter wave (mmWave) frequency range from 30GHz to 300 GHz. In mmWave 5G mobile networks, the path loss is high, which means that beamforming capabilities can be used to provide high antenna gain in order to overcome the loss. In addition, beamforming may reduce interference between different users, which is also desirable in mobile networks. To implement beamforming, using the example of a transmitter (Tx), a signal is constructed from a plurality of paths having a defined phase-shift relationship between the paths. In the techniques described below, a set of intermediate frequency beamformed signals are generated by introducing a phase shift based on the number of cycles of the higher frequency local oscillator signal used to upconvert the set of intermediate frequency signals. The set of intermediate frequency signals having a defined phase shift relationship is then mixed with a data signal, such as an in-phase/quadrature (I/Q) data signal, and then upconverted to generate a set of beamformed signals that are provided to an antenna array.

It should be understood that the present embodiments of the disclosure may be embodied in many different forms and that the scope of the claims should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of embodiments of the invention to those skilled in the art. Indeed, the present disclosure is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be apparent to one of ordinary skill in the art that the present embodiments of the disclosure may be practiced without these specific details.

Fig. 1 illustrates a wireless network for communicating data. Communication system 10 includes, for example, user equipment 11A-11C, radio Access Networks (RANs) 12A-12B, a core network 13, a Public Switched Telephone Network (PSTN) 14, the internet 15, and other networks 16. Additional or alternative networks include private and public packet data networks, including corporate intranets. Although some number of these components or elements are shown, any number of these components or elements may be included in the system 10.

In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station that employs orthogonal frequency-division multiplexing (OFDM) and/or non-OFDM and Transmission Time Interval (TTI) shorter than 1 millisecond (ms), e.g., 100 or 200 microseconds, to communicate with the communication device. In general, reference to a base station may refer to any one of an eNB and a 5G base station (gNB). Additionally, the network may further include a network server for processing information received from the communication device via at least one eNB or gNB base station.

System 10 enables multiple wireless users to send and receive data and other content. System 10 may implement one or more channel access methods such as, but not limited to, code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), frequency Division Multiple Access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

User Equipments (UEs) 11A-11C are configured to operate and/or communicate in system 10. For example, the user devices 11A-11C are configured to transmit and/or receive wireless signals or wired signals. Each user equipment 11A-11C represents any suitable end-user device and may include such devices as (or may be referred to as) user equipment/devices, wireless transmit/receive Units (UEs), mobile stations, fixed or mobile subscriber units, pagers, cellular telephones, personal Digital Assistants (PDAs), smart phones, laptops, computers, touch pads, wireless sensors, wearable devices, or consumer electronic devices.

In the illustrated embodiment, the RANs 12A-12B each include one or

more base stations

17A, 17B (collectively referred to as base stations 17). Each of the base stations 17 is configured to wirelessly interface with one or more of the

UEs

11A, 11B, 11C to allow access to the core network 13, PSTN 14, internet 15, and/or other networks 16. For example, the Base Station (BS) 17 may include one or more of several well-known devices, such as a Base Transceiver Station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a home NodeB, a home eNodeB, a site controller, an Access Point (AP), or a wireless router, or a server, a router, a switch, or other processing entity with a wired or wireless network.

In one embodiment, the base station 17A forms a portion of the RAN12A, and the RAN12A may include other base stations, elements, and/or devices. Similarly, the base station 17B forms a portion of the RAN 12B, and the RAN 12B may include other base stations, elements, and/or devices. Each of the base stations 17 transmits and/or receives wireless signals within a particular geographic region or area (sometimes referred to as a "cell"). In some embodiments, multiple-input multiple-output (MIMO) technology may be employed, with multiple transceivers for each cell.

The base station 17 communicates with one or more of the user equipment 11A-11C over one or more air interfaces (not shown) using a wireless communication link. The air interface may employ any suitable radio access technology.

It is contemplated that system 10 may use multi-channel access functionality including, for example, schemes in which base station 17 and user equipment 11A-11C are configured to implement long term evolution wireless communication standard (LTE), LTE-Advanced (LTE-a), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base station 17 and the user equipment 11A-11C are configured to implement UMTS, HSPA or HSPA + standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized.

The RANs 12A-12B communicate with a core network 13 to provide Voice, data, applications, voice over Internet Protocol (VoIP), or other services to the user devices 11A-11C. As is understood, the RANs 12A-12B and/or the core network 13 may be in direct or indirect communication with one or more other RANs (not shown). The core network 13 may also serve as a gateway access for other networks, such as the PSTN 14, the internet 15, and other networks 16. Additionally, some or all of the user devices 11A-11C may include functionality to communicate with different wireless networks over different wireless links using different wireless technologies and/or protocols.

The RANs 12A-12B may also include millimeter and/or microwave Access Points (APs). The AP may be part of the base station 17 or may be located remotely from the base station 17. The AP may include, but is not limited to, a connection point (mmW CP) or a base station 17 capable of mmW communication (e.g., mmW base station). mmW APs may transmit and receive signals in a frequency range, for example, from 24GHz to 100GHz, but need not operate over the entire range. As used herein, the term "base station" is used to refer to a base station and/or a wireless access point.

Although fig. 1 illustrates one example of a communication system, various changes may be made to fig. 1. For example, communication system 10 may include any number of user devices, base stations, networks, or other components in any suitable configuration. It should also be understood that the term "user equipment" may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are target devices, device-to-device (D2D) user equipment, machine-class user equipment, or machine-to-machine (M2M) communication capable user equipment, laptops, PDAs, ipads, tablets, mobile terminals, smart phones, laptop Embedded Equipment (LEEs), laptop Mounted Equipment (LMEs), and USB dongles.

Fig. 2 is a block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A-11C or base station 17, showing some of the elements discussed below. To transmit the output signal from the circuit elements of the processor 111, the transmitter (Tx) RF/analog section 101 up-converts the output signal from an Intermediate Frequency (IF) range to a Radio Frequency (RF) range, amplifies, filters,and may perform other processing before providing the transmit signal to the antenna 105. The output signal is provided in-phase/quadrature (I/Q) format to the Tx RF/analog section 101 as in-phase and quadrature signals I generated by the Tx digital baseband block 107 _Tx And Q _Tx . Although the Tx digital baseband block 107 is shown in fig. 2 as a separate block from the Tx RF/analog section 101, these elements may be combined differently into circuit elements and implemented in hardware, firmware, software, or a combination thereof according to embodiments.

The signal is received by an antenna 105 and provided to a receiver (Rx) RF/analog section 102. The Rx part 102 performs any required or desired signal processing such as down-conversion and filtering from the Radio Frequency (RF) range to the Intermediate Frequency (IF) range and then passes the signal to other components on the device represented at the processor 111. In the embodiment of fig. 2, the output of the Rx RF/analog section 102 is in I/Q format, which the Rx digital baseband section 117 converts into a receive signal provided to the processor. Although the Rx digital baseband section 117 is shown in fig. 2 as a separate block from the Rx RF/analog section 102, these elements may be combined differently into circuit elements and implemented in hardware, firmware, software, or a combination thereof, according to embodiments. Furthermore, although fig. 2 represents Tx RF/analog section 101 and Rx section RF/analog 102 as separate elements, the transmitter and receiver paths may share many elements or be implemented as a combined transceiver, depending on the embodiment. Hereinafter, "transceiver" may be used generally to refer to a combined transmitter/receiver, separate transceiver and receiver portions, or embodiments in which one or more components (e.g., local oscillators) are shared between a transmitter and a receiver.

To increase the data throughput of mobile networks, mobile networks may move to higher frequency ranges, such as millimeter wave (mmWave) in the range of 30GHz to 300 GHz. At such frequencies, the path loss is high, so the beamforming capability may be important to provide high antenna gain to overcome the loss. In addition, beamforming may reduce interference between different users, which is also desirable in mobile networks. To implement beamforming, using a transmitter (Tx) mobile station as an example, it is necessary to construct a signal from multiple paths with a defined phase shift relationship between the paths. A plurality of signals are transmitted from a corresponding array of antennas, and the relative phase shifts or delays are selected so that the respective antenna signals constructively interfere to form a beam at the receiver location and destructively interfere away from the receiver location.

There are different ways to achieve the relative phase shift of the component beamformed signals, ranging from purely digital phase shift implementations to RF delay line implementations. In general, digital phase shift implementations require N complete signal paths to form a set of N beamformed signals and result in high power consumption/large chip size; RF delay line implementations suffer from phase shift accuracy issues and have high losses, which means high power consumption. To help overcome these difficulties, alternative techniques for achieving fine phase shift control and low power consumption/small chip size are described below.

In applications with higher output (Tx) and input (Rx) frequencies, such as 5G mm wave mobile applications, the transmitter and receiver paths require high frequency clock generation capability regardless of beamforming. Embodiments presented herein take advantage of this capability to provide fine delay control in N beamforming paths by using a high frequency clock to control a lower frequency clock. For example, in a super-heterodyne architecture, a high frequency local oscillator clock (RFLO clock) is available. The Intermediate Frequency Local Oscillator (IFLO) clock may be generated by frequency division of the RFLO clock. By using high frequency RFLO clock edges to control the various IFLO clock generation blocks, delay values may be implemented on the IFLO paths. The IFLO path delay will be translated to the signal path by the IF mixer conversion process so that the transmitter or receiver can achieve the target signal path delay through IFLO clock edge control. Delay (τ) by ω _IF * τ is converted into a phase shift, where ω _IF Is the frequency of the IF signal, the different delays between the N paths provide different phase shifts between the N paths.

To describe these techniques, one transmitter example is first used. In a first example, assuming a Tx output frequency of 50ghz and an iflo frequency of RFout/25=2ghz, a total of N paths are used for beamforming. The selection of the IFLO frequency is relevant and will be discussed later. Fig. 3 is a block diagram illustrating this concept.

Fig. 3 is a block diagram of one embodiment of a beamforming transmitter using high frequency local oscillator clock edges to control various intermediate frequency local oscillator clock generation blocks to introduce defined delay values on the intermediate frequency local oscillator path. The transmitter (Tx) 201 of fig. 3 may correspond to the Tx RF/analog section 101 of fig. 2 and the I and Q data may correspond to in-phase/quadrature (I/Q) data I, respectively, from the Tx digital baseband block 107 of fig. 2 _Tx And Q _Tx Data, and antenna arrays 245-1, 245-2, \ 8230;, 245-N correspond to antenna 105 of fig. 2.

The beamforming transmitter Tx 201 comprises a high frequency synthesizer 203, which high frequency synthesizer 203 has an output frequency Fout =48GHz in this example, which output frequency also serves as an up-converted RF local oscillator signal RFLO at mixer 237-i and as an input frequency Freq1 of the IFLO generation circuit 210. The input frequency Freq1 (= Fout in this embodiment) is supplied to N intermediate frequency local oscillator generators IFLO Gen _ i 211-i (i.e. 211-1, 211-2, \ 8230;, 211-N, where i =1, 2, \ 8230;, N), each IFLO Gen _ i 211-i dividing Freq1 by a division factor of 24 to provide an intermediate frequency signal of 2GHz. In the embodiment presented in FIG. 3 and subsequent figures, the data is in I/Q format, with the output of each IFLO Gen _ I211-I being I/Q vs-IFLO I and IFLO Q.

To introduce a relative delay into each IFLO signal, each IFLO Gen _ i 211-i receives a delay value di. The delay is the number of cycles of the Freq1 signal, which may be an integer number of cycles or a half-integer number of cycles (i.e., 0, 1/2, 1, 3/2, 5/2 \8230;) according to an embodiment. Each intermediate frequency signal will have its leading edge locked to a corresponding edge of the high frequency signal Freq1 based on the corresponding delay value. For example, each IFLO signal will have its leading edge locked to each of the corresponding Freq1 signals, where this may be the leading edge of the Freq1 signal when di is an integer value, or the leading or trailing edge for half-integer values. This is schematically represented by the waveform at the input of each IFLO Gen _ i 211-i, and is described in more detail below with reference to FIG. 4.

The delay values d1, d2, \ 8230, dn are provided by control block 207. The control block may be one or more control circuits, and these elements may be variously combined into circuit elements and implemented in hardware, firmware, software, or a combination thereof according to embodiments. Referring back to fig. 1, the control 207 may be part of the processor 111, a separate control element dedicated to beamforming in the Tx RF/analog portion 101, or some combination thereof. Since the delays d1, d2, \ 8230, dn are the relative delays of each path, these may be provided as N separate values; alternatively, in other embodiments, only (n-1) delays may be provided, as, for example, the delay at IFLO Gen _1 211-1 may be fixed to 0, and another (n-1) delays are provided from control 207 relative to the signal. Since the delay will be a multiple of the same basic delay for evenly spaced antennas, the di value can be provided only from the basic differential delay. In addition to a set of relative delays or equivalent phases introduced into each of a set of beamformed signals of the antenna array, in some embodiments, a relative amplitude difference may be introduced into each signal. The corresponding relative amplitudes may be provided by control 207 as represented by gain values g1, g2, \ 8230;, gn provided to corresponding amplifiers 241-1, 241-2, \ 8230;, 241-N, as described below.

Based on the characteristics of the transmitter antenna array (245-1, 245-2, \ 8230;, 245-N), a set of relative delays and relative amplitudes for embodiments using them are selected to form a beam at the location of the receiver antenna. Thus, when transmitting to multiple receivers, each receiver has its own set of parameters. The parameter values may be determined based on signals exchanged between the transmitter and the receiver. In some embodiments, this may be based on pilot signals exchanged between the receiver and the transmitter, which may then be used to determine parameters at the transmitter or receiver, in which case they may be sent back to the transmitter over the control channel. The pilot signals may also be transmitted over the control channel, where the signals may be in-band control signals or out-of-band using a particular control signal channel. In other embodiments, the determination or updating of the parameter may alternatively or additionally be determined by monitoring the data signal itself.

The in-phase and quadrature outputs IFLO I and IFLO Q of each IFLO Gen _ I211-I are provided to corresponding in-phase data mixers 231-I and quadrature data mixers 233-I, respectively. In the embodiment of fig. 3, the I/Q base data signal is received in digital form. The I fundamental data signal is received at a digital-to-analog converter DAC I221, may pass through a low pass filter LPF I223, and then to each in-phase data mixer 231-I, where each mixer receives the same in-phase data signal I. The Q fundamental data signal is received at a digital-to-analog converter DAC Q225, may pass through a low pass filter LPF Q227, and then to each quadrature data mixer 233-i, where each mixer receives the same quadrature data signal Q. The I/Q pairs from each data mixer pair 231-I/233-I are combined to form an I/Q IF data signal and passed to a corresponding buffer/driver 235-I.

In this example, the frequency of the IF data signal is Freq1/24=2ghz. To upconvert each IF I/Q data signal pair, the combined output of the data mixer pair 231-I/233-I is an input of 235-I to a respective upconversion mixer 237-I, each upconversion mixer 237-I also receiving the RFLO signal from the frequency synthesizer 203 (48 GHz in this example). The result of the set of RF signals is a set of I/Q beamformed RF data signals of 50GHz for the antenna array. Each upconverted I/Q data signal is then amplified by a corresponding amplifier 241-I, where the gain of all amplifiers may be the same or set separately with a gain gi from control 207 to assist in beamforming, depending on the embodiment. As discussed in more detail below, the beamformed RF I/Q group data signals for the antennas may also be filtered at 243-I before going to the corresponding antennas 245-I of the antenna array.

For the entire operation, in the embodiment of fig. 3, the baseband digital I/Q data (I data, Q data) is converted to analog signals by the DACs of the I path and Q path (221, 225, respectively). The low pass filter LPF223/227 for the I/Q path is applied to remove any noise/distortion from the DAC 221/225 and the LPF output signal is fed to the IF mixer 231-I/233-I for quadrature upconversion. The phase shift/delay occurs in the IFLO quadrature generation block 210. After IF upconversion at the data mixer pair 231-i/233-i, another RF upconversion block of the RF upconversion mixer 237-i is used to convert the signal to the final radio frequency of the set of beamformed antenna signals. In this example, this RF up-conversion is done by a single mixer per path, i.e. in a non-quadrature fashion. An amplifier 241-i is used after the RF mixer 237-i. After the amplifiers 241-i, filters 243-i may be used, depending on the image (from RF non-quadrature upconversion) requirements. Finally, the N antenna signals are transmitted to the N antennas 245-i for beamforming.

In the arrangement of fig. 3 and other embodiments presented below, the critical phase shift/delay is not implemented directly in the signal path as in the prior art, but in the IFLO generation block 210. By synchronizing the N IFLO generation blocks 211-i to different edges of the input high frequency clock, the triggering edge generated by each IFLO may be delayed by a target value with respect to, for example, the first path IFLO generation block 211-1. This means that the IFLO generation block 210 can achieve the target delay/phase shift in all N paths.

Fig. 4 shows the synchronized intermediate local frequency oscillator signals in the N paths of the IFLO generation block 210. As shown in FIG. 3, in the example of FIG. 4, the RFLO also has a frequency of 48GHz, and the IFLO has a frequency of 2GHz, so the divide ratio is 24, so that 24 cycles of the RFLO clock fit into one cycle of the IFLO clock. The example of fig. 4 assumes that the goal is to achieve 0 x minimum delay for path 1, 1 x minimum delay for path 2, 2 x minimum delay for path 3, and so on. (in this example, the minimum value of delay is phase shift resolution, but in practice this will vary from case to case). Thus, as shown in FIG. 4, the leading edge of the IFLO 1 waveform is aligned with the first RFLO leading edge, the leading edge of the IFLO2 waveform is aligned with the second RFLO leading edge, the leading edge of the IFLO 3 waveform is aligned with the third RFLO leading edge, and so on for the remaining ones of the N IFLO waveforms.

In the case where the example frequency division ratio shown in fig. 4 is 24, each duty cycle (360-degree phase shift) of the RFLO clock (48 GHz) represents 360/24= 15-degree phase shift in the IFLO clock (2 GHz). If both rising and falling edges (i.e., half integer delay values) are used, half the LO domain duty cycle (180 degrees) represents 180/24=7.5 degrees in the 2GHz IFLO domain.

In general, the resolution of the phase shift depends on the ratio of RFLO to IFLO, so, assuming that both rising and falling edges are used, 48GHz RFLO to 2GHz IFLO (ratio of 24) provides a phase shift resolution of 180/24=7.5 degrees. Since this scheme uses high frequency clock (RFLO) edges to control delay, it can achieve more accurate delay than RF delay line implementations, depending on RFLO clock quality. In addition, since the delay is implemented in the IF upconversion block, the digital/DAC/LPF circuit does not have to be repeated N times, thereby enabling lower power consumption relative to a digital delay implementation.

With respect to IFLO frequency selection, a higher RFLO to IFLO ratio is preferred from a fine phase shift resolution perspective; however, a very low IFLO may cause image distortion problems for the RFLO upconversion process. The example RFLO upconversion of FIG. 3 is non-orthogonal and will generate the desired (RFLO + IFLO) and undesired (RFLO-IFLO) frequencies, so the image content (RFLO-IFLO) should be reduced to avoid interference with other users. Setting the IFLO frequency high enough so that the LO-IF distortion is outside the TX band, and using RF filters 243-i can reduce the undesirable image level. Furthermore, the antenna array and its individual antennas 245-i will typically be frequency selective, thus reducing the image distortion level. Finally, the beamforming itself is frequency dependent, meaning that the image distortion level is filtered when it reaches the target receiver. Therefore, a higher IFLO frequency makes things easier from the perspective of reducing image distortion. In this example, a balanced RFLO to IFLO ratio is selected.

The possibility of RFLO image distortion may be addressed in other ways. The embodiment of fig. 5 gives an example of using orthogonal RFLO up-conversion.

Fig. 5 is a block diagram of an embodiment of a beamforming transmitter 401 using quadrature RFLO up-conversion and using high frequency local oscillator clock edges to control various intermediate frequency local oscillator clock generation blocks to introduce delay values on the intermediate frequency local oscillator path. Fig. 5 includes a number of elements corresponding to those of fig. 3, which are similarly numbered (i.e., control 207/407, frequency synthesizer 203/403, IFLO generation block 210/410, etc.), and which may function as described above with respect to fig. 3.

In the embodiment of fig. 5, the frequency Fout = Freq1 of the frequency synthesizer 403 is now doubled to 96GHz, relative to fig. 3. In IFLO generation block 410, each IFLO Gen _ i 411-i now divides Freq1 by 48 and provides cos (ω) as _IF *t)、sin(ω _IF * t) and-sin (ω) _IF * t) 2GHz IF output. cos (omega) _IF * t) are separated and provided to the in-phase data signal mixer 451-i and the quadrature data signal mixer 457-i. sin (omega) _IF * t) output is provided to quadrature data signal mixer 453-i, and-sin (ω) _IF * t) is provided to the in-phase data signal mixer 455-i. In-phase cos (ω) _IF * t)/orthogonal sin (ω) _IF * t) pairs are combined and enter a buffer/driver 461-i, in-phase-sin (ω) _IF * t)/orthogonal cos (ω) _IF * t) pairs are combined and enter the buffer/driver 463-i, followed by RF up-conversion at the respective RF up-conversion mixers 465-i and 467-i.

In fig. 5, for RF up-conversion, the output of frequency synthesizer 403 at Fout =96GHz now enters RFLO generator 459 to generate cos (ω) at 48GHz _RF * t) and sin (ω) _RF * t) which are provided to RF up-conversion mixers 465-i and 467-i, respectively, to be combined with the outputs of 461-i and 463-i. The outputs of the pair of RF up-conversion mixers are then provided to the corresponding amplifiers 441-i. With respect to fig. 3, the output of amplifier 441-i is provided to antenna 445-i without an intermediate filter, because the embodiment of fig. 5 will not have the undesired LO-IFLO frequency as part of the image content, as shown below with respect to fig. 6A and 6B.

The quadrature RFLO upconversion embodiment of fig. 5 doubles the number of mixers (IF mixer and RF upconversion mixer) in each Tx path relative to the embodiment of fig. 3. Fig. 5 shows a single ended circuit, but in a practical implementation this is typically a differential circuit, which would use available-sin (ω) _IF * t) IFLO signal. In addition, to generate the quadrature clocks, frequency synthesizer block 403 generates clocks at least twice the RFLO clock rate, or in FIG. 5In an example of (c) is 96GHz. The higher clock frequency and higher power consumption of the embodiment of FIG. 5 is a compromise to reduce the (RFLO-IFLO) image level of FIG. 3.

Fig. 6A and 6B show the output of the non-image reject superheterodyne embodiment of fig. 3 and the image reject superheterodyne embodiment of fig. 5, respectively. In both fig. 6A and 6B, the signal level in decibels is plotted against frequency. FIG. 6A shows an example RFLO upconversion of the embodiment of FIG. 3 that is non-orthogonal and generates a desired (LO + IFLO) frequency (higher frequency peak) and an undesired (LO-IFLO) frequency (lower frequency peak). To remove the image content at (LO-IFLO), a filter 243-i may be used to reduce this peak to avoid interference with other users. FIG. 6B illustrates an example of quadrature RFLO upconversion of the embodiment of FIG. 5, lacking undesirable (LO-IFLO) image content. Since the (LO-IFLO) image content is suppressed, no RF filter for the set of antenna signals is used in the embodiment of fig. 6B.

Another variation of this architecture is to use a dedicated IFLO generation block, such as a Phase Locked Loop (PLL), which may be implemented in the embodiments of fig. 3 or 5. Fig. 7 is a block diagram of an embodiment similar to that of fig. 3, but incorporating a dedicated frequency synthesizer.

Fig. 7 is a block diagram of an embodiment of a beamforming transmitter 601 comprising a dedicated frequency synthesizer (frequency synthesizer 2 605) for generating an intermediate frequency local oscillator signal in an IFLO generation block 610. Fig. 7 repeats a number of elements corresponding to elements of fig. 3, which are similarly numbered (i.e., control 207/607, frequency synthesizer 203/603, IFLO generation block 210/610, etc.), and which may function as described above with respect to fig. 3.

With respect to fig. 3, in the embodiment of fig. 7a second frequency synthesizer 2 605, e.g. a PLL, is included which provides Freq1 to the IFLO generation block 610. In this example, freq1 is again taken to be 48GHz and the division ratio 24 is again used to generate the IFLO signal at 2GHz. Fout from the frequency synthesizer 603 can now be set independently of Freq1, providing greater flexibility. In the example of fig. 6, fout =50GHz. Since RFLO is now at 50GHz, the up-conversion at mixer 637-i produces a set of beamformed antenna signals at RFout =52 GHz.

In the embodiment of FIG. 7, dedicated frequency synthesizer 2 605 allows the IFLO frequency to be set to a constant, which may be helpful in signal path design in some cases, since the output of RFLO frequency synthesizer 603 is no longer used as an input to IFLO generation block 610. Because Freq1 is constant in the embodiment of fig. 7, frequency synthesizer 2 605 may be simpler than frequency synthesizer 603 block: for example, frequency synthesizer 2 605 may be an integer PLL instead of a fractional-N phase locked loop (Frac-NPLL). For the embodiment of fig. 5, additional dedicated frequency synthesizers may similarly be introduced for the IFLO generation block 410.

The beamforming transmitter presented above performs phase shifting/delaying to form beams in the IFLO generation block 210/410/610, an arrangement that is different from previous beamforming schemes. The scheme presented here does not use a signal path for phase shifting, but rather uses the clock generation block 210/410/610 to introduce phase shifting. This means that no signal path loss is introduced even IF the phase shift is done in the IF domain. Furthermore, the phase shift generated based on the IFLO is a balanced scheme compared to prior art techniques that use digital phase shift or RF delay line phase shift. The scheme proposed here requires fewer circuit blocks than digital phase shift implementations; and has better delay control accuracy and lower signal path loss than RF delay line phase shift implementations.

Fig. 8 is a flow diagram of an embodiment for forming a set of beamformed signals, wherein phase shifts/delays for forming the beams are introduced in the IFLO generation block. At 701, control block 207/407/607 receives or determines a delay value (d 1, d2, \8230;, dn). These values may be determined based on signals exchanged between the transmitter 201/401/601 and the receiver, where the signals may be data signals or control signals, such as beacons, either in-band on a data signal channel or through an out-of-band control channel. Depending on the embodiment, the delay may be calculated in the control block 207/407/607 or sent by the receiver to the control block.

At 703, each of IFLO211-i/411-i/611-i receives a first RFLO signal Freq1 (From frequency synthesizer 203/403 or frequency synthesizer 2 603) and from control 207/407/607. At 705, each of IFLO211-i/411-i/611-i generates an IFLO signal having a corresponding specified delay. In the embodiments of fig. 3 and 7, these are the respective IFLO I and IFLO Q signals, and in the embodiment of fig. 5, is cos (ω) _IF *t)、-sin(ω _IF * t) homorelative sum sin (ω) _IF *t)、cos(ω _IF * t) orthogonal pairs.

At 707, each data signal mixer (231-I/451-I for I, 455-I/631-I, and 233-I/453-I for Q, 457-I/633-I) receives the IF data signals (I data from LPF 1/423/623 and Q data from LPF 2227/427/627) and the corresponding IFLO signal. The data signal mixer then generates an IF data signal at 709.

At 711, each up-conversion mixer (237-i/465-i, 467-i/637-i) receives a second RFLO signal (Fout from 203/603, or cos (ω) from RFLO Gen 459 _IF *t)、sin(ω _IF * t)) and the corresponding IF data signal from one of the data signal mixers. (in the embodiments of FIGS. 3 and 5, the 703 second RFLO signal and the 703 first RFLO signal both originate from the frequency synthesizers 203/403). At 713, each up-conversion mixer generates one of a set of beamformed RF antenna signals, which may then be amplified, filtered, and passed to antenna arrays 245-1, 245-2, \ 8230;, 245-N, according to an embodiment.

Similar techniques can also be applied to receivers, as in the transmitter case described above, with much of the discussion of the transmitter also applying to the receiver case. Fig. 9, 10 and 11 present examples of receiver embodiments corresponding to the transmitter embodiments of fig. 3, 5 and 7, respectively. Although the receiver and transmitter embodiments are described separately, in some embodiments, components (e.g., the IFLO generation block, antenna array, etc.) may be shared between the transmitter and receiver sides, or both may be implemented as transceivers. Referring back to fig. 2, the transceiver embodiments presented below may correspond to the Rx RF/analog section 102.

Fig. 9 is a block diagram of an embodiment of a receiver 802 that uses a high frequency local oscillator clock edge to control various IFLO clock generation blocks to introduce delay values on an intermediate frequency local oscillator path. The example of fig. 9 uses a single frequency synthesizer with non-quadrature RF downconversion using an architecture similar to that of fig. 3, including a plurality of elements corresponding to and similarly numbered with the elements of fig. 3 (i.e., control 207/807, frequency synthesizer 203/803, IFLO generation block 210/810, etc.). In particular, the frequency synthesizer 803, control 807 and IFLO generation block 810 may operate as described above with reference to FIG. 3. Since fig. 9 is a receiver, rather than the transmitter of fig. 3, the elements on the right presented in fig. 9 are now arranged "in reverse" with respect to fig. 3, since signals are received from the antenna arrays 845-1, \8230;, 845-N and I/Q data are extracted.

More specifically, each antenna 845-i receives an RF signal from a transmitter, which may then be filtered at a corresponding RF filter 843-i and amplified in a corresponding amplifier 841-i. In some embodiments, each amplifier 841-i may individually set its differential gain gi based on the value provided by control 807. In the example of fig. 9, the received RF frequency is RFin =50GHz. The RF antenna signals are then each down-converted at a corresponding down-conversion mixer 837-i using an RFLO signal, which in this example is 48GHz, to produce a 2GHz down-converted antenna signal that enters the buffer/driver 835-i in each path.

To extract the I/Q data, each downconverted antenna signal enters an in-phase data signal mixer 831-I, which also receives an IFLO-I signal with a corresponding delay di from IFLO GEN _ I811-I, and a quadrature data signal mixer 833-I, which also receives an IFLO-Q signal with a corresponding delay di from IFLO GEN _ I811-I. The I and Q signals from the I and Q data signal mixers may then be filtered at LPF I823 and LPF Q827, respectively, and digitized in analog-to-digital converters ADC I821 and ADC Q825 to provide I/Q base data signals.

Fig. 10 is a block diagram of an embodiment of a receiver 902 that uses quadrature RFLO down conversion and uses high frequency local oscillator clock edges to control various intermediate frequency local oscillator clock generation blocks to introduce predefined delay values on the intermediate frequency local oscillator path. Thus, fig. 10 is a receiver counterpart of the transmitter embodiment of fig. 5. On the left, as shown, FIG. 10 includes a number of elements corresponding to those of FIG. 5, which are similarly numbered (i.e., control 407/907, frequency synthesizer 403/903, RFLO Gen 459/959, and IFLO generation block 410/910), and which may function as described above with respect to FIG. 5.

As shown in fig. 9, the elements shown on the right side of fig. 10 are arranged as a receiver 902, thereby receiving signals from antenna arrays 945-1, \ 8230;, 945-N and extracting I/Q data. More specifically, each antenna 945-i receives an RF signal from a transmitter, which may then be amplified in a corresponding amplifier 941-i. In some embodiments, each amplifier 941-i may individually set its differential gain gi based on the value provided by control 907. In the example of fig. 10, the received RF frequency is RFin =50GHz. In the quadrature RFLO down conversion of fig. 10, the RF filter between the antenna and the amplifier is not included, similar to the transmitter embodiment of fig. 5, and as discussed with respect to fig. 6A and 6B. Then, at the corresponding I/Q down-conversion mixers 965-I/965-I, a RFLO GEN signal of 48GHz (cos (ω) in this example) is used _RF * t) and sin (ω) _RF * t)) down-converts each of the RF antenna signals to produce a 2GHz down-converted antenna signal that enters a buffer/driver pair 961-i/963-i in each path.

To extract the I/Q data, each downconverted antenna signal from 961-I enters an in-phase data signal mixer 951-I and a quadrature data signal mixer 953-I, the in-phase data signal mixers 951-I also receiving cos (ω) with a corresponding delay di from the IFLO GEN _ I911-I _IF * t) signal, quadrature data signal mixer 953-i also receives sin (ω) with a corresponding delay di from IFLO GEN _ i 911-i _IF * t) signal. Each downconverted antenna signal from 963-I enters an in-phase data signal mixer 955-I and a quadrature data signal mixer 957-I, the in-phase data signal mixer 955-I also receives-sin (ω) with a corresponding delay di from IFLO GEN _ I911-I _IF * t) signal, positiveCross data signal mixer 957-i also receives cos (ω) with corresponding delay di from IFLO GEN _ i 911-i _IF * t) signal. The I and Q signals from the I and Q data signal mixers may then be filtered at LPFs I923 and Q927, respectively, and digitized in analog-to-digital converters ADC I921 and ADC Q925 to provide I/Q data.

Fig. 11 is a block diagram of an embodiment of a transmitter 1002 including a dedicated frequency synthesizer 1005 for generating an intermediate frequency local oscillator signal in an IFLO generation block 1010, similar to the transmitter 601 of fig. 7. Fig. 11 repeats a number of elements corresponding to those of fig. 9, which are similarly numbered (i.e., controls 807/1007, frequency synthesizers 803/1003, IFLO generation blocks 810/1010, etc.), and which may function as described above with respect to fig. 9.

With respect to fig. 9, the embodiment of fig. 11 includes a second frequency synthesizer 2 1005, e.g., a PLL, which provides Freq1 to the IFLO generation block 1010. In this example, freq1 is again taken to be 48GHz and the division ratio 24 is again used to generate the IFLO signal at 2GHz. Fout from frequency synthesizer 1003 can now be set independently of Freq1, providing greater flexibility. In the example of fig. 11, fout =50GHz, and the signal from antenna 1045-i is now at RFin =52GHz, such that the down-conversion at mixer 1037-i produces a 2GHz down-converted antenna signal.

In the embodiment of fig. 11, instead of using the RFLO frequency synthesizer 1003 output as an input to the IFLO generation block 610, a dedicated frequency synthesizer 2 1005 allows the IFLO frequency to be set to a constant, which may in some cases aid in signal path design. Because Freq1 is constant in the embodiment of fig. 11, frequency synthesizer 2 1005 may be simpler than the frequency synthesizer 1003 block: for example, an integer PLL may be used instead of a Frac-N PLL. For the embodiment of fig. 10, additional dedicated frequency synthesizers may similarly be introduced for the IFLO generation block 910.

Fig. 12 is a flow diagram of an embodiment for receiving a set of antenna signals and applying the phase shift/delay introduced in the IFLO generation block based on the embodiments of fig. 9-11 to extract the data content. At 1101, control block 807/907/1007 receives or determines a delay value (d 1, d2, \8230;, dn). These values may be determined based on signals exchanged between the transmitter 802/902/1002 and the transmitter, where the signals may be data signals or control signals, such as beacons, either in-band on a data signal channel or through an out-of-band control channel. Depending on the embodiment, the delay may be calculated in the control block 802/902/1002 or sent by the transmitter to the control block.

At 1103, each of the IFLOs 811-i/911-i/1011-i receives a first RFLO signal Freq1 (from frequency synthesizer 803/1003 or frequency synthesizer 2 903) and a corresponding delay value di from control 807/907/1007. At 1105, each of the IFLOs 811-i/911-i/1011-i generates an IFLO signal having a corresponding specified delay. In the embodiments of fig. 9 and 11, these are the respective IFLO I and IFLO Q signals, and in the embodiment of fig. 10, is cos (ω) _IF *t)、-sin(ω _IF * t) homorelative sin (ω) _IF *t)、cos(ω _IF * t) orthogonal pairs.

At 1107, each down-conversion mixer (837-i/965-i, 967-i/1037-i) receives a second RFLO signal (Fout also from 803/1003 in FIG. 9 and FIG. 11, or cos (ω) from RFLO generator 959 in FIG. 10 _IF *t)，sin(ω _IF * t)) and corresponding RF antenna signals from the antenna array, which may be amplified and filtered before being provided to the down-mixer. (in the embodiment of FIGS. 9 and 11, the second RFLO signal of 1103 and the first RFLO signal both originate from frequency synthesizers 803/1003). Each down conversion mixer generates an IF data signal at 1109, which may then be passed to a data signal mixer.

At 1111, each data signal mixer (831-I/951-I, 955-I/1031-I for I and 833-I/953-I, 957-I/1033-I for Q) receives a corresponding down-converted IF antenna signal and a corresponding IFLO signal. The data signal mixer then generates an I/Q data signal at 1113. The extracted I/Q data signals may then be filtered and converted to digital form.

The techniques described herein may be implemented using hardware, firmware, software, or a combination thereof. The software or firmware used may be stored on one or more processor readable storage devices to program one or more of the blocks of fig. 3-12 to perform the functions described herein. The processor-readable storage device may include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer-readable storage media may be implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the above components. One or more computer-readable media do not include propagated, modulated, or transitory signals.

Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

In alternative embodiments, some or all of the software or firmware may be replaced by dedicated hardware logic components. By way of example, and not limitation, exemplary types of hardware Logic components that may be used include Field-Programmable Gate arrays (FPGAs), application-specific Integrated circuits (ASICs), application-specific Standard Products (ASSPs), system-on-a-chips (SOCs), complex Programmable Logic Devices (CPLDs), dedicated computers, and the like. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors may communicate with one or more computer-readable media/storage devices, peripherals, and/or communication interfaces.

It should be understood that the present subject matter may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. It will be apparent, however, to one skilled in the art that the present subject matter may be practiced without these specific details.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various modifications as are suited to the particular use contemplated.

For purposes herein, each process associated with the disclosed technology may be performed continuously by one or more computing devices. Each step in the process may be performed by the same or different computing device as used in the other steps, and each step need not be performed by a single computing device.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A transmitter, comprising:

one or more frequency synthesizers, each frequency synthesizer configured to generate a corresponding Radio Frequency (RF) local oscillator signal;

a plurality of Intermediate Frequency (IF) local oscillators, each IF local oscillator configured to:

receiving a first RF local oscillator signal of the one or more RF local oscillator signals;

receiving a corresponding delay value of a plurality of delay values, each specifying a delay of a plurality of cycles of the first RF local oscillator signal; and

generating a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and offsetting the first RF local oscillator signal by a corresponding delay value;

a plurality of first data signal mixers, each configured to receive a first base data signal and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals and generate therefrom a corresponding first IF data signal of the first plurality of IF data signals; and

a plurality of upconversion mixers each configured to receive a second one of the one or more RF local oscillator signals and a corresponding one of the first IF data signals and generate therefrom a beamformed RF antenna signal of a plurality of beamformed RF antenna signals.

2. The transmitter of claim 1, wherein each of the plurality of IF local oscillators is further configured to generate a second IF local oscillator signal by dividing the first RF local oscillator signal by the integer divide ratio and offsetting a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair, the transmitter further comprising:

a plurality of second data signal mixers, each configured to receive a second base data signal and a corresponding one of a plurality of second IF local oscillator signals and generate therefrom a corresponding one of a plurality of second IF data signals, wherein the first base data signal and the second base data signal are in-phase/quadrature pairs and the plurality of first IF data signals and the plurality of second IF data signals are a plurality of in-phase/quadrature pairs of IF data signals,

wherein the plurality of up-conversion mixers are each further configured to receive a corresponding second one of the plurality of first IF data signals, and the plurality of beamformed RF antenna signals are formed from a combined in-phase/quadrature IF data signal pair.

3. The transmitter of any one of claims 1 to 2, further comprising:

one or more control circuits configured to provide the plurality of delay values to the IF local oscillator.

4. The transmitter of claim 3, further comprising:

a plurality of amplifiers connected to receive and amplify corresponding ones of the plurality of beamformed RF antenna signals.

5. The transmitter of claim 4, the one or more control circuits further configured to provide the plurality of delay values to the IF local oscillator and to provide a corresponding gain factor to each amplifier of the plurality of amplifiers,

wherein each of the amplifiers is configured to amplify a received beamforming RF antenna signal of the plurality of beamforming RF antenna signals according to the corresponding gain factor.

6. The transmitter of any one of claims 1 to 5, further comprising:

a plurality of RF filters, each RF filter configured to receive and filter a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

7. The transmitter of any one of claims 1 to 6, further comprising:

an array of multiple antennas, each antenna configured to receive and transmit a corresponding beamformed RF antenna signal of the multiple beamformed RF antenna signals.

8. The transmitter of any one of claims 1 to 7, wherein:

the number of frequency synthesizers is one, and the first RF local oscillator signal is the same as the second RF local oscillator signal.

9. The transmitter of any one of claims 1 to 8, wherein:

the one or more frequency synthesizers include a first frequency synthesizer configured to provide the first RF local oscillator signal and a second frequency synthesizer configured to provide the second RF local oscillator signal.

10. The transmitter of any one of claims 1 to 9, wherein:

each of the delay values specifies a delay of an integer number of cycles.

11. The transmitter of any one of claims 1 to 10, wherein:

each of the delay values specifies a delay of a half integer number of cycles.

12. A method of transmitting a beamformed signal, comprising:

receiving, at each of a plurality of Intermediate Frequency (IF) local oscillators, a first Radio Frequency (RF) local oscillator signal and a corresponding delay value of a plurality of delay values, each of the delay values specifying a delay of a plurality of cycles of the first RF local oscillator signal;

generating, at each of the IF local oscillators, a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and offsetting the first IF local oscillator signal by a corresponding delay value;

receiving, at each of a plurality of first data signal mixers, a first base data signal and a corresponding first IF local oscillator signal of a plurality of first IF local oscillator signals;

generating, by each of the first data signal mixers, a first IF data signal from the first base data signal and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals;

receiving, at each of a plurality of upconversion mixers, a second RF local oscillator signal and a corresponding first IF data signal of a plurality of first IF data signals; and

generating, by each of the up-conversion mixers, a corresponding beamformed RF antenna signal from the second RF local oscillator signal and a corresponding first IF data signal of the plurality of first IF data signals.

13. The method of claim 12, further comprising:

exchanging one or more control signals between a transmitter controller and a receiver;

determining, by the transmitter controller, the delay value from the exchanged control signals; and

providing the determined delay value from the transmitter controller to the IF local oscillator.

14. The method of claim 13, wherein:

the determination of the delay value comprises calculating, by the transmitter controller, the delay value from the exchanged control signals.

15. The method of claim 13, wherein:

the determining of the delay value comprises receiving the delay value from the receiver in the exchanged control signals.

16. The method of claim 13, further comprising:

receiving, at each amplifier of the plurality of amplifiers, a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals and a corresponding gain factor;

amplifying, at each of the amplifiers, a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals according to the gain factor;

determining, by the transmitter controller, the gain factor from the exchanged control signals; and

providing the determined gain factor from the transmitter controller to the IF local oscillator.

17. The method of any of claims 12 to 16, further comprising:

generating, at each of the IF local oscillators, a second IF local oscillator signal by dividing the second RF local oscillator signal by the integer divide ratio and offsetting the second IF local oscillator signal by a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair;

receiving, at each of a plurality of second data signal mixers, a second base data signal and a corresponding second IF local oscillator signal of a plurality of second IF local oscillator signals;

generating, by each of the second data signal mixers, a second IF data signal from the second base data signal and a corresponding second IF local oscillator signal of the plurality of second IF local oscillator signals, wherein the first base data signal and the second base data signal are in-phase/quadrature pairs and a plurality of first IF data signals and a plurality of second IF data signals are a plurality of in-phase/quadrature IF data signal pairs; and

forming a combined in-phase/quadrature IF data signal pair, wherein said generating by each of said up-conversion mixers a corresponding beamformed RF antenna signal from said second RF local oscillator signal and a corresponding first IF data signal of said plurality of first IF data signals comprises generating said corresponding beamformed RF antenna signal from a corresponding combined in-phase/quadrature IF data signal pair of a combined in-phase/quadrature IF data signal pair.

18. The method of any of claims 12 to 17, further comprising:

each RF filter of a plurality of RF filters a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

19. The method of any of claims 12 to 18, further comprising:

each antenna of the plurality of antennas transmits a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

20. The method of any one of claims 12 to 19, wherein the first RF local oscillator signal is the same as the second RF local oscillator signal.

21. A receiver, comprising:

a plurality of down-conversion mixers, each configured to receive a second one of the one or more RF local oscillator signals and an RF antenna signal of a plurality of RF antenna signals and to generate therefrom a corresponding first one of a plurality of first IF data signals; and

a plurality of first data signal mixers, each configured to receive a corresponding one of the plurality of first IF data signals and a corresponding one of a plurality of first IF local oscillator signals and generate a first base data signal therefrom.

22. The receiver of claim 21, wherein each of the plurality of IF local oscillators is further configured to generate a second IF local oscillator signal by dividing the first RF local oscillator signal by the integer divide ratio and offsetting a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair, the receiver further comprising:

a plurality of second data signal mixers, each second data signal mixer configured to receive a corresponding second IF data signal of a plurality of second IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals and generate a second base data signal therefrom, the first base data signal and the second base data signal forming a plurality of in-phase/quadrature base data signal pairs.

23. The receiver of any of claims 21 to 22, further comprising:

24. The receiver of claim 23, further comprising:

a plurality of amplifiers connected to receive and amplify corresponding ones of the plurality of RF antenna signals and provide each amplified RF antenna signal to a corresponding one of the plurality of down-conversion mixers.

25. The receiver of claim 24, the one or more control circuits further configured to provide the plurality of delay values to the IF local oscillator and to provide a corresponding gain factor to each amplifier of the plurality of amplifiers,

wherein each of the amplifiers is configured to amplify a received RF antenna signal of the plurality of RF antenna signals according to the corresponding gain factor.

26. The receiver of any of claims 21 to 25, further comprising:

a plurality of RF filters, each RF filter configured to receive and filter a corresponding RF antenna signal of the plurality of RF antenna signals.

27. The receiver of any of claims 21 to 26, further comprising:

an array of multiple antennas, each antenna configured to receive an RF signal and provide the RF signal to the multiple down-conversion mixers.

28. The receiver of any one of claims 21 to 27, wherein:

29. The receiver of any one of claims 21 to 28, wherein:

30. The receiver of any one of claims 21 to 29, wherein:

each of the delay values specifies a delay of an integer number of cycles.

31. The receiver of any one of claims 21 to 30, wherein:

each of the delay values specifies a delay of a half integer number of cycles.

32. A method of receiving a Radio Frequency (RF) signal, comprising:

receiving, at each of a plurality of Intermediate Frequency (IF) local oscillators, a first RF local oscillator signal and a corresponding delay value of a plurality of delay values, each of the delay values specifying a delay of a plurality of cycles of the first RF local oscillator signal;

generating, by each of the IF local oscillators, a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer divide ratio and offsetting the first IF local oscillator signal by a corresponding delay value;

receiving, at each of a plurality of down-conversion mixers, a second RF local oscillator signal and a corresponding RF antenna signal of a plurality of RF antenna signals;

generating, at each of the plurality of down-conversion mixers, a corresponding first IF data signal of a plurality of first IF data signals from the second RF local oscillator signal and the corresponding RF antenna signal;

receiving, at each of a plurality of first data signal mixers, a corresponding first IF data signal of the plurality of first IF data signals and a corresponding first IF local oscillator signal of a plurality of first IF local oscillator signals; and

generating, at each of the plurality of first data signal mixers, a first fundamental data signal from a corresponding first IF data signal of the plurality of first IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals.

33. The method of claim 32, further comprising:

exchanging one or more control signals between a receiver controller and a transmitter;

determining, by the receiver controller, the delay value from the exchanged control signals; and

providing the determined delay value from the receiver controller to the IF local oscillator.

34. The method of claim 33, wherein:

the determination of the delay value comprises calculating, by the receiver controller, the delay value from the exchanged control signals.

35. The method of claim 33, wherein:

the determining of the delay value comprises receiving the delay value from the transmitter in the exchanged control signals.

36. The method of claim 33, further comprising:

receiving, at each amplifier of a plurality of amplifiers, a corresponding RF antenna signal of the plurality of RF antenna signals and a corresponding gain factor;

amplifying, at each of the amplifiers, a corresponding RF antenna signal of the plurality of RF antenna signals according to the gain factor;

the receiver controller determining the gain factor from the exchanged control signals; and

providing the determined gain factor from the receiver controller to the IF local oscillator.

37. The method of any of claims 32 to 36, further comprising:

generating, by each of the IF local oscillators, a second IF local oscillator signal by dividing the first RF local oscillator signal by the integer divide ratio and offsetting a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase/quadrature IF local oscillator signal pair;

receiving, at each of a plurality of second data signal mixers, a corresponding second IF data signal of a plurality of second IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals; and

generating, at each of the second data signal mixers, a corresponding second fundamental data signal from a corresponding second IF data signal of the plurality of second IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals, the first fundamental data signal and the second fundamental data signal forming a plurality of in-phase/quadrature fundamental data signal pairs.

38. The method of any of claims 32 to 37, further comprising:

filtering at each of a plurality of RF filters, a corresponding one of the plurality of RF antenna signals is filtered.

39. The method of any one of claims 32 to 38, wherein: