WO2021082747A1 - Operational apparatus and related product - Google Patents

Abstract

An operational apparatus and a related product. The product comprises a control module; the control module comprises: an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used for storing a calculation instruction associated with an artificial neural network operation; the instruction processing unit is used for parsing the calculation instruction to obtain multiple operation instructions; and the storage queue unit is used for storing an instruction queue, the instruction queue comprising multiple operation instructions or calculation instructions to be executed according to the sequence of the queue. The present application can improve the operation efficiency of a related product when carrying out an operation of a neural network model.

Description

Computing devices and related products

The present disclosure claims the priority of the Chinese patent application number 201911060683.9 filed on November 1, 2019, and the entire content of which is incorporated herein by reference.

Technical field

The present disclosure relates to the field of data processing technology, and in particular to a computing device and related products.

Background technique

In the field of artificial intelligence technology, neural network algorithm is a very popular machine learning algorithm recently, and has achieved very good results in various fields, such as image recognition, speech recognition, natural language processing, etc. With the development of neural network algorithms, the complexity of the algorithm is getting higher and higher. In order to improve the recognition, the scale of the model is gradually increasing. Using GPU and CPU to process these large-scale models requires a lot of computing time and consumes a lot of power.

Summary of the invention

Based on this, it is necessary to provide a computing device and related products that can reduce the amount of calculation, save calculation time, and save energy in response to the above technical problems.

According to an aspect of the present disclosure, there is provided an arithmetic device including: a master instruction processing unit, a master functional unit, a slave instruction processing unit, and a slave functional unit,

Wherein, the main instruction processing unit is configured to send a first control signal to the main function unit according to the input instruction after receiving the input instruction;

The main functional unit is used to decompose the winograd positive transformation of the input data into a summation operation according to the first control signal, perform calculations to obtain the winograd positive transformation result of the input data, and send all the data to the slave functional unit. The winograd positive transformation result of the input data,

Wherein, the winograd positive transformation result of the input data includes the winograd positive transformation result of the input neuron;

The master instruction processing unit is further configured to send a second control signal to the slave instruction processing unit, and the slave instruction processing unit is configured to send the second control signal to the slave functional unit;

The slave functional unit is configured to perform bit-multiplication on the winograd positive transformation result of the input neuron and the winograd positive transformation result of the weight value according to the second control signal to obtain the bit-multiply result, and to obtain the winograd result of the bit-multiply result. The inverse transform is disassembled into a summation operation, and calculation is performed to obtain the winograd convolution result of the input data.

According to another aspect of the present disclosure, there is provided an artificial intelligence chip, the chip including the arithmetic device described above

According to another aspect of the present disclosure, there is provided an electronic device, characterized in that the electronic device includes the artificial intelligence chip as described above.

According to the arithmetic device of the present disclosure, the winograd forward transformation result of the input data is obtained by calculating the winograd forward transformation result of the input data by disassembling the winograd forward transformation of the input data into a summation operation, and the winograd forward transformation result of the input data includes the winograd of the input neuron The result of the positive transformation, and then multiply the result of the winograd positive transformation of the input neuron and the result of the weight of the winograd positive transformation to obtain the result of the parallel multiplication. The inverse winograd transform of the result of the alignment multiply is disassembled into a summation operation, and Perform calculation to obtain the winograd convolution result of the input data. According to the arithmetic device of the present disclosure, disassembling the multiplication operation into a summation operation can save calculation time and reduce energy consumption.

According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear.

Description of the drawings

The drawings included in the specification and constituting a part of the specification together with the specification illustrate exemplary embodiments, features, and aspects of the present disclosure, and are used to explain the principle of the present disclosure.

Fig. 1 shows a block diagram of an arithmetic device according to an embodiment of the present disclosure;

FIG. 2 shows a flowchart of a winograd positive transformation result of input data calculated according to a first subtensor according to an embodiment of the present disclosure;

Fig. 3 shows a block diagram of an arithmetic device according to an embodiment of the present disclosure;

Fig. 4 shows a flow chart of performing winograd inverse transformation on a bit multiplication result according to an embodiment of the present disclosure;

Fig. 5 shows a schematic diagram of a processor according to an embodiment of the present disclosure;

Fig. 6 shows a structural block diagram of a board according to an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of the present disclosure.

It should be understood that the terms "first", "second", "third" and "fourth" in the claims, specification and drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order. . The terms "comprising" and "comprising" used in the specification and claims of the present disclosure indicate the existence of the described features, wholes, steps, operations, elements and/or components, but do not exclude one or more other features, wholes The existence or addition of, steps, operations, elements, components, and/or their collections.

It should also be understood that the terms used in this specification of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms. It should be further understood that the term "and/or" used in the specification and claims of the present disclosure refers to any combination of one or more of the items listed in association and all possible combinations, and includes these combinations.

As used in this specification and claims, the term "if" can be interpreted as "when" or "once" or "in response to determination" or "in response to detection" depending on the context. Similarly, the phrase "if determined" or "if detected [described condition or event]" can be interpreted as meaning "once determined" or "in response to determination" or "once detected [described condition or event]" depending on the context ]" or "in response to detection of [condition or event described]".

Winograd convolution is a convolution acceleration implementation method based on polynomial interpolation algorithm. It passes the two inputs of the convolution operation: neurons and weights are divided into a certain scale and then linearly transformed (winograd positive transformation), and then the transformed neurons and weights are multiplied by bit, and finally the pair The bit multiplication result is linearly transformed again (winograd inverse transformation) to obtain a convolution result equivalent to the original convolution operation.

The expression of winograd transformation is as follows:

For one-dimensional neurons and weights:

For two-dimensional neurons and weights:

Among them, g represents the weight value, G represents the left multiplication positive transformation matrix ^{corresponding to the weight value, G T} represents the right multiplication positive transformation matrix corresponding to the weight value, d represents the input neuron, and B represents the right multiplication positive transformation matrix corresponding to the input neuron , B ^T represents the left multiplication positive transformation matrix corresponding to the input neuron,

Represents the bitwise multiplication operation, A represents the right multiplication inverse transformation matrix, and ^AT represents the left multiplication inverse transformation matrix. For input neurons of different dimensions, there are B and B ^{T corresponding to them} ; similarly, for the weights of different dimensions, there are G and G ^{T corresponding to them} .

Replacing the original convolution operation by winograd convolution can bring greater benefits in hardware energy efficiency and computing time, and at the same time, higher neural network performance can be achieved without increasing or increasing less hardware overhead. However, the disadvantages of winograd convolution are still more obvious, and a large number of multiplication operations still consume a long time in the calculation process.

In order to solve the above technical problems, the present disclosure provides an arithmetic device that can disassemble the multiplication operation in the winograd convolution process into an addition operation, thereby saving calculation time and reducing energy consumption.

Fig. 1 shows a block diagram of an arithmetic device according to an embodiment of the present disclosure. As shown in FIG. 1, the computing device provided by the present disclosure may include a master instruction processing unit, a master function unit, and a master memory unit, a slave instruction processing unit, a slave function unit, and a slave memory unit.

Wherein, the main instruction processing unit is configured to send a first control signal to the main function unit according to the input instruction after receiving the input instruction;

The main functional unit is used to decompose the winograd positive transformation of the input data into a summation operation according to the first control signal, perform calculations to obtain the winograd positive transformation result of the input data, and send all the data to the slave functional unit. The winograd positive transformation result of the input data,

Wherein, the winograd positive transformation result of the input data includes the winograd positive transformation result of the input neuron;

The master instruction processing unit is further configured to send a second control signal to the slave instruction processing unit, and the slave instruction processing unit is configured to send the second control signal to the slave functional unit;

The slave functional unit is configured to perform bit-multiplication on the winograd positive transformation result of the input neuron and the winograd positive transformation result of the weight value according to the second control signal to obtain the bit-multiply result, and to obtain the winograd result of the bit-multiply result. The inverse transform is disassembled into a summation operation, and calculation is performed to obtain the winograd convolution result of the input data.

According to the arithmetic device of the present disclosure, the winograd forward transformation result of the input data is obtained by calculating the winograd forward transformation result of the input data by disassembling the winograd forward transformation of the input data into a summation operation, and the winograd forward transformation result of the input data includes the winograd of the input neuron The result of the positive transformation, and then multiply the result of the winograd positive transformation of the input neuron and the result of the weight of the winograd positive transformation to obtain the result of the parallel multiplication. The inverse winograd transform of the result of the alignment multiply is disassembled into a summation operation, and Perform calculation to obtain the winograd convolution result of the input data. According to the arithmetic device of the present disclosure, disassembling the multiplication operation into a summation operation can save calculation time and reduce energy consumption.

Wherein, the above-mentioned input instruction may refer to the "WINO_CONV" instruction, which includes the processes of winograd forward transformation, bitwise multiplication, and winograd inverse transformation. The input instruction may carry information about the operation and operand corresponding to the input instruction, and the operand information may include: the address information of the operand, the size of the operand, and so on. For example, the operand information can include the address information of the input neuron, the address information of the weight, and the output operand obtained (the input operand of the next layer, or the input neuron of the next layer) to be stored Address information and so on.

For any layer in the neural network, the input data of this layer can include input neurons, the input neurons of this layer can be the output results of the previous layer, and for the first layer in the neural network, the input neurons can be the initial Input data. The initial input data can be image data, sound data, or video data.

The processes of winograd forward transformation, bit multiplication, and winograd inverse transformation are described below.

winograd is transforming

The main instruction processing unit is further configured to send a first control signal to the main memory unit according to the input instruction after receiving an input instruction; the main memory unit is configured to send a first control signal to the main functional unit according to the first control signal The input data.

In a possible implementation manner, after receiving the input instruction, the main instruction processing unit can decode and parse the input instruction to obtain the address information of the operation and the operand. Then the main instruction processing unit may send the first control signal to the main memory unit and the main function unit according to the information obtained by the analysis.

After receiving the first control signal, the main memory unit may obtain input data according to the first control signal. The input data may include input neurons, etc., and the input data may be data represented in the form of a tensor. Taking the input data as image data as an example, the input data can be expressed in the form of NHWC (batch, height, width, channels), N represents the number of images, HW can respectively represent the number of pixels in the height and width directions of the image, C It can represent the number of channels, for example, C can represent three channels of RGB (Red, Green, Blue). It should be noted that the above representation is only an example of the present disclosure, and the present disclosure is not limited to this.

The main memory unit can send the input data to the main function unit after obtaining the input data.

After receiving the first control signal and the input data, the main functional unit can perform calculations according to the operation in the first control signal and the input data, and disassemble the winograd forward transformation of the input data into a summation operation, and perform calculations to obtain the The winograd of the input data is transforming the result.

The specific process may be that the main function unit is used to disassemble the input data into a plurality of first sub-tensors according to the first control signal, and perform winograd forward transformation on the plurality of first sub-tensors and sum them. Obtain the winograd positive transformation result of the input data.

In a possible implementation manner, the number of the plurality of first sub-tensors is the same as the number of elements of the input data. In each of the plurality of first sub-tensors, one element in each first sub-tensor is the same as the element at the corresponding position in the input data, and other elements are all zero.

Or, in another possible implementation manner, the number of the plurality of first sub-tensors is the same as the number of non-zero elements of the input data, and each of the plurality of first sub-tensors One element in the first sub-tensor is the same as the element at the corresponding position in the input data, and the other elements are all 0.

For example, suppose the input neuron is represented as:

The input neuron is a 4×4 matrix including 16 elements. Therefore, the input data can be decomposed into 16 first sub-tensors.

Then, according to the disassembly method of the present disclosure, the 16 first sub-tensors are:

There is an element in each first subtensor that is the same as the element at the corresponding position in the input data, and the other elements are all 0. This means: taking the first subtensor d ₀₀ as an example, the position in the first row and first column is The element is the same as the element at the position of the input neuron in the first row and first column. Other elements are all 0, and the other first subtensors also have the same attributes.

It should be noted that the above disassembly methods are only some examples of the present disclosure, and do not limit the present disclosure in any way. For example, if the input data has an element with a value of 0, the number of first subtensors obtained by the disassembly can be The number of elements less than the input data, for example, the number of multiple first subtensors is the same as the number of non-zero elements of the input data.

Fig. 2 shows a flow chart of a winograd positive transformation result of input data calculated according to a first subtensor according to an embodiment of the present disclosure. As shown in FIG. 2, in a possible implementation manner, performing winograd forward transformation on the multiple first subtensors and summing them to obtain the winograd forward transformation result of the input data may include the following process:

Step S21: Obtain the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor; wherein, the first sub-tensor corresponding to the first sub-tensor is: the first position in the first sub-tensor The value of the element is 1, where the position of the first position in the first sub-tensor is the same as the position of the non-zero element in the first sub-tensor;

Step S22, multiplying the value of an element in the first sub-tensor that is not 0 as a coefficient by the winograd positive transformation result of the corresponding first-element sub-tensor to obtain the winograd positive transformation result of the first sub-tensor;

Step S23, adding the winograd positive transformation results of the multiple first subtensors to obtain the winograd positive transformation result of the input data.

For step S21, still taking the first sub-tensor d ₀₀ as an example, the first-element sub-tensor corresponding to _{d 00 can be}

In other words, the first sub-tensor is to extract the values of non-zero elements in the first sub-tensor, and the values of non-zero elements can be used as coefficients of the first sub-tensor.

Among them, the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor can be obtained in advance through the following process: For each first sub-tensor, the first sub-tensor corresponding to the first sub-tensor The left side of the sub-tensor is multiplied by the positive transformation, the left-multiplied matrix, and the right is multiplied by the positive transformation, and the right-multiplied matrix is used to obtain the winograd positive transformation result of the first sub-tensor.

For matrices of different sizes, the form of the corresponding first element sub-tensor is determined, and the corresponding positive transformation left-multiplication matrix and forward transformation right-multiplication matrix are also determined.

Therefore, the winograd positive transformation result of the first sub-tensor can be calculated in advance, and the specific process is as described above. For example, still taking d ₀₀ as an example, the corresponding winograd positive transformation result of the first sub-tensor is:

For another example, taking d ₀₁ as an example, the winograd positive transformation result of the corresponding first-element sub-tensor is:

Since the element values of the positive transformation left multiplication matrix and the positive transformation right multiplication matrix are both 0 and ±1, the element value of the first sub-tensor is 0 or 1, and the element in the winograd positive transformation result of the first sub-tensor is also 0, ±1. Therefore, the matrix multiplication operation can be broken down into an addition operation.

The process of calculating the winograd positive transformation result of the first element sub-tensor involves more multiplication operations. Through the method of the present disclosure, the pre-calculated winograd positive transformation results of the first element subtensor of various scales can be stored in In the computing device, in this way, in the actual computing process, it can be directly obtained without repeated computing, thereby shortening computing time and saving computing resources.

After obtaining the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor, the value of the non-zero element in the first sub-tensor can be multiplied by the winograd positive transformation result of the corresponding first sub-tensor, then The winograd positive transformation result of the first subtensor can be obtained. For example, still taking d ₀₀ as an example, the corresponding winograd positive transformation result is:

For another example, taking d ₀₁ as an example, the winograd positive transformation result of _{d 01 is}

The winograd positive transformation results of all the first sub-tensors are calculated through the above process, and the winograd positive transformation results of multiple first sub-tensors are added to obtain the winograd positive transformation results of the input data.

Since the elements in the winograd positive transformation result of the first element subtensor obtained by the conversion are also 0 and ±1, the right side of the above equations (1) and (2) only involves the summation operation.

According to the above-mentioned embodiments of the present disclosure, it can be known that multiple first sub-tensors are obtained by disassembling the input data, and the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor obtained in advance and the first The non-zero element value of the subtensor can be summed to obtain the winograd positive transformation result of the input data. According to the arithmetic device of the present disclosure, disassembling the multiplication operation into a summation operation can save calculation time and reduce energy consumption.

In a possible implementation manner, the main functional unit includes a cache module, and the main functional unit stores the winograd positive transformation result of the input data in the cache module.

Fig. 3 shows a block diagram of an arithmetic device according to an embodiment of the present disclosure. As shown in FIG. 3, the main function unit may include a main processing module and a cache module, and the main processing module may be used to execute the main function unit of all the above-mentioned embodiments to input data according to the first control signal. The winograd positive transformation is decomposed into a summation operation, and the process of calculating the winograd positive transformation result of the input data is performed. The main functional unit can store the winograd positive conversion result of the input data in the cache module, and the cache module sends the winograd positive conversion result of the input data to the slave functional unit, so that the slave functional unit of the computing device can check the winograd positive conversion result. The transformation result is a process of bitwise multiplication and winograd inverse transformation.

As shown in Figure 3, the master instruction processing unit is also used to send a second control signal to the slave instruction processing unit. For example, after the winograd positive transformation process is completed, the winograd positive transformation result of the input data is ready, and the master instruction processing unit can The second control signal is sent to the slave instruction processing unit according to the WINO_MIT instruction, and the master functional unit (specifically, the cache module in the master functional unit) is also used to send the winograd positive transformation result of the input data to the slave functional unit. The second control signal may be used to instruct the slave command processing unit to control the slave functional unit to further process the winograd conversion result of the input data.

Counterpoint multiplication, winograd inverse transform

Specifically, the slave instruction processing unit is configured to receive the second control signal sent by the master instruction processing unit, and send the second control signal to the slave functional unit and the slave memory unit. The slave memory unit is configured to send the winograd positive transformation result of the weight to the slave functional unit according to the second control signal. The slave functional unit is used to receive the winograd positive transformation result of the input data sent by the main functional unit, and the winograd positive transformation result of the input data includes the winograd positive transformation result of the input neuron.

Wherein, the winograd positive transformation result of the weight can be pre-calculated, and the calculation method of the winograd positive transformation result of the weight can adopt a traditional matrix multiplication operation, or refer to the disassembly mentioned above as a summation operation. Calculated.

For example, the weights are disassembled into a plurality of first sub-tensors, and winograd positive transformations are performed on the plurality of first sub-tensors and summed to obtain the winograd positive transformation results of the weights.

Assuming that the weight can be expressed as:

A matrix with a weight of 3×3 includes 9 elements. Therefore, the input data can be decomposed into 9 first sub-tensors.

Then, according to the disassembly method of the present disclosure, the 9 first sub-tensors are:

Similarly, one element in each first subtensor is the same as the element at the corresponding position in the weight, and the other elements are all zero.

Referring to the process of step S21-step S23, the winograd positive transformation result of the weight can be calculated, which will not be repeated.

The functional unit is used to perform bit-multiplication on the winograd forward transformation result of the input neuron and the winograd forward transformation result of the weight value according to the second control signal to obtain the bit-on multiplication result, and to inverse the winograd result of the bit-on multiplication result The transformation and disassembly are summation operations, and calculations are performed to obtain the winograd convolution result of the input data.

Wherein, the bitwise multiplication may refer to the data obtained by multiplying the data at the corresponding positions of the two tensors as the value of the corresponding position in the bitwise multiplication result.

Assuming that the winograd positive transformation result B ^T d _4×4 B of the input neuron can be expressed as:

Weighted winograd positive transformation result

It can be expressed as:

The result of counter multiplication can be:

The winograd convolution result of the input data can be expressed as

The slave function processing unit of the present disclosure can combine

The disassembly is a summation operation, and calculation is performed to obtain the winograd convolution result of the input data, which can further save calculation time and reduce energy consumption.

The specific process is similar to the above-mentioned winograd forward transform disassembly method. In a possible implementation manner, the slave function unit is used to disassemble the alignment multiplication result into a plurality of second sub-tensors. The multiple second sub-tensors are subjected to winograd inverse transformation and summed to obtain the winograd convolution result of the input data.

In a possible implementation manner, the number of the multiple second sub-tensors is the same as the number of elements of the parametric multiplication result, and each of the multiple second sub-tensors has one The element is the same as the element at the corresponding position in the result of the bitwise multiplication, and the other elements are all 0.

In a possible implementation manner, the number of the plurality of second sub-tensors is the same as the number of non-zero elements in the result of the bitwise multiplication, and each second sub-tensor of the plurality of second sub-tensors One element is the same as the element at the corresponding position in the result of the bitwise multiplication, and the other elements are all 0.

Assume that the result of counter multiplication is

The result of the alignment multiplication is disassembled into multiple second sub-tensors, for example, it can be disassembled into 16, and the 16 second sub-tensors are:

After the disassembly is completed, winograd inverse transformation can be performed on the multiple second sub-tensors and summed to obtain the winograd convolution result of the input data.

Fig. 4 shows a flow chart of performing winograd inverse transformation on a bit multiplication result according to an embodiment of the present disclosure. As shown in FIG. 4, in a possible implementation manner, performing winograd inverse transformation on the multiple second subtensors and summing them to obtain the winograd convolution result of the input data may include the following process:

Step S41: Obtain the winograd inverse transform result of the second sub-tensor corresponding to the second sub-tensor; wherein, the second sub-tensor corresponding to the second sub-tensor is: the second position in the second sub-tensor The value of the element is 1, where the position of the second position in the second sub-tensor is the same as the position of the non-zero element in the second sub-tensor;

Step S42, multiplying the non-zero element value of the second sub-tensor as a coefficient by the winograd inverse transform result of the corresponding second-element sub-tensor to obtain the winograd inverse transform result of the second sub-tensor;

Step S43: Add the winograd inverse transform results of the multiple second sub-tensors to obtain the winograd convolution result of the input data.

The method for determining the second meta-sub-tensor corresponding to the second sub-tensor is the same as the method for determining the first meta-sub-tensor above, and will not be repeated here. Among them, the winograd inverse transform result of the second sub-tensor is obtained in advance through the following process: For each second sub-tensor, the left side of the second sub-tensor corresponding to the second sub-tensor is multiplied by the inverse transform Multiplying the matrix on the left, multiplying the matrix on the right by the inverse transformation, and multiplying the matrix on the right to obtain the winograd inverse transformation result of the second element subtensor.

For matrices of different sizes, the form of the corresponding second-element sub-tensor is determined, and the corresponding inverse transform left multiplication matrix and inverse transform right multiplication matrix are also determined. Therefore, the winograd inverse transformation result of the second sub-tensor can be calculated in advance, and the specific process is as described above. For the examples listed in this article, the left multiplication matrix of the inverse transformation is a 2×4 matrix, for example:

The inverse transformation right multiplication matrix is a 4×2 matrix, for example:

The dimension of the inverse transformation matrix can be determined according to the dimension of the input neuron and the dimension of the weight value and the convolution step length. The above is only an example, and the present disclosure is not limited in any way.

The inverse transformation matrix is given by

Therefore, the matrix multiplication operation of the inverse transformation can be broken down into addition and shift operations. Multiply the inverse transformation matrix by the second-element sub-tensor to obtain the winograd inverse transformation result of the second-element sub-tensor. The element value in the winograd inverse transformation result of the second-element sub-tensor is determined by

With other configurations, fractions can be calculated by simple shift operations, which can still save calculation time compared to multiplication operations.

For the specific process of steps S42 and S43, please refer to the above steps S22 and S23, except that the winograd inverse transformation result of the second element subtensor is not completely 0, ±1, but the score can be calculated by a simple shift operation, Compared with the multiplication operation, the present disclosure can still achieve the effects of saving calculation time and reducing energy consumption after disassembling the ordinary inverse transformation process.

According to the above-mentioned embodiments of the present disclosure, it can be known that multiple second sub-tensors are obtained by disassembling the bit-multiplication results, and the winograd inverse transform results of the second-element sub-tensors corresponding to the second sub-tensors obtained in advance and The non-zero element value of the second subtensor can be summed to obtain the winograd convolution result of the input data. According to the arithmetic device of the present disclosure, disassembling the multiplication operation into a summation operation can save calculation time and reduce energy consumption.

In a possible implementation, as shown in FIG. 3, the slave function unit may include an alignment multiplication module and an inverse transformation module, wherein the alignment multiplication module can be used to perform the above alignment multiplication operation to obtain the alignment. The result of the bit multiplication can be sent to the inverse transform module, and the inverse transform module executes the above-mentioned winograd inverse transform of the result of the bit multiplication into a summation operation, and performs calculation to obtain the Winograd convolution result of input data.

In a possible implementation manner, the slave function unit is further configured to perform post-processing on the winograd convolution result of the input data, and the post-processing includes a bitwise rounding operation and a revolution operation.

Among them, the rounding operation may round the winograd convolution result of the input data according to the set number of rounding bits. The number of revolution operations may refer to processing the arrangement of the winograd convolution result of the input data. For example, the arrangement of the winograd convolution result of the input data can be changed according to storage requirements. Post-processing the winograd convolution results of the input data is more conducive to subsequent operations and calculations.

In a possible implementation manner, the slave function unit is further configured to send the winograd convolution result of the input data to the main memory unit as the input neuron of the next layer of convolution operation.

The computing device according to the embodiments of the present disclosure can be applied to a processor, and the processor can be a general-purpose processor, such as a CPU (Central Processing Unit, central processing unit), or an artificial intelligence processor for performing artificial intelligence operations. (IPU). Artificial intelligence operations can include machine learning operations, brain-like operations, and so on. Among them, machine learning operations include neural network operations, k-means operations, support vector machine operations, and so on. The artificial intelligence processor may, for example, include GPU (Graphics Processing Unit), NPU (Neural-Network Processing Unit, neural network processing unit), DSP (Digital Signal Process, digital signal processing unit), field programmable gate array (Field-Programmable Gate Array, FPGA) One or a combination of chips. The present disclosure does not limit the specific types of processors.

In a possible implementation manner, the processor mentioned in the present disclosure may include multiple processing units, and each processing unit can independently run various tasks assigned to it, such as convolution computing tasks and pooling tasks. Or fully connected tasks, etc. The present disclosure does not limit the processing unit and the tasks run by the processing unit.

Fig. 5 shows a schematic diagram of a processor according to an embodiment of the present disclosure. Referring to FIG. 5, the processor is used to perform machine learning calculations. The processor includes a controller unit 141 and an arithmetic unit 142. The controller unit 141 is connected to the arithmetic unit 142. The arithmetic unit 142 includes: a main processing circuit and Multiple slave processing circuits;

The controller unit 141 is configured to obtain input data and calculation instructions; the calculation instructions obtained by the controller unit 141 may be one or more operators in the first fusion set after the operators are fused by the first processor.

In an optional solution, one main processing circuit and multiple slave processing circuits may have a tree structure, an H-type structure or a pulse array machine structure. The present disclosure does not limit the connection between the main processing circuit and the slave processing circuit.

In an optional solution, specifically, the input data and calculation instructions may be obtained through a data input and output unit, and the data input and output unit may specifically be one or more data I/O interfaces or I/O pins.

The above calculation instructions include but are not limited to: forward operation instructions or reverse training instructions, or other neural network operation instructions, such as convolution operation instructions, or may also be the “WINO_CONV” instruction mentioned above. This application specifically The implementation manner does not limit the specific expression form of the foregoing calculation instruction.

The controller unit 141 is further configured to parse the calculation instruction to obtain multiple calculation instructions, and send the multiple calculation instructions and the input data to the main processing circuit;

The main processing circuit 101 is configured to perform pre-processing on the input data and transmit data and operation instructions with the plurality of slave processing circuits;

A plurality of slave processing circuits 102 are configured to perform intermediate operations in parallel to obtain a plurality of intermediate results according to the data and operation instructions transmitted from the main processing circuit, and transmit the plurality of intermediate results to the main processing circuit;

The main processing circuit 101 is configured to perform subsequent processing on the multiple intermediate results to obtain the calculation result of the calculation instruction.

The technical solution provided by this application sets the arithmetic unit into a master-multi-slave structure. For the calculation instructions of the forward operation, it can split the data according to the calculation instructions of the forward operation, so that multiple slave processing circuits can be used The larger part of the calculation is performed in parallel, thereby increasing the speed of the calculation, saving the calculation time, and thereby reducing the power consumption.

Optionally, the above-mentioned machine learning calculation may specifically include: artificial neural network operations, and the above-mentioned input data may specifically include: input neuron data and weight data. The above calculation result may specifically be: the result of the artificial neural network operation is the output neuron data.

The operation in the neural network can be the operation of one layer in the neural network. For the multi-layer neural network, the realization process is that in the forward operation, when the operation of the artificial neural network of the previous layer is completed, the operation of the next layer The instruction will operate the output neuron calculated in the computing unit as the input neuron of the next layer (or perform some operations on the output neuron and then use it as the input neuron of the next layer), and at the same time, set the weight It is also replaced with the weight of the next layer; in the reverse operation, when the reverse operation of the artificial neural network of the previous layer is completed, the next layer operation instruction will use the input neuron gradient calculated in the operation unit as the next The output neuron gradient of one layer is calculated (or some operation is performed on the input neuron gradient and then used as the output neuron gradient of the next layer), and the weights are replaced with the weights of the next layer.

The above-mentioned machine learning calculations may also include support vector machine calculations, k-nearest neighbor (k-nn) calculations, k-means calculations, principal component analysis calculations, and so on. For the convenience of description, the following takes artificial neural network operation as an example to illustrate the specific scheme of machine learning calculation.

For artificial neural network operations, if the artificial neural network operation has multi-layer operations, the input neurons and output neurons of the multi-layer operation do not refer to the neurons in the input layer and the neurons in the output layer of the entire neural network. For any two adjacent layers in the network, the neuron in the lower layer of the network forward operation is the input neuron, and the neuron in the upper layer of the network forward operation is the output neuron. Take the convolutional neural network as an example, suppose a convolutional neural network has L layers, K=1, 2,...,L-1, for the Kth layer and the K+1th layer, we will use the Kth layer It is called the input layer, and the neurons in it are the input neurons, and the K+1th layer is called the output layer, and the neurons in it are the output neurons. That is, except for the top layer, each layer can be used as the input layer, and the next layer is the corresponding output layer.

Optionally, the foregoing processor may further include: the storage unit 140 and the direct memory access unit 50. The storage unit 140 may include one or any combination of a register and a cache. Specifically, the cache is used to store the Calculation instruction; the register is used to store the input data and scalar; the cache is a high-speed temporary storage cache. The direct memory access unit 50 is used to read or store data from the storage unit 10.

Optionally, the controller unit includes: an instruction storage unit 410, an instruction processing unit 411, and a storage queue unit 413;

The instruction storage unit 410 is configured to store calculation instructions associated with the artificial neural network operation;

The instruction processing unit 411 is configured to parse the calculation instructions to obtain multiple operation instructions;

The storage queue unit 413 is configured to store an instruction queue, and the instruction queue includes: a plurality of operation instructions or calculation instructions to be executed in the sequence of the queue.

For example, in an optional technical solution, the main arithmetic processing circuit may also include a controller unit, and the controller unit may include a main instruction processing unit, which is specifically configured to decode instructions into micro instructions. Of course, in another optional solution, the slave operation processing circuit may also include another controller unit, and the other controller unit includes a slave instruction processing unit, which is specifically configured to receive and process micro instructions. The above-mentioned micro-instructions may be the next-level instructions of the instructions. The micro-instructions can be obtained by splitting or decoding the instructions, and can be further decoded into control signals of various components, units or processing circuits.

In an optional solution, the structure of the calculation instruction may be as shown in the following table.

Opcode

Register or immediate

Register/immediate

…

The ellipsis in the above table indicates that multiple registers or immediate data can be included.

In another optional solution, the calculation instruction may include: one or more operation domains and an operation code. The calculation instruction may include a neural network operation instruction. Taking neural network operation instructions as an example, as shown in Table 1, among them, register number 0, register number 1, register number 2, register number 3, and register number 4 can be operation domains. Among them, each register number 0, register number 1, register number 2, register number 3, and register number 4 may be the numbers of one or more registers.

The above-mentioned register can be an off-chip memory. Of course, in practical applications, it can also be an on-chip memory for storing data. The data can be n-dimensional data, and n is an integer greater than or equal to 1. For example, when n=1, It is one-dimensional data, that is, a vector. For example, when n=2, it is a two-dimensional data, that is, a matrix. When n=3 or more, it is a multi-dimensional tensor.

Optionally, the controller unit may further include:

The dependency processing unit 412 is configured to determine whether there is an association relationship between the first operation instruction and the zeroth operation instruction before the first operation instruction when there are multiple operation instructions, such as the first operation instruction and the first operation instruction. If there is an association relationship between the zero operation instruction, the first operation instruction is cached in the instruction storage unit, and after the zeroth operation instruction is executed, the first operation instruction is fetched from the instruction storage unit and transmitted to The arithmetic unit;

The determining whether there is an association relationship between the first operation instruction and the zeroth operation instruction before the first operation instruction includes:

According to the first operation instruction, extract the first storage address interval of the required data (such as a matrix) in the first operation instruction, and extract the zeroth of the required matrix in the zeroth operation instruction according to the zeroth operation instruction The storage address interval, if the first storage address interval and the zeroth storage address interval have an overlapping area, it is determined that the first operation instruction and the zeroth operation instruction have an association relationship, as in the first storage If the address interval and the zeroth storage address interval do not have an overlapping area, it is determined that the first operation instruction and the zeroth operation instruction do not have an association relationship.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited by the described sequence of actions. Because according to the present disclosure, certain steps can be performed in other order or at the same time. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the involved actions and modules are not necessarily required by the present disclosure.

It should be further noted that although the various steps in the flowchart are displayed in sequence according to the directions of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless specifically stated in this article, there is no strict order for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution of these sub-steps or stages The sequence is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

It should be understood that the foregoing device embodiments are only illustrative, and the device of the present disclosure may also be implemented in other ways. For example, the division of units/modules in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components may be combined or integrated into another system, or some features may be omitted or not implemented.

In addition, unless otherwise specified, the functional units/modules in the various embodiments of the present disclosure may be integrated into one unit/module, or each unit/module may exist alone physically, or two or more units/modules may exist. The modules are integrated together. The above-mentioned integrated unit/module can be implemented in the form of hardware or software program module.

If the integrated unit/module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, and so on. The physical realization of the hardware structure includes but is not limited to transistors, memristors and so on. Unless otherwise specified, the artificial intelligence processor may be any appropriate hardware processor, such as CPU, GPU, FPGA, DSP, ASIC, and so on. Unless otherwise specified, the storage unit may be any suitable magnetic storage medium or magneto-optical storage medium, such as RRAM (Resistive Random Access Memory), DRAM (Dynamic Random Access Memory), Static random access memory SRAM (Static Random-Access Memory), enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), high-bandwidth memory HBM (High-Bandwidth Memory), hybrid storage cube HMC (Hybrid Memory Cube), etc. Wait.

If the integrated unit/module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer readable memory. Based on this understanding, the technical solution of the present disclosure essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, It includes several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned memory includes: U disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

In a possible implementation manner, an artificial intelligence chip is also disclosed, which includes the aforementioned computing device.

In a possible implementation manner, a board card is also disclosed, which includes a storage device, an interface device, a control device, and the aforementioned artificial intelligence chip; wherein, the artificial intelligence chip is connected to the storage device and the control device And the interface devices are respectively connected; the storage device is used to store data; the interface device is used to realize data transmission between the artificial intelligence chip and an external device; the control device is used to The state of the artificial intelligence chip is monitored.

Fig. 6 shows a structural block diagram of a board card according to an embodiment of the present disclosure. Referring to Fig. 6, the board card may include other supporting components in addition to the chip 389 described above. The supporting components include, but are not limited to: a storage device 390, Interface device 391 and control device 392;

The storage device 390 is connected to the artificial intelligence chip through a bus for storing data. The storage device may include multiple groups of storage units 393. Each group of the storage unit and the artificial intelligence chip are connected through a bus. It can be understood that each group of the storage units may be DDR SDRAM (English: Double Data Rate SDRAM, double-rate synchronous dynamic random access memory).

DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows data to be read on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In an embodiment, the storage device may include 4 groups of the storage units. Each group of the storage unit may include a plurality of DDR4 particles (chips). In one embodiment, the artificial intelligence chip may include four 72-bit DDR4 controllers. In the 72-bit DDR4 controller, 64 bits are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of the storage units, the theoretical bandwidth of data transmission can reach 25600MB/s.

In one embodiment, each group of the storage unit includes a plurality of double-rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling the DDR is provided in the chip, which is used to control the data transmission and data storage of each storage unit.

The interface device is electrically connected with the artificial intelligence chip. The interface device is used to implement data transmission between the artificial intelligence chip and an external device (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transferred from the server to the chip through a standard PCIE interface to realize data transfer. Preferably, when the PCIE3.0X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device may also be other interfaces. The present disclosure does not limit the specific manifestations of the other interfaces mentioned above, as long as the interface unit can realize the switching function. In addition, the calculation result of the artificial intelligence chip is still transmitted by the interface device back to an external device (such as a server).

The control device is electrically connected with the artificial intelligence chip. The control device is used to monitor the state of the artificial intelligence chip. Specifically, the artificial intelligence chip and the control device may be electrically connected through an SPI interface. The control device may include a single-chip microcomputer (Micro Controller Unit, MCU). For example, the artificial intelligence chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Therefore, the artificial intelligence chip can be in different working states such as multi-load and light-load. The control device can realize the regulation and control of the working states of multiple processing chips, multiple processing and or multiple processing circuits in the artificial intelligence chip.

In a possible implementation manner, an electronic device is disclosed, which includes the aforementioned artificial intelligence chip. Electronic equipment includes data processing devices, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, cameras, projectors, watches, headsets , Mobile storage, wearable devices, vehicles, household appliances, and/or medical equipment. The transportation means include airplanes, ships, and/or vehicles; the household appliances include TVs, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes nuclear magnetic resonance, B-ultrasound and/or electrocardiograph.

The embodiments of the present disclosure also provide a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above-mentioned method when executed by a processor. The computer-readable storage medium may be a non-volatile computer-readable storage medium.

An embodiment of the present disclosure also provides an electronic device, including: a processor; a memory for storing executable instructions of the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

The foregoing can be better understood according to the following clauses:

Clause A1. An arithmetic device comprising: a master instruction processing unit, a master functional unit, a slave instruction processing unit, and a slave functional unit,

Wherein, the main instruction processing unit is configured to send a first control signal to the main function unit according to the input instruction after receiving the input instruction;

The main functional unit is used to decompose the winograd positive transformation of the input data into a summation operation according to the first control signal, perform calculations to obtain the winograd positive transformation result of the input data, and send all the data to the slave functional unit. The winograd positive transformation result of the input data,

Wherein, the winograd positive transformation result of the input data includes the winograd positive transformation result of the input neuron;

The master instruction processing unit is further configured to send a second control signal to the slave instruction processing unit, and the slave instruction processing unit is configured to send the second control signal to the slave functional unit;

The slave functional unit is configured to perform bit-multiplication on the winograd positive transformation result of the input neuron and the winograd positive transformation result of the weight value according to the second control signal to obtain the bit-multiply result, and to obtain the winograd result of the bit-multiply result. The inverse transform is disassembled into a summation operation, and calculation is performed to obtain the winograd convolution result of the input data.

Clause A2. The computing device according to clause A1, wherein the main function unit is used to decompose the input data into a plurality of first sub-tensors according to the first control signal, Perform winograd positive transformation on the tensor and sum to obtain the winograd positive transformation result of the input data.

Clause A3. The computing device according to clause A2, wherein the input data is expressed in the form of a tensor, and the number of the plurality of first sub-tensors is the same as the number of non-zero elements of the input data, One element in each first sub-tensor of the plurality of first sub-tensors is the same as the element at the corresponding position in the input data, and other elements are all zero.

Clause A4. According to the arithmetic device described in Clause A3, performing winograd forward transformation on the plurality of first subtensors and summing them to obtain the winograd forward transformation result of the input data, including:

Obtain the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor; where the first sub-tensor corresponding to the first sub-tensor is: the value of the element at the first position in the first sub-tensor Is 1, where the position of the first position in the first sub-tensor is the same as the position of the non-zero element in the first sub-tensor;

Multiplying the non-zero element value of the first sub-tensor by the coefficient of the winograd positive transformation result of the corresponding first-element sub-tensor to obtain the winograd positive transformation result of the first sub-tensor;

The winograd positive transformation results of the multiple first subtensors are added to obtain the winograd positive transformation result of the input data.

Clause A5. According to the arithmetic device described in Clause A4, the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor is obtained in advance through the following process:

For each first sub-tensor, multiply the left side of the first sub-tensor corresponding to the first sub-tensor by the positive transformation left-multiplying matrix, and the right multiplying the positive transformation right-multiplying matrix to obtain the winograd of the first-element sub-tensor Positive transformation result.

Clause A6. The computing device according to clause A2, wherein the main functional unit includes a cache module, and the main functional unit stores the winograd conversion result of the input data in the cache module, and the cache module also uses To send the winograd positive transformation result of the input data to the slave functional unit.

Clause A7. The computing device according to clause A1, the computing device comprising: a main memory unit,

The main instruction processing unit is configured to send a first control signal to the main memory unit according to the input instruction after receiving the input instruction;

The main memory unit is configured to send the input data to the main function unit according to the first control signal.

Clause A8. The arithmetic device according to clause A1, wherein the slave function unit is used to decompose the alignment multiplication result into a plurality of second sub-tensors, and perform winograd inverse on the plurality of second sub-tensors Transform and sum to obtain the winograd convolution result of the input data.

Clause A9. The arithmetic device according to clause A8, wherein the number of the plurality of second sub-tensors is the same as the number of non-zero elements of the result of the bitwise multiplication, and each of the plurality of second sub-tensors One element of the second subtensor is the same as the element at the corresponding position in the result of the bitwise multiplication, and the other elements are all 0.

Clause A10. The computing device according to clause A9, performing winograd inverse transformation on the plurality of second subtensors and summing them to obtain the winograd convolution result of the input data, including:

Obtain the winograd inverse transform result of the second sub-tensor corresponding to the second sub-tensor; where the second sub-tensor corresponding to the second sub-tensor is: the value of the element at the second position in the second sub-tensor Is 1, where the position of the second position in the second sub-tensor is the same as the position of the non-zero element in the second sub-tensor;

Multiplying the non-zero element value of the second sub-tensor by the winograd inverse transform result of the corresponding second-element sub-tensor as the coefficient to obtain the winograd inverse transform result of the second sub-tensor;

The winograd inverse transform results of the multiple second subtensors are added to obtain the winograd convolution result of the input data.

Clause A11. According to the arithmetic device described in Clause A10, the winograd inverse transformation result of the second-element subtensor is obtained in advance through the following process:

For each second sub-tensor, multiply the left side of the second-element sub-tensor corresponding to the second sub-tensor by the inverse transform left-multiply matrix, and the right-side multiply the inverse transform right-multiply matrix to obtain the winograd of the second-element sub-tensor Inverse transform result.

Clause A12. The computing device according to clause A1, wherein the computing device further includes: a slave memory unit,

The slave instruction processing unit is also used to send the second control signal to the slave memory unit;

The slave memory unit is configured to send the winograd positive transformation result of the weight to the slave functional unit according to the second control signal.

Clause A13. The computing device according to any one of clauses A7-A12, wherein the computing device further includes a main memory unit, and the slave function unit is further configured to send the winograd convolution result of the input data to the master Memory unit.

Clause A14. The arithmetic device according to any one of clauses A7-A12, wherein the slave function unit is also used to perform post-processing on the winograd convolution result of the input data, and the post-processing includes bitwise rounding operations and Revolution operation.

Clause A14. An artificial intelligence chip including the computing device as described in any one of clauses A1-A14.

Clause A15. An electronic device including the artificial intelligence chip as described in Clause A14.

The embodiments of the present disclosure are described in detail above, and specific examples are used in this article to illustrate the principles and implementations of the present disclosure. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present disclosure. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present disclosure, the specific embodiments and the scope of application of the present disclosure, are all within the protection scope of the present disclosure. In summary, the content of this specification should not be construed as a limitation of this disclosure.

Claims (16)

1. An arithmetic device, characterized in that the arithmetic device comprises: a master instruction processing unit, a master functional unit, a slave instruction processing unit, and a slave functional unit,

   Wherein, the main instruction processing unit is configured to send a first control signal to the main function unit according to the input instruction after receiving the input instruction;

   The main functional unit is used to decompose the winograd positive transformation of the input data into a summation operation according to the first control signal, perform calculations to obtain the winograd positive transformation result of the input data, and send all the data to the slave functional unit. The winograd positive transformation result of the input data,

   Wherein, the winograd positive transformation result of the input data includes the winograd positive transformation result of the input neuron;

   The master instruction processing unit is further configured to send a second control signal to the slave instruction processing unit, and the slave instruction processing unit is configured to send the second control signal to the slave functional unit;

   The slave functional unit is configured to perform bit-multiplication on the winograd positive transformation result of the input neuron and the winograd positive transformation result of the weight value according to the second control signal to obtain the bit-multiply result, and to obtain the winograd result of the bit-multiply result. The inverse transform is disassembled into a summation operation, and calculation is performed to obtain the winograd convolution result of the input data.
2. The computing device according to claim 1, wherein the main function unit is configured to decompose the input data into a plurality of first sub-tensors according to the first control signal, and perform a calculation on the plurality of first sub-tensors. A sub-tensor is subjected to winograd positive transformation and summed to obtain the winograd positive transformation result of the input data.
3. The computing device according to claim 2, wherein the input data is expressed in a tensor form, and the number of the plurality of first sub-tensors and the number of non-zero elements of the input data Same, one element in each first sub-tensor of the plurality of first sub-tensors is the same as the element at the corresponding position in the input data, and other elements are all zero.
4. 3. The computing device of claim 3, wherein performing winograd forward transformation on the plurality of first sub-tensors and summing them to obtain the winograd forward transformation result of the input data comprises:

   Obtain the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor; where the first sub-tensor corresponding to the first sub-tensor is: the value of the element at the first position in the first sub-tensor Is 1, where the position of the first position in the first sub-tensor is the same as the position of the non-zero element in the first sub-tensor;

   Multiplying the non-zero element value of the first sub-tensor by the coefficient of the winograd positive transformation result of the corresponding first-element sub-tensor to obtain the winograd positive transformation result of the first sub-tensor;

   The winograd positive transformation results of the multiple first subtensors are added to obtain the winograd positive transformation result of the input data.
5. The computing device according to claim 4, wherein the winograd positive transformation result of the first sub-tensor corresponding to the first sub-tensor is obtained in advance through the following process:

   For each first sub-tensor, multiply the left side of the first sub-tensor corresponding to the first sub-tensor by the positive transformation left-multiplying matrix, and the right multiplying the positive transformation right-multiplying matrix to obtain the winograd of the first-element sub-tensor Positive transformation result.
6. The computing device according to claim 2, wherein the main functional unit comprises a cache module, the main functional unit stores the winograd positive transformation result of the input data in the cache module, and the cache module It is also used to send the winograd positive transformation result of the input data to the slave functional unit.
7. The computing device according to claim 1, wherein the computing device comprises: a main memory unit,

   The main instruction processing unit is configured to send a first control signal to the main memory unit according to the input instruction after receiving the input instruction;

   The main memory unit is configured to send the input data to the main function unit according to the first control signal.
8. The computing device according to claim 1, wherein the slave function unit is used to decompose the alignment multiplication result into a plurality of second sub-tensors, and perform operations on the plurality of second sub-tensors. The winograd inverse transform and summation obtain the winograd convolution result of the input data.
9. 8. The arithmetic device according to claim 8, wherein the number of the plurality of second sub-tensors is the same as the number of non-zero elements of the result of the bitwise multiplication, and the plurality of second sub-tensors Each second sub-tensor of has an element that is the same as the element at the corresponding position in the result of the bitwise multiplication, and the other elements are all 0.
10. 9. The computing device of claim 9, wherein performing winograd inverse transformation on the plurality of second sub-tensors and summing them to obtain a winograd convolution result of the input data comprises:

    Obtain the winograd inverse transform result of the second sub-tensor corresponding to the second sub-tensor; where the second sub-tensor corresponding to the second sub-tensor is: the value of the element at the second position in the second sub-tensor Is 1, where the position of the second position in the second sub-tensor is the same as the position of the non-zero element in the second sub-tensor;

    Multiplying the non-zero element value of the second sub-tensor by the winograd inverse transform result of the corresponding second-element sub-tensor as the coefficient to obtain the winograd inverse transform result of the second sub-tensor;

    The winograd inverse transform results of the multiple second subtensors are added to obtain the winograd convolution result of the input data.
11. 11. The arithmetic device according to claim 10, wherein the winograd inverse transformation result of the second-element sub-tensor is obtained in advance through the following process:

    For each second sub-tensor, multiply the left side of the second-element sub-tensor corresponding to the second sub-tensor by the inverse transform left-multiply matrix, and the right-side multiply the inverse transform right-multiply matrix to obtain the winograd of the second-element sub-tensor Inverse transform result.
12. The computing device according to claim 1, wherein the computing device further comprises: a slave memory unit,

    The slave instruction processing unit is also used to send the second control signal to the slave memory unit;

    The slave memory unit is configured to send the winograd positive transformation result of the weight to the slave functional unit according to the second control signal.
13. The arithmetic device according to any one of claims 7-12, wherein the arithmetic device further comprises a main memory unit, and the slave functional unit is also used to send the winograd convolution result of the input data to the The main memory unit.
14. The arithmetic device according to any one of claims 7-12, wherein the slave function unit is further configured to perform post-processing on the winograd convolution result of the input data, and the post-processing includes bitwise rounding Operation and revolution operation.
15. An artificial intelligence chip, characterized in that the chip includes the computing device according to any one of claims 1-14.
16. An electronic device, wherein the electronic device comprises the artificial intelligence chip according to claim 15.

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