WO2022001500A1

WO2022001500A1 - Computing apparatus, integrated circuit chip, board card, electronic device, and computing method

Info

Publication number: WO2022001500A1
Application number: PCT/CN2021/095705
Authority: WO
Inventors: 陶劲桦; 刘少礼
Original assignee: 上海寒武纪信息科技有限公司
Priority date: 2020-06-30
Filing date: 2021-05-25
Publication date: 2022-01-06
Also published as: CN113867800A; CN118012505A

Abstract

A computing apparatus, an integrated circuit chip, a board card, an electronic device, and a method of executing an arithmetic operation using said computing apparatus. The computing apparatus may be comprised in a combined processing apparatus, the combined processing apparatus may further comprise a universal interconnection interface and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus. The storage apparatus is connected to the device and other processing apparatuses, respectively, and used for storing data of the device and other processing apparatuses.

Description

Computing device, integrated circuit chip, board card, electronic device and computing method

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed on June 30, 2020, the application number is 2020106194608, and the title is "computing device, integrated circuit chip, board card, electronic equipment and computing method", the full text of which is hereby incorporated Incorporated by reference.

technical field

The present disclosure relates generally to the field of computing. More particularly, the present disclosure relates to a computing device, an integrated circuit chip, a board, an electronic device, and a computing method.

Background technique

In a computing system, an instruction set is a set of instructions for performing computations and controlling the computing system, and plays a key role in improving the performance of computing chips (eg, processors) in the computing system. Various current computing chips (especially chips in the field of artificial intelligence) can complete various general or specific control operations and data processing operations by using associated instruction sets. However, the current instruction set still has many defects. For example, the existing instruction set is limited by hardware architecture and is less flexible in terms of flexibility. Further, many instructions can only complete a single operation, and the execution of multiple operations usually requires multiple instructions, which potentially leads to an increase in on-chip I/O data throughput. In addition, the current instructions have improvements in execution speed, execution efficiency, and power consumption on the chip.

In addition, the arithmetic instructions of conventional processor CPUs are designed to perform basic single-data scalar arithmetic operations. Here, a single data operation means that each operand of the instruction is a scalar data. However, in tasks such as image processing and pattern recognition, the oriented operands are often multi-dimensional vector (ie, tensor data) data types, and only using scalar operations cannot enable hardware to efficiently complete computing tasks. Therefore, how to efficiently perform multi-dimensional tensor operations is also an urgent problem to be solved in the current computing field.

SUMMARY OF THE INVENTION

In order to at least solve the above-mentioned problems in the prior art, the present disclosure provides a hardware architecture platform and a solution of related instructions. With the solution disclosed in the present disclosure, the flexibility of the instruction can be increased, the efficiency of the instruction execution can be improved, and the calculation cost and overhead can be reduced. Further, the solution of the present disclosure supports efficient memory access and processing of tensor data on the basis of the aforementioned hardware architecture, thereby accelerating tensor operations and reducing the cost of tensor operations when multi-dimensional vector operands are included in the calculation instructions. computational overhead.

In a first aspect, the present disclosure discloses a computing device comprising a master processing circuit and at least one slave processing circuit, wherein: the master processing circuit is configured to perform a master arithmetic operation in response to a master instruction, the slave processing circuit be configured to perform a slave operation operation in response to a slave instruction, wherein the master operation operation includes a pre-processing operation and/or a post-processing operation for the slave operation operation, the master instruction and the slave instruction according to the The calculation instruction received by the computing device is obtained by parsing, wherein the operand of the calculation instruction includes a descriptor used to indicate the shape of the tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand, wherein the main The processing circuit and/or the slave processing circuit are configured to perform respective corresponding master arithmetic operations and/or slave processing operations according to the storage address.

In a second aspect, the present disclosure discloses an integrated circuit chip comprising the computing device mentioned in the previous aspect and described in the various embodiments that follow.

In a third aspect, the present disclosure discloses a board including the integrated circuit chip mentioned in the previous aspect and described in various embodiments later.

In a fourth aspect, the present disclosure discloses an electronic device comprising the integrated circuit chip mentioned in the previous aspect and described in the various embodiments that follow.

In a fifth aspect, the present disclosure discloses a method of performing a computing operation using the aforementioned computing device, wherein the computing device includes a master processing circuit and at least one slave processing circuit, the method comprising: converting the master processing circuit The circuit is configured to perform a master arithmetic operation in response to a master instruction, and the slave processing circuit is configured to perform a slave arithmetic operation in response to the slave instruction, wherein the master arithmetic operation includes a preprocessing operation for the slave arithmetic operation and /or post-processing operation, the master instruction and the slave instruction are parsed according to the calculation instruction received by the computing device, wherein the operand of the calculation instruction includes a descriptor for indicating the shape of the tensor, the description The operator is used to determine the storage address of the data corresponding to the operand, wherein the method further includes configuring the master processing circuit and/or the slave processing circuit to perform the respective corresponding master operation and/or according to the storage address. from the processing operation.

Using the computing device, integrated circuit chip, board, electronic device and method disclosed in the present disclosure, the master and slave instructions related to the master operation and the slave operation can be efficiently executed, thereby speeding up the execution of the operation. Further, due to the combination of the master operation and the slave operation, the computing device of the present disclosure can support more types of operations and operations. In addition, based on the pipeline operation arrangement of the computing device of the present disclosure, the computing instructions can be flexibly configured to meet computing requirements.

Description of drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation, and like or corresponding reference numerals refer to like or corresponding parts wherein:

1a is a schematic diagram illustrating a computing device according to an embodiment of the present disclosure;

Figure 1b is a schematic diagram illustrating a data storage space according to an embodiment of the present disclosure;

2 is a block diagram illustrating a computing device according to an embodiment of the present disclosure;

3 is a block diagram illustrating a main processing circuit of a computing device according to an embodiment of the present disclosure;

4a, 4b and 4c are schematic diagrams illustrating matrix conversion performed by a data conversion circuit according to an embodiment of the present disclosure;

5 is a block diagram illustrating a slave processing circuit of a computing device according to an embodiment of the present disclosure;

FIG. 6 is a block diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and

FIG. 7 is a schematic structural diagram illustrating a board according to an embodiment of the present disclosure.

detailed description

The solution of the present disclosure utilizes the hardware architecture of a master processing circuit and at least one slave processing circuit to perform associated data operations, so that relatively complex operations can be performed using relatively flexible and simplified computing instructions. Specifically, the solution of the present disclosure utilizes the master instruction and the slave instruction obtained by parsing the computing instruction, and causes the master processing circuit to execute the master instruction to realize the master operation, and the slave processing circuit to execute the slave instruction to realize the slave operation, so as to Implements various complex operations including, for example, vector operations. Here, the master arithmetic operation may include a pre-processing operation and/or a post-processing operation with respect to the slave arithmetic operation. In one embodiment, the preprocessing operation may be, for example, a data conversion operation and/or a data concatenation operation. In another embodiment, the post-processing operation may be, for example, an arithmetic operation on the result output from the processing circuit. In some scenarios, when an operand of a computation instruction includes a descriptor for indicating the shape of a tensor, the disclosed scheme utilizes the descriptor to determine the storage address of the data corresponding to the operand. Based on this, the master processing circuit and/or the slave processing circuit may be configured to perform respective corresponding master operation and/or slave operation according to the storage address, wherein the master operation and/or the slave operation may involve a Various operations on data. In addition, according to different arithmetic circuits or arithmetic units in the main processing circuit, the computing instructions of the present disclosure support flexible and personalized configurations to meet different application scenarios.

The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1a is a schematic diagram illustrating a computing device 100 according to an embodiment of the present disclosure. As shown in FIG. 1a, computing device 100 may include a master processing circuit 102 and slave processing circuits, such as

slave processing circuits

104, 106 and 108 shown in the figure. Although three slave processing circuits are shown here, those skilled in the art will understand that the computing device 100 of the present disclosure may include any suitable number of slave processing circuits, and between multiple slave processing circuits, multiple slave processing circuits and a master processing circuit The circuits may be connected in different ways, and this disclosure does not make any limitation. In one or more embodiments, the multiple slave processing circuits of the present disclosure can execute various slave instructions (eg, obtained by parsing the computing instructions) in parallel, so as to improve the processing efficiency of the computing device.

In the context of the present disclosure, a computing instruction may be an instruction in an instruction system of an interactive interface between software and hardware, which may be a binary or other form of machine language that is received and processed by hardware such as a processor (or processing circuit) . Compute instructions may include opcodes and operands for instructing the processor to operate. According to different application scenarios, the calculation instruction may include one or more operation codes, and when the foregoing calculation instruction includes one operation code, the operation code may be used to instruct multiple operations of the processor. Additionally, a compute instruction may also include one or more operands. According to the solution of the present disclosure, the operand may include a descriptor for indicating the shape of the tensor, and the descriptor may be used to determine the storage address of the data corresponding to the operand.

In one embodiment, the master instruction and the slave instruction may be obtained by parsing the computing instruction received by the computing device. In operation, the master processing circuit may be configured to perform a master arithmetic operation in response to a master instruction, and the slave processing circuit may be configured to perform a slave arithmetic operation in response to a slave instruction. According to the solution of the present disclosure, the aforementioned master instruction or slave instruction may be a microinstruction or a control signal running inside the processor, and may include (or instruct) one or more operations. When the operands of the compute instruction include descriptors as previously described, the master processing circuit and/or the slave processing circuit may be configured to fetch the tensors according to the memory addresses obtained based on the descriptors. Through the descriptor-based memory access mechanism, the solution of the present disclosure can significantly improve the reading and storage speed of tensor data in performing tensor operations, thereby speeding up computation and reducing computation overhead.

In one embodiment, the aforementioned master arithmetic operations may include pre-processing operations and/or post-processing operations for the slave arithmetic operations. Specifically, for the main instruction executed by the main processing circuit, it may include, for example, a preprocessing operation of performing data conversion and/or data splicing on the data to be involved in the operation. In some application scenarios, the master instruction may also include preprocessing operations that only selectively read data, such as reading and sending data stored in a dedicated or private buffer to the slave processing circuit, or for the slave processing circuit The operation generates the corresponding random number. In other application scenarios, depending on the type and number of operators included in the main processing circuit, the main instruction may include one or more post-processing operations associated with the functions of the operators. For example, the main instruction may include various types of operations such as addition, multiplication, table lookup, comparison, averaging, filtering, etc., on the intermediate or final operation result obtained after the slave processing circuit executes the slave instruction. In some application scenarios, the aforementioned intermediate operation result or final operation result may be the aforementioned tensor, and its storage address may be obtained according to the descriptor of the present disclosure.

In order to facilitate the identification of the pre-processing operation and/or the post-processing operation, in some application scenarios, the main instruction may include an identification bit for identifying the pre-processing operation and/or the post-processing operation. Therefore, when acquiring the main instruction, the main processing circuit can determine whether to perform a pre-processing operation or a post-processing operation on the operation data according to the identification bit. Additionally or alternatively, the pre-processing operation and the post-processing operation in the main instruction may be matched by a preset position (or called an instruction field segment) of the calculation instruction. For example, when a preset position including (master instruction+slave instruction) is set in the calculation instruction, it can be determined that the master instruction in the calculation instruction involves the preprocessing operation for the slave operation. For another example, when a preset position including (slave instruction+master instruction) is set in the calculation instruction, it can be determined that the master instruction in the calculation instruction involves the post-processing operation on the slave operation. For ease of understanding, it is assumed that the calculation instruction has a length of three predetermined bit widths (that is, the aforementioned preset positions), then the instruction located in the first predetermined bit width can be designated as the main instruction for the preprocessing operation, located in the middle position The second segment of pre-width instructions is designated as a slave instruction for slave operations, and the third segment of pre-width instructions in the last position is designated as a master instruction for post-processing operations.

For a slave instruction to be executed by the slave processing circuit, it may include one or more operations associated with the functionality of one or more arithmetic circuits in the slave processing circuit. The slave instruction may include an operation for performing an operation on the data after the preprocessing operation is performed by the master processing circuit. In some application scenarios, the slave instruction may include various operations such as arithmetic operation, logical operation, and data type conversion. For example, the slave instruction may include performing various vector-related multiply-add operations on the data subjected to the preprocessing operation, including, for example, convolution operations. In other application scenarios, when the aforementioned calculation instruction does not include a master instruction related to the preprocessing operation, the slave processing circuit may also directly perform a slave operation on the input data according to the slave instruction.

In one or more embodiments, the master processing circuit 102 may be configured to obtain and parse the computational instructions to obtain the aforementioned master and slave instructions, and to send the slave instructions to the slave processing circuits. Specifically, the main processing circuit may include one or more decoding circuits (or decoders) for parsing computational instructions. Through the internal decoding circuit, the master processing circuit can parse the received calculation instruction into one or more master instructions and/or slave instructions, and send the corresponding slave instructions to the slave processing circuit, so that the slave processing circuit can execute the slave operation. operate. Here, depending on the application scenario, the slave instruction can be sent to the slave processing circuit in various ways. For example, when storage circuitry is included in a computing device, the master processing circuitry may send slave instructions to the storage circuitry, and via the storage circuitry to slave processing circuitry. For another example, when multiple slave processing circuits perform parallel operations, the master processing circuit may broadcast the same slave instruction to the multiple slave processing circuits. Additionally or alternatively, in some hardware architecture scenarios, the computing device may further include a separate circuit, unit or module dedicated to parsing the computing instructions received by the computing device, such as the architecture described later in conjunction with FIG. 2 . .

In one or more embodiments, the slave processing circuits of the present disclosure may include a plurality of arithmetic circuits for performing slave arithmetic operations, wherein the plurality of arithmetic circuits may be connected and configured to perform multi-stage pipelined arithmetic operations. Depending on the operation scenario, the operation circuit may include one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit for performing at least vector operations. In one embodiment, when the computing device of the present disclosure is applied to computing in the field of artificial intelligence, the slave processing circuit can perform the multi-dimensional convolution operation in the neural network according to the slave instruction.

As mentioned above, the master operation and/or the slave operation of the present disclosure may also include various types of operations on tensor data, for which the solution of the present disclosure proposes to use descriptors to obtain information about the shape of the tensor , so as to determine the storage address of the tensor data, so as to obtain and save the tensor data through the aforementioned storage address.

In a possible implementation, the shape of the N-dimensional tensor data can be indicated by a descriptor, where N is a positive integer, such as N=1, 2, or 3, or zero. Among them, tensors can contain various forms of data composition. Tensors can be of different dimensions. For example, scalars can be regarded as 0-dimensional tensors, vectors can be regarded as 1-dimensional tensors, and matrices can be 2-dimensional or 2-dimensional. A tensor of more than dimensionality. The shape of a tensor includes information such as the dimension of the tensor and the dimensions of each dimension of the tensor. For example, for tensors:

The shape of the tensor can be described by the descriptor as (2, 4), that is, two parameters indicate that the tensor is a two-dimensional tensor, and the size of the first dimension (column) of the tensor is 2, the first dimension The dimension of the two dimensions (rows) is 4. It should be noted that the present application does not limit the manner in which the descriptor indicates the shape of the tensor.

In a possible implementation manner, the value of N may be determined according to the dimension (order) of the tensor data, and may also be set according to the usage requirements of the tensor data. For example, when the value of N is 3, the tensor data is three-dimensional tensor data, and the descriptor can be used to indicate the shape (eg offset, size, etc.) of the three-dimensional tensor data in the three-dimensional direction. It should be understood that those skilled in the art can set the value of N according to actual needs, which is not limited in the present disclosure.

In a possible implementation manner, the descriptor may include the identifier of the descriptor and/or the content of the descriptor. The identifier of the descriptor is used to distinguish the descriptor, for example, the identifier of the descriptor may be numbered; the content of the descriptor may include at least one shape parameter representing the shape of the tensor data. For example, the tensor data is 3-dimensional data. Among the three dimensions of the tensor data, the shape parameters of two dimensions are fixed, and the content of the descriptor may include the shape representing the other dimension of the tensor data. parameter.

In one possible implementation, the identifier and/or content of the descriptor may be stored in a descriptor storage space (internal memory), such as a register, on-chip SRAM or other medium caches, and the like. The tensor data indicated by the descriptor can be stored in data storage space (internal memory or external memory), such as on-chip cache or off-chip memory, etc. The present disclosure does not limit the specific locations of the descriptor storage space and the data storage space.

In a possible implementation, the identifier, content of the descriptor, and tensor data indicated by the descriptor can be stored in the same area of the internal memory, for example, a continuous area of the on-chip cache can be used to store the related information of the descriptor content, its address is ADDR0-ADDR1023. Among them, the addresses ADDR0-ADDR63 can be used as the descriptor storage space to store the identifier and content of the descriptor, and the addresses ADDR64-ADDR1023 can be used as the data storage space to store the tensor data indicated by the descriptor. In the descriptor storage space, addresses ADDR0-ADDR31 can be used to store the identifier of the descriptor, and addresses ADDR32-ADDR63 can be used to store the content of the descriptor. It should be understood that the address ADDR is not limited to 1 bit or one byte, and is used here to represent an address, which is an address unit. Those skilled in the art can determine the descriptor storage space, the data storage space and their specific addresses according to actual conditions, which are not limited in this disclosure.

In one possible implementation, the identifier, content of the descriptor, and tensor data indicated by the descriptor may be stored in different areas of the internal memory. For example, a register can be used as a descriptor storage space to store the identifier and content of the descriptor in the register, and an on-chip cache can be used as a data storage space to store the tensor data indicated by the descriptor.

In a possible implementation manner, when a register is used to store the identifier and content of the descriptor, the number of the register may be used to represent the identifier of the descriptor. For example, when the number of the register is 0, the identifier of the descriptor it stores is set to 0. When the descriptor in the register is valid, an area can be allocated in the cache space for storing the tensor data according to the size of the tensor data indicated by the descriptor.

In a possible implementation manner, the identifier and content of the descriptor may be stored in an internal memory, and the tensor data indicated by the descriptor may be stored in an external memory. For example, the identifier and content of the descriptor can be stored on-chip, and the tensor data indicated by the descriptor can be stored off-chip.

In a possible implementation manner, the data address of the data storage space corresponding to each descriptor may be a fixed address. For example, a separate data storage space can be divided for tensor data, and the starting address of each tensor data in the data storage space corresponds to a descriptor one-to-one. In this case, the control circuit can determine the data address in the data storage space of the data corresponding to the operand according to the descriptor.

In a possible implementation manner, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor may also be used to indicate the address of N-dimensional tensor data, wherein the descriptor The content of can also include at least one address parameter representing the address of the tensor data. For example, if the tensor data is 3-dimensional data, when the descriptor points to the address of the tensor data, the content of the descriptor may include an address parameter indicating the address of the tensor data, such as the starting physical address of the tensor data, It may also include multiple address parameters of the address of the tensor data, such as the start address + address offset of the tensor data, or address parameters of the tensor data based on each dimension. Those skilled in the art can set address parameters according to actual needs, which are not limited in the present disclosure.

In a possible implementation manner, the address parameter of the tensor data may include a reference address of the data reference point of the descriptor in the data storage space of the tensor data. Among them, the reference address can be different according to the change of the data reference point. This disclosure does not limit the selection of data benchmarks.

In a possible implementation manner, the reference address may include a start address of the data storage space. When the data reference point of the descriptor is the first data block of the data storage space, the reference address of the descriptor is the starting address of the data storage space. When the data reference point of the descriptor is other data than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

In a possible implementation manner, the shape parameter of the tensor data includes at least one of the following: the size of the data storage space in at least one direction of N dimensions, the size of the storage area in N dimensions The size in at least one direction of , the offset of the storage area in at least one direction of N dimensions, the position of at least two vertices at the diagonal positions of N dimensions relative to the data reference point , the mapping relationship between the data description location of the tensor data indicated by the descriptor and the data address. The data description position is the mapping position of the point or area in the tensor data indicated by the descriptor. For example, when the tensor data is 3-dimensional data, the descriptor can be represented by three-dimensional space coordinates (x, y, z). The shape of the tensor data, and the data description position of the tensor data may be the position of a point or area in the three-dimensional space that the tensor data is mapped to, represented by three-dimensional space coordinates (x, y, z).

It should be understood that those skilled in the art can select the shape parameters representing the tensor data according to the actual situation, which is not limited in the present disclosure. By using descriptors in the data access process, the association between data can be established, thereby reducing the complexity of data access and improving the efficiency of instruction processing.

In a possible implementation manner, the reference address of the data reference point of the descriptor in the data storage space of the tensor data, the reference address of the data storage space in at least one of the N dimension directions of the data storage space may be used in a possible implementation manner. The size, the size of the storage area in at least one of the N-dimensional directions, and/or the offset of the storage area in at least one of the N-dimensional directions, determine the size of the descriptor of the tensor data. content.

Figure 1b shows a schematic diagram of a data storage space according to an embodiment of the present disclosure. As shown in Figure 1b, the data storage space 21 stores a two-dimensional data in a row-first manner, which can be represented by (x, y) (where the X axis is horizontally to the right, and the Y axis is vertically downward), and the X axis direction The size (the size of each line) on the ori_x (not shown in the figure), the size in the Y-axis direction (the total number of lines) is ori_y (not shown in the figure), the starting address of the data storage space 21 PA_start (reference address) is the physical address of the first data block 22. The data block 23 is part of the data in the data storage space 21, the offset 25 in the X-axis direction is represented as offset_x, the offset 24 in the Y-axis direction is represented as offset_y, and the size in the X-axis direction is represented by is size_x, and the size in the Y-axis direction is represented by size_y.

In a possible implementation manner, when a descriptor is used to define the data block 23, the data reference point of the descriptor may use the first data block of the data storage space 21, and the reference address of the descriptor may be agreed as the data storage space 21 The starting address of PA_start. Then the size ori_x on the X axis, the size ori_y on the Y axis of the data storage space 21, and the offset amount offset_y in the Y axis direction, the offset amount offset_x in the X axis direction, and the offset amount in the X axis direction of the data block 23 can be combined. The content of the descriptor of the data block 23 is determined by the size size_x and the size size_y in the Y-axis direction.

In a possible implementation, the following formula (1) can be used to represent the content of the descriptor:

It should be understood that although in the above example, the content of the descriptor represents a two-dimensional space, those skilled in the art can set the specific dimension of the content of the descriptor according to the actual situation, which is not limited in the present disclosure.

In a possible implementation manner, a reference address of the data reference point of the descriptor in the data storage space may be agreed, and on the basis of the reference address, according to at least two diagonal positions in the N dimension directions The position of each vertex relative to the data reference point determines the content of the descriptor of the tensor data.

For example, the base address PA_base of the data base point of the descriptor in the data storage space may be agreed. For example, one piece of data (for example, the data at the position (2, 2)) may be selected in the data storage space 21 as the data reference point, and the physical address of the data in the data storage space may be used as the reference address PA_base. The content of the descriptor of the data block 23 in FIG. 1b can be determined according to the positions of the two diagonal vertices relative to the data reference point. First, the positions of at least two vertices of the diagonal positions of the data block 23 relative to the data reference point are determined, for example, the positions of the diagonal position vertices relative to the data reference point in the upper left to lower right direction are used, wherein the upper left corner vertex is The relative position is (x_min, y_min), the relative position of the lower right vertex is (x_max, y_max), and then the relative position of the upper left vertex (x_min, y_min) and the relative position of the lower right vertex (x_max, y_max) determines the content of the descriptor of the data block 23.

In a possible implementation, the following formula (2) can be used to represent the content of the descriptor (the base address is PA_base):

It should be understood that, although the vertices in the upper left corner and the lower right corner are used to determine the content of the descriptor in the above example, those skilled in the art can set the specific vertices of the at least two vertices in the diagonal positions according to actual needs. , this disclosure does not limit this.

In a possible implementation manner, the reference address of the data reference point of the descriptor in the data storage space and the distance between the data description position and the data address of the tensor data indicated by the descriptor may be used. The mapping relationship determines the content of the descriptor of the tensor data. Among them, the mapping relationship between the data description position and the data address can be set according to actual needs. For example, when the tensor data indicated by the descriptor is three-dimensional space data, the function f(x, y, z) can be used to define The data describes the mapping relationship between the location and the data address.

In a possible implementation, the following formula (3) can be used to represent the content of the descriptor:

In a possible implementation manner, the descriptor is further used to indicate the address of N-dimensional tensor data, wherein the content of the descriptor further includes at least one address parameter indicating the address of the tensor data, such as description The content of the character can be:

D:

Where PA is the address parameter. The address parameter can be a logical address or a physical address. The descriptor parsing circuit can take PA as any one of the vertex, middle point or preset point of the vector shape, and obtain the corresponding data address in combination with the shape parameters in the X and Y directions.

In a possible implementation manner, the address parameter of the tensor data includes a reference address of the data reference point of the descriptor in the data storage space of the tensor data, and the reference address includes the data storage The starting address of the space.

In a possible implementation manner, the descriptor may further include at least one address parameter representing the address of the tensor data, for example, the content of the descriptor may be:

D:

Among them, PA_start is a reference address parameter, which is not repeated here.

It should be understood that those skilled in the art can set the mapping relationship between the data description location and the data address according to the actual situation, which is not limited in the present disclosure.

In a possible implementation manner, a predetermined reference address may be set in a task, the descriptors in the instructions under this task all use the reference address, and the content of the descriptor may include shape parameters based on the reference address. The base address can be determined by setting the environment parameters for this task. For the relevant description and usage of the reference address, reference may be made to the foregoing embodiments. In this implementation, the content of the descriptor can be mapped to the data address more quickly.

In a possible implementation manner, a reference address may be included in the content of each descriptor, and the reference address of each descriptor may be different. Compared with the method of setting a common reference address by using environmental parameters, each descriptor in this method can describe data more flexibly and use a larger data address space.

In a possible implementation manner, the data address in the data storage space of the data corresponding to the operand of the processing instruction may be determined according to the content of the descriptor. Among them, the calculation of the data address is automatically completed by the hardware, and when the representation of the content of the descriptor is different, the calculation method of the data address is also different. This disclosure does not limit the specific calculation method of the data address.

For example, the content of the descriptor in the operand is represented by formula (1), the offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y respectively, and the size is size_x*size_y, then, the _{The starting data address PA1 (x, y) of the} tensor data indicated by the descriptor in the data storage space can be determined using the following formula (4):

PA1 _(x,y) =PA_start+(offset_y-1)*ori_x+offset_x(4)

_{According to the data starting address PA1 (x,y} ) determined by the above formula (4), combined with the offset offset_x and offset_y, and the size_x and size_y of the storage area, it can be determined that the tensor data indicated by the descriptor is stored in the data storage area. storage area in space.

In a possible implementation manner, when the operand further includes a data description location for the descriptor, the data address in the data storage space of the data corresponding to the operand can be determined according to the content of the descriptor and the data description location. In this way, part of the data (eg, one or more data) in the tensor data indicated by the descriptor can be processed.

For example, the content of the descriptor in the operand is represented by formula (1). The offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y respectively, and the size is size_x*size_y. The operand includes The data description position for the descriptor is (x _q , y _q _{), then, the data address PA2 (x, y) of the} tensor data indicated by the descriptor in the data storage space can use the following formula (5) to make sure:

PA2 _(x,y) = PA_start+(offset_y+y _q -1)*ori_x+(offset_x+x _q ) (5)

The computing device of the present disclosure has been described above in conjunction with FIG. 1a and FIG. 1b. By using the computing device and the master instruction and the slave instruction of the present disclosure, one computing instruction can be used to complete multiple operations, reducing the need for multiple instructions for multiple operations. Completing the data transfer required for each instruction caused by it solves the IO bottleneck problem of the computing device, effectively improving the computing efficiency and reducing the computing overhead. In addition, the solution of the present disclosure can also flexibly set the parameters included in the calculation instruction according to the type of the arithmetic unit configured in the master processing circuit, the function of the arithmetic circuit configured in the slave processing circuit, and through the cooperation of the master processing circuit and the slave processing circuit. The type and number of operations can be used so that the computing device can perform various types of computing operations, thereby expanding and enriching the application scenarios of the computing device and meeting different computing requirements.

In addition, since the master processing circuit and the slave processing circuit can be configured to support multi-stage pipeline operations, the execution efficiency of the operators in the master processing circuit and the slave processing circuit is improved, and the calculation time is further shortened. Based on the above description, those skilled in the art can understand that the hardware architecture shown in FIG. 1a is only exemplary and not limiting. Under the disclosure and teaching of the present disclosure, those skilled in the art can also add new circuits or devices based on the architecture to realize more functions or operations. For example, memory circuits can be added to the architecture shown in FIG. 1a to store various types of instructions and data (eg, tensor data). Further, the master processing circuit and the slave processing circuit can also be arranged in different physical or logical positions, and the two can be connected through various data interfaces or interconnection units, so that the above master processing circuit can be completed through the interaction of the two. Arithmetic operations and slave arithmetic operations include various operations on the tensors described in connection with Figure 1b.

FIG. 2 is a block diagram illustrating a computing device 200 according to an embodiment of the present disclosure. It can be understood that the computing device 200 shown in FIG. 2 is a specific implementation of the computing device 100 shown in FIG. 1a, so the details of the master processing circuit and the slave processing circuit of the computing device 100 described in conjunction with FIG. 1a The same applies to the computing device 200 shown in FIG. 2 .

As shown in FIG. 2 , a computing device 200 according to the present disclosure includes a master processing circuit 202 and a plurality of

slave processing circuits

204 , 206 and 208 . Since the operations of the master processing circuit and the slave processing circuit have been described in detail above with reference to FIG. 1a, they will not be repeated here. In addition to including the same master processing circuitry and slave processing circuitry as computing device 100 shown in FIG. 1 a , computing device 200 of FIG. 2 also includes control circuitry 210 and storage circuitry 212 . In one embodiment, the control circuit may be configured to obtain and parse the calculation instruction to obtain the master and slave instructions, and to send the master instruction to the master processing circuit 202 and to The slave instructions are sent to one or more of the plurality of

slave processing circuits

204 , 206 and 208 . In one scenario, the control circuit may send the parsed slave instruction to the slave processing circuit through the master processing circuit, as shown in FIG. 2 . Alternatively, when there is a connection between the control circuit and the slave processing circuit, the control circuit may also directly send the parsed slave instruction to the slave processing circuit. Similarly, when there is a connection between the storage circuit and the slave processing circuit, the control circuit may also send slave instructions to the slave processing circuit via the storage circuit. In some computing scenarios, when the computing instruction includes operands involving tensor operations, the control circuit can use the previously discussed descriptor to determine the storage address of the data corresponding to the operand, such as the starting address of the tensor, and can indicate The master processing circuit or the slave processing circuit acquires the tensor data participating in the tensor operation from the corresponding storage address in the storage circuit 212 in order to perform the tensor operation.

In one or more embodiments, storage circuitry 212 may store various types of computation-related data or instructions, including, for example, the tensors described above. In one scenario, the storage circuit may store neuron or weight data related to the operation of the neural network, or store the final operation result obtained after the main processing circuit performs post-processing operations. Additionally, the storage circuit may store an intermediate result obtained after the preprocessing operation is performed by the main processing circuit, or an intermediate result obtained after the operation operation is performed by the slave processing circuit. In operations on tensors, the aforementioned intermediate results can also be tensor-type data, and are read and stored through the storage address determined by the descriptor. In some application scenarios, storage circuitry may be used as on-chip memory for computing device 200 to perform data read and write operations with off-chip memory, such as through a direct memory access ("DMA") interface. In some scenarios, when the calculation instruction is parsed by the control circuit, the storage circuit may store the operation instruction obtained after parsing by the control circuit, such as a master instruction and/or a slave instruction. In addition, although the storage circuit is shown in a block diagram in FIG. 2, according to different application scenarios, the storage circuit can be implemented as a memory including a main memory and a main buffer, wherein the main memory can be used to store related operation data such as neural elements, weights and various constant items, and the main cache module can be used to temporarily store intermediate data, such as the data after the pre-processing operation and the data before the post-processing operation, and these intermediate data can be used for the operator according to the settings. Invisible.

In the interactive application between the main memory and the main processing circuit, the pipeline operation circuit in the main processing circuit can also perform corresponding operations by means of the mask stored in the main storage circuit. For example, in the process of performing the pipeline operation, the operation circuit may read a mask from the main storage circuit, and the mask may be used to indicate whether the data in the operation circuit to perform the operation operation is valid. The main storage circuit can not only perform internal storage applications, but also have the function of data interaction with storage devices outside the computing device of the present disclosure, such as data exchange with external storage devices through direct memory access ("DMA").

3 is a block diagram illustrating a main processing circuit 300 of a computing device according to an embodiment of the present disclosure. It can be understood that the main processing circuit 300 shown in FIG. 3 is also the main processing circuit shown and described in conjunction with FIG. 1 a and FIG. 2 , so the description of the main processing circuit in FIG. 1 a and FIG. In conjunction with the description of FIG. 3 .

As shown in FIG. 3, the main processing circuit 300 may include a data processing unit 302, a first group of pipeline operation circuits 304, a last group of pipeline operation circuits 306, and one or more groups of pipeline operation circuits located between the two groups (replace with black circles). In one embodiment, the data processing unit 302 includes a data conversion circuit 3021 and a data splicing circuit 3022 . As mentioned above, when the master operation includes a preprocessing operation for the slave operation, such as a data conversion operation or a data splicing operation, the data conversion circuit 3021 or the data splicing circuit 3022 will perform the corresponding conversion according to the corresponding master instruction operation or stitching operation. The conversion operation and the splicing operation will be described below with an example.

As far as the data conversion operation is concerned, when the data bit width input to the data conversion circuit is relatively high (for example, the data bit width is 1024 bits wide), the data conversion circuit can convert the input data to a lower bit width according to the operation requirements. data (for example, the bit width of the output data is 512 bits wide). According to different application scenarios, the data conversion circuit can support conversion between multiple data types, such as FP16 (floating point 16-bit), FP32 (floating point 32-bit), FIX8 (fixed-point 8-bit), FIX4 (fixed-point 8-bit) Conversion between data types with different bit widths, such as 4-bit point), FIX16 (16-bit fixed point), etc. When the data input to the data conversion circuit is a matrix, the data conversion operation may be a conversion performed on the arrangement positions of the matrix elements. The transformation may include, for example, matrix transposition and mirroring (described later in conjunction with Figures 4a-4c), matrix rotation according to a predetermined angle (eg, 90 degrees, 180 degrees or 270 degrees), and transformation of matrix dimensions.

As far as the data splicing operation is concerned, the data splicing circuit can perform parity splicing and other operations on the data blocks extracted from the data according to, for example, the bit length set in the instruction. For example, when the data bit length is 32 bits wide, the data splicing circuit can divide the data into 8 data blocks from 1 to 8 according to the bit width length of 4 bits, and then divide the data blocks 1, 3, 5 and 7 into four data blocks. The data blocks are spliced together, and four data blocks of data 2, 4, 6, and 8 are spliced together for operation.

In other application scenarios, the above-mentioned data splicing operation may also be performed on the data M (for example, a vector) obtained after performing the operation. It is assumed that the data splicing circuit can split the lower 256 bits of the even-numbered lines of the data M first with an 8-bit bit width as 1 unit data to obtain 32 even-numbered line unit data (represented as M_2i ₀ to M_2i _{31 respectively} ). Similarly, the lower 256 bits of the odd-numbered rows of the data M can also be split with an 8-bit bit width as 1 unit data to obtain 32 odd-numbered row unit data (represented as M_(2i+1) ₀ to M_ (2i+1) ₃₁ ). Further, according to the sequence of the data bits from low to high, the even-numbered rows first and then the odd-numbered rows, the split 32 odd-numbered row unit data and 32 even-numbered row unit data are alternately arranged. Specifically, the even-numbered line unit data 0 (M_2i ₀ ) is arranged in the lower order, and then the odd-numbered line unit data 0 (M_(2i+1) ₀ ) is sequentially arranged. Next, even line unit data 1 (M_2i ₁ ) . . . are arranged. By analogy, when the arrangement of odd row unit data 31 (M_(2i+1) ₃₁ ) is completed, 64 unit data are spliced together to form a new data with a bit width of 512 bits.

According to different application scenarios, the data conversion circuit and the data splicing circuit in the data processing unit can be used together to perform data preprocessing more flexibly. For example, depending on the different operations included in the host instruction, the data processing unit may perform only data conversion without data splicing, only data splicing without data conversion, or both data conversion and data splicing. In some scenarios, when the master instruction does not include a preprocessing operation for the slave operation, the data processing unit may be configured to disable the data conversion circuit and the data splicing circuit.

As previously mentioned, the main processing circuit according to the present disclosure may include one or more groups of multi-stage pipeline operation circuits, such as two groups of multi-stage

pipeline operation circuits

304 and 306 as shown in FIG. 3 , wherein each group of multi-stage pipeline operation circuits The circuit performs a multi-stage pipeline operation including the first stage to the Nth stage, wherein each stage may include one or more operators to perform the multi-stage pipeline operation according to the main instruction. In one embodiment, the main processing circuit of the present disclosure may be implemented as a single instruction multiple data (Single Instruction Multiple Data, SIMD) module, and each group of multi-stage pipeline operation circuits may form an operation pipeline. According to the operation requirements, the operation pipeline can be provided with different, different or the same functional modules (that is, the operators of the present disclosure), such as an addition module (or an adder), a multiplication module (or a multiplier), a checker Various types of functional modules such as table modules (or table look-ups).

In some application scenarios, when the sequence requirements of the pipeline are met, different functional modules on a pipeline can be used in combination, and the first-level pipeline completes the operation represented by an operation code ("op") in a microinstruction. Thus, the SIMD of the present disclosure can support different levels of pipelining. That is, the SIMD of the present disclosure can flexibly support combinations of different numbers of ops based on the arrangement of the operators on the operation pipeline.

It is assumed that there is a pipeline (named "stage1") similar to the first group of multi-stage pipeline operation circuits 304 and the second group of multi-stage pipeline operation circuits 306, and six pipelines are arranged in order from top to bottom Function modules to form a six-stage pipeline, specifically: stage1-1-adder 1 (first-stage adder), stage1-2-adder 2 (second-stage adder), stage1-3-multiplier 1 ( First stage multiplier), stage1-4-multiplier 2 (second stage multiplier), stage1-5-adder 1 (first stage adder), stage1-6-adder 2 (second stage adder) ). It can be seen that the first stage adder (which acts as the first stage of the pipeline) and the second stage adder (which acts as the second stage of the pipeline) cooperate to complete the two-stage operation of the addition operation. Likewise, the first-stage multiplier and the second-stage multiplier also perform similar two-stage operations. Of course, the two-stage adder or multiplier here is merely an example and not a limitation, and in some application scenarios, only one-stage adder or multiplier may be provided in a multi-stage pipeline.

In some embodiments, two or more pipelines as described above may also be provided, wherein each pipeline may include several same or different operators to achieve the same or different functions. Further, different pipelines may include different arithmetic units, so that each pipeline implements arithmetic operations of different functions. The operators or circuits that realize the aforementioned different functions may include, but are not limited to, random number processing circuits, addition and subtraction circuits, subtraction circuits, table look-up circuits, parameter configuration circuits, multipliers, dividers, poolers, comparators, and absolute values. circuit, logic operator, position index circuit or filter. Here, a pooler is taken as an example, which can be exemplarily constituted by operators such as an adder, a divider, a comparator, etc., so as to perform the pooling operation in the neural network.

In some application scenarios, multi-stage pipeline operations in the main processing circuit can support unary operations (ie, a situation where there is only one item of input data). Taking the operation operation at the scale layer + relu layer in the neural network as an example, it is assumed that the calculation instruction to be executed is expressed as result=relu(a*ina+b), where ina is the input data (for example, it can be a vector, matrix or sheet amount), a and b are both arithmetic constants. For the calculation instruction, a set of three-stage pipeline operation circuits including a multiplier, an adder, and a nonlinear operator of the present disclosure can be applied to perform the operation. Specifically, the multiplier of the first-stage pipeline can be used to calculate the product of the input data ina and a to obtain the first-stage pipeline operation result. Next, the adder of the second-stage pipeline can be used to perform an addition operation on the first-stage pipeline operation result (a*ina) and b to obtain the second-stage pipeline operation result. Finally, the relu activation function of the third-stage pipeline can be used to activate the second-stage pipeline operation result (a*ina+b) to obtain the final operation result result.

In some application scenarios, the multi-stage pipeline operation circuit in the main processing circuit can support binary operations (such as convolution calculation instruction result=conv(ina, inb)) or ternary operation (such as convolution calculation instruction result=conv( ina, inb, bias)), where the input data ina, inb, and bias can be either one-dimensional tensors (ie, vectors, which can be integer, fixed-point, or floating-point data, for example), or two-dimensional tensors (i.e. a matrix), or a tensor with 3 or more dimensions. Taking the convolution calculation instruction result=conv(ina, inb) as an example here, multiple multipliers, at least one addition tree and at least one nonlinear operator included in the three-stage pipeline operation circuit structure can be used to execute the calculation instruction. Expressed convolution operation, where the two input data ina and inb can be, for example, neuron data. Specifically, firstly, the first-stage pipeline multiplier in the three-stage pipeline operation circuit can be used for calculation, so that the first-stage pipeline operation result product=ina*inb can be obtained (as a microinstruction in the operation instruction, which corresponds to for multiplication). Then, an addition operation may be performed on the first-stage pipeline operation result "product" by using the addition tree in the second-stage pipeline operation circuit to obtain the second-stage pipeline operation result sum. Finally, use the nonlinear operator of the third-stage pipeline operation circuit to perform an activation operation on "sum" to obtain the final convolution operation result.

In some application scenarios, a bypass operation can be performed on a one-stage or multi-stage pipeline operation circuit that will not be used in the operation operation, that is, one or more stages of the multi-stage pipeline operation circuit can be selectively used according to the needs of the operation operation. , without having to make the operation go through all the multi-stage pipeline operations. Taking the operation of calculating Euclidean distance as an example, assuming that the calculation instruction is expressed as dis=sum((ina-inb)^2), you can only use several stages of pipeline operations consisting of adders, multipliers, addition trees and accumulators The circuit is used to perform operations to obtain the final operation result, and the pipeline operation circuit that is not used can be bypassed before or during the operation of the pipeline operation.

In the aforementioned pipeline operations, each group of pipeline operation circuits can independently perform the pipeline operations. However, each of the plurality of groups of pipelined circuits may also perform the pipelining operations cooperatively. For example, the output of the first stage and the second stage in the first group of pipeline operation circuits after performing serial pipeline operation can be used as the input of the third stage of pipeline operation of another group of pipeline operation circuits. For another example, the first stage and the second stage in the first group of pipeline operation circuits perform parallel pipeline operations, and respectively output the results of their pipeline operations as the first and/or second stage pipelines of another group of pipeline operation circuits. Operation input.

4a, 4b and 4c are schematic diagrams illustrating matrix conversion performed by a data conversion circuit according to an embodiment of the present disclosure. In order to better understand the conversion operation performed by the data conversion circuit 3021 in the main processing circuit, the following will take the transpose operation and the horizontal mirror operation performed by the original matrix (which can be regarded as a 2-dimensional tensor in the present disclosure) as an example for further details. describe.

As shown in Figure 4a, the original matrix is a matrix of (M+1) rows by (N+1) columns. According to the requirements of the application scenario, the data conversion circuit can perform a transposition operation on the original matrix shown in FIG. 4a to obtain the matrix shown in FIG. 4b. Specifically, the data conversion circuit can exchange the row numbers and column numbers of elements in the original matrix to form a transposed matrix. Specifically, the coordinate in the original matrix shown in Fig. 4a is the element "10" in the 1st row and 0th column, and its coordinate in the transposed matrix shown in Fig. 4b is the 0th row and the 1st column. By analogy, in the original matrix shown in Figure 4a, the coordinate is the element "M0" in the M+1th row and the 0th column, and its coordinate in the transposed matrix shown in Figure 4b is the 0th row M+ 1 column.

As shown in FIG. 4c, the data conversion circuit may perform a horizontal mirror operation on the original matrix shown in FIG. 4a to form a horizontal mirror matrix. Specifically, the data conversion circuit can convert the arrangement order from the first row element to the last row element in the original matrix into the arrangement order from the last row element to the first row element through the horizontal mirror operation, and the elements in the original matrix The column numbers remain the same. Specifically, the coordinates in the original matrix shown in Figure 4a are the element "00" in the 0th row and the 0th column and the element "10" in the 1st row and the 0th column, respectively. In the horizontal mirror matrix shown in Figure 4c The coordinates are the M+1 row, column 0, and the M row, column 0, respectively. By analogy, in the original matrix shown in Fig. 4a, the coordinate is the element "M0" in the M+1th row and 0th column, and in the horizontal mirror matrix shown in Fig. 4c, the coordinate is the 0th row and 0th column.

5 is a block diagram illustrating a slave processing circuit 500 of a computing device according to an embodiment of the present disclosure. It can be understood that the structures shown in the figures are only exemplary and not limiting, and those skilled in the art can also think of adding more arithmetic units to form more stages of pipeline arithmetic circuits based on the teachings of the present disclosure.

As shown in FIG. 5 , the slave processing circuit 500 includes a four-stage pipeline operation circuit composed of a multiplier 502 , a comparator 504 , a selector 506 , an accumulator 508 and a converter 510 . In one application scenario, the slave processing circuit as a whole may perform vector (including eg matrix) operations.

When performing the vector operation, the slave processing circuit 500 controls the vector data including weight data and neuron data according to the received microinstructions (control signals as shown in the figure) (which can be regarded as 1-dimensional under the present disclosure). tensor) into the multiplier. After performing the multiplication operation, the multiplier inputs the result to the selector 506 . Here, selector 506 chooses to pass the result of the multiplier, rather than the result from the comparator, to accumulator 508, performing the accumulation operation in the vector operation. Next, the accumulator transmits the accumulated result to the converter 510 to perform the data conversion operation described above. Finally, the accumulated sum (ie "ACC_SUM" as shown in the figure) is output as the final result by the converter.

In addition to performing the above-mentioned matrix multiply-add ("MAC") operation between neuron data and weight data, the four-stage pipeline operation circuit shown in FIG. 5 can also be used to perform histogram operations, depthwise operations in neural network operations Operations such as layer multiplication and addition, integration and winograd multiplication and addition. When the histogram operation is performed, in the first stage of operation, input data is input to the comparator from the processing circuit according to the microinstruction. Accordingly, here selector 506 chooses to pass the result of the comparator, rather than the result of the multiplier, to the accumulator for subsequent operations.

From the above description, those skilled in the art can understand that in terms of hardware arrangement, the slave processing circuit of the present disclosure may include a plurality of operation circuits for performing slave operation operations, and the plurality of operation circuits are connected and configured to perform Multi-stage pipeline operation. In one or more embodiments, the aforementioned arithmetic circuits may include, but are not limited to, one or more of multiplying circuits, comparing circuits, accumulating circuits, and turning circuits to perform at least vector operations, such as multi-dimensional volumes in neural networks Product operation.

In an operation scenario, the slave processing circuit of the present disclosure may perform operations on the data pre-processing operations performed by the master processing circuit according to slave instructions (implemented as, for example, one or more microinstructions or control signals) to obtain expected operation results . In another operation scenario, the slave processing circuit may send the intermediate result obtained after its operation (eg, via an interconnect interface) to the data processing unit in the master processing circuit, so that the data conversion circuit in the data processing unit can convert the intermediate result to the data processing unit. The result performs data type conversion or data splitting and splicing operations on the intermediate result by the data splicing circuit in the data processing unit, thereby obtaining the final operation result. The operation of the master and slave processing circuits of the present disclosure will be described below in conjunction with several exemplary instructions.

Taking the calculation instruction "COSHLC" including preprocessing operations as an example, the operations performed by it (including the preprocessing operations performed by the master processing circuit and the slave operation operations performed by the slave processing circuits) can be expressed as:

COSHLC=FPTOFIX+SHUFFLE+LT3DCONV,

Among them, FPTOFIX represents the data type conversion operation performed by the data conversion circuit in the main processing circuit, that is, the input data is converted from a floating-point number to a fixed-point number, SHUFFLE represents the data splicing operation performed by the data splicing circuit, and LT3DCONV represents the slave processing circuit ( 3DCONV operation performed by "LT" designation), that is, a convolution operation of 3-dimensional data. It can be understood that when only the convolution operation of 3-dimensional data is performed, both FPTOFIX and SHUFFLE, which are part of the main operation, can be set as optional operations.

Taking the calculation instruction LCSU including post-processing operations as an example, the operations performed by it (including the slave operation operations performed by the slave processing circuit and the post-processing operations performed by the main processing circuit) can be expressed as:

LCSU=LT3DCONV+SUB,

Wherein, after the slave processing circuit performs the LT3DCONV operation to obtain the 3D convolution result, the subtractor in the main processing circuit can perform the subtraction operation SUB on the 3D convolution result. Thus, in the execution cycle of each instruction, one binary operand (that is, the convolution result and the subtrahend) can be input, and one unary operand (that is, the final result obtained after executing the LCSU instruction) can be output.

Taking the calculation instruction SHLCAD including the preprocessing operation, the slave operation operation and the postprocessing operation as an example, the operations performed by it (including the preprocessing operation performed by the main processing circuit, the slave operation operation performed by the slave processing circuit and the operation performed by the main processing circuit) post-processing operations) can be expressed as:

SHLCAD=SHUFFLE+LT3DCONV+ADD

Wherein, in the preprocessing operation, the data splicing circuit performs the data splicing operation represented by SHUFFLE. Next, the LT3DCONV operation is performed on the concatenated data by the slave processing circuit to obtain a convolution result in 3D. Finally, the addition operation ADD is performed on the 3D convolution result by the adder in the main processing circuit to obtain the final calculation result.

Through the above examples, those skilled in the art can understand that after parsing the calculation instructions, the operation instructions obtained by the present disclosure include one of the following combinations according to specific operation operations: preprocessing instructions and slave processing instructions; slave processing instructions and postprocessing instructions; and preprocessing instructions, slave processing instructions, and postprocessing instructions. Based on this, in some embodiments, the preprocessing instruction may include a data conversion instruction and/or a data splicing instruction. In other embodiments, the post-processing instructions include one or more of the following: random number processing instructions, addition instructions, subtraction instructions, table lookup instructions, parameter configuration instructions, multiplication instructions, pooling instructions, and activation instructions , comparison instruction, absolute value instruction, logical operation instruction, position index instruction or filter instruction. In other embodiments, the slave processing instructions may include various types of operation instructions, including but not limited to instructions similar to post-processing instructions and instructions for complex data processing, such as vector operation instructions or tensors Operation instructions.

Based on the above descriptions in conjunction with FIG. 1 (including FIG. 1a and FIG. 1b ) to FIG. 5 , those skilled in the art can understand that the present disclosure also discloses a method for performing computing operations using a computing device, wherein the computing device includes a host computer. A processing circuit and at least one slave processing circuit (ie, the computing device discussed above in connection with FIGS. 1-5 ), the method includes configuring the master processing circuit to perform a master arithmetic operation in response to a master instruction, and The slave processing circuit is configured to perform slave arithmetic operations in response to the slave instruction. In one embodiment, the aforementioned main operation includes a pre-processing operation and/or a post-processing operation for the slave operation, and the main instruction and the slave instruction are obtained by parsing according to the calculation instruction received by the computing device . In another embodiment, the operand of the calculation instruction includes a descriptor for indicating the shape of the tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand.

Based on the above descriptor settings, the method may further include configuring the master processing circuit and/or the slave processing circuit to perform respective corresponding master arithmetic operations and/or slave processing operations according to the storage address. As mentioned above, through the descriptor setting of the present disclosure, the efficiency of tensor operation and the speed of data access can be improved, and the overhead of tensor operation can be further reduced. In addition, although other steps of the method are not described here for the purpose of brevity, those skilled in the art can understand from the content disclosed in the present disclosure that the method of the present disclosure can perform various operations described above in conjunction with FIGS. 1-5 . .

FIG. 6 is a structural diagram illustrating a combined processing apparatus 600 according to an embodiment of the present disclosure. As shown in FIG. 6 , the combined processing device 600 includes a computing processing device 602 , an interface device 604 , other processing devices 606 and a storage device 608 . According to different application scenarios, one or more computing devices 610 may be included in the computing processing device, and the computing devices may be configured to perform the operations described herein in conjunction with FIG. 1 to FIG. 5 .

In various embodiments, the computing processing devices of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within a computing processing device may be implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a part of the hardware structure of an artificial intelligence processor core, for the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure.

In an exemplary operation, the computing processing apparatus of the present disclosure may interact with other processing apparatuses through an interface apparatus to jointly complete an operation specified by a user. According to different implementations, other processing devices of the present disclosure may include central processing units (Central Processing Unit, CPU), graphics processing units (Graphics Processing Unit, GPU), artificial intelligence processors and other general-purpose and/or special-purpose processors. One or more types of processors. These processors may include, but are not limited to, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable Logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and the number thereof can be determined according to actual needs. As mentioned above, only for the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when computing processing devices and other processing devices are considered together, the two can be viewed as forming a heterogeneous multi-core structure.

In one or more embodiments, the other processing device may serve as an interface for the computing processing device of the present disclosure (which may be embodied as a related computing device for artificial intelligence such as neural network operations) with external data and control, performing operations including but not limited to Limited to basic controls such as data movement, starting and/or stopping computing devices. In other embodiments, other processing apparatuses may also cooperate with the computing processing apparatus to jointly complete computing tasks.

In one or more embodiments, the interface device may be used to transfer data and control instructions between the computing processing device and other processing devices. For example, the computing and processing device may obtain input data from other processing devices via the interface device, and write the input data into the on-chip storage device (or memory) of the computing and processing device. Further, the computing and processing device may obtain control instructions from other processing devices via the interface device, and write them into the control cache on the computing and processing device chip. Alternatively or alternatively, the interface device can also read the data in the storage device of the computing processing device and transmit it to other processing devices.

Additionally or alternatively, the combined processing device of the present disclosure may also include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, a storage device may be used to store data of the computing processing device and/or the other processing device. For example, the data may be data that cannot be fully stored in an internal or on-chip storage device of a computing processing device or other processing device.

In some embodiments, the present disclosure also discloses a chip (eg, chip 702 shown in FIG. 7). In one implementation, the chip is a System on Chip (SoC) and integrates one or more combined processing devices as shown in FIG. 6 . The chip can be connected with other related components through an external interface device (such as the external interface device 706 shown in FIG. 7 ). The relevant component may be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as video codecs) and/or interface modules (such as DRAM interfaces) may be integrated on the chip. In some embodiments, the present disclosure also discloses a chip package structure including the above-mentioned chip. In some embodiments, the present disclosure also discloses a board including the above-mentioned chip package structure. The board will be described in detail below with reference to FIG. 7 .

FIG. 7 is a schematic structural diagram illustrating a board 700 according to an embodiment of the present disclosure. As shown in FIG. 7 , the board includes a storage device 704 for storing data, which includes one or more storage units 710 . The storage device can be connected to the control device 708 and the chip 702 described above for connection and data transmission through, for example, a bus. Further, the board also includes an external interface device 706, which is configured for data relay or transfer function between the chip (or a chip in a chip package structure) and an external device 712 (such as a server or a computer, etc.). For example, the data to be processed can be transmitted to the chip by an external device through an external interface device. For another example, the calculation result of the chip may be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device may have different interface forms, for example, it may adopt a standard PCIE interface and the like.

In one or more embodiments, the control device in the board of the present disclosure may be configured to regulate the state of the chip. To this end, in an application scenario, the control device may include a single-chip microcomputer (Micro Controller Unit, MCU) for regulating the working state of the chip.

According to the above description in conjunction with FIG. 6 and FIG. 7 , those skilled in the art can understand that the present disclosure also discloses an electronic device or device, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and/or one or a plurality of the above-mentioned combined processing devices.

According to different application scenarios, the electronic devices or devices of the present disclosure may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC equipment, IoT terminals, mobile Terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and/or medical equipment. The vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lamps, gas stoves, and range hoods; the medical equipment includes nuclear magnetic resonance instruments, B-ultrasound and/or electrocardiograph. The electronic equipment or device of the present disclosure can also be applied to the Internet, Internet of Things, data center, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical care and other fields. Further, the electronic device or device of the present disclosure can also be used in application scenarios related to artificial intelligence, big data and/or cloud computing, such as cloud, edge terminal, and terminal. In one or more embodiments, the electronic device or device with high computing power according to the solution of the present disclosure can be applied to a cloud device (eg, a cloud server), while the electronic device or device with low power consumption can be applied to a terminal device and/or Edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that the hardware resources of the cloud device can be obtained from the hardware information of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device. Matching appropriate hardware resources to simulate the hardware resources of terminal devices and/or edge devices, so as to complete the unified management, scheduling and collaborative work of device-cloud integration or cloud-edge-device integration.

It should be noted that, for the purpose of simplicity, the present disclosure expresses some methods and their embodiments as a series of actions and their combinations, but those skilled in the art can understand that the solutions of the present disclosure are not limited by the order of the described actions . Accordingly, those of ordinary skill in the art, based on the disclosure or teachings of this disclosure, will appreciate that some of the steps may be performed in other orders or concurrently. Further, those skilled in the art can understand that the embodiments described in the present disclosure may be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the realization of one or some solutions of the present disclosure. In addition, according to different solutions, the present disclosure also has different emphases in the description of some embodiments. In view of this, those skilled in the art can understand the parts that are not described in detail in a certain embodiment of the present disclosure, and can also refer to the related descriptions of other embodiments.

In terms of specific implementation, based on the disclosure and teaching of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented in other ways not disclosed herein. For example, as for each unit in the foregoing electronic device or apparatus embodiment, this article divides them on the basis of considering logical functions, and there may also be other division methods in actual implementation. As another example, multiple units or components may be combined or integrated into another system, or some features or functions of a unit or component may be selectively disabled. As far as the connection relationship between different units or components is concerned, the connections discussed above in conjunction with the accompanying drawings may be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In this disclosure, units illustrated as separate components may or may not be physically separate, and components shown as units may or may not be physical units. The aforementioned components or elements may be co-located or distributed over multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solutions described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit physically exists independently.

In some implementation scenarios, the above integrated units may be implemented in the form of software program modules. If implemented in the form of a software program module and sold or used as a stand-alone product, the integrated unit may be stored in a computer-readable memory. Based on this, when the aspects of the present disclosure are embodied in the form of a software product (eg, a computer-readable storage medium), the software product may be stored in a memory, which may include several instructions to cause a computer device (eg, a personal computer, a server or network equipment, etc.) to execute some or all of the steps of the methods described in the embodiments of the present disclosure. The aforementioned memory may include, but is not limited to, a U disk, a flash disk, a read-only memory (Read Only Memory, ROM), a random access memory (Random Access Memory, RAM), a mobile hard disk, a magnetic disk, or a CD, etc. that can store programs. medium of code.

In other implementation scenarios, the above-mentioned integrated units may also be implemented in the form of hardware, that is, specific hardware circuits, which may include digital circuits and/or analog circuits, and the like. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, and the physical devices may include, but are not limited to, devices such as transistors or memristors. In this regard, the various types of devices described herein (eg, computing devices or other processing devices) may be implemented by suitable hardware processors, such as CPUs, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device can be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, a variable resistance memory (Resistive Random Access Memory, RRAM), dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), Static Random Access Memory (Static Random Access Memory, SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High Bandwidth Memory (High Bandwidth Memory) , HBM), hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

The foregoing can be better understood in accordance with the following terms:

Clause 1. A computing device comprising a master processing circuit and at least one slave processing circuit, wherein:

the main processing circuit is configured to perform main arithmetic operations in response to a main instruction,

the slave processing circuit is configured to perform a slave arithmetic operation in response to a slave instruction,

Wherein, the master computing operation includes a pre-processing operation and/or a post-processing operation for the slave computing operation, the master instruction and the slave instruction are parsed and obtained according to the computing instruction received by the computing device, wherein the The operand of the calculation instruction includes a descriptor for indicating the shape of the tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The master processing circuit and/or the slave processing circuit are configured to perform respective corresponding master arithmetic operations and/or slave processing operations according to the storage addresses.

Clause 2. The computing device of clause 1, wherein the computing instruction includes an identification of a descriptor and/or content of the descriptor, the content of the descriptor including at least one shape parameter representing the shape of the tensor data.

Clause 3. The computing device of clause 2, wherein the content of the descriptor further comprises at least one address parameter representing an address of tensor data.

Clause 4. The computing device of Clause 3, wherein the address parameter of the tensor data comprises a base address of a data base point of the descriptor in the data storage space of the tensor data.

Clause 5. The computing device of Clause 4, wherein the shape parameter of the tensor data comprises at least one of the following:

The size of the data storage space in at least one of the N-dimensional directions, the size of the storage area of the tensor data in at least one of the N-dimensional directions, the size of the storage area in at least one of the N-dimensional directions The offset in one direction, the position of at least two vertices at diagonal positions in N dimension directions relative to the data reference point, the data description position of the tensor data indicated by the descriptor and the data address. The mapping relationship between , where N is an integer greater than or equal to zero.

Clause 6. The computing device of clause 1, wherein the main processing circuit is configured to:

obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

The slave instruction is sent to the slave processing circuit.

Clause 7. The computing device according to Clause 1, further comprising a control circuit, the control circuit configured to: obtain the calculation instruction and parse the calculation instruction to obtain the master instruction and the slave instruction; as well as

The master instruction is sent to the master processing circuit and the slave instruction is sent to the slave processing circuit.

Clause 8. The computing device of clause 1, wherein the host instruction includes an identification bit for identifying the preprocessing operation and/or the postprocessing operation.

Clause 9. The computing device of Clause 1, wherein the computing instruction includes a preset bit for distinguishing the preprocessing operation and the postprocessing operation in the main instruction.

Clause 10. The computing device of clause 1, wherein the main processing circuit comprises a data processing unit for performing the main arithmetic operation, and the data processing unit comprises a data conversion circuit for performing a data conversion operation and /or a data splicing circuit for performing data splicing operations.

Clause 11. The computing device of clause 10, wherein the data conversion circuit includes one or more converters for enabling conversion of computational data between a plurality of different data types.

Item 12. The computing device according to Item 10, wherein the data splicing circuit is configured to split the computing data with a predetermined bit length, and splicing a plurality of data blocks obtained after the splitting in a predetermined order.

Clause 13. The computing device of clause 1, wherein the main processing circuit comprises one or more sets of pipelined arithmetic circuits, each set of pipelined arithmetic circuits forming an arithmetic pipeline and comprising one or more operators, wherein when When each group of pipeline arithmetic circuits includes a plurality of arithmetic units, the plurality of arithmetic units are connected and configured to selectively participate in performing the main arithmetic operation according to the main instruction.

Clause 14. The computing device of clause 13, wherein the main processing circuit comprises at least two arithmetic pipelines, and each arithmetic pipeline comprises one or more operators or circuits of:

Random number processing circuit, addition and subtraction circuit, subtraction circuit, look-up table circuit, parameter configuration circuit, multiplier, divider, pooler, comparator, absolute value circuit, logic operator, position index circuit or filter.

Clause 15. The computing device of clause 1, wherein the slave processing circuit includes a plurality of arithmetic circuits for performing the slave arithmetic operations, and the plurality of arithmetic circuits are connected and configured to perform multi-stage pipelined An arithmetic operation, wherein the arithmetic circuit includes one or more of a multiplying circuit, a comparing circuit, an accumulating circuit, and a revolution number circuit to perform at least vector operations.

Clause 16. The computing device of clause 15, wherein the slave instruction comprises a convolution instruction that performs a convolution operation on the computed data subjected to the preprocessing operation, the slave processing circuit configured to:

A convolution operation is performed on the calculated data subjected to the preprocessing operation according to the convolution instruction.

Clause 17. An integrated circuit chip comprising the computing device of any of clauses 1-16.

Clause 18. A board comprising the integrated circuit chip of clause 17.

Clause 19. An electronic device comprising the integrated circuit chip of clause 17.

Clause 20. A method of performing computing operations using a computing device, wherein the computing device includes a master processing circuit and at least one slave processing circuit, the method comprising:

configuring the main processing circuit to perform main arithmetic operations in response to a main instruction,

configuring the slave processing circuit to perform a slave arithmetic operation in response to a slave instruction,

The master operation includes preprocessing and/or postprocessing for the slave operation, and the master instruction and the slave instruction are parsed and obtained according to the calculation instruction received by the computing device, wherein the calculation The operand of the instruction includes a descriptor for indicating the shape of the tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The method further includes configuring the master processing circuit and/or the slave processing circuit to perform respective corresponding master arithmetic operations and/or slave processing operations according to the storage address.

Clause 21. The method of clause 20, wherein the computation instruction includes an identification of a descriptor and/or content of the descriptor, the content of the descriptor including at least one shape parameter representing the shape of the tensor data.

Clause 22. The method of clause 21, wherein the content of the descriptor further comprises at least one address parameter representing an address of tensor data.

Clause 23. The method of clause 22, wherein the address parameter of the tensor data comprises a base address of a data base point of the descriptor in the data storage space of the tensor data.

Clause 24. The method of clause 23, wherein the shape parameter of the tensor data comprises at least one of the following:

Clause 25. The method of clause 20, wherein the main processing circuit is configured to:

The slave instruction is sent to the slave processing circuit.

Clause 26. The method of clause 20, wherein the computing device includes a control circuit, the method further comprising configuring the control circuit to:

Clause 27. The method of clause 20, wherein the host instruction includes an identification bit for identifying the preprocessing operation and/or the postprocessing operation.

Clause 28. The method of clause 20, wherein the computing instruction includes preset bits for distinguishing between the preprocessing operations and the postprocessing operations in the host instruction.

Clause 29. The method of clause 20, wherein the main processing circuit comprises a data processing unit, and the data processing unit comprises a data conversion circuit and/or a data splicing circuit, the method comprising configuring the data processing unit to perform The main arithmetic operation is performed, and the data conversion circuit is configured to perform a data conversion operation, and the data stitching circuit is configured to perform a data stitching operation.

Clause 30. The method of clause 29, wherein the data conversion circuit comprises one or more converters, the method comprising configuring the one or more converters to enable conversion of computational data between a plurality of different data types. convert.

Item 31. The method of Item 29, wherein the data splicing circuit is configured to split the calculated data with a predetermined bit length, and splicing the plurality of data blocks obtained after the splitting in a predetermined order.

Clause 32. The method of clause 20, wherein the main processing circuit comprises one or more sets of pipelined arithmetic circuits, each set of pipelined arithmetic circuits forming an arithmetic pipeline and comprising one or more operators, wherein when all When each set of pipeline arithmetic circuits includes a plurality of arithmetic units, the method includes connecting the plurality of arithmetic units and configuring to selectively participate in performing the main arithmetic operation according to the host instruction.

Clause 33. The method of clause 32, wherein the main processing circuit comprises at least two arithmetic pipelines, and each arithmetic pipeline comprises one or more operators or circuits of:

Clause 34. The method of clause 20, wherein the slave processing circuit comprises a plurality of arithmetic circuits, the method comprising configuring the plurality of arithmetic circuits to perform the slave arithmetic operations, and the method further comprising The plurality of arithmetic circuits are connected and configured to perform multi-stage pipeline arithmetic operations, wherein the arithmetic circuits include one or more of a multiplying circuit, a comparing circuit, an accumulating circuit, and a revolution number circuit to perform at least vector operations.

Clause 35. The method of clause 34, wherein the slave instruction comprises a convolution instruction that performs a convolution operation on computational data subjected to the preprocessing operation, the method comprising configuring the slave processing circuit to:

While various embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes and substitutions may occur to those skilled in the art without departing from the spirit and spirit of this disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. The appended claims are intended to define the scope of the disclosure, and therefore to cover equivalents and alternatives within the scope of these claims.

Claims

A computing device comprising a master processing circuit and at least one slave processing circuit, wherein:

the main processing circuit is configured to perform main arithmetic operations in response to a main instruction,

the slave processing circuit is configured to perform a slave arithmetic operation in response to a slave instruction,

Wherein, the master computing operation includes a pre-processing operation and/or a post-processing operation for the slave computing operation, the master instruction and the slave instruction are parsed and obtained according to the computing instruction received by the computing device, wherein the The operand of the calculation instruction includes a descriptor for indicating the shape of the tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The master processing circuit and/or the slave processing circuit are configured to perform respective corresponding master arithmetic operations and/or slave processing operations according to the storage addresses.
The computing device of claim 1, wherein the computing instruction includes an identification of a descriptor and/or content of the descriptor, the content of the descriptor including at least one shape parameter representing the shape of the tensor data.
2. The computing device of claim 2, wherein the content of the descriptor further includes at least one address parameter representing an address of tensor data.
The computing device of claim 3, wherein the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data.
The computing device of claim 4, wherein the shape parameter of the tensor data includes at least one of the following:

The size of the data storage space in at least one of the N-dimensional directions, the size of the storage area of the tensor data in at least one of the N-dimensional directions, the size of the storage area in at least one of the N-dimensional directions The offset in one direction, the position of at least two vertices at diagonal positions in N dimension directions relative to the data reference point, the data description position of the tensor data indicated by the descriptor and the data address. The mapping relationship between , where N is an integer greater than or equal to zero.
The computing device of claim 1, wherein the main processing circuit is configured to:

obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

The slave instruction is sent to the slave processing circuit.
The computing device of claim 1, further comprising a control circuit configured to:

obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

The master instruction is sent to the master processing circuit and the slave instruction is sent to the slave processing circuit.
The computing device of claim 1, wherein the host instruction includes an identification bit for identifying the preprocessing operation and/or the postprocessing operation.
The computing device of claim 1, wherein the computing instruction includes a preset bit for distinguishing the pre-processing operation and the post-processing operation in the main instruction.
The computing device of claim 1, wherein the main processing circuit comprises a data processing unit for performing the main arithmetic operation, and the data processing unit comprises a data conversion circuit for performing a data conversion operation and/or A data stitching circuit for performing data stitching operations.
11. The computing device of claim 10, wherein the data conversion circuit includes one or more converters for converting computational data between a plurality of different data types.
The computing device according to claim 10, wherein the data splicing circuit is configured to split the computing data with a predetermined bit length, and splicing a plurality of data blocks obtained after the splitting in a predetermined order.
The computing device of claim 1, wherein the main processing circuit comprises one or more sets of pipelined arithmetic circuits, each set of pipelined arithmetic circuits forming an arithmetic pipeline and comprising one or more operators, wherein when the When each group of pipeline arithmetic circuits includes a plurality of arithmetic units, the plurality of arithmetic units are connected and configured to selectively participate in performing the main arithmetic operation according to the main instruction.
14. The computing device of claim 13, wherein the main processing circuit includes at least two arithmetic pipelines, and each arithmetic pipeline includes one or more operators or circuits of:

Random number processing circuit, addition and subtraction circuit, subtraction circuit, look-up table circuit, parameter configuration circuit, multiplier, divider, pooler, comparator, absolute value circuit, logic operator, position index circuit or filter.
The computing device of claim 1, wherein the slave processing circuit includes a plurality of arithmetic circuits for performing the slave arithmetic operations, and the plurality of arithmetic circuits are connected and configured to perform multi-stage pipelined arithmetic operations , wherein the operation circuit includes one or more of a multiplying circuit, a comparing circuit, an accumulating circuit, and a rotation number circuit to perform at least vector operations.
16. The computing device of claim 15, wherein the slave instruction comprises a convolution instruction that performs a convolution operation on the calculated data subjected to the preprocessing operation, the slave processing circuit being configured to:

A convolution operation is performed on the calculated data subjected to the preprocessing operation according to the convolution instruction.
An integrated circuit chip comprising the computing device according to any one of claims 1-16.
A board, comprising the integrated circuit chip according to claim 17 .
An electronic device comprising the integrated circuit chip of claim 17 .
A method of performing computing operations using a computing device, wherein the computing device includes a master processing circuit and at least one slave processing circuit, the method comprising:

configuring the main processing circuit to perform main arithmetic operations in response to a main instruction,

configuring the slave processing circuit to perform a slave arithmetic operation in response to a slave instruction,

The master operation includes preprocessing and/or postprocessing for the slave operation, and the master instruction and the slave instruction are parsed and obtained according to the calculation instruction received by the computing device, wherein the calculation The operand of the instruction includes a descriptor for indicating the shape of the tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The method further includes configuring the master processing circuit and/or the slave processing circuit to perform respective corresponding master arithmetic operations and/or slave processing operations according to the storage address.
21. The method of claim 20, wherein the computation instruction includes an identification of a descriptor and/or the content of the descriptor including at least one shape parameter representing the shape of the tensor data.
21. The method of claim 21, wherein the content of the descriptor further includes at least one address parameter representing an address of tensor data.
23. The method of claim 22, wherein the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in the data storage space of the tensor data.
The method of claim 23, wherein the shape parameter of the tensor data comprises at least one of the following:

The size of the data storage space in at least one of the N-dimensional directions, the size of the storage area of the tensor data in at least one of the N-dimensional directions, the size of the storage area in at least one of the N-dimensional directions The offset in one direction, the position of at least two vertices at diagonal positions in N dimension directions relative to the data reference point, the data description position of the tensor data indicated by the descriptor and the data address. The mapping relationship between , where N is an integer greater than or equal to zero.
21. The method of claim 20, wherein the main processing circuit is configured to:

obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

The slave instruction is sent to the slave processing circuit.
21. The method of claim 20, wherein the computing device includes a control circuit, the method further comprising configuring the control circuit to:

obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

The master instruction is sent to the master processing circuit and the slave instruction is sent to the slave processing circuit.
21. The method of claim 20, wherein the main instruction includes an identification bit for identifying the pre-processing operation and/or the post-processing operation.
21. The method of claim 20, wherein the computing instructions include preset bits for distinguishing between the preprocessing operations and the postprocessing operations in the main instruction.
21. The method of claim 20, wherein the main processing circuit comprises a data processing unit and the data processing unit comprises a data conversion circuit and/or a data splicing circuit, the method comprising configuring the data processing unit to perform the A main arithmetic operation is performed, and the data conversion circuit is configured to perform a data conversion operation, and the data stitching circuit is configured to perform a data stitching operation.
30. The method of claim 29, wherein the data conversion circuit comprises one or more converters, the method comprising configuring the one or more converters to effect conversion of computational data between a plurality of different data types.
29. The method according to claim 29, wherein the data splicing circuit is configured to split the calculated data with a predetermined bit length, and splicing a plurality of data blocks obtained after the splitting in a predetermined order.
21. The method of claim 20, wherein the main processing circuit includes one or more sets of pipelined arithmetic circuits, each set of pipelined arithmetic circuits forming an arithmetic pipeline and comprising one or more operators, wherein when each of the pipelined arithmetic circuits is formed When the group pipelined arithmetic circuit includes a plurality of arithmetic units, the method includes connecting the plurality of arithmetic units and configuring to selectively participate in performing the primary arithmetic operation according to the host instruction.
33. The method of claim 32, wherein the main processing circuit includes at least two arithmetic pipelines, and each arithmetic pipeline includes one or more operators or circuits of:

Random number processing circuit, addition and subtraction circuit, subtraction circuit, look-up table circuit, parameter configuration circuit, multiplier, divider, pooler, comparator, absolute value circuit, logic operator, position index circuit or filter.
21. The method of claim 20, wherein the slave processing circuit comprises a plurality of arithmetic circuits, the method comprising configuring the plurality of arithmetic circuits to perform the slave arithmetic operations, and the method further comprising A plurality of arithmetic circuits are connected and configured to perform multi-stage pipeline arithmetic operations, wherein the arithmetic circuits include one or more of a multiplying circuit, a comparing circuit, an accumulating circuit, and a revolution number circuit to perform at least vector operations.
35. The method of claim 34, wherein the slave instruction comprises a convolution instruction that performs a convolution operation on computational data subjected to the preprocessing operation, the method comprising configuring the slave processing circuit to:

A convolution operation is performed on the calculated data subjected to the preprocessing operation according to the convolution instruction.