WO2021081955A1 - 一种振荡器电路 - Google Patents

一种振荡器电路 Download PDF

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Publication number
WO2021081955A1
WO2021081955A1 PCT/CN2019/114883 CN2019114883W WO2021081955A1 WO 2021081955 A1 WO2021081955 A1 WO 2021081955A1 CN 2019114883 W CN2019114883 W CN 2019114883W WO 2021081955 A1 WO2021081955 A1 WO 2021081955A1
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WO
WIPO (PCT)
Prior art keywords
terminal
coupled
inductance
inductor
transconductance amplifier
Prior art date
Application number
PCT/CN2019/114883
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English (en)
French (fr)
Inventor
周云芳
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980101598.4A priority Critical patent/CN114586279A/zh
Priority to EP19950453.1A priority patent/EP4044426A4/en
Priority to PCT/CN2019/114883 priority patent/WO2021081955A1/zh
Publication of WO2021081955A1 publication Critical patent/WO2021081955A1/zh
Priority to US17/733,158 priority patent/US11757405B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
    • H03B5/1243—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising voltage variable capacitance diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1296—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the feedback circuit comprising a transformer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/323—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator the resonator having more than two terminals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
    • H03B2201/02—Varying the frequency of the oscillations by electronic means

Definitions

  • This application relates to the field of electronic technology, and in particular to an oscillator circuit.
  • VCO voltage controlled oscillator
  • RF radio frequency
  • ASIC application specific integrated circuit
  • the noise performance of an LC resonant VCO is directly related to its signal power, and its signal power is directly proportional to the energy stored in the resonant inductor-capacitor (LC) tank circuit.
  • the energy stored in the LC circuit is proportional to the size of the inductor and the square of the power supply voltage of the amplifier in the VCO.
  • the power supply voltage of amplifiers also needs to be reduced.
  • the size of the inductor used in the LC tank circuit must also be reduced, so that the noise performance generated by the VCO remains unchanged.
  • Increasing the required frequency also requires reducing the size of the inductor.
  • reducing the size of the inductor is extremely challenging, because as the size of the inductor continues to decrease, the quality factor (Q) of the inductor will also decrease, thereby further increasing the thermal noise of the VCO.
  • the present application provides an oscillator circuit for improving the performance of the oscillator.
  • this application adopts the following technical solutions:
  • an oscillator circuit including: an amplifier including a first transconductance amplifier and a second transconductance amplifier; a resonator including a capacitive element and an inductance element, the capacitive element including a first capacitor and a second capacitor, and an inductance
  • the component includes a tapped inductor, the tapped inductor includes a first section of inductance and a second section of inductance, the first section of inductance and the second section of inductance are coupled by a first capacitor; the first section of inductance includes a first terminal and a second terminal;
  • the second section of inductance includes a third terminal and a fourth terminal; the first terminal and the second terminal are respectively coupled to the input terminal and the output terminal of the first transconductance amplifier; the third terminal and the fourth terminal are respectively coupled to the input of the second transconductance amplifier Terminal and output terminal; the first terminal and the fourth terminal are coupled through a second capacitor.
  • the first transconductance amplifier and the first section of the inductor can be used as a single-ended three-point oscillation oscillator
  • the second transconductance amplifier and the second section of the inductor can be used as another single-ended three-point oscillation oscillator.
  • the two single-ended three-point oscillation oscillators are coupled together through the first capacitor and the second capacitor, so that the phase noise of the oscillator circuit can be reduced, thereby improving the performance of the oscillator circuit.
  • the tapped inductor includes a plurality of conductive segments, and the plurality of conductive segments form a figure-eight physical loop by means of layer jumps and crossings.
  • the tapped inductor is composed of two half-circle loops with opposite magnetic field directions. When the two opposite magnetic fields are interfered by the magnetic field, the induced currents generated will cancel out, so it has a good The anti-jamming performance.
  • a plurality of conductive segments are respectively wired on the top metal layer and the sub-top metal layer, or the top metal layer and the redistribution layer.
  • the plurality of conductive segments included in the figure-eight physical loop 401 are divided into a non-intersecting part and two intersecting parts during routing. One of the non-intersecting part and the two intersecting parts can be routed to the top metal, and the other The crossing part can be wired on the next top metal layer or the redistribution layer.
  • the first terminal and the fourth terminal are two output ends of the tapped inductor, and the second terminal and the third terminal are two tapped ends of the tapped inductor.
  • the changes in the positions of the second terminal and the third terminal can be used to adjust the power consumption, output amplitude, and phase noise of the oscillator circuit, thereby improving the performance of the oscillator circuit.
  • two tap segments corresponding to the second terminal and the third terminal are wired in the middle of the tapped inductor.
  • the parts of the two tap segments that do not overlap with the physical loop can be routed to the top metal layer, and the overlapped part can be routed to the next metal of the next top metal layer Layer:
  • the parts of the two tap segments that do not overlap with the physical loop can be routed to the top metal layer, and the overlapping part can be routed to the next top metal layer.
  • the input voltage of the amplifier exceeds the power supply voltage of the amplifier.
  • the gain of the oscillator circuit can be increased, and the power requirement on the oscillator circuit can be reduced at the same time.
  • both the first transconductance amplifier and the second transconductance amplifier include: an NMOS tube and a PMOS tube; wherein the source of the NMOS tube is coupled to the positive power rail, and the NMOS tube and the PMOS tube The gate of the tube is coupled as the input terminal, the drain of the NMOS tube and the PMOS tube are coupled as the output terminal, and the source of the PMOS tube is coupled to the ground terminal.
  • the first transconductance amplifier and the second transconductance amplifier form negative resistance through cross positive feedback, which can offset the loss of the tank formed by the resonator, thereby improving the performance of the oscillator circuit; in addition, the first transconductance amplifier
  • the input impedance and output impedance of the amplifier and the second transconductance amplifier are different. By adjusting the ratio of the input impedance to the output impedance, the oscillator circuit can be operated in a linear region, so that the oscillator circuit has better phase noise.
  • a non-transitory computer-readable medium for use with a computer.
  • the computer has software for creating integrated circuits, and the computer-readable medium stores one or more computer-readable data structures, one or A plurality of computer-readable data structures have photomask data for manufacturing an oscillator circuit, the oscillator circuit includes: an amplifier, including a first transconductance amplifier and a second transconductance amplifier; a resonator, including a capacitive element and an inductive element,
  • the capacitive element includes a first capacitor and a second capacitor
  • the inductance element includes a tapped inductor, the tapped inductor includes a first section of inductance and a second section of inductance, the first section of inductance and the second section of inductance are coupled through the first capacitor;
  • One section of the inductance includes a first terminal and a second terminal; the second section of inductance includes a third terminal and a fourth terminal; the first terminal and the second terminal are respectively coupled to the input terminal and the output
  • the tapped inductor includes a plurality of conductive segments, and the plurality of conductive segments form a figure-eight physical loop by means of layer jumps and crossings.
  • a plurality of conductive segments are respectively wired on the top metal layer and the sub-top metal layer, or the top metal layer and the redistribution layer.
  • the first terminal and the fourth terminal are two output ends of the tapped inductor, and the second terminal and the third terminal are two tapped ends of the tapped inductor.
  • two tap segments corresponding to the second terminal and the third terminal are wired in the middle of the tapped inductor.
  • the input voltage of the amplifier exceeds the power supply voltage of the amplifier.
  • both the first transconductance amplifier and the second transconductance amplifier include: an NMOS tube and a PMOS tube; wherein the source of the NMOS tube is coupled to the positive power rail, and the NMOS tube and the PMOS tube The gate of the tube is coupled as the input terminal, the drain of the NMOS tube and the PMOS tube are coupled as the output terminal, and the source of the PMOS tube is coupled to the ground terminal.
  • any non-transitory computer-readable medium for use with a computer provided above includes the oscillator circuit provided above. Therefore, the beneficial effects that can be achieved can refer to the above provided The beneficial effects in the oscillator circuit will not be repeated here.
  • FIG. 1 is a schematic diagram of a differential LC energy storage circuit provided by an embodiment of the application
  • FIG. 2 is an example layout of a first differential tapped inductor provided by an embodiment of the application
  • Fig. 3 is a first differential tapped LC energy storage circuit provided by an embodiment of the application.
  • Fig. 5 is a second differential tapped LC tank circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a first differential VCO provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a second differential VCO provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a third differential VCO provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of a fourth differential VCO provided by an embodiment of the application.
  • FIG. 10 is a design flowchart of an ASIC provided by an embodiment of the application.
  • FIG. 11 is an illustrative example of a computing device provided by an embodiment of the application.
  • circuits/components used with the term “for” include hardware, such as circuits that perform operations, and the like. The statement that the circuit/component is "used" to perform one or more tasks clearly indicates that 35U.S.C.112(f) will not be called.
  • references to "one embodiment,” “an embodiment,” “a specific embodiment,” or “a specific embodiment” mean that a specific feature, structure, or characteristic described in combination with a specific embodiment is included in at least one implementation. In the example, it is not necessarily included in all specific embodiments. Therefore, each occurrence of the phrase “in a specific embodiment”, “in an embodiment” or “in a specific embodiment” in different places in this specification does not necessarily refer to the same embodiment.
  • the specific features, structures, or characteristics of any specific embodiment can be combined with one or more other specific embodiments in any suitable manner. It should be understood that, based on the teachings herein, other changes and modifications of the specific embodiments described and illustrated herein are possible, and will be regarded as part of the spirit and scope of the present application.
  • FIG. 1 shows a schematic diagram of an LC tank circuit 100 including parasitic resistances R c and R l for use in a differential voltage controlled oscillator (VCO).
  • the LC tank circuit 100 may also be referred to as LC Resonant circuit, LC resonator or resonator, etc.
  • the VCO amplifier provides current to the input impedance of the LC tank circuit 100, and the voltage generated by the LC tank circuit 100 through the LC circuit is equal to the voltage at the input terminal of the amplifier.
  • the amplifier drives impedance Z 2 ( ⁇ o ), and the voltage at the input of the amplifier is expressed as a voltage through Z 2 ( ⁇ o ).
  • a single inductor is tapped according to the coefficient K (for example, divided into at least two parts).
  • the amplifier drives the inductor tap defined by impedance Z 1 ( ⁇ o ), and the voltage at the input of the amplifier comes from a signal passing through the inductor tap defined by impedance Z 2 ( ⁇ o ).
  • the inductor sections KL and (1-K)/2*L can be regarded as separate inductors due to their small inductance and very high frequency. However, due to physical size requirements and mutual coupling, a separate inductor is impractical.
  • the input and output of the amplifier are located at different points of the LC tank circuit 100 (ie Z 2 and Z 1 ), the input voltage of the amplifier in the VCO can be much larger than that determined by the voltage divider measurement of the tapped inductor The output voltage of the amplifier. This arrangement has many advantages.
  • the amplifier's HCI voltage limit is limited to the output. This allows the input signal to exceed the amplifier's power supply voltage limit. Since the input voltage represents the energy stored in the LC tank circuit 100, when the total inductance is the same, the VCO noise is lower than that of a VCO with a traditional resonator. This is because the LC tank circuit 100 has a higher voltage . In addition, the inductor does not have to be reduced in size to meet the noise requirements, resulting in a higher inductor Q when integrated into an integrated circuit (for example, as part of an ASIC).
  • the output current of the amplifier is the product of the input voltage through Z 2 and its transconductance g m. As the input voltage increases, the amplifier has more gain with the same current. This reduces the power requirements on the system.
  • the impedance at Z 1 ( ⁇ o ) in the LC tank circuit 100 is lower than the impedance at Z 2 ( ⁇ o ) by a factor K 2 .
  • the linearity of the amplifier is determined by the linearity of its output rather than the linearity of its input.
  • the low impedance at the output of the VCO reduces the non-linear mixing of flicker noise and the VCO frequency, thereby improving the spectral utilization of the sideband noise near it.
  • the flicker noise at the baseband frequency is a kind of electronic noise with a 1/ ⁇ density spectrum but mixed through a nonlinear element, which generates the 1/ ⁇ 3 part of the VCO single-sideband phase noise.
  • ⁇ o is the oscillation frequency (radians/second);
  • L is the inductance
  • C is the capacitance
  • R l is the parasitic resistance of the inductor
  • R c is the parasitic resistance of the capacitor
  • K is a constant related to Z 1 and Z 2;
  • X o is the reactance of the inductor L when the resonance frequency is ⁇ o.
  • FIG. 2 there is shown an example layout of a differential tapped inductor 200 used in an LC tank circuit (such as the LC tank circuit shown in FIG. 1) and integrated on an integrated circuit according to the principles of the present application.
  • Fig. 3 shows an ideal schematic diagram of a differential tapped LC tank circuit 302, including a representation of the equivalent inductance 200' of the tapped inductor 200 coupled in parallel with the capacitor C in Fig. 2.
  • the segments V1-V5a, V2-V5a, V3-V5b, V4-V5b, and V5a-V5b in FIG. 2 correspond to inductors L1, L2, L3, L4, and L5 in the schematic diagram of FIG. 3, respectively.
  • the differential tapped inductor 200 includes one or more conductive segments (for example, V1-V5a, V4-V5b, and V5a-V5b) constituting a physical loop 201.
  • the term "physical loop” refers to a closed or nearly closed geometric shape that has a start point and an end point co-located or immediately adjacent to each other and includes at least one distinct convex portion, wherein the convex portion defines the inside of the convex portion
  • the internal space e.g. ring-shaped polygon or ring-shaped polygon segment. Therefore, a physical loop is different from an "electrical loop", which usually represents a closed path of any shape through which current may flow.
  • the physical loop 201 is preferably symmetrical and, when in the inductor 200, is shown as a substantially octagonal shape. Without departing from the scope of the present application, those skilled in the art will recognize that the physical loop 201 may include other symmetrical and asymmetrical shapes (such as rectangles, squares, hexagons, etc.).
  • Inductor 200 is tapped with segments V2-V5a and V3-V5b at V5a and V5b through electrical connection devices to form electrical loops (L2 and L3). These electrical loops are arranged in the physical loop 21 (including L1, L5). And L4) in the internal space.
  • the capacitive element C of the tapped LC tank circuit 302 can be embodied as a PMOS varactor diode, an NMOS varactor diode, a metal-insulator-metal (MIM) device or any other suitable capacitive element.
  • MIM metal-insulator-metal
  • two types of varactor diodes can be used, namely reverse-biased pn junction diodes or MOS capacitor varactor diodes.
  • the MOS capacitor varactor diode can be composed of a MOS tube whose drain, source, and body connector are coupled together, and the capacitance is adjusted based on the voltage applied between the body and the gate connector.
  • the quality factor (Q) of the tapped LC tank circuit 302 depends on the inductor 200 with low resistance.
  • a thick/wide metallization process such as but not limited to aluminum, copper, gold or other suitable materials, is used to reduce the series resistance, thereby minimizing the resistance of the inductor 200.
  • the inductor 200 is preferably made of a high-dielectric substrate material such as silicon, gallium arsenide or other suitable materials. Surface micromachining technology can be used to create an air gap between the inductor and the substrate to further improve the dielectric properties.
  • the inductor tap sections V2-V5a and V3-V5b (L2 and L3) are coupled to the amplifier output and do not belong to the LC tank circuit. Therefore, their parasitic resistance is not as important as the parasitic resistance of the inductor segments L1, L4, and L5. Therefore, the sections L2 and L3 can be constructed using thinner metal materials as shown in FIG. 2.
  • the actual problem involved when using multiple inductors is the mutual inductance in any connection from the amplifier output to the tap points V5a and V5b.
  • the inductor current in the LC tank circuit is usually much higher than the current provided by the circuit factor Q from the amplifier.
  • the mutual inductance is high, the induced current from the LC tank circuit becomes high enough in the lead from the amplifier output to the tap point, so that the input impedance to the tap becomes high so that the amplifier cannot provide any current.
  • the tap segments V2-V5a (L2) and V3-V5b (L3) are guided upward in the middle of the inductor 200 (as shown in Figure 2), so that the induced currents from the two symmetrical halves of the inductor 200 cancel out .
  • the tap positions V5a and V5b can be adjusted on the metal to change the power consumption, VCO output swing and phase noise performance. This can be used to fine-tune the metal design, as shown in V5a' and V5b'.
  • the substrate may be doped with additives to have a high resistivity, and/or the distance between the metal layer and the substrate may be increased by etching or micromachining.
  • the embodiment of the present application also shows another example layout of a differential tapped inductor 400 integrated on an integrated circuit.
  • the tapped inductor 400 is divided into two sections of inductance (ie, the first section of inductance and the second section of inductance), and the two sections of inductance are coupled through the first capacitor C1.
  • Each inductance in the first and second inductances can be a single three-terminal tapped inductor, that is, an inductor with two output terminals and one tapped end.
  • each inductance can be one with two The output end and a winding coil at the tap end.
  • the first section of inductance may include V1-V5a, V5a-V5c, and V5a-V2.
  • V1 and V5c may be the two output terminals of the first section of inductance, and V2 may be the tap end of the first section of inductance;
  • the second-stage inductance may include V4-V5b, V5b-V5d, and V5b-V3.
  • V4 and V5d may be the two output terminals of the second-stage inductance, and V2 may be the tap end of the second-stage inductance.
  • FIG. 5 shows an ideal schematic diagram of the differential tapped LC tank circuit 502 corresponding to FIG. 4, including a representation of the equivalent inductance 400' of the tapped inductor 400 coupled in parallel with the second capacitor C2 in FIG.
  • the segments V1-V5a in FIG. 4 correspond to the inductors L1 in the schematic diagram of FIG. 5
  • V2-V5a correspond to the inductors L2 in the schematic diagram of FIG. 5
  • V3-V5b correspond to the inductors in the schematic diagram of FIG. L3
  • V4-V5b correspond to inductor L4 in the schematic diagram of FIG.
  • V5a-V5c correspond to L5a in the schematic diagram of FIG. 5
  • V5b-V5d correspond to L5b in the schematic diagram of FIG.
  • the differential tapped inductor 400 includes one or more conductive segments (for example, V1-V5b, V4-V5b, V5a-V5c, and V5b-V5d) forming a figure-eight physical loop 401.
  • the "figure eight" here can be understood as: it includes two circular or approximately circular (for example, polygonal) geometric shapes that make up the figure eight, and the two geometric shapes are both axisymmetric structures. These two shapes can be The closed shape may also be a non-closed shape.
  • Each conductive section here can be understood as an inductor with two terminals. For example, each conductive section can be a coil with two terminals.
  • the multiple conductive segments constituting the physical loop 401 can be routed by layer-jumping, specifically, a figure-eight physical loop can be formed.
  • the plurality of conductive segments may be respectively wired on the top metal layer and the sub-top metal layer, or respectively wired on the top metal layer and the redistribution layer (RDL).
  • RDL redistribution layer
  • the figure-eight physical loop 401 can be divided into a non-crossing part and two crossing parts when routing. One of the non-crossing part and the two crossing parts can be wired to the top metal, and the other crossing part can be wired.
  • the two crossing parts can include P0-P1 and P2-P3, and the non-crossing part includes the physical loop 401 except for P0-P1 and P2-P3. other parts.
  • the parts of the two tap segments that do not overlap with the physical loop 401 can be routed on the top metal layer, and the overlapping part can be routed under the next top metal layer.
  • a metal layer when the physical loop 401 is routed to the top metal layer and the redistribution layer, the parts of the two tap segments that do not overlap with the physical loop 401 can be routed to the top metal layer, and the overlapping part can be routed to the next top metal layer Floor.
  • the multiple conductive segments can also be wired on other metal layers, which is not specifically limited in the embodiment of the present application.
  • the integrated circuit chip (also called a die) will include multiple metal layers.
  • the metal layer close to the substrate of the integrated circuit can be called a low-level metal layer, and the metal away from the substrate
  • the layer may be referred to as a high-level metal layer.
  • the above-mentioned top-level metal layer may refer to the metal layer farthest from the substrate in the high-level metal layer, and the sub-top metal layer may refer to the next metal layer of the top metal layer.
  • the aforementioned rewiring layer is located between the chip and the package of the integrated circuit, and the rewiring layer may specifically be an aluminum layer.
  • communication devices usually sample a multiple input multiple output (MIMO) working mode, which also means that multiple oscillators are required to work at the same time.
  • MIMO multiple input multiple output
  • the chip area of current communication equipment is developing toward a smaller size. Therefore, when multiple oscillators work at the same time, if there are two or more oscillators with the same frequency or a secondary frequency relationship, these There will be interference between the oscillators, thereby deteriorating each other's performance.
  • the tapped inductor 400 shown in FIG. 4 is composed of two half-eight-shaped loops with opposite magnetic fields. When the two magnetic fields with opposite directions are interfered by the magnetic field, the induced currents generated will cancel each other, so it has a good The anti-jamming performance.
  • Fig. 6 shows a schematic structural diagram of a differential VCO 600 practiced according to the principles of the present application.
  • the first transconductance amplifier in the amplifier includes a PMOS tube 604 and an NMOS tube 608, and the second transconductance amplifier includes a PMOS tube 606 and an NMOS tube 610.
  • the sources of the PMOS transistors 604 and 606 are coupled to the positive power rail (VDD), and the gates are coupled to the gates of the NMOS transistors 608 and 610.
  • the gates of the PMOS transistor 604 and the NMOS transistor 608 are coupled to the tap V1 of the differential tapped LC tank circuit 502.
  • the gates of the PMOS transistor 606 and the NMOS transistor 610 are coupled to the tap V4 of the differential tapped LC tank circuit 502.
  • the sources of the NMOS transistors 608 and 610 are coupled to the negative power rail (ground), and the drains are coupled to the drains of the PMOS transistors 604 and 606.
  • the taps V2 and V3 of the tapped LC tank circuit 502 are coupled to the normally coupled drains of the PMOS transistor 604 and the NMOS transistor 608 and the normally coupled drains of the PMOS transistor 606 and the NMOS transistor 610, respectively.
  • the amplifier includes two amplifying pairs, namely a first amplifying pair gm1 (also called a first transconductance amplifier) and a second amplifying pair gm2 (also called a second transconductance amplifier),
  • the two amplifier pairs both include a PMOS tube and an NMOS tube.
  • the sources of the PMOS tubes in gm1 and gm2 are both coupled to the positive power rail (VDD), and the sources of the NMOS tube are both coupled to the negative power rail (ground).
  • the gate A of the PMOS tube and NMOS tube in gm1 is coupled to the tap V1 of the tapped LC tank circuit 302, and the drain B of the PMOS tube and NMOS tube in gm1 is coupled to the tap V2 of the differential tapped LC tank circuit 302. ;
  • the gate C of the PMOS tube and NMOS tube in gm2 is coupled to the tap V4 of the differential tapped LC tank circuit 302, and the drain D of the PMOS tube and NMOS tube in gm2 is coupled to the tap V3 of the differential tapped LC tank circuit 302 .
  • the equivalent inductances L1-L5 in the tapped LC tank circuit 302 can be designed through the inductances shown in L11-L14 in FIG. 7 in actual application, and L11-L14 are only exemplary. It does not limit the embodiments of the present application.
  • L11-L14 and C1 are connected in parallel to form an oscillator tank.
  • the first amplifying pair gm1 and the second amplifying pair gm2 form a negative resistance through cross positive feedback to offset the loss of the tank to form a class AB mode Of the oscillator.
  • the amplitude of the AC signal seen by the gate A and the drain B is different. This is because L11 and L13 will make the impedance seen by the B end smaller than the impedance seen by the A end. According to the linear analysis of the small signal, the proportional relationship is approximately (L14+L11+L12)/(L11+L12+L13+L14).
  • the first amplifier pair gm1 can work in the linear region of the class AB mode.
  • the gate of the class AB oscillator formed by the inductance feedback shown in Fig. 7 has a larger oscillation amplitude, reduces the nonlinearity of the drain, and thus has better phase noise.
  • the amplifier includes two amplifying pairs of tubes, namely a first amplifying pair of tubes gm1 and a second amplifying pair of tubes gm2, where the first amplifying pair of tubes gm1 and the second amplifying pair of tubes gm2 are the same as the gm1 in Figure 7 above. It is consistent with gm2, and the specific description can be referred to the related description in FIG. 7, and the details are not repeated here in the embodiment of the present application.
  • the equivalent inductances L1-L5b in the differential tapped LC tank circuit 502 can be designed through the inductances shown in L21-L24 in FIG. 8 in practical applications, and L21-L24 are only exemplary and not The embodiment of this application constitutes a limitation.
  • the class AB oscillator composed of inductance feedback shown in FIG. 8 is consistent with the class AB oscillator shown in FIG. 7 and also has better phase noise.
  • FIG. 7 For a detailed description of the principle, please refer to the related description in FIG. 7.
  • the two oscillators can be coupled to work through a transformer or a capacitor.
  • This power coupling method reduces the VCO output signal-to-noise ratio by half, so as to achieve the effect of optimizing the noise by 3dB.
  • the middle tap of the inductor L22 is coupled with the output stage of the first amplifying pair gm1, so that gm1, L21, and L22 form a single-ended three-point oscillation VCO circuit; in the same way, the middle tap of the inductor L24 is connected with The output stage of the second amplifier pair gm2 is coupled, so that gm2, L23 and L24 form another symmetrical VCO circuit with a single-ended three-point oscillation.
  • the two VCOs are coupled together with the first capacitor C1 and the second capacitor C2. , Which can double the equivalent inductance and halve the equivalent capacitance, thereby doubling the signal energy and reducing the phase noise by 3dB.
  • L21-L24 in Figure 8 as a figure-eight physical loop can make L21-L24 form two magnetic fields in opposite directions to achieve the purpose of anti-interference.
  • the positions of L22 and L24 in figure 8 can be interchanged, and then L1 and L3 are set to a half circle of the figure of eight, and L2 and L4 are set For the other half circle of the figure eight, a physical loop of figure eight is obtained.
  • EDA Electronic Design Automation
  • FIG. 10 a simplified general-purpose ASIC design process for using (EDA) tools to produce an ASIC with embodiments of the present application is shown.
  • EDA electronic circuit design
  • step 1000 create a functional design of an ASIC that may include a VCO with a tapped inductor according to the principles of the present application.
  • the functional design is usually presented by writing Register Transfer Level (RTL) code in a hardware description language (Hardware Descriptive Language, HDL), such as but not limited to VHDL or Verilog. Then preferably perform functional verification (behavior simulation) on the HDL data structure to ensure that the RTL design conforms to the logic specification.
  • RTL Register Transfer Level
  • HDL Hard Descriptive Language
  • a schematic capture program can be used to capture schematics of digital logic.
  • the simulation function design is usually presented by capturing the schematic diagram with a schematic capture program. Then convert (synthesize) the output of the schematic capture program into a grid/tube-level netlist data structure.
  • the data structure is simulated by the integrated circuit simulation program (simulation program with integrated circuits emphasis, SPICE).
  • the data structure obtained from step 1002 is instantiated through its geometric representation, and the physical layout of the ASIC is executed.
  • the first step in the physical layout is usually the so-called "layout plan", in which the total area on the integrated circuit chip is allocated and input/output (I/O) pins are defined.
  • Place hard cores such as arrays, analog blocks, inductors, etc.
  • Place the clock routing usually called the clock tree
  • Modify the layout where possible, while keeping consistent with the design rules specified by the selected own or external semiconductor manufacturing foundries, thereby improving production efficiency. Such modifications may include adding additional vias or dummy metal/diffusion/polymer layers.
  • the physical design is verified.
  • Perform design rule checking (DRC) to determine whether the physical layout of the ASIC meets a series of recommended parameters, that is, the design rules of the foundry.
  • Design rules are a series of parameters provided by foundries for specific semiconductor manufacturing processes. Design rules specify certain geometric and connectivity constraints to ensure that there is enough leeway to deal with the variability in the semiconductor manufacturing process to ensure that ASICs work properly.
  • a layout versus schematic (LVS) check is performed to verify that the physical layout corresponds to the original schematic or circuit diagram of the design. Then, a complete simulation is preferably performed to ensure that the layout phase is completed correctly.
  • the mask generation design data which is usually in the form of a GDSII data structure, is referred to as the "tape out" used to prepare the photomask at step 1008.
  • the GDSII data structure is transmitted from the circuit designer to the photomask supplier/manufacturer or directly to the semiconductor foundry through the communication medium (such as memory or network).
  • a photomask is created and used to fabricate an ASIC according to the principles of the present application.
  • Some of the technologies described herein can be implemented by software stored on one or more computer-readable storage media and executed on a computer.
  • the selected technique can be executed on a single computer or on a computer networked with another computer or computers.
  • Product details that are well known in the art can be omitted.
  • FIG. 11 shows an illustrative example of a computing device 1101 used to practice the design flow of FIG. 11.
  • the computing device 1101 includes a computing unit 1103 having a processing unit 1105 and a system memory 1107.
  • the processing unit 1105 may be any type of programmable electronic device for executing software instructions, but is usually a microprocessor.
  • the system memory 1107 may include both a read-only memory (ROM) 1109 and a random access memory (RAM) 1111. Those of ordinary skill in the art should understand that both the read-only memory 1109 and the random access memory 1111 can store software instructions executed by the processing unit 1105.
  • the processing unit 1105 and the system memory 1107 are directly or indirectly connected to one or more peripheral devices through a bus 1113 or an alternative communication structure.
  • the processing unit 1105 or the system memory 1107 may be directly or indirectly connected to one or more additional storage devices 1115.
  • the storage device 1115 may include a "hard" disk drive, a solid-state disk drive, an optical disk drive, a removable disk drive, and the like.
  • the processing unit 1105 and the system memory 1107 may also be directly or indirectly connected to one or more input devices 1117 and one or more output devices 1119.
  • the input device 1117 may include a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a navigation ball, or a joystick), a scanner, a camera, a microphone, and the like.
  • the output device 1119 may include a display device, a printer, a speaker, and so on.
  • one or more of the peripheral devices 1115 to 1119 may be equipped with a computing unit 1103 inside.
  • one or more of the peripheral devices 1115 to 1519 may be outside the housing of the computing unit 1103, and pass through a universal serial bus (Universal Serial Bus, USB) connector or a digital visual interface (digital visual interface, DVI) connector. Wait for the connection to the bus 1113.
  • USB Universal Serial Bus
  • DVI digital visual interface
  • the computing unit 1103 may also be directly or indirectly connected to one or more network interface cards (NIC) 1121 for communicating with other devices that make up the network.
  • the network interface card 1121 converts the data and control signals in the computing unit 1103 into network messages according to one or more communication protocols, such as transmission control protocol (TCP) and Internet protocol (IP).
  • TCP transmission control protocol
  • IP Internet protocol
  • the network interface card 1121 can use any suitable connection agent (or combination of agents) used to connect to the network, including a wireless transceiver, a modem, or an Ethernet connection.
  • the computing device 1101 is only shown as an example and is not restrictive.
  • One or more computing devices may be used to implement the embodiments of the present application.
  • the one or more computing devices include components of the computing device 1101 shown in FIG. 11 or include components (including components not shown in FIG. 11). ) Replacement combination.
  • a multi-processor computer, a plurality of single and/or multi-processor computers arranged in a network, or some combination of the two may be used to implement the embodiments of the present application.
  • the amplifying device includes a first transconductance amplifier and a second transconductance amplifier
  • the resonant device includes an inductance element and a capacitive element
  • the capacitive element includes a first capacitor and a second transconductance amplifier
  • the inductance element includes a tapped inductor
  • the tapped inductor includes a first section of inductance and a second section of inductance, the first section of inductance and the second section of inductance are coupled through a first capacitor;
  • the first section of inductance includes a first terminal and The second terminal;
  • the second section of inductance includes a third terminal and a fourth terminal;
  • the first terminal and the second terminal are respectively coupled to the input and output of the first transconductance amplifier;
  • the third terminal and the fourth terminal are respectively coupled to the second transconductance amplifier
  • the input terminal and the output terminal of the conductance amplifier; the first terminal and the fourth terminal are coupled through the second capacitor.
  • the tapped inductor includes a plurality of conductive segments, and the plurality of conductive segments form a figure-eight physical loop by means of layer jumps and crossings.
  • the computer device includes a storage device for storing computer instructions with a photomask data device for manufacturing an oscillator including a resonance device and an amplifier device.
  • the amplifying device includes a first transconductance amplifier and a second transconductance amplifier;
  • the resonant device includes a capacitive element and an inductive element, the capacitive element includes a first capacitor and a second capacitor, the inductive element includes a tapped inductor, and the tapped inductor includes a first Section inductance and second section inductance, the first section of inductance and the second section of inductance are coupled through the first capacitor;
  • the first section of inductance includes a first terminal and a second terminal;
  • the second section of inductance includes a third terminal and a fourth terminal;
  • One terminal and the second terminal are respectively coupled to the input terminal and the output terminal of the first transconductance amplifier;
  • the third terminal and the fourth terminal are respectively coupled to the input terminal and the output terminal of the second transconductance amplifier;
  • the floorplanning device includes logic for defining or allocating a total area on the integrated circuit and for defining input/output (I/O) pins.
  • the layout planning device includes hard cores (such as arrays, analog blocks, inductors, etc.) placement devices for placing them in the total area based on design constraints (such as trace length, timing, etc.).
  • a clock routing device (usually called a clock tree) is used to place the connection between the clock tree and the guide gate/analog block. Global and detailed guides are used to design connections to connect all elements together.
  • the physical design verification device including the design rule checking device is used to verify that the physical design of the circuit (for example, ASIC) satisfies one or more design rules.
  • Design rules specify certain geometric and connectivity constraints to ensure that there is enough leeway to deal with the variability in the semiconductor manufacturing process to ensure that ASICs work properly.
  • the layout versus schematic (LVS) device is used to verify that the physical layout corresponds to the original schematic or circuit diagram of the design.
  • the simulation device is used to perform a complete simulation to ensure that the layout phase is completed correctly.
  • the tape-out device is used to generate mask generation design data that is usually presented in the form of a GDSII data structure for preparing photomasks.
  • the GDSII data structure is transmitted from the circuit designer to the photomask supplier/manufacturer or directly to the semiconductor foundry through the communication medium (such as memory or network).
  • the photomask creation device creates a photomask for manufacturing an ASIC according to the principles of the present application.
  • the above-mentioned devices are optionally used to produce resonant devices and amplifying devices as described and required herein.
  • Some of the technologies described herein can be implemented by software stored on one or more computer-readable storage media and executed on a computer.
  • the selected technique can be executed on a single computer or on a computer networked with another computer or computers.
  • Product details that are well known in the art can be omitted.
  • Examples of computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic devices such as built-in hard disks and removable disks. Media, magneto-optical media, optical media such as CD-ROM discs, and digital versatile disk (DVD).
  • each MOS tube in any embodiment or drawing can be a single MOS tube that meets the required start-up gain or the required conduction current.
  • It can also be a combination of multiple MOS transistors in parallel that needs to meet the required start-up gain or the required conduction current, that is, the sum of the corresponding start-up gains of each of the multiple MOS transistors is greater than or equal to The required startup gain;
  • each capacitor in the embodiment of the present application can be a capacitor that meets the required capacitance value, or it can be a combination of capacitors that meet the required capacitance value formed by multiple capacitors in parallel or in series, that is, the After multiple capacitors are connected in series or in parallel, the corresponding capacitance value is equal to the required capacitance value;
  • each inductor in the embodiment of the present application can be an inductor that meets the required inductance value, or multiple inductors can be connected in series or in parallel.
  • each resistor in the embodiment of the present application can be a resistor that meets the required resistance value, or it can be composed of multiple resistors that meet the required resistance value in parallel or in series.
  • the resistance combination that is, the corresponding resistance value after the multiple resistances are connected in series or in parallel is equal to the required resistance value.

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Abstract

本申请提供一种振荡器电路，涉及电子技术领域，用于提高振荡器的性能。所述振荡器电路，包括：放大器，第一跨导放大器和第二跨导放大器；谐振器，包括电容元件和电感元件，电容元件包括第一电容器和第二电容器，电感元件包括抽头式电感器，抽头式电感器包括第一段电感和第二段电感，第一段电感和第二段电感通过第一电容耦合；第一段电感包括第一端子和第二端子；第二段电感包括第三端子和第四端子；第一端子和第二端子分别耦合第一跨导放大器的输入端和输出端；第三端子和第四端子分别耦合第二跨导放大器的输入端和输出端；第一端子和第四端子通过第二电容器耦合。

Description

一种振荡器电路 技术领域
本申请涉及电子技术领域，尤其涉及一种振荡器电路。
背景技术
随着蜂窝、无线局域网(wireless local area network，WLAN)、卫星通信，全球定位系统(global positioning system，GPS)等无线通信系统的发展，对尺寸小、成本低、频率高的产品的需求也在不断增加。在这方面，压控振荡器(voltage controlled oscillator，VCO)在通信系统中发挥了关键作用，为数字电路中的定时和射频(radio frequency，RF)电路中的频率转换提供了所需的周期信号。VCO可以实现为与其它电路分离或集成到专用集成电路(application specific integrated circuit，ASIC)中的独立模块以在设备中使用，这些设备是例如但不限于手机、基站以及几乎每个通信设备。随着RF频率的提高和电源电压的降低，越来越难设计出既满足系统噪声和功率需求，又满足尺寸小、成本低、频率高的产品需求的VCO。
LC谐振VCO的噪声性能与其信号功率直接相关，其信号功率与存储在谐振电感-电容(inductor-capacitor，LC)储能电路中的能量成正比。在传统的VCO设计中，存储在LC电路中的能量与电感器的尺寸和VCO中放大器的电源电压的平方成正比。随着半导体设备的几何形状的缩小，放大器的电源电压也需要降低。为了对电压下降进行补偿，LC储能电路中使用的电感器的尺寸也必须减小，从而使VCO产生的噪声性能保持不变。增加所需频率也需要减小电感器的尺寸。但是，减小电感器尺寸极具挑战性，因为随着电感器的尺寸不断变小，电感器的品质因数(quality factor，Q)也会降低，从而进一步增加VCO的热噪声。
发明内容
本申请提供一种振荡器电路，用于提高振荡器的性能。为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种振荡器电路，包括：放大器，包括第一跨导放大器和第二跨导放大器；谐振器，包括电容元件和电感元件，电容元件包括第一电容器和第二电容器，电感元件包括抽头式电感器，抽头式电感器包括第一段电感和第二段电感，第一段电感和第二段电感通过第一电容器耦合；第一段电感包括第一端子和第二端子；第二段电感包括第三端子和第四端子；第一端子和第二端子分别耦合第一跨导放大器的输入端和输出端；第三端子和第四端子分别耦合第二跨导放大器的输入端和输出端；第一端子和第四端子通过第二电容器耦合。上述技术方案中，第一跨导放大器和第一段电感可以作为一个单端三点振荡的振荡器，第二跨导放大器和第二段电感可以作为另一个单端三点振荡的振荡器，通过第一电容器和第二电容器将这两个单端三点振荡的振荡器耦合在一起，可以降低该振荡器电路的相位噪声，从而提高该振荡器电路的性能。
在第一方面的一种可能的实现方式中，抽头式电感器包括多个导电段，多个导电段通过跳层交叉的方式构成一个8字形的物理环路。上述可能的实现方式中，抽头式电感器由具有两个磁场方向相反的半圈环路组成，这两个方向相反的磁场在受到磁场的干扰时，产生的感应电流相抵消，因此具有很好的抗干扰性能。
在第一方面的一种可能的实现方式中，多个导电段分别布线于顶层金属层和次顶层金属层，或者顶层金属层和重布线层。可选的，8字形物理环路401包括的多个导电段在布线时分为非交叉部分和两个交叉部分，非交叉部分和两个交叉部分中的一个交叉部分可以布线于顶层金属，另一个交叉部分可以布线于次顶层金属或是重布线层。上述可能的实现方式中，能够减小振荡器电路中其他元件对抽头式电感器的干扰。
在第一方面的一种可能的实现方式中，第一端子和第四端子为抽头式电感器的两个输出端，第二端子和第三端子为抽头式电感器的两个抽头端。上述可能的实现方式中，第二端子和第三端子位置的改变可用于调节振荡器电路的功耗、输出幅度和相位噪声，从而提高了振荡器电路的性能。
在第一方面的一种可能的实现方式中，第二端子和第三端子对应的两个抽头段布线于抽头式电感器的中间。当物理环路布线于顶层金属层和次顶层金属层时，两个抽头段中与物理环路未重叠的部分可以布线于顶层金属层、重叠的部分可以布线于次顶层金属层的下一金属层；当物理环路布线于顶层金属层和重布线层时，两个抽头段中与物理环路未重叠的部分可以布线于顶层金属层、重叠的部分可以布线于次顶层金属层。上述可能的实现方式中，通过将这两个抽头段布线于抽头式电感器的中间，可以使得抽头式电感器对称两半的感应电流相抵消，从而提高振荡器电路的性能。
在第一方面的一种可能的实现方式中，放大器的输入电压超出放大器的电源电压。上述可能的实现方式中，当该输入电压超出该电源电压时，可以提高该振荡器电路的增益，同时也降低了对振荡器电路的功率要求。
在第一方面的一种可能的实现方式中，第一跨导放大器和第二跨导放大器均包括：NMOS管和PMOS管；其中，NMOS管的源极耦合至正电源轨，NMOS管和PMOS管的栅极耦合作为输入端，NMOS管和PMOS管的漏极耦合作为输出端，PMOS管的源极耦合至接地端。上述可能的实现方式，第一跨导放大器和第二跨导放大器通过交叉正反馈构成负阻，可以抵消谐振器形成的tank的损耗，从而提高该振荡器电路的性能；另外，第一跨导放大器和第二跨导放大器的输入阻抗和输出阻抗不同，通过调节该输入阻抗与输出阻抗的比值，可以使该振荡器电路工作在线性区域，从而使该振荡器电路具有更好的相位噪声。
第二方面，提供了一种与计算机一起使用的非瞬时性计算机可读介质，计算机具有用于创建集成电路的软件，计算机可读介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构具有用于制造振荡器电路的光掩膜数据，振荡器电路包括：放大器，包括第一跨导放大器和第二跨导放大器；谐振器，包括电容元件和电感元件，电容元件包括第一电容器和第二电容器，电感元件包括抽头式电感器，抽头式电感器包括第一段电感和第二段电感，第一段电感和第二段电感通过第一电容器耦合；第一段电感包括第一端子和第二端子；第二段电感包括第三端子和第四端子；第一端子和第二端子分别耦合第一跨导放大器的输入端和输出端；第三端子和第四端 子分别耦合第二跨导放大器的输入端和输出端；第一端子和第四端子通过第二电容器耦合。
在第二方面的一种可能的实现方式中，抽头式电感器包括多个导电段，多个导电段通过跳层交叉的方式构成一个8字形的物理环路。
在第二方面的一种可能的实现方式中，多个导电段分别布线于顶层金属层和次顶层金属层，或者顶层金属层和重布线层。
在第二方面的一种可能的实现方式中，第一端子和第四端子为抽头式电感器的两个输出端，第二端子和第三端子为抽头式电感器的两个抽头端。
在第二方面的一种可能的实现方式中，第二端子和第三端子对应的两个抽头段布线于抽头式电感器的中间。
在第二方面的一种可能的实现方式中，放大器的输入电压超出放大器的电源电压。
在第二方面的一种可能的实现方式中，第一跨导放大器和第二跨导放大器均包括：NMOS管和PMOS管；其中，NMOS管的源极耦合至正电源轨，NMOS管和PMOS管的栅极耦合作为输入端，NMOS管和PMOS管的漏极耦合作为输出端，PMOS管的源极耦合至接地端。
可以理解地，上述提供的任一种与计算机一起使用的非瞬时性计算机可读介质均包括了上文所提供的振荡器电路，因此，其所能达到的有益效果可参考上文所提供的振荡器电路中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种差分LC储能电路的示意图；
图2为本申请实施例提供的第一种差分抽头式电感器的示例布局；
图3为本申请实施例提供的第一种差分抽头式LC储能电路；
图4为本申请实施例提供的第二种差分抽头式电感器的示例布局；
图5为本申请实施例提供的第二种差分抽头式LC储能电路；
图6为本申请实施例提供的第一种差分VCO的示意图；
图7为本申请实施例提供的第二种差分VCO的示意图；
图8为本申请实施例提供的第三种差分VCO的示意图；
图9为本申请实施例提供的第四种差分VCO的示意图；
图10为本申请实施例提供的一种ASIC的设计流程图；
图11为本申请实施例提供的一种计算设备的说明性示例。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路 系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。陈述电路/组件“用于”执行一项或多项任务明确表明不会调用35U.S.C.112(f)。
在本说明书中，对“一项实施例”、“实施例”、“具体实施例”或“特定实施例”的引用表示结合特定实施例描述的特定特征、结构或特性包括在至少一项实施例中，而不一定包括在所有特定实施例中。因此，在本说明书的不同位置中，短语“在特定实施例中”、“在一项实施例中”或“在具体实施例中”的每一出现不一定指代相同的实施例。此外，任何具体实施例的特定特征、结构或特性可以通过任何合适的方式与一项或多项其它特定实施例组合。应当理解，根据本文的教示，本文描述和示出的特定实施例的其它变更和修改是可能的，并且将视为本申请的精神和范围的一部分。
图1示出了包括寄生电阻R c和R l的LC储能电路100的示意图，用于在差分压控振荡器(voltage controlled oscillator，VCO)中使用，LC储能电路100也可以称为LC谐振电路、LC谐振器或者谐振器等。VCO放大器向LC储能电路100的输入阻抗提供电流，LC储能电路100产生的通过LC电路的电压等于放大器输入端的电压。在传统的单个电感器VCO(例如Pierce配置)中，放大器驱动阻抗Z 2(ω o)，并且放大器输入端的电压表示为通过Z 2(ω o)的电压。
在本申请中，将单个电感器根据系数K进行分接(例如划分为至少两个部分)。放大器驱动由阻抗Z 1(ω o)定义的电感器抽头，而放大器输入端的电压来自通过由阻抗Z 2(ω o)定义的电感器抽头的信号。理论上，电感器段KL和(1-K)/2*L因电感小且频率非常高而可以看作单独的电感器。然而，由于物理尺寸要求和互耦合，单独的电感器是不切实际的。
由于放大器的输入端和输出端分别位于LC储能电路100(即Z 2和Z 1)的不同点处，所以VCO中的放大器的输入电压可远大于由抽头式电感器的分压器测量确定的放大器输出电压。这种布置有很多优点。
放大器的HCI电压限制仅限于输出端。这支持输入信号超出放大器的电源电压限制。由于输入电压代表存储在LC储能电路100中的能量，所以在总电感相同的情况下，与具有传统谐振器的VCO相比，VCO噪声较低，这是因为LC储能电路100电压较高。此外，电感器不必减小尺寸即可满足噪声要求，使得在集成到集成电路(例如作为ASIC的一部分)时具有较高的电感器Q。
由于输入到放大器的电压超出电源轨，所以放大器的增益高于给定的功耗。放大器的输出电流是通过Z 2的输入电压与其跨导g m的乘积。由于输入电压增加，所以在电流相同的情况下，放大器具有更多增益。这降低了对系统的功率要求。
从图1和下面的等式(1)至(5)可以看出，LC储能电路100中Z 1(ω o)处的阻抗比Z 2(ω o)处的阻抗低一个因数K 2。在大信号条件下，放大器的线性度由其输出端的线性度而不是其输入端的线性度决定。VCO的输出端处的低阻抗降低了闪烁噪声与VCO频率的非线性混合，从而提高其附近的边带噪声谱利用率。本领域技术人员将认识到，基带频率的闪烁噪声是具有1/ω密度谱但是经由非线性元件混合的一种电子噪声，其产生VCO单边带相位噪声的1/ω 3部分。
谐振值
Figure PCTCN2019114883-appb-000001
并且ω oL＝X o                (1)
Figure PCTCN2019114883-appb-000002
Figure PCTCN2019114883-appb-000003
Figure PCTCN2019114883-appb-000004
Figure PCTCN2019114883-appb-000005
其中：ω o是振荡频率(弧度/秒)；
L是电感；
C是电容；
R l是电感器的寄生电阻；
R c是电容器的寄生电阻；
K是将Z 1与Z 2相关的常数；
X o是谐振频率为ω o时电感器L的电抗。
现参考图2，示出了根据本申请原理用于LC储能电路(例如图1所示的LC储能电路)中并用于集成到集成电路上的差分抽头式电感器200的一种示例布局。图3示出了差分抽头式LC储能电路302的理想示意图，包括图2中与电容器C并联耦合的抽头式电感器200的等效电感200’的表示。注意，图2中的段V1-V5a、V2-V5a、V3-V5b、V4-V5b和V5a-V5b分别对应于图3的示意图中的电感器L1、L2、L3、L4和L5。
差分抽头式电感器200包括构成物理环路201的一个或多个导电段(例如V1-V5a、V4-V5b和V5a-V5b)。本文使用的术语“物理环路”是指具有共置或彼此紧邻的起始点和终点并且包括至少一个明显凸形部分的闭合或近似闭合的几何形状，其中，凸形部分限定了凸形部分内的内部空间(例如环状多边形或环状多边形段)。因此，物理环路不同于“电气环路”，电气环路通常表示电流可能流过的任何形状的封闭路径。
物理环路201优选地为对称的，在处于电感器200中时，示为大体上为八边形。在不脱离本申请的范围的情况下，本领域技术人员将认识到物理环路201可以包括其它对称和非对称形状(例如矩形、正方形、六边形等)。电感器200在V5a和V5b处通过电气连接装置与段V2-V5a和V3-V5b分接，构成电气环路(L2和L3)，这些电气环路设置在由物理环路21(包括L1、L5和L4)构成的内部空间内。
抽头式LC储能电路302的电容元件C可以体现为PMOS变容二极管、NMOS变容二极管、金属-绝缘体-金属(metal-insulator-metal，MIM)设备或任何其它合适的电容元件。在硅工艺中，可以使用两种类型的变容二极管，即反向偏压pn结型二极管或MOS电容器变容二极管。MOS电容器变容二极管可以由MOS管构成，MOS管的漏极、源极和主体接头耦合在一起，并且基于施加在主体与栅极接头之间的电压来调整 电容。在不脱离本申请的范围的情况下，本领域技术人员将认识到可以使用LC储能电路的电容元件C的其它替代元件。
抽头式LC储能电路302的品质因数(quality factor，Q)取决于具有低电阻的电感器200。通过使用厚/宽的金属化工艺，例如但不限于铝、铜、金或其它合适的材料，来减小串联电阻，从而使电感器200的电阻最小化。电感器200优选地由硅、砷化镓或其它适当材料等高电介质基板材料构成。可以使用表面微加工技术来在电感器与基板之间产生空气间隙，以进一步提高介电性能。
电感器抽头段V2-V5a和V3-V5b(L2和L3)耦合到放大器输出端并且不属于LC储能电路。因此，它们的寄生电阻不如电感器段L1、L4和L5的寄生电阻重要。因此，段L2和L3可以使用如图2所示的较薄金属材料来构造。
在使用多个电感器(例如L1至L5)时涉及的实际问题是从放大器输出端到抽头点V5a和V5b的任何连接中的互感。LC储能电路中的电感器电流通常比从放大器按电路因数Q提供的电流高得多。当互感高时，来自LC储能电路的感应电流在从放大器输出端到抽头点的引线中变得足够高，使得到抽头的输入阻抗变高，以至于放大器不能提供任何电流。为了克服这个问题，将抽头段V2-V5a(L2)和V3-V5b(L3)在电感器200的中间向上引导(如图2所示)，使得来自电感器200对称两半的感应电流相抵消。
可以在金属上调整抽头位置V5a和V5b以改变功耗、VCO输出摆幅和相位噪声性能。这可用于微调金属方面的设计，如V5a'和V5b'所示。为了最小化基板的寄生效应，可以将基板掺杂添加剂以具有高电阻率，和/或可以通过蚀刻或微加工来增加金属层与基板之间的距离。
进一步的，结合图2，如图4所示，本申请实施例还示出了另一种用于集成到集成电路上的差分抽头式电感器400的示例布局。在图4中，抽头式电感器400被分割为两段电感(即第一段电感和第二段电感)，这两段电感通过第一电容器C1耦合。第一段电感和第二段电感中的每段电感可以是一个单独的三端式抽头电感器，即具有两个输出端和一个抽头端的电感器，比如，每段电感可以是一个具有两个输出端和一个抽头端的绕阻线圈。在图4中，第一段电感可以包括V1-V5a、V5a-V5c和V5a-V2，V1和V5c可以是第一段电感的两个输出端，V2可以是第一段电感的抽头端；第二段电感可以包括V4-V5b、V5b-V5d和V5b-V3，V4和V5d可以是第二段电感的两个输出端，V2可以是第二段电感的抽头端。
图5示出了图4对应的差分抽头式LC储能电路502的理想示意图，包括图4中与第二电容器C2并联耦合的抽头式电感器400的等效电感400’的表示。注意，图4中的段V1-V5a对应于图5的示意图中的电感器L1，V2-V5a对应于图5的示意图中的电感器L2，V3-V5b对应于图5的示意图中的电感器L3，V4-V5b对应于图5的示意图中的电感器L4，V5a-V5c对应于图5的示意图中的L5a，V5b-V5d对应于图5的示意图中的L5b。
差分抽头式电感器400包括构成一个8字形的物理环路401的一个或多个导电段(例如V1-V5b、V4-V5b、V5a-V5c和V5b-V5d)。这里的“8字形”可以理解为：包括组成8字形的两个环形或者近似环形(比如，多边形)的几何形状、且这两个几何 形状均呈轴对称结构，这两个几个形状可以是闭合形状，也可以是非闭合形状。这里的每个导电段可以理解为具有两个端子的电感器，比如，每个导电段可以为一个具有两个端子的线圈。
在实际应用中，构成物理环路401的多个导电段可以通过跳层交叉的方式进行布线，具体可以构成一个8字形的物理环路。可选的，这多个导电段可以分别布线于顶层金属层和次顶层金属层，或者分别布线于顶层金属层和重布线层(redistribution layer，RDL)。示例性的，8字形物理环路401在布线时可以分为非交叉部分和两个交叉部分，非交叉部分和两个交叉部分中的一个交叉部分可以布线于顶层金属，另一个交叉部分可以布线于次顶层金属或是重布线层，以图4为例，两个交叉部分可以包括P0-P1和P2-P3，非交叉部分包括物理环路401中除P0-P1和P2-P3之外的其他部分。当物理环路401布线于顶层金属层和次顶层金属层时，两个抽头段中未与物理环路401重叠的部分可以布线于顶层金属层、重叠的部分可以布线于次顶层金属层的下一金属层；当物理环路401布线于顶层金属层和重布线层时，两个抽头段中与物理环路401未重叠的部分可以布线于顶层金属层、重叠的部分可以布线于次顶层金属层。当然，这多个导电段也可以布线于其他金属层，本申请实施例对此不作具体限制。
需要说明的是，通常集成电路的芯片(也可以称为裸片die)中会包括多层金属层，可以将靠近集成电路的衬底的金属层可以称为低层金属层，远离衬底的金属层可以称为高层金属层，上述顶层金属层可以是指高层金属层中距离衬底最远的一层金属层，次顶层金属层可以是指顶层金属层的下一层金属层。上述重布线层位于集成电路的芯片与封装之间，该重布线层具体可以是铝层。
目前，为了提高通信质量，通信设备通常采样多输入多输出(Multiple Input Multiple Output，MIMO)的工作模式，这也意味着需要多个振荡器同时工作。而当前通信设备的芯片面积向着更小尺寸的方向发展，因此，当多个振荡器同时工作时，若存在某两个或者多个振荡器的频率相同或者是二次频的关系时，则这些振荡器之间会产生干扰，从而恶化彼此的性能。而图4所示的抽头式电感器400由具有两个磁场方向相反的半八字环路组成，这两个方向相反的磁场在受到磁场的干扰时，产生的感应电流相抵消，因此具有很好的抗干扰性能。
需要说明的是，对应图2和图3的相关描述，也同样适用于图4和图5，本申请实施例在此不再赘述。
图6示出了根据本申请原理实践的差分VCO 600的结构示意图。参考图6，放大器中第一跨导放大器包括PMOS管604和NMOS管608，第二跨导放大器包括PMOS管606和NMOS管610。PMOS管604和606的源极耦合到正电源轨(VDD)，栅极耦合到NMOS管608和610的栅极。PMOS管604和NMOS管608的栅极耦合到差分抽头式LC储能电路502的抽头V1。PMOS管606和NMOS管610的栅极耦合到差分抽头式LC储能电路502的抽头V4。NMOS管608和610的源极耦合到负电源轨(地线)，漏极耦合到PMOS管604和606的漏极。
抽头式LC储能电路502的抽头V2和V3分别耦合到PMOS管604和NMOS管608的通常耦合的漏极以及PMOS管606和NMOS管610的通常耦合的漏极。
示例性的，参考图7，示出了使用根据本申请原理实践的抽头式LC储能电路302 的示例class AB振荡器的一种电路示意图。在图7中，放大器包括两个放大对管，即第一放大对管gm1(也可以称为第一跨导放大器)和第二放大对管gm2(也可以称为第二跨导放大器)，两个放大对管均包括一个PMOS管和一个NMOS管，gm1和gm2中PMOS管的源极均耦合到正电源轨(VDD)，NMOS管的源极均耦合到负电源轨(地线)。其中，gm1中PMOS管和NMOS管的栅极A耦合到抽头式LC储能电路302的抽头V1，gm1中PMOS管和NMOS管的漏极B耦合到差分抽头式LC储能电路302的抽头V2；gm2中PMOS管和NMOS管的栅极C耦合到差分抽头式LC储能电路302的抽头V4，gm2中PMOS管和NMOS管的漏极D耦合到差分抽头式LC储能电路302的抽头V3。
需要说明的是，抽头式LC储能电路302中的等效电感L1-L5在实际应用时，可通过图7中的L11-L14所示的电感进行设计，L11-L14仅为示例性的，并不对本申请实施例构成限定。
在图7中，L11-L14和C1并联形成一个振荡器的tank，第一放大对管gm1和第二放大对管gm2通过交叉正反馈构成负阻，抵消该tank的损耗，以形成class AB模式的振荡器。对于第一放大对管gm1，栅极A和漏极B看到的交流信号的幅度是不一样的，这是由于L11和L13会使得B端看到的阻抗要小于A端看到的阻抗，按照小信号线性分析，其比例关系大约为(L14+L11+L12)/(L11+L12+L13+L14)。所以，通过选择不同的L3和L4的比例关系来改善第一放大对管gm1的漏极B看到的阻抗大小，可以使得第一放大对管gm1工作在class AB模式的线性区域。与传统的CMOS振荡器相比，图7所示的电感反馈构成的class AB振荡器的栅极具有更大的振荡幅度，减小了漏极的非线性，从而具有更好的相位噪声。
示例性的，参考图8，示出了使用根据本申请原理实践的抽头式LC储能电路502的示例class AB振荡器的一种电路示意图。在图8中，放大器包括两个放大对管，即第一放大对管gm1和第二放大对管gm2，这里的第一放大对管gm1和第二放大对管gm2与上述图7中的gm1和gm2一致，具体描述可以参见图7中的相关描述，本申请实施例在此不再赘述。
其中，差分抽头式LC储能电路502中的等效电感L1-L5b在实际应用时，可通过图8中的L21-L24所示的电感进行设计，L21-L24仅为示例性的，并不对本申请实施例构成限定。另外，图8所示的电感反馈构成的class AB振荡器与图7所示的class AB振荡器一致，同样具有较好的相位噪声，具体原理描述可以参见图7中的相关描述。
此外，为了降低振荡器的相位噪声，可以通过变压器或是电容把两个振荡器耦合在一起工作的方法，这种功率耦合的方法VCO输出信噪比减半，从而达到优化噪声3dB的效果。在图8中，将电感L22的中间抽头与第一放大对管gm1的输出级耦合，这样gm1、L21和L22构成一个单端三点振荡的VCO电路；同理，将电感L24的中间抽头与第二放大对管gm2的输出级耦合，这样gm2、L23和L24构成另一个对称的一个单端三点振荡的VCO电路，把这两个VCO用第一电容器C1和第二电容器C2耦合在一起，可以使得等效电感加倍、等效电容减半，从而使得信号能量加倍，进而降低相位噪声3dB。
由于8字形的电感具有抗干扰的特性，因此将图8中的L21-L24设置为8字形的 物理环路，可以使得L21-L24形成两个方向相反的磁场，以达到抗干扰的目的。示例性的，如图9所示，在设计为8字形时，可以将图8中的L22和L24的位置互换，然后将L1和L3设置为8字形的一个半圈，将L2和L4设置为8字形的另一个半圈，即得到一个8字形的物理环路。
现代集成电路设计和制造通常使用电子设计自动化(Electronic Design Automation，EDA)工具自动实现。示例工具可以从诸如但不限于Synopsys、Cadence和Mentor Graphics等公司查找。本申请无需这些EDA工具的细节。
现参考图10，示出了使用(EDA)工具生产具有本申请实施例的ASIC的简化通用ASIC设计流程。在步骤1000处，创建可以包括VCO的ASIC的功能设计，该VCO具有根据本申请原理的抽头式电感器。
实际上，对于这些ASIC数字，功能设计通常通过以硬件描述语言(Hardware Descriptive Language，HDL)，诸如但不限于VHDL或Verilog，编写寄存器传输级(Register Transfer Level，RTL)代码来呈现。然后优选地对HDL数据结构执行功能验证(行为模拟)，以确保RTL设计符合逻辑规范。或者，可以使用示意图捕获程序来捕获数字逻辑的示意图。
对于实际模拟的部分ASIC(例如具有本申请的抽头式电感器的VCO)，模拟功能设计通常通过用示意图捕获程序捕获示意图来呈现。然后将示意图捕获程序的输出转换(合成)为栅极/管级网表数据结构。
在步骤1002处，通过集成电路通用模拟程序(simulation program with integrated circuits emphasis，SPICE)模拟数据结构。在步骤1004处，将从步骤1002获得的数据结构通过其几何表示来实例化，并且执行ASIC的物理布局。
物理布局中的第一步通常是所谓的“布局规划”，在该步骤中，分配集成电路芯片上的总区域，并且定义输入/输出(I/O)引脚。将硬核(例如阵列、模拟块、电感器等)基于设计限制(例如迹线长度、时序等)放置在总区域内。放置时钟布线(通常称为时钟树)，并引导栅极/模拟块之间的连接。当放置好所有元件时，运行全局和详细的布线以将所有元件连接在一起。优选地进行布线后优化以提高性能(时序收敛)、噪声(信号完整性)和产量。在可能的情况下修改布局，同时与由选定的自有或外部半导体制造代工厂规定的设计规则保持一致，从而提高生产效率。这样的修改可以包括添加额外的通孔或虚拟金属/扩散/聚合物层。
在步骤1006处，验证物理设计。执行设计规则检查(design rule checking，DRC)以确定ASIC的物理布局是否满足一系列推荐参数，即代工厂的设计规则。设计规则是由代工厂针对特定半导体制造工艺提供的一系列参数。设计规则指定某些几何和连接性限制，以确保有足够的余地来应对半导体制造过程中的可变性，从而确保ASIC正常工作。优选地执行布局对原理图(layout versus schematic，LVS)检查以验证物理布局对应于设计的原始示意图或电路图。然后，优选地执行完整模拟，以确保布局阶段正确完成。
在步骤1006中验证布局之后，通常呈现为GDSII数据结构形式的掩模生成设计数据被称为用于在步骤1008处制备光掩模的"流片"。GDSII数据结构通过通信介质(例如存储器或网络)从电路设计师传输到光掩模供应商/制造商或直接传输到半导体代工 厂。
在步骤1010处，创建光掩模并使用光掩模根据本申请原理来制造ASIC。
本文描述的一些技术可以通过存储在一个或多个计算机可读存储介质上并在计算机上执行的软件来实现。所选技术可以在单个计算机或与另一台或多台计算机联网的计算机上执行。为清楚起见，仅描述与所公开技术密切相关的工具或计算机的那些方面。本领域中众所周知的产品细节可以省略。
图11所示为用于实践图11的设计流程的计算设备1101的说明性示例。如图11所示，计算设备1101包括具有处理单元1105和系统存储器1107的计算单元1103。处理单元1105可以是用于执行软件指令的任何类型的可编程电子设备，但是通常是微处理器。系统存储器1107可以包括只读存储器(read-only memory，ROM)1109和随机存取存储器(random access memory，RAM)1111两者。本领域普通技术人员应理解，只读存储器1109和随机存取存储器1111都可以存储由处理单元1105执行的软件指令。
处理单元1105和系统存储器1107通过总线1113或替代通信结构直接或间接连接到一个或多个外围设备。例如，处理单元1105或系统存储器1107可以直接或间接连接到一个或多个附加存储设备1115。存储设备1115可以包括“硬”磁盘驱动器、固态磁盘驱动器、光盘驱动器和可移动磁盘驱动器等。处理单元1105和系统存储器1107还可以直接或间接连接到一个或多个输入设备1117以及一个或多个输出设备1119。输入设备1117可以包括键盘、定点设备(如鼠标、触摸板、手写笔、导航球或操纵杆)、扫描仪、照相机和麦克风等。输出设备1119可以包括显示设备、打印机和扬声器等。对于计算设备1101的各种示例，外围设备1115至1119中的一个或多个可以在内部配备有计算单元1103。或者，外围设备1115至1519中的一个或多个可以在计算单元1103的壳体的外部，并且通过通用串行总线(Universal Serial Bus，USB)接头或数字视频接口(digital visual interface，DVI)接头等连接到总线1113。
在一些实施方式中，计算单元1103还可以直接或间接连接到一个或多个网络接口卡(network interfaces card，NIC)1121，用于与组成网络的其它设备进行通信。网络接口卡1121根据一个或多个通信协议，例如传输控制协议(transmission control protocol，TCP)和互联网协议(Internet protocol，IP)，将计算单元1103中的数据和控制信号转换成网络消息。而且，网络接口卡1121可以使用任何合适的用来连接网络的连接代理(或代理的组合)，包括无线收发器、调制解调器或以太网连接等。
应当理解，计算设备1101仅作为示例示出，并不具有限制性。可以使用一个或多个计算设备来实现本申请的各实施例，一个或多个计算设备包括图11所示的计算设备1101的各组件或者包括各组件(包括未在图11中示出的组件)的替换组合。例如，可以使用多处理器计算机、布置在网络中的多个单和/或多处理器计算机或两者的某种组合来实现本申请的各实施例。
在一项实施例中，具有谐振装置和放大装置的振荡电路中，放大装置包括第一跨导放大器和第二跨导放大器，谐振装置包括电感元件和电容元件，电容元件包括第一电容器和第二电容器，电感元件包括抽头式电感器，抽头式电感器包括第一段电感和第二段电感，第一段电感和第二段电感通过第一电容耦合；第一段电感包括第一端子 和第二端子；第二段电感包括第三端子和第四端子；第一端子和第二端子分别耦合第一跨导放大器的输入端和输出端；第三端子和第四端子分别耦合第二跨导放大器的输入端和输出端；第一端子和第四端子通过第二电容器耦合。在一项实施例中，抽头式电感器包括多个导电段，所述多个导电段通过跳层交叉的方式构成一个8字形的物理环路。
在另一项实施例中，计算机装置包括用于存储具有光掩模数据装置的计算机指令的存储装置，用于制造包括谐振装置和放大装置的振荡器。放大装置包括第一跨导放大器和第二跨导放大器；谐振装置包括电容元件和电感元件，电容元件包括第一电容器和第二电容器，电感元件包括抽头式电感器，抽头式电感器包括第一段电感和第二段电感，第一段电感和第二段电感通过第一电容耦合；第一段电感包括第一端子和第二端子；第二段电感包括第三端子和第四端子；第一端子和第二端子分别耦合第一跨导放大器的输入端和输出端；第三端子和第四端子分别耦合第二跨导放大器的输入端和输出端；第一端子和第四端子通过第二电容器耦合。
在又一项实施例中，布局规划装置包括用于在集成电路上定义或分配总区域并用于定义输入/输出(I/O)引脚的逻辑。布局规划装置包括硬核(例如阵列、模拟块、电感器等)摆放装置，用于基于设计限制(例如迹线长度、时序等)放置在总区域内。时钟布线摆放装置(通常称为时钟树)用于放置时钟树和引导栅极/模拟块之间的连接。全局和详细的引导装置用于设计连接以将所有元件连接在一起。
包括设计规则检查装置的物理设计验证装置用于验证电路(例如ASIC)的物理设计满足一个或多个设计规则。设计规则指定某些几何和连接性限制，以确保有足够的余地来应对半导体制造过程中的可变性，从而确保ASIC正常工作。布局对原理图(layout versus schematic，LVS)装置用于验证物理布局对应于设计的原始示意图或电路图。模拟装置用于执行完整模拟，以确保布局阶段正确完成。
流片装置用于生成通常以GDSII数据结构形式呈现的掩模生成设计数据，以用于制备光掩模。GDSII数据结构通过通信介质(例如存储器或网络)从电路设计师传输到光掩模供应商/制造商或直接传输到半导体代工厂。光掩模创建装置创建用于根据本申请原理制造ASIC的光掩模。在其它特征中，应当理解，上述装置视情况用于产生如本文所述和要求的谐振装置和放大装置。
本文描述的一些技术可以通过存储在一个或多个计算机可读存储介质上并在计算机上执行的软件来实现。所选技术可以在单个计算机或与另一台或多台计算机联网的计算机上执行。为清楚起见，仅描述与所公开技术密切相关的工具或计算机的那些方面。本领域中众所周知的产品细节可以省略。
尽管上文是在特定组合中描述特征和元件，但是每个特征或元件可以在没有其他特征和元件的情况下单独使用，或在有或没有其他特征和元件的情况下以各种组合形式使用。计算机可读存储介质的例子包括只读存储器(read only memory，ROM)、随机存取存储器(random access memory，RAM)、寄存器、超速缓存内存、半导体存储器设备、如内置硬盘和可移动磁盘等磁性介质、磁光介质、如CD-ROM光盘等光介质和数字多用光盘(digital versatile disk，DVD)。
虽然本申请就某些实施例和一般相关方法进行了描述，但是这些实施例和方法的 变更和置换对于本领域技术人员将是显而易见的。特别地，应当注意，虽然已经在CMOS放大器的上下文中描述了本申请，但是在不脱离本申请的范围的情况下，本领域技术人员将认识到对PMOS和NMOS放大器、双极性放大器以及其它合适的拓扑的应用。本申请适用于几乎所有通信系统。例如，本申请可以用于蜂窝收发器、双向无线电通信、Wi-Fi应用、卫星接收器以及使用压控振荡器的任何应用。
需要说明的是，本申请实施例和附图仅仅是一种示例，任一实施例或附图中的每个MOS管可以为一个单独的满足所需要启动增益或者所需要导通电流的MOS管，也可以为通过多个MOS管并联组合成的需要满足所需要启动增益或者所需要导通电流的MOS管组合，也即该多个MOS管中每个MOS管对应的启动增益之和大于等于所需要启动增益；本申请实施例中的每个电容可以为满足所需电容值的一个电容，也可以是由多个电容通过并联或者串联组成的满足所需电容值的电容组合，也即该多个电容串联或并联后对应的电容值等于所需要的电容值；本申请实施例中的每个电感可以为满足所需要电感值的一个电感，也可以是由多个电感通过串联或者并联方式组成的满足所需要电感值的电感组合；本申请实施例中的每个电阻可以为满足所需电阻值的一个电阻，也可以是由多个电阻通过并联或者串联组成的满足所需电阻值的电阻组合，也即，该多个电阻串联或并联后对应的电阻值等于所需要的电阻值。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种振荡器电路，其特征在于，包括：
    放大器，包括第一跨导放大器(gm)和第二跨导放大器(gm)；
    谐振器，包括电容元件和电感元件，所述电容元件包括第一电容器和第二电容器，所述电感元件包括抽头式电感器，所述抽头式电感器包括第一段电感和第二段电感，所述第一段电感和第二段电感通过所述第一电容器耦合；
    所述第一段电感包括第一端子和第二端子；
    所述第二段电感包括第三端子和第四端子；
    所述第一端子和所述第二端子分别耦合所述第一跨导放大器的输入端和输出端；
    所述第三端子和所述第四端子分别耦合所述第二跨导放大器的输入端和输出端；
    所述第一端子和所述第四端子通过所述第二电容器耦合。
  2. 根据权利要求1所述的电路，其特征在于，所述抽头式电感器包括多个导电段，所述多个导电段通过跳层交叉的方式构成一个8字形的物理环路。
  3. 根据权利要求2所述的电路，其特征在于，所述多个导电段分别布线于顶层金属层和次顶层金属层，或者顶层金属层和重布线层。
  4. 根据权利要求1-3任一项所述的电路，其特征在于，所述第一端子和所述第四端子为所述抽头式电感器的两个输出端，所述第二端子和所述第三端子为所述抽头式电感器的两个抽头端。
  5. 根据权利要求4所述的电路，其特征在于，所述第二端子和所述第三端子对应的两个抽头段布线于所述抽头式电感器的中间。
  6. 根据权利要求1-5任一项所述的电路，其特征在于，所述放大器的输入电压超出所述放大器的电源电压。
  7. 根据权利要求1-6任一项所述的电路，其特征在于，所述第一跨导放大器和所述第二跨导放大器均包括：NMOS管和PMOS管；
    其中，所述NMOS管的源极耦合至正电源轨，所述NMOS管和所述PMOS管的栅极耦合作为所述输入端，所述NMOS管和所述PMOS管的漏极耦合作为所述输出端，所述PMOS管的源极耦合至接地端。
  8. 一种与计算机一起使用的非瞬时性计算机可读介质，其特征在于，所述计算机具有用于创建集成电路的软件，所述计算机可读介质上存储有一个或多个计算机可读数据结构，所述一个或多个计算机可读数据结构具有用于制造振荡器电路的光掩膜数据，所述振荡器电路包括：
    放大器，包括第一跨导放大器(gm)和第二跨导放大器(gm)；
    谐振器，包括电容元件和电感元件，所述电容元件包括第一电容器和第二电容器，所述电感元件包括抽头式电感器，所述抽头式电感器包括第一段电感和第二段电感，所述第一段电感和第二段电感通过所述第一电容器耦合；
    所述第一段电感包括第一端子和第二端子；
    所述第二段电感包括第三端子和第四端子；
    所述第一端子和所述第二端子分别耦合所述第一跨导放大器的输入端和输出端；
    所述第三端子和所述第四端子分别耦合所述第二跨导放大器的输入端和输出端；
    所述第一端子和所述第四端子通过所述第二电容器耦合。
  9. 根据权利要求8所述的计算机可读介质，其特征在于，所述抽头式电感器包括多个导电段，所述多个导电段通过跳层交叉的方式构成一个8字形的物理环路。
  10. 根据权利要求9所述的计算机可读介质，其特征在于，所述多个导电段分别布线于顶层金属层和次顶层金属层，或者顶层金属层和重布线层。
  11. 根据权利要求8-10任一项所述的计算机可读介质，其特征在于，所述第一端子和所述第四端子为所述抽头式电感器的两个输出端，所述第二端子和所述第三端子为所述抽头式电感器的两个抽头端。
  12. 根据权利要求11所述的计算机可读介质，其特征在于，所述第二端子和所述第三端子对应的两个抽头段布线于所述抽头式电感器的中间。
  13. 根据权利要求8-12任一项所述的计算机可读介质，其特征在于，所述放大器的输入电压超出所述放大器的电源电压。
  14. 根据权利要求8-13任一项所述的计算机可读介质，其特征在于，所述第一跨导放大器和所述第二跨导放大器均包括：NMOS管和PMOS管；
    其中，所述NMOS管的源极耦合至正电源轨，所述NMOS管和所述PMOS管的栅极耦合作为所述输入端，所述NMOS管和所述PMOS管的漏极耦合作为所述输出端，所述PMOS管的源极耦合至接地端。
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