WO2021077477A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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WO2021077477A1
WO2021077477A1 PCT/CN2019/117112 CN2019117112W WO2021077477A1 WO 2021077477 A1 WO2021077477 A1 WO 2021077477A1 CN 2019117112 W CN2019117112 W CN 2019117112W WO 2021077477 A1 WO2021077477 A1 WO 2021077477A1
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layer
gate insulating
insulating layer
gate
thickness
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French (fr)
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陈梦
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics

Definitions

  • the invention relates to the technical field of display panels, in particular to an array substrate and a preparation method thereof.
  • Flat panel display devices have many advantages such as thin body, power saving, and no radiation, and have been widely used.
  • Existing flat panel display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD) and Organic Light Emitting Display (OLED).
  • Array substrate Thin Film Transistor (TFT) is an important part of flat panel display devices, which can be formed on a glass substrate or a plastic substrate, and is usually used as a switch and driving device in LCDs and OLEDs.
  • TFT Thin Film Transistor
  • An object of the present invention is to provide an array substrate, which can solve the problem of the increase in the thickness of the gate insulating layer caused by the increase in the thickness of the copper film of the gate structure in the display panel in the prior art.
  • an array substrate of the present invention includes: a base substrate; a first gate insulating layer provided on the base substrate, the first gate insulating layer having a groove; a gate layer , Arranged in the groove of the first gate insulating layer; a second gate insulating layer, covering the first gate insulating layer and the gate layer; an active layer, arranged in the The second gate insulating layer.
  • it further includes a source and drain layer, which is provided on the active layer; a flat layer, which is provided on the source and drain layer; and a pixel definition layer, which is provided on the flat layer on.
  • the material used for the gate layer is copper metal, and the thickness of the gate layer ranges from 200 nm to 5000 nm.
  • the materials of the first gate insulating layer and the second gate insulating layer are any one or more of nitrogen oxide, silicon oxide, or silicon nitride, so The thickness of the first gate insulating layer ranges from 100 nm to 500 nm, and the thickness of the second gate insulating layer ranges from 100 nm to 500 nm.
  • the material of the active layer is any one or more of zinc oxide, indium zinc oxide, and indium zinc gallium oxide, and the thickness of the active layer ranges from 100 nm to 100 nm. 200nm.
  • the material of the flat layer is silicon oxide or silicon nitride
  • the thickness of the flat layer is 150 nm to 400 nm
  • the material of the pixel electrode layer is indium tin oxide
  • the pixel The thickness of the electrode layer is 30 nm to 100 nm.
  • the material of the base substrate is polyimide.
  • the material used for the source/drain layer is aluminum or molybdenum or a combination of both, and the thickness of the source/drain layer ranges from 20 nm to 600 nm.
  • the present invention also provides a method for preparing the array substrate of the present invention, which includes the following steps:
  • S1 providing a base substrate
  • S2 depositing a gate insulating material to form a first gate insulating film on the base substrate
  • S3 patterning the first gate insulating film to form a first gate insulating layer, The first gate insulating layer has a corresponding groove
  • S4 depositing a gate material on the first gate insulating layer and the groove to form a gate film
  • S5 wet etching the gate film , Removing the gate film on the first gate insulating layer and forming a gate layer in the groove
  • S6 depositing a gate insulating material on the first gate insulating layer and the gate layer Forming a second gate insulating layer
  • S7 forming an active layer on the second gate insulating layer.
  • the gate insulating layer is prepared in two steps, which can reduce the risk of poor step coverage caused by one-step preparation in the prior art.
  • the thickness of the second gate insulating layer is related to the electrical characteristics of the array substrate. By controlling the thickness ratio of the first gate insulating layer and the second gate insulating layer, it is possible to ensure that the on-state current of the array substrate is not Will reduce the risk of insufficient charging rate of the panel.
  • step S2 and step S6 a plasma-enhanced chemical vapor deposition method is used to deposit the gate insulating material.
  • step S6 before the step S6, it further includes S100: using any one or more of hydrogen, nitrogen, ammonia, or argon to insulate the first grid Layer for processing.
  • S100 using any one or more of hydrogen, nitrogen, ammonia, or argon to insulate the first grid Layer for processing.
  • step S7 it further includes S8: forming a source and drain layer on the active layer; S9: forming a flat layer on the source and drain layer; S10: forming a pixel electrode Layer on the flat layer.
  • the beneficial effect of the present invention is that the present invention provides an array substrate and a preparation method thereof.
  • the gate insulating layer is prepared in two steps, which can reduce the step coverage caused by the one-step preparation in the prior art. Poor risk, where the thickness of the second gate insulating layer is related to the electrical characteristics of the array substrate. By controlling the ratio of the thickness of the first gate insulating layer to the second gate insulating layer, it can be ensured that the on-state current of the array substrate will not decrease , To reduce the risk of insufficient panel charging rate.
  • Embodiment 1 is a schematic diagram of the structure of an array substrate provided by Embodiment 1 of the present invention.
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate provided by Embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram of the structure of the array substrate in step S1 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram of the structure of the array substrate in step S2 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram of the structure at step S3 in the preparation method provided in Example 1 of the present invention.
  • FIG. 6 is a schematic diagram of the structure of the array substrate in step S4 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 7 is a schematic diagram of the structure of the array substrate in step S5 in the preparation method provided by the embodiment 1 of the present invention.
  • FIG. 8 is a schematic diagram of the structure of the array substrate at step S6 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 9 is a schematic diagram of the structure of the array substrate in step S7 in the preparation method provided by the embodiment 1 of the present invention.
  • FIG. 10 is a schematic diagram of the structure of the array substrate at step S8 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 11 is a schematic diagram of the structure of the array substrate at step S9 in the manufacturing method provided by the embodiment 1 of the present invention.
  • FIG. 12 is a schematic diagram of the structure of the array substrate in step S10 in the manufacturing method provided by Embodiment 1 of the present invention.
  • Pixel electrode layer-70 is a Pixel electrode layer-70.
  • the array substrate 200 of the present invention includes a base substrate 10, a first gate insulating material 21, a gate layer 30, a second gate insulating layer 22, and an active layer. 40.
  • the first gate insulating layer 21 is disposed on the base substrate 10, the first gate insulating layer 21 has a groove 11, and the gate layer 30 is disposed in the groove 11 of the first gate insulating layer 21.
  • the second gate insulating layer 22 covers the first gate insulating layer 21 and the gate layer 30, and the active layer 40 is provided on the second gate insulating layer 22.
  • the material of the base substrate 10 uses polyimide (PI), that is, polyimide film, as the base of the array substrate;
  • PI polyimide
  • the polyimide film is a film-like insulating material with better performance in the world, and has relatively high performance. Strong tensile strength, it is made of pyromellitic dianhydride and diaminodiphenyl ether in a strong polar solvent through polycondensation and casting into a film and then imidization.
  • the material of the gate layer 30 is copper metal, and the thickness of the gate layer 30 ranges from 200 nm to 5000 nm.
  • the materials of the first gate insulating layer 21 and the second gate insulating layer 22 are any one or more of nitrogen oxide, silicon oxide or silicon nitride, and the thickness of the first gate insulating layer 21 ranges from 100 nm to 100 nm. 500 nm, the thickness of the second gate insulating layer 22 ranges from 100 nm to 500 nm.
  • the material of the active layer 40 is any one or two or more of zinc oxide, indium zinc oxide, and indium zinc gallium oxide, and the thickness of the active layer 40 ranges from 100 nm to 200 nm.
  • the active layer 40 is further provided with a source-drain layer 50, the source-drain layer 50 is provided with a flat layer 60, and the flat layer 60 is provided with a pixel definition layer 70.
  • the source and drain layer 50 is made of aluminum or molybdenum or a combination of the two.
  • the thickness of the source and drain layer 50 ranges from 20 nm to 600 nm.
  • the material of the flat layer 60 is silicon oxide or silicon nitride.
  • the thickness of the flat layer 60 is The thickness of the pixel electrode layer 70 is from 150 nm to 400 nm, the material of the pixel electrode layer 70 is indium tin oxide, and the thickness of the pixel electrode layer 70 is from 30 nm to 100 nm.
  • this embodiment also provides a preparation method to prepare the array substrate of the present invention.
  • FIG. 2 shows a flow chart of the method for manufacturing the array substrate provided by this embodiment, including steps S1 to S10.
  • FIG. 3 shows a schematic diagram of the structure of the array substrate in step S1 of the manufacturing method provided by this embodiment; step S1: providing a base substrate 10.
  • FIG. 4 shows a schematic diagram of the structure of the array substrate at step S2 in the method of manufacturing the array substrate provided by this embodiment; step S2: depositing a gate insulating material on the base substrate 10 to form a first gate insulating ⁇ 211 ⁇ Membrane 211.
  • the deposition of the first gate insulating material is a vapor deposition method using plasma enhanced chemistry.
  • FIG. 5 shows a schematic diagram of the structure of the array substrate in step S3 in the method of manufacturing the array substrate provided by this embodiment; step S3; patterning the first gate insulating film 211 to form the first gate insulating layer 21 ,
  • the first gate insulating layer 21 has a corresponding groove 11 therein.
  • the material of the first gate insulating layer 21 is any one or more of nitrogen oxide, silicon oxide, or silicon nitride, and the thickness of the first gate insulating layer 21 ranges from 100 nm to 500 nm.
  • FIG. 6 shows a schematic diagram of the structure of the array substrate in step S4 in the preparation method of the array substrate provided by this embodiment; step S4: depositing gate material on the first gate insulating layer 21 and in the groove The gate film 31 is formed.
  • FIG. 7 shows a schematic diagram of the structure of the array substrate at step S5 in the preparation method of the array substrate provided by this embodiment; step S5: wet etching the gate film 31 to remove the first gate insulating layer 21
  • the gate film 31 forms a gate layer 30 in the groove; wherein the material used for the gate layer 30 is copper metal, and the thickness of the gate layer 30 ranges from 200 nm to 5000 nm.
  • FIG. 8 shows a schematic diagram of the structure of the array substrate at step S6 in the preparation method of the array substrate provided by this embodiment; step S6: depositing a gate insulating material on the first gate insulating layer 21 and the gate layer A second gate insulating layer 22 is formed on 30.
  • step S6 it also includes using any one or more of hydrogen, nitrogen, ammonia, or argon to treat the surface of the first gate insulating layer 21, so as to reduce the first gate insulating layer 21 and the second gate insulating layer 21.
  • the difference in film quality between the gate insulating layer 22 prevents the film quality difference of the two layers from being too large, which will deteriorate the electrical and optical characteristics of the insulating layer, and ensure that the first gate insulating layer 21 and the second gate There will be no breakage between the polar insulating layers 22, which ensures that the optical characteristics of the pixel area will not deteriorate.
  • the second gate insulating layer 22 is deposited by plasma-enhanced chemical vapor deposition, and the material of the second gate insulating layer 22 is any one or more of nitrogen oxide, silicon oxide, or silicon nitride.
  • the thickness of the second gate insulating layer 22 ranges from 100 nm to 500 nm.
  • the gate insulating layer is prepared in two steps, which can reduce the risk of poor step coverage caused by one-step preparation in the prior art.
  • the thickness of the second gate insulating layer 22 is related to the electrical characteristics of the array substrate. By controlling the thickness ratio of the first gate insulating layer 21 and the second gate insulating layer 22, it can be ensured that the on-state current of the array substrate will not decrease. Reduce the risk of insufficient panel charging rate.
  • FIG. 9 shows a schematic diagram of the structure of the array substrate at step S7 in the method of manufacturing the array substrate provided by this embodiment; step S7: forming an active layer 40 on the second gate insulating layer 22; active
  • the material of the layer 40 is any one or two or more of zinc oxide, indium zinc oxide, and indium zinc gallium oxide, and the thickness of the active layer 40 ranges from 100 nm to 200 nm.
  • FIG. 10 shows a schematic diagram of the structure of the array substrate at step S8 in the method for manufacturing the array substrate provided in this embodiment.
  • Step S8 forming a source-drain layer 50 on the active layer 40; wherein the material of the source-drain layer 50 is aluminum or molybdenum or a combination of both, and the thickness of the source-drain layer 50 ranges from 20 nm to 600 nm.
  • FIG. 11 shows a schematic diagram of the structure of the array substrate in step S9 in the method of manufacturing the array substrate provided by this embodiment; step S9: forming a flat layer 60 on the source and drain layer 50;
  • the material is silicon oxide or silicon nitride, and the thickness of the flat layer 60 is 150 nm to 400 nm.
  • FIG. 12 shows a schematic diagram of the structure of the array substrate at step S10 in the method of manufacturing the array substrate provided by this embodiment; step S10: forming a pixel electrode layer 70 on the flat layer 60;
  • the material is indium tin oxide, and the thickness of the pixel electrode layer 70 is 30 nm-100 nm.
  • the beneficial effect of the present invention is that the present invention provides an array substrate and a preparation method thereof.
  • the gate insulating layer is prepared in two steps, which can reduce the risk of poor step coverage caused by one-step preparation in the prior art.
  • the thickness of the second gate insulating layer is related to the electrical characteristics of the array substrate. By controlling the thickness ratio of the first gate insulating layer and the second gate insulating layer, it can ensure that the on-state current of the array substrate will not decrease and reduce the panel charging rate. risks of.

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Abstract

一种阵列基板（200）及其制备方法，阵列基板（200）包括衬底基板（10）；第一栅极绝缘层（21），设于所述衬底基板（10）上，所述第一栅极绝缘层（21）中具有凹槽（11）；栅极层（30），设于所述第一栅极绝缘层（21）的所述凹槽（11）中；第二栅极绝缘层（22），覆于所述第一栅极绝缘层（21）和所述栅极层（30）上；有源层（40），设于所述第二栅极绝缘层（22）上。

Description

一种阵列基板及其制备方法 技术领域
本发明涉及显示面板技术领域，特别涉及一种阵列基板及其制备方法。
 背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。阵列基板(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED。
随着显示面板的分辨率升高和尺寸的增大，“信号延迟”现象将更加严重，降低布线电阻成为一项迫切的需求。铜(Cu)的导电性仅次于银(Ag)，而且原材料价格低廉，被认为是最有希望的低电阻率布线材料，现有技术中已有使用铜作为TFT的栅电极的材料。
在高世代液晶面板中，铜材料作为栅极金属线因其阻抗低、抗电迁移能力强等优点使得代替传统的铝材料成为趋势。随着面板尺寸的增大、分辨率的提高，一般的3000Å的铜导线厚度越来越难以解决电路延迟等问题，增加铜导线厚度成为解决问题的方向之一。
伴随铜导线厚度的增加，因台阶覆盖性问题，在栅极结构中将铜膜层厚度增加会导致栅极绝缘层的厚度增加，这会降低阵列基板的开态电流，面板充电率不足的风险提高。
因此，确有必要来开发一种新型的阵列基板的制备方法，以克服现有技术的缺陷。
 技术问题
本发明的一个目的是提供一种阵列基板，其能够解决现有技术中显示面板中栅极结构铜膜厚度增加带来的栅极绝缘层厚度增加的问题。
 技术解决方案
为实现上述目的，本发明一种阵列基板，包括：衬底基板；第一栅极绝缘层，设于所述衬底基板上，所述第一栅极绝缘层中具有凹槽；栅极层，设于所述第一栅极绝缘层的所述凹槽中；第二栅极绝缘层，覆于所述第一栅极绝缘层和所述栅极层上；有源层，设于所述第二栅极绝缘层上。
进一步的，在其他实施方式中，其中其还包括源漏极层，设于所述有源层上；平坦层，设于所述源漏极层上；像素定义层，设于所述平坦层上。
进一步的，在其他实施方式中，其中所述栅极层采用的材料为铜金属，所述栅极层的厚度范围为200nm～5000nm。
进一步的，在其他实施方式中，其中所述第一栅极绝缘层和所述第二栅极绝缘层的材料采用氧化氮或氧化硅或氮化硅中的任意一种或两种以上，所述第一栅极绝缘层的厚度范围为100nm～500nm，所述第二栅极绝缘层的厚度范围为100nm～500nm。
进一步的，在其他实施方式中，其中所述有源层的材料采用氧化锌、氧化铟锌、氧化铟锌镓中的任意一种或两种以上，所述有源层的厚度范围为100nm～200nm。
进一步的，在其他实施方式中，其中所述平坦层的材料采用氧化硅或氮化硅，所述平坦层的厚度为150nm～400nm，所述像素电极层的材料采用氧化铟锡，所述像素电极层的厚度为30nm～100nm。
进一步的，在其他实施方式中，其中所述衬底基板的材料采用聚醯亚胺。
进一步的，在其他实施方式中，其中所述源漏极层采用的材料为铝或钼或两者的结合，所述源漏极层的厚度范围为20nm～600nm。
为实现上述目的，本发明还提供一种制备本发明涉及的阵列基板的方法，包括以下步骤：
S1：提供一衬底基板；S2：沉积栅极绝缘材料于所述衬底基板上形成第一栅极绝缘膜；S3：图案化所述第一栅极绝缘膜形成第一栅极绝缘层，所述第一栅极绝缘层中具有相应的凹槽；S4：沉积栅极材料于所述第一栅极绝缘层以及所述凹槽中形成栅极膜；S5：湿蚀刻所述栅极膜，去除所述第一栅极绝缘层上的栅极膜并在所述凹槽中形成栅极层；S6：沉积栅极绝缘材料于所述第一栅极绝缘层和所述栅极层上形成第二栅极绝缘层；S7：形成有源层于所述第二栅极绝缘层上。
其中栅极绝缘层分成两个步骤制备，能够降低现有技术中一步制备带来的台阶覆盖性较差的风险。
其中所述第二栅极绝缘层的厚度与阵列基板的电学特性相关，通过控制所述第一栅极绝缘层和所述第二栅极绝缘层的厚度比例，能够确保阵列基板开态电流不会降低，降低面板充电率不足的风险。
进一步的，在其他实施方式中，其中在步骤S2和步骤S6中，采用等离子体增强化学的气相沉积法沉积所述栅极绝缘材料。
进一步的，在其他实施方式中，其中在所述S6步骤之前，还包括S100:使用氢气、氮气、氨气或氩气中的任意一种或两种以上的气体对所述第一栅极绝缘层进行处理。通过S100步骤，保证所述第一栅极绝缘层和所述第二栅极绝缘层之间不会出现断层现象，保证像素区域的光学特性不会恶化。
进一步的，在其他实施方式中，其中在步骤S7之后还包括S8：形成源漏极层于所述有源层上；S9：形成平坦层于所述源漏极层上；S10：形成像素电极层于所述平坦层上。
 有益效果
相对于现有技术，本发明的有益效果在于：本发明提供一种阵列基板及其制备方法，栅极绝缘层分成两个步骤制备，能够降低现有技术中一步制备带来的台阶覆盖性较差的风险，其中第二栅极绝缘层的厚度与阵列基板的电学特性相关，通过控制第一栅极绝缘层和第二栅极绝缘层的厚度比例，能够确保阵列基板开态电流不会降低，降低面板充电率不足的风险。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例1提供的阵列基板的结构示意图；
图2为本发明实施例1提供的阵列基板的制备方法的流程图；
图3为本发明实施例1提供的制备方法中步骤S1时阵列基板的结构示意图；
图4为本发明实施例1提供的制备方法中步骤S2时阵列基板的结构示意图；
图5为本发明实施例1提供的制备方法中步骤S3时的结构示意图；
图6为本发明实施例1提供的制备方法中步骤S4时阵列基板的结构示意图；
图7为本发明实施例1提供的制备方法中步骤S5时阵列基板的结构示意图；
图8为本发明实施例1提供的制备方法中步骤S6时阵列基板的结构示意图；
图9为本发明实施例1提供的制备方法中步骤S7时阵列基板的结构示意图；
图10为本发明实施例1提供的制备方法中步骤S8时阵列基板的结构示意图；
图11为本发明实施例1提供的制备方法中步骤S9时阵列基板的结构示意图；
图12为本发明实施例1提供的制备方法中步骤S10时阵列基板的结构示意图。
附图标记：
阵列基板-200；
衬底基板-10；
第一栅极绝缘膜-211；第一栅极绝缘层-21；凹槽-11；
栅极膜-31；栅极层-30；
第二栅极绝缘层-22；
有源层-40；
源漏极-50；
平坦层-60；
像素电极层-70。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本发明的示例性实施例的目的。但是本发明可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
如图1所示，在本发明一实施例中，本发明的阵列基板200包括衬底基板10、第一栅极绝缘材21、栅极层30、第二栅极绝缘层22、有源层40。具体地讲，第一栅极绝缘层21设于衬底基板10上，第一栅极绝缘层21中具有凹槽11，栅极层30设于第一栅极绝缘层21的凹槽11中，第二栅极绝缘层22覆于第一栅极绝缘层21和栅极层30上，有源层40设于第二栅极绝缘层22上。
其中衬底基板10的材料采用聚醯亚胺（PI），即聚酰亚胺薄膜，作为阵列基板的基底；所述聚酰亚胺薄膜是世界上性能较好的薄膜类绝缘材料，具有较强的拉伸强度，由均苯四甲酸二酐和二氨基二苯醚在强极性溶剂中经缩聚并流延成膜再经亚胺化而成。
栅极层30采用的材料为铜金属，栅极层30的厚度范围为200nm～5000nm。
第一栅极绝缘层21和第二栅极绝缘层22的材料采用氧化氮或氧化硅或氮化硅中的任意一种或两种以上，第一栅极绝缘层21的厚度范围为100nm～500nm，第二栅极绝缘层22的厚度范围为100nm～500nm。
有源层40的材料采用氧化锌、氧化铟锌、氧化铟锌镓中的任意一种或两种以上，有源层40的厚度范围为100nm～200nm。
有源层40上还设有源漏极层50，源漏极层50上设有平坦层60，平坦层60上设有像素定义层70。
其中源漏极层50采用的材料为铝或钼或两者的结合，源漏极层50的厚度范围为20nm～600nm，平坦层60的材料采用氧化硅或氮化硅，平坦层60的厚度为150nm～400nm，像素电极层70的材料采用氧化铟锡，像素电极层70的厚度为30nm～100nm。
为了更清楚的解释本发明的设计要点，本实施例还提供了一种制备方法，以制备本发明的阵列基板。
请参阅图2，图2所示为本实施例提供的阵列基板的制备方法的流程图，包括步骤S1-步骤S10。
请参阅图3，图3所示为本实施例提供的制备方法中步骤S1时阵列基板的结构示意图；步骤S1：提供一衬底基板10。
请参阅图4，图4所示为本实施例提供阵列基板的的制备方法中步骤S2时阵列基板的结构示意图；步骤S2：沉积栅极绝缘材料于衬底基板10上形成第一栅极绝缘膜211。
其中沉积第一栅极绝缘材料是采用等离子体增强化学的气相沉积法。
请参阅图5，图5所示为本实施例提供阵列基板的的制备方法中步骤S3时阵列基板的结构示意图；步骤S3；图案化第一栅极绝缘膜211形成第一栅极绝缘层21，述第一栅极绝缘层21中具有相应的凹槽11。
其中第一栅极绝缘层21的材料采用氧化氮或氧化硅或氮化硅中的任意一种或两种以上，第一栅极绝缘层21的厚度范围为100nm～500nm。
请参阅图6，图6所示为本实施例提供阵列基板的的制备方法中步骤S4时阵列基板的结构示意图；步骤S4：沉积栅极材料于第一栅极绝缘层21上以及凹槽中形成栅极膜31。
请参阅图7，图7所示为本实施例提供阵列基板的的制备方法中步骤S5时阵列基板的结构示意图；步骤S5：湿蚀刻栅极膜31，去除第一栅极绝缘层21上的栅极膜31并在凹槽中形成栅极层30；其中栅极层30采用的材料为铜金属，栅极层30的厚度范围为200nm～5000nm。
请参阅图8，图8所示为本实施例提供阵列基板的的制备方法中步骤S6时阵列基板的结构示意图；步骤S6：沉积栅极绝缘材料于第一栅极绝缘层21和栅极层30上形成第二栅极绝缘层22。
其中步骤S6之前还包括使用氢气、氮气、氨气或氩气中的任意一种或两种以上的气体进行对第一栅极绝缘层21表面处理，减少第一栅极绝缘层21和第二栅极绝缘层22之间的膜质差异，避免两层膜膜质差异过大，对绝缘层的电学特性、光学特性等膜质特性造成恶化，保证第一栅极绝缘层21和第二栅极绝缘层22之间不会出现断层现象，保证像素区域的光学特性不会恶化。
其中沉积第二栅极绝缘层22是采用等离子体增强化学的气相沉积法，第二栅极绝缘层22的材料采用氧化氮或氧化硅或氮化硅中的任意一种或两种以上，第二栅极绝缘层22的厚度范围为100nm～500nm。
其中栅极绝缘层分成两个步骤制备，能够降低现有技术中一步制备带来的台阶覆盖性较差的风险。
其中第二栅极绝缘层22的厚度与阵列基板的电学特性相关，通过控制第一栅极绝缘层21和第二栅极绝缘层22的厚度比例，能够确保阵列基板开态电流不会降低，降低面板充电率不足的风险。
请参阅图9，图9所示为本实施例提供阵列基板的的制备方法中步骤S7时阵列基板的结构示意图；步骤S7：形成有源层40于第二栅极绝缘层上22；有源层40的材料采用氧化锌、氧化铟锌、氧化铟锌镓中的任意一种或两种以上，有源层40的厚度范围为100nm～200nm。
请参阅图10，图10所示为本实施例提供阵列基板的的制备方法中步骤S8时阵列基板的结构示意图。步骤S8：形成源漏极层50于有源层40上；其中源漏极层50采用的材料为铝或钼或两者的结合，源漏极层50的厚度范围为20nm～600nm。
请参阅图11，图11所示为本实施例提供阵列基板的的制备方法中步骤S9阵列基板时的结构示意图；步骤S9：形成平坦层60于源漏极层50上；其中平坦层60的材料采用氧化硅或氮化硅，平坦层60的厚度为150nm～400nm。
请参阅图12，图12所示为本实施例提供阵列基板的的制备方法中步骤S10时阵列基板的结构示意图；步骤S10：形成像素电极层70于平坦层60上；其中像素电极层70的材料采用氧化铟锡，像素电极层70的厚度为30nm～100nm。
本发明的有益效果在于：本发明提供一种阵列基板及其制备方法，栅极绝缘层分成两个步骤制备，能够降低现有技术中一步制备带来的台阶覆盖性较差的风险，其中第二栅极绝缘层的厚度与阵列基板的电学特性相关，通过控制第一栅极绝缘层和第二栅极绝缘层的厚度比例，能够确保阵列基板开态电流不会降低，降低面板充电率不足的风险。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (15)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    第一栅极绝缘层，设于所述衬底基板上，所述第一栅极绝缘层中具有凹槽；
    栅极层，设于所述第一栅极绝缘层的所述凹槽中；
    第二栅极绝缘层，覆于所述第一栅极绝缘层和所述栅极层上；
    有源层，设于所述第二栅极绝缘层上。
  2. 根据权利要求1所述的阵列基板，其中，其还包括
    源漏极层，设于所述有源层上；
    平坦层，设于所述源漏极层上；
    像素定义层，设于所述平坦层上。
  3. 根据权利要求1所述的阵列基板，其中，所述栅极层采用的材料为铜金属，所述栅极层的厚度范围为200nm～5000nm。
  4. 根据权利要求1所述的阵列基板，其中，所述第一栅极绝缘层和所述第二栅极绝缘层的材料采用氧化氮或氧化硅或氮化硅中的任意一种或两种以上，所述第一栅极绝缘层的厚度范围为100nm～500nm，所述第二栅极绝缘层的厚度范围为100nm～500nm。
  5. 根据权利要求1所述的阵列基板，其中，所述有源层的材料采用氧化锌、氧化铟锌、氧化铟锌镓中的任意一种或两种以上，所述有源层的厚度范围为100nm～200nm。
  6. 根据权利要求2所述的阵列基板，其中，所述平坦层的材料采用氧化硅或氮化硅，所述平坦层的厚度为150nm～400nm，所述像素电极层的材料采用氧化铟锡，所述像素电极层的厚度为30nm～100nm。
  7. 一种制备如权利要求1所述阵列基板的方法，其中，包括以下步骤：
    S1：提供一衬底基板；
    S2：沉积栅极绝缘材料于所述衬底基板上形成第一栅极绝缘膜；
    S3： 图案化所述第一栅极绝缘膜形成第一栅极绝缘层，所述第一栅极绝缘层中具有相应的凹槽；
    S4：沉积栅极材料于所述第一栅极绝缘层以及所述凹槽中形成栅极膜；
    S5：湿蚀刻所述栅极膜，去除所述第一栅极绝缘层上的栅极膜并在所述凹槽中形成栅极层；
    S6：沉积栅极绝缘材料于所述第一栅极绝缘层和所述栅极层上形成第二栅极绝缘层；
    S7：形成有源层于所述第二栅极绝缘层上。
  8. 根据权利要求7所述的制备方法，其中，在所述步骤S2和步骤S6中，采用等离子体增强化学的气相沉积法沉积所述栅极绝缘材料。
  9. 根据权利要求7所述的制备方法，其中，在所述S6步骤之前，还包括S100:使用氢气、氮气、氨气或氩气中的任意一种或两种以上的气体对所述第一栅极绝缘层进行处理。
  10. 根据权利要求7所述的制备方法，其中，其还包括
    源漏极层，设于所述有源层上；
    平坦层，设于所述源漏极层上；
    像素定义层，设于所述平坦层上。
  11. 根据权利要求10所述的制备方法，其中，在步骤S7之后还包括
    S8：形成源漏极层于所述有源层上；
    S9：形成平坦层于所述源漏极层上；
    S10：形成像素电极层于所述平坦层上。
  12. 根据权利要求7所述的制备方法，其中，所述栅极层采用的材料为铜金属，所述栅极层的厚度范围为200nm～5000nm。
  13. 根据权利要求7所述的制备方法，其中，所述第一栅极绝缘层和所述第二栅极绝缘层的材料采用氧化氮或氧化硅或氮化硅中的任意一种或两种以上，所述第一栅极绝缘层的厚度范围为100nm～500nm，所述第二栅极绝缘层的厚度范围为100nm～500nm。
  14. 根据权利要求7所述的制备方法，其中，所述有源层的材料采用氧化锌、氧化铟锌、氧化铟锌镓中的任意一种或两种以上，所述有源层的厚度范围为100nm～200nm。
  15. 根据权利要求10所述的制备方法，其中，所述平坦层的材料采用氧化硅或氮化硅，所述平坦层的厚度为150nm～400nm，所述像素电极层的材料采用氧化铟锡，所述像素电极层的厚度为30nm～100nm。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646924A (zh) * 2013-12-04 2014-03-19 京东方科技集团股份有限公司 薄膜晶体管阵列基板及其制备方法、显示装置
CN104393019A (zh) * 2014-11-07 2015-03-04 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
US20150279690A1 (en) * 2012-03-22 2015-10-01 Samsung Display Co., Ltd. Trench forming method, metal wiring forming method, and method of manufacturing thin film transistor array panel
CN106449660A (zh) * 2016-11-11 2017-02-22 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101123211A (zh) * 2006-08-10 2008-02-13 中芯国际集成电路制造(上海)有限公司 双镶嵌结构的制造方法
CN100576496C (zh) * 2006-12-05 2009-12-30 中芯国际集成电路制造(上海)有限公司 双镶嵌结构的形成方法
KR101986245B1 (ko) * 2013-01-17 2019-09-30 삼성전자주식회사 수직형 반도체 소자의 제조 방법
JP6607013B2 (ja) * 2015-12-08 2019-11-20 株式会社リコー 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム
KR102611499B1 (ko) * 2015-12-15 2023-12-06 엘지디스플레이 주식회사 플렉서블 표시장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150279690A1 (en) * 2012-03-22 2015-10-01 Samsung Display Co., Ltd. Trench forming method, metal wiring forming method, and method of manufacturing thin film transistor array panel
CN103646924A (zh) * 2013-12-04 2014-03-19 京东方科技集团股份有限公司 薄膜晶体管阵列基板及其制备方法、显示装置
CN104393019A (zh) * 2014-11-07 2015-03-04 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN106449660A (zh) * 2016-11-11 2017-02-22 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置

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