WO2021073048A1 - 一种pcie设备的调试装置和方法 - Google Patents

一种pcie设备的调试装置和方法 Download PDF

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WO2021073048A1
WO2021073048A1 PCT/CN2020/082073 CN2020082073W WO2021073048A1 WO 2021073048 A1 WO2021073048 A1 WO 2021073048A1 CN 2020082073 W CN2020082073 W CN 2020082073W WO 2021073048 A1 WO2021073048 A1 WO 2021073048A1
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pcie
module
debugging
request
jtag
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PCT/CN2020/082073
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English (en)
French (fr)
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朱敏
吴汉明
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芯创智（北京）微电子有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • the invention belongs to the field of computer system structure, and specifically relates to a debugging device and method for PCIE equipment.
  • PCIE Peripheral Component Interconnect Express
  • PCIE Peripheral Component Interconnect Express
  • PCIE is a high-speed serial computer expansion bus standard designed to replace the old PCI, PCI-X and AGP bus standards.
  • PCIE is a high-speed serial point-to-point dual-channel high-bandwidth transmission.
  • the connected devices allocate exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging and quality of service ( QOS) and other functions.
  • the topology of a typical PCIE includes four functional types, Root Complex, Switch, Endpoints, and Bridge.
  • PCIE devices such as Root Complex, Switch, and Endpoints
  • PCIE protocol analyzers can only capture PCIE data packets and analyze data; they lack a controllable device that can accurately generate PCIE data packet stimuli and debug the underlying PCIE protocol.
  • PCIE protocol analyzers can only capture PCIE data packets and analyze data; they lack a controllable device that can accurately generate PCIE data packet stimuli and debug the underlying PCIE protocol.
  • controllable debugging methods In the process of designing and testing PCIE devices (special PCIE chips), there is a lack of controllable debugging methods.
  • the purpose of the present invention is to provide a PCIE device debugging device and method for debugging and testing the underlying protocol of the PCIE device. Through the communication module on the host side, it is possible to precisely control the generation of PCIE storage, IO, configuration and message packets, and to read the status information and data in the process of link training, testing, enumeration, and transaction sending and receiving.
  • the technical solution adopted by the present invention is a PCIE device debugging device, which includes: a host client, a JTAG host communication module, a protocol analysis module, an internal buffer and bus request generation module, and a PCIE protocol packet generation and transmission module, among them:
  • the host client is used to configure the number of PCIE ports and link width of the device to be tested, translate the PCIE debugging command script into a debugging sequence, and send it to the JTAG host communication module through the JTAG interface; at the same time collect the debugging results and print out;
  • the JTAG host communication module is used to receive JTAG requests issued by the host, and implement JTAG instructions and data extension registers;
  • the protocol analysis module is used to detect the JTAG read and write status of the instruction and data registers, analyze the debugging and test protocol, and convert the JTAG protocol into a test request command;
  • the internal buffer and bus request generation module includes a read and write request buffer and a receiving response data buffer, and a bus request generation module.
  • the read and write request buffer is used to store read and write requests from JTAG
  • the receive response data buffer is used to Store the data returned by the read request
  • the bus request generation module is used to convert the test request of the buffer into an on-chip bus request.
  • the PCIE protocol packet generating and sending module includes the following sub-modules: AMBA bus controller sub-module, several RC Ctrl Top sub-modules, several EP Ctrl Top sub-modules, and several GTX sub-modules.
  • AMBA bus controller sub-module provides interconnection channels between other sub-modules.
  • the GTX sub-module is a high-speed SerDes module that comes with the FPGA, which implements the physical layer function of PCIE, and the specific number thereof is determined according to the requirements of the number of PCIE ports of the device to be tested.
  • the RC Ctrl Top sub-module is a Root Complex controller conforming to the PCIE standard
  • the EP Ctrl Top sub-module is an Endpoint controller conforming to the PCIE standard.
  • the two share the AMBA bus communication interface, and the realized communication functions include: PCIE Storage transaction package sending and receiving, PCIE IO read and write transaction sending and receiving, communication status monitoring, message grouping and sending, interrupt event monitoring, link negotiation, data link layer packet formation and sending functions.
  • RC Ctrl Top sub-module and EP Ctrl Top sub-module include: RC Ctrl module, EP Ctrl module, on-chip RAM, APP module, CSR module, and BIU module, among which:
  • the APP module realizes that the debugging request is converted into a PCIE request
  • the CSR module realizes PCIE input control and output status
  • the BIU module is directly connected with the AMBA bus to realize data interaction with the internal buffer.
  • the PIPE-MUX data selector of the PCIE protocol packet generating and sending module realizes that the PCIE link width can be dynamically configured, and supports PCIE devices with various link widths of X32, X16, X8, X4, X2, X1.
  • a PCIE device debugging method includes the following steps:
  • the JTAG host communication module receives the request sequence and sends it to the protocol analysis module.
  • the protocol analysis module parses the request sequence and stores the parsed request sequence in the internal buffer.
  • the bus request generation module sends the buffer test request Converted to on-chip bus request;
  • the PCIE protocol packet generation and sending module receives the bus request sequence from the internal buffer and the bus request generation module, converts it into a PCIE protocol packet, and sends it to the PCIE device to be debugged; at the same time, it reads the debugging result information and stores it in the internal buffer to receive the response.
  • the data buffer module In the data buffer module;
  • the protocol analysis module reads the debugging result information from the internal buffer and the receiving response data buffer module of the bus request generation module;
  • the debugging script includes but not limited to PCIE configuration, MEM transaction, IO transaction, message transaction, DMA transaction, test result, etc.
  • the debugging result information read by the PCIE protocol packet generating and sending module includes, but is not limited to, data information in the process of link training, testing, enumeration, transaction sending and receiving, etc.
  • the JTAG host communication module can use the on-chip bus to uniformly schedule and control multiple PCIE RC and EP controllers, which can debug PCIE Root Complex and Endpoint devices, and Can debug PCIE Switch;
  • Figure 1 is a structural diagram of a PCIE equipment debugging device according to the present invention.
  • FIG. 2 is a structural diagram of the internal buffer and bus request generation module of the PCIE equipment debugging device according to the present invention
  • FIG. 3 is a structural diagram of the PCIE protocol packet generating and sending module of the PCIE equipment debugging device according to the present invention
  • FIG. 4 is a flowchart of a PCIE device debugging method according to the present invention.
  • FIG. 5 is a schematic diagram of the header format of the PCIE transaction layer protocol involved in the present invention.
  • a PCIE device debugging device includes the following devices: a host client (101), a JTAG host communication module (102), a protocol analysis module (103), an internal buffer and bus request generation module (104), PCIE protocol packet generation and sending module (105), where:
  • the host client (101) is used to configure the number of PCIE ports and link width of the device under test, translate the PCIE debugging command script into a debugging sequence, and send it to the JTAG host communication module (102) through the JTAG interface; at the same time collect the debugging results, and Printout
  • the JTAG host communication module (102) is used to receive JTAG requests issued by the host, and implement JTAG instructions and data extension registers;
  • the protocol analysis module (103) is used to detect the JTAG read and write status of instructions and data registers, analyze the debugging and test protocols, and convert the JTAG protocol into PCIE request commands;
  • the internal buffer and bus request generation module (104) includes read and write request buffer and receive response data buffer, and a bus request generation module.
  • the read and write request buffer is used to store read and write requests from JTAG
  • the receive response data buffer is used to store Read the data returned by the request
  • the bus request generation module is used to convert the test request to generate an on-chip bus request;
  • the PCIE protocol packet generating and sending module (105) generates protocol data packets according to the commands generated by the debugging script and sends them through the communication interface.
  • the internal buffer and bus request generation module (104) structure includes ReqCFifo (201), ReqDFifo (202), RspFifo (203) and AMBAMU interface request execution module (204), among which:
  • ReqC/DFifo module (201) command buffer that receives read and write requests from JTAG;
  • ReqDFifo module (202) Receive data buffer for reading and writing requests from JTAG;
  • RspFifo module (203) Receive the response data of the AMBA read request
  • AMBAMU interface request execution module (204) realizes the function of the AMBA Master controller. When it detects that there is a JTAG request in the buffer of the ReqCfifo module (201) and the ReqDFifo module (202), the request command is parsed according to the protocol format, Then it is converted into an AMBA request and sent; the data returned to the AMBA read request is saved in the buffer of the RspFifo module (203).
  • the PCIE protocol packet generation and transmission module (105) includes the following sub-modules: AMBA bus controller sub-module (301), several GTX sub-modules (302), several RC Ctrl Top sub-modules (303) , Several EP Ctrl Top sub-modules (304) and PIPE-MUX data selector (305), among them:
  • the AMBA bus controller sub-module (301) provides interconnection channels between the sub-modules;
  • the GTX sub-module (302) is a high-speed SerDes module that comes with FPGA, which realizes the physical layer function of PCIE.
  • the specific number is configured by the user through the host side according to the number of PCIE ports of the device under test;
  • the RC Ctrl Top sub-module (303) is a Root Complex controller that complies with the PCIE standard, including the RC Ctrl module, on-chip RAM, APP module, CSR module, and BIU module.
  • the EP Ctrl Top sub-module (304) is an Endpoint controller that complies with the PCIE standard, and includes the EP Ctrl module, on-chip RAM, APP module, CSR module, and BIU module.
  • the APP module realizes the conversion of debugging requests into PCIE requests
  • the CSR module realizes the PCIE input control and output status
  • the BIU module directly connects with the AMBA bus to realize data interaction with the internal buffer;
  • PIPE-MUX data selector (305) realizes that the PCIE link width can be dynamically configured, and supports PCIE devices with various link widths of X32, X16, X8, X4, X2, and X1;
  • PIPE-MUX (305) is responsible for the physical link The user selects the corresponding configuration on the host side according to the requirements of the link width configuration, and the device automatically loads the FPGA bitstream file of the corresponding link configuration; through the PIPE_MUX module, the PIPE interface signal of each PCIE controller is mapped To the GTX corresponding to each PCIE lane.
  • FPGA For example, if you need to configure to the X4 mode, first select the corresponding settings on the host side, and then the FPGA automatically selects and loads the bit stream file of the X4 configuration mode.
  • the logic mapping inside FPGA is that the pipe interface of X4 PCIE controller is connected with the pipe interface of X4GTX.
  • FPGA automatically selects and loads 4 bit stream files of X1 configuration mode.
  • the logic mapping inside FPGA is that the pipe interfaces of 4 X1PCIE controllers are connected with the pipe interfaces of 4 X1 GTX.
  • a PCIE device debugging method includes the following steps:
  • S401 Input the required number of PCIE ports and the link width of each PCIE port into the client according to the number of PCIE ports and the link width of the device to be tested, and load the corresponding FPGA bitstream file;
  • the JTAG host communication module receives the request sequence and sends it to the protocol analysis module.
  • the protocol analysis module parses the request sequence and stores the parsed request sequence in the internal buffer.
  • the bus request generation module stores the internal buffer The test request is converted to an on-chip bus request;
  • the PCIE protocol packet generation and sending module converts the bus request sequence received from the internal buffer and bus request generation module into a PCIE protocol packet and sends it to the PCIE device to be debugged; at the same time, reads the debugging result information and stores it in the internal buffer In the receiving response data buffer module;
  • the protocol analysis module reads the debugging result information from the receiving response data buffer module of the internal buffer
  • S406 Send to the host client software through the JTAG host communication module, and print out.
  • the debugging script includes but not limited to PCIE configuration, MEM transaction, IO transaction, message transaction, DMA transaction, test result, etc.
  • the debugging result information read by the PCIE protocol packet generating and sending module includes, but is not limited to, data information in the process of link training, testing, enumeration, transaction receiving and sending.
  • protocol package (TLP) of the PCIE protocol packet generation and transmission module can support the following four transaction types: PCIE configuration, Mem transaction, IO transaction, and message transaction, including two address formats: 32-bit and 64-bit.
  • the Fmt[1:0] field indicates the header length and whether the protocol packet contains data payload information, where: 00 indicates 3 double-word length headers, no data; 01 indicates 4 double-word length headers, no data; 10 means 3 double-word length headers with data; 11 means 4 double-word lengths with data;
  • the Type[4:0] field and the Fmt[1:0] field together specify the transaction type, header length, and whether there is a data payload.
  • the TC[2:0] bits indicate the transmission type, which means that the device core applies to the request.
  • the transmission category number of the protocol package and the completion protocol package, TC0 is the default category, and TC1-TC7 are used to request differentiated services for TLP;
  • Attr[1:0] represents the attribute, among which, the high bit is the loose sort bit, when the high bit is 1, the PCI-X-style loose sort is enabled, when the high bit is 0, the PCI-style strict sort is used; the low bit is the non-monitoring cache bit When the low bit is 1, it indicates that there is no processor cache coherency problem in this protocol package, and the system hardware is not required to monitor the processor cache. When the low bit is 0, PCI-style cache monitoring is required;
  • the AT bit indicates the address type, indicating whether the MEM read and write request has undergone address conversion
  • Length represents the data payload length of this TLP, in double words as the unit, the maximum length is 1024 double words;
  • the R bit represents a reserved field.

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Abstract

本发明涉及一种PCIE设备的调试装置和调试方法。现有的调试与测试装置，只能抓取PCIE数据包与分析数据，缺少可控的能够精确产生PCIE数据包激励的机制，无法对PCIE底层协议进行调试，缺乏在PCIE设备，特别是PCIE芯片，设计与测试过程中的可控调试手段。本发明所述的装置及方法可以对PCIE设备底层协议进行调试与测试，通过主机端的通信模块，可以精确控制产生PCIE存储、IO、配置与消息包，并可以读取链路训练、测试、枚举、事务收发过程中的状态信息与数据。采用本发明所述装置和方法可实现PCIE设备特别是底层协议的可控调试，提高调试准确性和效率。

Description

一种PCIE设备的调试装置和方法 技术领域
本发明属于计算机系统结构领域，具体涉及一种PCIE设备的调试装置和方法。
背景技术
PCIE(Peripheral Component Interconnect Express)是一种高速串行计算机扩展总线标准，旨在替代旧的PCI，PCI-X和AGP总线标准。PCIE属于高速串行点对点双通道高带宽传输，所连接的设备分配独享通道带宽，不共享总线带宽，主要支持主动电源管理，错误报告，端对端的可靠性传输，热插拔以及服务质量(QOS)等功能。典型PCIE的拓扑结构包括四个功能类型，根联合体(Root Complex)、交换器(Switch)、端点(Endpoints)和桥(bridge)。
对于Root Complex、Switch与Endpoints等PCIE设备，在调试与测试时，需要验证其功能是否能够协议要求。但是目前的调试与测试装置，比如PCIE协议分析仪，只能抓取PCIE数据包与分析数据；缺少一种可控的能够精确产生PCIE数据包激励，对PCIE底层协议进行调试的装置。在PCIE设备(特别PCIE芯片)设计与测试过程中，缺乏可控的调试手段。
发明内容
针对现有技术中所存在的问题，为了支持上述可控的调试与测试手段，需要设计一种可以精确控制产生PCIE数据包激励，且可以自动收集测试结果的装置。本发明的目的在于提供一种PCIE设备调试装置及方法，用以对PCIE设备底层协议进行调试与测试。通过主机端的通信模块，可以精确控制产生PCIE存储、IO、配置与消息包，并可以读取链路训练、测试、枚举、 事务收发过程中的状态信息与数据。
为达到以上目的，本发明采用的技术方案是一种PCIE设备调试装置，包括：主机客户端、JTAG主机通信模块、协议解析模块、内部缓冲与总线请求生成模块、PCIE协议包生成与发送模块，其中：
所述主机客户端用于配置待测试设备的PCIE端口数量与链路宽度，将PCIE调试命令脚本翻译成调试序列，通过JTAG接口送入JTAG主机通信模块；同时收集调试结果，并打印输出；
所述JTAG主机通信模块用于接收主机端下发的JTAG请求，并实现JTAG指令和数据扩展寄存器；
所述协议解析模块用于检测JTAG对指令和数据寄存器的读写状态，对调试与测试协议进行解析，将JTAG协议转换为测试请求命令；
所述内部缓冲与总线请求生成模块包括读写请求缓冲区与接收响应数据缓冲区，以及总线请求生成模块，读写请求缓冲区用于存放来自JTAG的读写请求，接收响应数据缓冲区用于存放读请求返回的数据，总线请求生成模块用于将缓冲区的测试请求转换为片内总线请求。
进一步，所述的PCIE协议包生成与发送模块包括以下子模块：AMBA总线控制器子模块、若干个RC Ctrl Top子模块、若干个EP Ctrl Top子模块、若干个GTX子模块。
进一步，所述AMBA总线控制器子模块为其他各子模块之间提供互联通道。
进一步，所述GTX子模块为FPGA自带的高速SerDes模块，实现PCIE的物理层功能，其具体个数根据待测试设备的PCIE端口数量的需求确定。
进一步，所述RC Ctrl Top子模块是符合PCIE标准的Root Complex控 制器，所述EP Ctrl Top子模块作为符合PCIE标准的Endpoint控制器，二者共享AMBA总线通信接口，实现的通信功能包括：PCIE存储事务包收发、PCIE IO读写事务收发、通信状态监测、消息组包与发送、中断事件监测、链路协商、数据链路层包形成与发送功能。
进一步，所述RC Ctrl Top子模块和EP Ctrl Top子模块包括：RC Ctrl模块、EP Ctrl模块、片上RAM、APP模块、CSR模块、BIU模块，其中：
所述APP模块实现将调试请求转化成PCIE请求；
所述CSR模块实现PCIE输入控制与输出状态；
所述BIU模块直接与AMBA总线相接，实现与内部缓冲区数据交互。
进一步，所述的PCIE协议包生成与发送模块的PIPE-MUX数据选择器实现PCIE链路宽度可动态配置，同时支持X32、X16、X8、X4、X2、X1各种链路宽度的PCIE设备。
一种PCIE设备调试方法，包括以下步骤：
根据待测试设备的PCIE端口数量与链路宽度，将所需要的PCIE端口的个数，以及每个PCIE端口的链路宽度输入客户端，加载相应的FPGA位流文件；
将编写好的调试脚本输入主机客户端，主机客户端软件翻译成调试请求序列；
JTAG主机通信模块接收请求序列，并送至协议解析模块，再由协议解析模块对请求序列进行解析，并将解析后的请求序列存放入内部缓冲区，由总线请求生成模块将缓冲区的测试请求转换为片内总线请求；
PCIE协议包生成与发送模块从内部缓冲与总线请求生成模块收到总线请求序列，转换成PCIE协议包，发送给待调试的PCIE设备；同时，读取调试结果信息存入内部缓冲区的接收响应数据缓冲模块中；
协议解析模块从内部缓冲与总线请求生成模块的接收响应数据缓冲模块中读取调试结果信息；
通过JTAG主机通信模块发送到主机客户端端软件，并打印输出。
进一步，所述的调试脚本包括但不限于PCIE配置、MEM事务、IO事务、消息事务、DMA事务、测试结果等。
进一步，所述的PCIE协议包生成与发送模块读取的调试结果信息包括但不限于链路训练、测试、枚举、事务收发等过程中数据信息。
本发明的效果在于：
(1)通过为每个PCIE控制器分配规定的地址空间，JTAG主机通信模块可以利用片内总线统一调度、控制多个PCIE RC与EP控制器，这样既可以调试PCIE Root Complex与Endpoint设备，又可以调试PCIE Switch；
(2)采用PIPE-MUX实现PCIE链路宽度可动态配置，同时支持X32、X16、X8、X4、X2、X1各种链路宽度的PCIE设备；
(3)调试方法：采用导入编写好的调试与测试脚本以精确控制PCIE包的产生，同时方便读取内部寄存器与RAM中的数据以观察调试结果。
附图说明
图1是本发明所述一种PCIE设备调试装置结构图；
图2是本发明所述一种PCIE设备调试装置内部缓冲与总线请求生成模块结构图；
图3是本发明所述一种PCIE设备调试装置PCIE协议包生成与发送模块结构图；
图4是本发明所述一种PCIE设备调试方法流程图；
图5是本发明所涉及到PCIE事务层协议头格式示意图。
具体实施方式
下面结合附图和具体实施方式对本发明作进一步描述。
如图1所示，一种PCIE设备调试装置，包括以下装置：主机客户端(101)、JTAG主机通信模块(102)、协议解析模块(103)、内部缓冲与总线请求生成模块(104)、PCIE协议包生成与发送模块(105)，其中：
主机客户端(101)用于配置待测试设备的PCIE端口数量与链路宽度，将PCIE调试命令脚本翻译成调试序列，通过JTAG接口送入JTAG主机通信模块(102)；同时收集调试结果，并打印输出；
JTAG主机通信模块(102)用于接收主机端下发的JTAG请求，并实现JTAG指令和数据扩展寄存器；
协议解析模块(103)用于检测JTAG对指令和数据寄存器的读写状态，对调试与测试协议进行解析，将JTAG协议转换为PCIE的请求命令；
内部缓冲与总线请求生成模块(104)包括读写请求缓冲与接收响应数据缓冲，以及总线请求生成模块，读写请求缓冲区用于存放来自JTAG的读写请求，接收响应数据缓冲区用于存放读请求返回的数据，总线请求生成模块用于将测试请求转换生成片内总线请求；
PCIE协议包生成与发送模块(105)根据调试脚本生成的命令生成协议数据包并通过通信接口进行发送。
如图2所示，内部缓冲与总线请求生成模块(104)结构包括ReqCFifo(201)、ReqDFifo(202)、RspFifo(203)与AMBAMU接口请求执行模块(204)，其中：
ReqC/DFifo模块(201)：接收来自JTAG的读写请求的命令缓冲；
ReqDFifo模块(202)：接收来自JTAG的读写请求的数据缓冲；
RspFifo模块(203)：接收AMBA读请求的响应数据；
AMBAMU接口请求执行模块(204)：实现AMBA Master控制器的功能，当检测到ReqCfifo模块(201)与ReqDFifo模块(202)的缓冲中有JTAG请求时，则根据协议格式，对请求命令进行解析，然后转换成AMBA请求发出；返回AMBA读请求的数据，保存至RspFifo模块(203)的缓冲中。
如图3所示，PCIE协议包生成与发送模块(105)包括以下子模块：AMBA总线控制器子模块(301)、若干个GTX子模块(302)、若干个RC Ctrl Top子模块(303)、若干个EP Ctrl Top子模块(304)和PIPE-MUX数据选择器(305)，其中：
AMBA总线控制器子模块(301)为各子模块之间提供互联通道；
GTX子模块(302)为FPGA自带的高速SerDes模块，实现PCIE的物理层功能，其具体个数由使用者通过主机端根据待测试设备的PCIE端口的数量来配置；
RC Ctrl Top子模块(303)和EP Ctrl Top子模块(304)共享AMBA总线通信接口，实现的通信功能包括：PCIE存储事务包收发、PCIE IO读写事务收发、通信状态监测、消息组包与发送、中断事件监测、链路协商、数据链路层包形成与发送功能，其中：
RC Ctrl Top子模块(303)是符合PCIE标准的Root Complex控制器，包括RC Ctrl模块、片上RAM、APP模块、CSR模块、BIU模块。EP Ctrl Top子模块(304)作为符合PCIE标准的Endpoint控制器，包括EP Ctrl模块、片上RAM、APP模块、CSR模块、BIU模块。其中，APP模块实现将调试请求转化成PCIE请求；CSR模块实现PCIE输入控制与输出状态；BIU模块直接与AMBA总线相接，实现与内部缓冲区的数据交互；
PIPE-MUX数据选择器(305)实现PCIE链路宽度可动态配置，同时支持X32、X16、X8、X4、X2、X1各种链路宽度的PCIE设备；PIPE-MUX(305)负责物理链路的选择，使用者根据链路宽度配置的需求，在主机端选择对应的配置，则本装置自动加载对应链路配置的FPGA位流文件；通过PIPE_MUX模块，将各个PCIE控制器的PIPE接口信号映射到各个PCIE lane对应的GTX上。
举例说明，如果需要配置成X4模式，则首先在主机端选择对应的设置，然后FPGA自动选择加载X4配置方式的位流文件。FPGA内部的逻辑映射为，X4的PCIE控制器的pipe接口与X4GTX的pipe接口对接。
如果需要配置成4个X1模式，则首先在主机端选择对应的设置，然后FPGA自动选择加载4个X1配置方式的位流文件。FPGA内部的逻辑映射为，4个X1PCIE控制器的pipe接口与4个X1的GTX的pipe接口对接。
如图4所示，一种PCIE设备调试方法包括以下步骤：
S401：根据待测试设备的PCIE端口数量与链路宽度，将所需要的PCIE端口的个数，以及每个PCIE端口的链路宽度输入客户端，加载相应的FPGA位流文件；
S402：将编写好的调试脚本输入主机客户端，主机客户端软件翻译成调试请求序列；
S403：JTAG主机通信模块接收请求序列，并送至协议解析模块，再由协议解析模块对请求序列进行解析，并将解析后的请求序列存放入内部缓冲区，由总线请求生成模块将内部缓冲区的测试请求转换为片内总线请求；
S404：PCIE协议包生成与发送模块从内部缓冲与总线请求生成模块接收到的总线请求序列，转换成PCIE协议包，发送给待调试的PCIE设备；同时，读取调试结果信息存入内部缓冲区的接收响应数据缓冲模块中；
S405：协议解析模块从内部缓冲区的接收响应数据缓冲模块中读取调试结果信息；
S406：通过JTAG主机通信模块发送到主机客户端端软件，并打印输出。
进一步，调试脚本包括但不限于PCIE配置、MEM事务，IO事务，消息事务，DMA事务，测试结果等。
进一步，PCIE协议包生成与发送模块读取的调试结果信息包括但不限于链路训练、测试、枚举、事务收发等过程中数据信息。
进一步，PCIE协议包生成与发送模块的协议包(TLP)，可支持如下四 种事务类型：PCIE配置、Mem事务、IO事务和消息事务，包括两种地址格式：32位和64位。
优选地，PCIE协议包协议头格式的相同部分如图5所示，其中：
Fmt[1:0]字段表示头标长度和该协议包是否含有数据载荷的信息,其中：00表示3个双字长度头标，无数据；01表示4个双字长度头标，无数据；10表示3个双字长度头标，有数据；11表示4个双字长度，有数据；
Type[4:0]字段与Fmt[1:0]字段一起来规定事务类型、头标长度和是否有数据载荷，其中，TC[2:0]位表示传输类别，是指设备核施加于请求协议包及完成协议包的传输类别编号，TC0是默认的类别，TC1-TC7用来要求对TLP提供有区别的服务；
TD位表示事务汇总存在位，TD＝1表示本协议包含有Digest字段，值为ECRC；
EP位表示错误和中毒位，EP＝1时表示包中数据视为无效；
Attr[1:0]表示属性，其中，高位为宽松排序位，高位为1时则使能PCI-X式的宽松排序，高位为0时则使用PCI式的严格排序；低位为不监听缓存位，低位为1时表明本协议包不存在处理器缓存一致性问题，不要求系统硬件去监听处理器缓存，低位为0时要求PCI式缓存监听；
AT位表示地址类型，表示MEM读写请求是否进行了地址转换；
Length表示本TLP的数据载荷长度，以双字为单位，最大长度为1024双字；
R位表示保留字段。
本领域技术人员应该明白，本发明所述的方法和系统并不限于具体实施方式中所述的实施例，上面的具体描述只是为了解释本发明的目的，并非用于限制本发明。本领域技术人员根据本发明的技术方案得出其他的实施方式，同样属于本发明的技术创新范围，本发明的保护范围由权利要求及其等 同物限定。

Claims (10)

  1. 一种PCIE设备的调试装置，其特征是，包括：主机客户端、JTAG主机通信模块、协议解析模块、内部缓冲与总线请求生成模块、PCIE协议包生成与发送模块，其中：
    所述主机客户端用于根据使用者的需要配置具体的PCIE链路宽度；将PCIE调试命令脚本翻译成调试序列，通过JTAG接口送入JTAG主机通信模块；同时收集调试结果，并打印输出；
    所述JTAG主机通信模块用于接收主机端下发的JTAG请求，并实现JTAG指令和数据扩展寄存器；
    所述协议解析模块用于检测JTAG对指令和数据寄存器的读写状态，对调试与测试协议进行解析，将JTAG协议转换为测试请求命令；
    所述内部缓冲与总线请求生成模块包括读写请求缓冲区与接收响应数据缓冲区，以及总线请求生成模块，读写请求缓冲区用于存放来自JTAG的读写请求，接收响应数据缓冲区用于存放读请求返回的数据，总线请求生成模块用于将测试请求转换生成片内总线请求。
  2. 如权利要求1所述的一种PCIE设备的调试装置，其特征是，所述的PCIE协议包生成与发送模块包括：AMBA总线控制器子模块、若干个RC Ctrl Top子模块、若干个EP Ctrl Top子模块、若干个GTX子模块。
  3. 如权利要求2所述的一种PCIE设备的调试装置，其特征是，所述AMBA总线控制器子模块为其他各子模块之间提供互联通道。
  4. 如权利要求2述的一种PCIE设备的调试装置，其特征是，所述GTX子模块为FPGA自带的高速SerDes模块，实现PCIE的物理层功能，其具体个数根据待测试设备的PCIE端口数量的需求确定。
  5. 如权利要求2所述的一种PCIE设备调试装置，其特征是，所述RC Ctrl Top子模块是符合PCIE标准的Root Complex控制器，所述EP Ctrl Top子模块作为符合PCIE标准的Endpoint控制器，二者共享AMBA总线通信接口，实现的通信功能包括：PCIE存储事务包收发、PCIE IO读写事务收发、通信状态监测、消息组包与发送、中断事件监测、链路协商、数据链路层包形成 与发送功能。
  6. 如权利要求5所述的一种PCIE设备的调试装置，其特征是，所述RC Ctrl Top子模块和EP Ctrl Top子模块包括：RC Ctrl模块、EP Ctrl模块、片上RAM、APP模块、CSR模块、BIU模块，其中：
    所述APP模块实现将调试请求转化成PCIE请求；
    所述CSR模块实现PCIE输入控制与输出状态；
    所述BIU模块直接与AMBA总线相接，实现与内部缓冲区数据交互。
  7. 如权利要求5-6任一项所述的一种PCIE设备的调试装置，其特征是，所述的PCIE协议包生成与发送模块中的PIPE-MUX数据选择器实现PCIE链路宽度可动态配置，同时支持X32、X16、X8、X4、X2、X1各种链路宽度的PCIE设备。
  8. 一种PCIE设备的调试方法，包括以下步骤：
    根据待测试设备的PCIE端口数量与链路宽度，将所需要的PCIE端口的个数，以及每个PCIE端口的链路宽度输入客户端，加载相应的FPGA位流文件；
    将编写好的调试脚本输入主机客户端，主机客户端软件翻译成调试请求序列；
    JTAG主机通信模块接收请求序列，并送至协议解析模块，再由协议解析模块对请求序列进行解析，并将解析后的请求序列存放入内部缓冲区；
    PCIE协议包生成与发送模块从内部缓冲与总线请求生成模块接收到请求序列，转换成PCIE协议包，发送给待调试的PCIE设备；同时，读取调试结果信息存入内部缓冲区的接收响应数据缓冲模块中；
    协议解析模块从内部缓冲区的接收响应数据缓冲模块中读取调试结果信息；
    通过JTAG主机通信模块发送到主机客户端端软件，并打印输出。
  9. 如权利要求8所述的一种PCIE设备的调试方法，其特征是所述的调 试脚本包括但不限于PCIE配置、MEM事务、IO事务、消息事务、DMA事务、测试结果。
  10. 如权利要求8或9所述的一种PCIE设备的调试方法，其特征是所述的PCIE协议包生成与发送模块读取的调试结果信息包括但不限于链路训练、测试、枚举、事务收发等过程数据信息。
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