WO2021068374A1 - 控制系统、交换机以及对执行装置进行控制的方法 - Google Patents

控制系统、交换机以及对执行装置进行控制的方法 Download PDF

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WO2021068374A1
WO2021068374A1 PCT/CN2019/121098 CN2019121098W WO2021068374A1 WO 2021068374 A1 WO2021068374 A1 WO 2021068374A1 CN 2019121098 W CN2019121098 W CN 2019121098W WO 2021068374 A1 WO2021068374 A1 WO 2021068374A1
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Prior art keywords
control
address
module
execution device
control system
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PCT/CN2019/121098
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English (en)
French (fr)
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郑冠儒
姜开永
薛广营
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苏州浪潮智能科技有限公司
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Priority to US17/760,838 priority Critical patent/US11650950B2/en
Publication of WO2021068374A1 publication Critical patent/WO2021068374A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
    • H04L67/125—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks involving control of end-device applications over a network
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24215—Scada supervisory control and data acquisition
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • This application relates to control technology, in particular to control systems, switches, and methods for controlling execution devices.
  • each port of the switch generally has at least 3 to 4 low-speed control signals, so there are at least 200 control signals for the optical module on a single backplane.
  • the existing method of controlling the operation of the switch is that the processor sends instructions to the FPGA (Field-Programmable Gate Array) through the PCIe (Peripheral Component Interconnect express) bus, and the FPGA directly controls the optical module. For each port, this method occupies a lot of FPGA pins, and the leads occupy a lot of space on the board.
  • Another way to control the operation of the switch is that the processor sends instructions to the control module through the PCIe bus.
  • the control module connects multiple IO expansion modules through the I2C bus, and each IO expansion module controls an optical module. This method has complex control logic. It is necessary to integrate a driver specially developed for the hardware architecture of the IO expansion module, which is difficult to develop and low in efficiency, and is prone to abnormalities.
  • the present application provides an optical module control system, its implementation method and implementation device, and a switch. It can reduce the number of pins of the control module occupied, and does not require a specially developed driver, the control logic is simple and the operation is stable.
  • an embodiment of the present application provides a control system for controlling an execution device, characterized in that the control system includes a processor, a control module, and an address resolution module; wherein,
  • the processor is connected to the control module through the peripheral component interconnection high-speed PCIe bus, the control module is connected to one or more address resolution modules through the address bus, and each address resolution module is set to be connected to an execution device; among them,
  • the processor is pre-configured with address information of the port to be controlled on each execution device, and the address information is used to enable the processor to address the corresponding address resolution module through the control module.
  • the processor is configured to send a control instruction to the control module; where the control instruction includes address information and control action information of the port to be controlled of the execution device;
  • the control module is used to address the corresponding address resolution module according to the address information of the port to be controlled of the execution device contained in the control instruction;
  • the address resolution module is used to send a control signal to the port to be controlled of the corresponding execution device according to the control action information in the control instruction.
  • the address resolution module includes an address resolver and a flip-flop with a latch function, the address resolver is connected to the flip-flop in a one-to-one correspondence, and the flip-flop is set to be connected to an execution device, wherein,
  • the address resolver is used to determine that the address information in the control instruction matches the address of the execution device connected to the trigger, and send control action information to the corresponding trigger;
  • the trigger is used to execute the control action for the corresponding execution device according to the control action information.
  • control module is a complex programmable logic device CPLD, a micro-control unit MCU or a field programmable logic gate array FPGA.
  • the address resolution module is packaged with the corresponding execution device.
  • control system includes multiple address resolution modules, and the address bus between the multiple address resolution modules and the control module adopts a daisy chain topology structure.
  • multiple address resolvers are encapsulated into one data selector, and the data selector is used to parse address information.
  • the address resolver is a data selector, and the output end of the address resolver is connected to a plurality of flip-flops.
  • the execution device is an optical module or a hard disk.
  • an embodiment of the present application provides a switch, which includes the control system and an execution device in any one of the foregoing embodiments of the claims; wherein the execution device is an optical module.
  • an embodiment of the present application provides a method for controlling an execution device.
  • the method is executed by a control system.
  • the control system includes a processor, a control module, and an address resolution module.
  • the method includes:
  • the processor sends a control instruction to the control module; where the control instruction includes address information and control action information of the port to be controlled of the execution device;
  • the control module addresses the corresponding address resolution module according to the address information of the port to be controlled of the execution device contained in the control instruction;
  • the address analysis module sends a control signal to the port to be controlled of the corresponding execution device according to the control action information in the control instruction.
  • the beneficial effect of the embodiments of the present application is that the control system provided by the embodiments of the present application uses an address bus to connect the control module and the address resolution module, which can reduce the use of pins of the control module, so that a control module with fewer pins can be selected, which reduces
  • the size of the control module is small, thereby reducing the footprint of the backplane, enriching the selection range of the control module, and reducing the cost of the control module; and the use of a bus to connect each address resolution module can enable the location of the address resolution module on the switch backplane and
  • the wiring is more flexible, so overall the size of the switch backplane is reduced, and even the number of layers of the switch backplane is reduced, thereby reducing the manufacturing cost;
  • the control module uses the index address allocated for the port to be controlled of the execution device to address the execution device There is no need to specifically develop
  • FIG. 1 is a block diagram of an optical module control system provided by an embodiment of the application
  • Fig. 2 is a flowchart of an implementation method of an optical module control system provided by an embodiment of the application.
  • an embodiment of the present application provides a control system for controlling an execution device.
  • the control system includes a processor 100, a control module 200, and an address resolution module 300, as shown in FIG.
  • the execution device 400 connected to the address resolution module 300 is also shown in.
  • the processor 100 is connected to the control module 200 through a PCIe bus, the control module 200 is connected to one or more address resolution modules 300 through an address bus, and each address resolution module 300 is connected to the execution device 400 through a wire;
  • the processor 100 is pre-configured with address information of the port to be controlled on each execution device 400, and the address information is used to enable the processor 100 to address the corresponding address resolution module 300 through the control module.
  • FPGA Field-Programmable Gate Array
  • IO Input/Output, input/output
  • FPGA Field-Programmable Gate Array
  • the processor sends instructions to the FPGA through the PCIe (Peripheral Component Interconnect express) bus, and the FPGA directly controls the ports of the optical module after parsing the instructions.
  • PCIe Peripheral Component Interconnect express
  • the disadvantage is that the leads of all actuators need to occupy a pin of the FPGA, so the leads occupy a large amount of board space, which is a great waste of both FPGA resources and board space.
  • all the control signals of the execution device are connected to their respective IO expansion modules, and then all the IO expansion modules are connected to the control module through the I2C bus.
  • the processor will issue instructions to the control module through the PCIe bus, and then the control module will parse the instructions and then convert them into I2C instructions and issue them to the corresponding IO expansion module, thereby achieving control of the execution device.
  • the advantage is that by increasing the IO expansion module, the requirement for the number of pins of the control module is reduced, and the IO expansion module can be placed nearby, and the control signal of the actuator does not need to span far to lead, saving a lot of board Space.
  • the disadvantage is that the control logic is complex, and the driver program specially developed for the hardware architecture of the IO expansion module needs to be integrated, so the development is difficult and inefficient, and abnormalities are prone to occur.
  • the control module 200 is connected to one or more address resolution modules 300 through an address bus, and the control module 200 can use a small number of pins to connect to the address bus. , It can control a larger number of address resolution modules 300, so compared with the FPGA-based architecture, when a larger number of address resolution modules 300 need to be controlled, a smaller number of pins of the control module 200 can be occupied.
  • pre-configured address information of the port to be controlled is used to address the address resolution module 300, thereby controlling the execution device 400 corresponding to the addressed address resolution module 300.
  • the implementation in this application In the technical solution provided in the example, there is no need to develop a special driver for the hardware architecture of the control system. Therefore, when constructing the control system and controlling the execution device, the solution of addressing the address resolution module 300 with the pre-set port address information It is universally applicable to various collocations of the control system and the execution device 400, so it can reduce the workload of developing the driver program, and the efficiency of creating the control system and running the control system and the execution device is high; in addition, because the solution is generally applicable to the control system and Various collocations of the device 400 are executed, so the driver program of the control system is stable and not prone to failure.
  • the processor 100 is configured to send a control instruction to the control module; where the control instruction includes address information and control action information of the port to be controlled of the execution device;
  • the control module 200 is configured to address the corresponding address resolution module according to the address information of the port to be controlled of the execution device contained in the control instruction;
  • the address resolution module 300 is configured to send a control signal to the port to be controlled of the corresponding execution device according to the control action information in the control instruction.
  • the processor 100 sends control instructions to the control module 200 through the PCIe bus; the processor 100 is used to query the execution device to be controlled when controlling a certain port to be controlled of the execution device 400 After the pre-allocated address of the port, a control instruction is sent to the control module 200 to control a certain execution device (410, 420, etc.) in the control system.
  • the address allocated in advance for the port to be controlled of the execution device is stored in the memory of the control system, and the memory of the control system stores the index address allocated for the execution device when the port to be controlled of the execution device is initialized.
  • the memory accepts the access sent by the processor 100, and after inquiring the index address of the port to be controlled of the execution device, returns the index address of the inquired port to be controlled of the execution device to the processor 100.
  • the control module 200 After receiving the control instruction sent by the processor 100 through the PCIe bus, the control module 200 parses the control instruction from the address information and control action information of the port to be controlled of the execution device.
  • the address information refers to the index address of the execution device of the control system in the memory, and the control action information indicates that the trigger connected to the execution device 400 is triggered or de-triggered, so as to control the operation and stop of the execution device 400.
  • the address resolution module 300 is used to index the port of the execution device 400 corresponding to the address information according to the address information obtained from the control module 200 through the address bus, and execute the control action information obtained from the control module 200 through the address bus.
  • the control action of the execution device 400 corresponding to the address information is used to index the port of the execution device 400 corresponding to the address information according to the address information obtained from the control module 200 through the address bus, and execute the control action information obtained from the control module 200 through the address bus.
  • the index address queried in the memory is used to control the processor 100
  • the action information is indexed to the execution device 400 that needs to execute the control instruction.
  • the control module 200 is used to parse the address information and control action information from the control instructions from the processor 100, and then the resolved address information and control action information are transmitted to the address resolution module 300 through the address bus. According to the address information, the address resolution module 300 indexes the control action information to the execution device 400 that needs to execute the control instruction.
  • the control system provided by the embodiments of the present application adopts the address mapping method, it can index to the execution device 400 only by using the address bus.
  • the number of leads used is smaller. Therefore, the space occupied by the wiring and the number of pins occupied are reduced; therefore, when the same number of execution devices 400 are controlled, compared with the design based on the FPGA architecture, the control system in the control system provided by the embodiment of the application is The module 200 can use a smaller number of pins, the selection range of the control module 200 becomes larger, and a device with fewer pins can be used as the control module 200 in the control system provided by the embodiment of the present application, so the cost of the control module 200 It can be reduced accordingly; on the other hand, the control module 200 does not need to be an FPGA, but other types of control modules 200 can be used.
  • control modules 200 can take up less space than the FPGA, thus reducing the control module 200 on the backplane. The space occupied.
  • the use of a large number of devices that support the I2C communication protocol will bring logical complexity, because all the devices that support the I2C communication protocol are based on the I2C bus protocol, and the controller must Integrate different I2C bus protocols for different architectures (for example, under different architectures, if the addresses of devices that support the I2C communication protocol are different, then the code needs to be re-modified, which will bring development costs).
  • the hardware used in the solution provided by the embodiment of the application is decoupled from the logic of the loaded program, so the program developer does not need to follow the actual hardware architecture Then for development, you only need to start the software work according to the address table of the control pins on a set of hardware devices; and the hardware also adapts the hardware according to this address table, which greatly improves the development of the driver. effectiveness.
  • the control system provided by the embodiments of the present application does not need to use the IO expansion module. Therefore, when executing the control instructions, the IO expansion module does not need to occupy the space on the bottom plate.
  • the bottom plate can be made smaller in size, even making the printed circuit board used as the bottom plate.
  • the number of layers can be fewer, thus reducing the cost when manufacturing the backplane; and because the control system adopts the address mapping method, there is no need to integrate the driver of the IO expansion module and the driver of the expansion module to find the target execution device to perform the action, so the control Logically, it is easier to implement and more stable when executing control actions.
  • the control system provided by the embodiment of the application adopts both the control module 200 and the address resolution module 300 to realize the function of the FPGA; compared with the design based on the IO expansion module, the embodiment of the application provides In the control system, the control module 200 plus the address resolution module 300 are used to realize the functions of the control module and the IO expansion module. Among them, the control module 200 is only used for parsing control instructions. Therefore, the material selection range of the control module 200 is very large.
  • the control module 200 may be a CPLD (Complex Programmable Logic Device), an MCU (Microcontroller Unit, micro control unit), an FPGA, or other sizes.
  • the address resolution module 300 may use an address resolver and a flip-flop with a latch function.
  • the address resolver and the flip-flop are connected in a one-to-one correspondence to trigger
  • the device is set to be connected to an execution device; where the address resolver is used to determine the execution device (410, 420, etc.) indexed by the address information: the address information in the judgment control instruction is connected to the address of the execution device connected to the trigger
  • the control action information is sent to the corresponding trigger; the trigger is used to execute the control action of the execution device corresponding to the trigger according to the control action information.
  • the trigger may be a JK trigger or an RS trigger.
  • the trigger can be connected to the corresponding execution device through its output terminal.
  • the actions of the JK flip-flop include: hold state, reset state, set state, and state flip.
  • the JK flip-flop has only one output pin, which is connected to the input terminal of the actuator, and the input signal of the actuator is controlled by the level change on the output pin of the JK flip-flop.
  • the output signal of the JK flip-flop is in the form of pulses, and each pulse will change the output level once to switch between high level and low level.
  • the actions of the RS flip-flop include: hold state, reset state, and set state.
  • the size of the address resolution module 300 is very small, and the address resolution module 300 can even be packaged in a silicon-level package, so the size is much smaller than large-scale programmable control devices such as FPGA.
  • the control system uses an address bus to connect the control module 200 and the address resolution module 300, the address resolution module 300 can be flexibly arranged, The address resolution module 300 is arranged close to the execution device 400.
  • the address resolution module 300 and the corresponding execution device 400 may be packaged together, thereby further reducing the space occupied by the address resolution module 300 on the bottom board.
  • the address resolution module 300 is on the execution device 400.
  • the address resolution module 300 is on the backplane.
  • the address bus is used to connect the control module 200 and the address resolution module 300, it is not necessary to connect the control module and the execution device (or in the design based on the IO expansion module) like the existing technical solutions. In, it is to connect the control module, the IO expansion module and the execution device). First, all the leads are summarized at the control module, and then connected to the execution device across most of the backplane (or in the design based on the IO expansion module, summary at the control module All the leads connected to the IO expansion module are respectively drawn from the IO expansion module and connected to each actuator.
  • the address bus does not take up a lot of backplane space. For example, if there are 56 execution devices 400 in the control system, and each execution device 400 has 3 control signals, at this time, there are a total of 168 control signals. If a design based on FPGA architecture is adopted, at least 168 FPGAs are required. Pins, so the specification requirements for FPGAs are very high.
  • FPGAs are large in size and take up a lot of floor space due to wiring.
  • the control is completed, so the screening range of the control module 200 is very large, and the control module 200 that is as small in size and meets the needs of use can be screened out as much as possible.
  • a very compact control module 200 can be selected, and the routing of the address bus is very concise, so a smaller number of layers can be selected.
  • the printed circuit board serves as the bottom plate, which will reduce the cost of the printed circuit board. For example, a 14-layer printed circuit board has a cost reduction of 40% compared to a 16-layer printed circuit board.
  • the control system includes multiple address resolution modules (310, 320, etc.), and these multiple addresses
  • the address bus between the parsing module and the control module adopts a daisy chain topology structure, and these multiple address parsing modules are also connected accordingly.
  • the execution device corresponding to the address information is indexed through the daisy chain formed by the mutual connection of the address resolution modules.
  • the wiring on the printed circuit board connects the input interfaces of all address resolution modules in series. All address resolution modules are actually in a parallel relationship. When the control module sends address information, all address resolution modules are connected in parallel.
  • the modules basically receive the information at the same time. Which address resolution module can resolve the matched address, and then the address resolution module that matches the address sends a trigger signal. If the address resolved by the address resolution module is not a matched address, then the address The parsing module ignores the received address information and control action information. In the solution using the address resolver and the JK flip-flop, the address resolver with the matching address will trigger the JK flip-flop at the back end, and the JK flip-flop level will be reversed to complete the triggering/de-triggering of the controlled signal.
  • the address resolver may be a data selector, such as a 8-to-1 data selector with a model of Hitachi 74LS151; the output end of the address resolver may be connected to multiple flip-flops.
  • multiple address resolvers connected in a daisy chain can be taken as a whole, set in the style of a data selector and have the function of a data selector.
  • the processor 100 is selected as Intel’s Xeon D-1527 processor, which is connected to the control module through a set of PCIe bus; the control module 200 is selected as LFE5U- from lattice company For the 12F-6MG285C processor, the control module 200 is connected to the address resolver through a set of address buses.
  • the address resolver can be a data selector.
  • the data selector is selected as the Hitachi 74LS151 8 out of 1 data selector; For the application of 48 actuators, a total of 18 8-to-1 data selectors are required.
  • Each downstream port of the data selector is connected to a JK trigger. If the JK trigger is selected as Hitachi 74LS76, a total of 72 such models are required.
  • the data selector and JK flip-flop constitute the address resolution module 300, which is placed close to the execution device 400. A small package can be selected to save space; the addressing bus output from the control module 200 connects the address resolution module through a daisy chain stand up.
  • the execution device 400 is an optical module.
  • the execution device 400 sends instructions to the optical module through the DIS, RS0, and RS1 pins of the optical module to control the actions of the corresponding optical module.
  • the signal sent by the trigger to the optical module through the DIS pin of the corresponding optical module is responsible for controlling whether the corresponding optical module is working;
  • the signal introduced by the RS0 and RS1 pins is responsible for controlling the working mode of the optical module and is used to switch the optical module. rate.
  • the execution device 400 is a hard disk, a plurality of hard disks connected to the control system form a hard disk array, and the control system is used to control whether the hard disks in the hard disk array operate.
  • the embodiment of the present application provides a method for controlling an execution device.
  • the method is executed by a control system.
  • the control system includes a processor, a control module, and an address resolution module. As shown in FIG. 2, the method includes step S101-step S105.
  • Step S101 the processor sends a control instruction to the control module.
  • control instruction includes address information and control action information of the port to be controlled of the execution device.
  • step S103 the control module addresses the corresponding address resolution module according to the address information of the port to be controlled of the execution device contained in the control instruction.
  • Step S105 the address resolution module sends a control signal to the port to be controlled of the corresponding execution device according to the control action information in the control instruction.

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Abstract

一种控制系统、交换机以及对执行装置进行控制的方法。该控制系统包括处理器、控制模块、地址解析模块；处理器通过外围组件互连高速PCIe总线与所述控制模块连接，所述控制模块通过地址总线与一个或多个地址解析模块连接，每个地址解析模块被设置为与一个执行装置连接；其中，处理器上预先配置有每个执行装置上的待控制端口的地址信息，地址信息用于使所述处理器通过所述控制模块寻址相应的地址解析模块。该控制系统能减少所占用的控制模块的引脚的数量，并且无需专门开发的驱动程序，控制逻辑简单而且运行稳定。

Description

控制系统、交换机以及对执行装置进行控制的方法
本申请要求于2019年10月10日提交中国专利局、申请号为201910956928.X、名称为“控制系统、交换机以及对执行装置进行控制的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及控制技术，具体涉及控制系统、交换机以及对执行装置进行控制的方法。
背景技术
过去十年间，云数据中心获得了飞速的发展，从政府到企业，业务上云已达成共识。在此背景下，云数据中心对网络的质量有了越来越高的要求。这些要求主要体现在网络带宽和网络时延以及存储能力上。对于数据中心运营商来说，获得更大的网络带宽主要的手段就是增加交换机上的端口数量和带宽密度，也就是说，控制交换机中的更多光模块；提高存储能力的方式是增加存储服务器中的硬盘的数量。随着光模块或者硬盘的数量增加，在其中包括这些光模块或者硬盘的设施的底板的设计难度也随着增长。尤其是对于交换端口上的光模块控制信号，一般交换机每个端口都会有至少3到4个低速控制信号，因此单个底板上光模块的控制信号就至少有200个以上。
现有的控制交换机运行的方法是处理器通过PCIe(Peripheral Component Interconnect express，外围组件互连高速)总线给FPGA(Field-Programmable Gate Array，现场可编程门阵列)发指令，FPGA直接控制光模块的各个端口，此种方法占用FPGA引脚多，引线占用板上空间大。另一种控制交换机运行的方法是处理器会通过PCIe总线给控制模块发指令，控制模块通过I2C总线连接多个IO拓展模块，每个IO扩展模块控制一个光模块，此种方法控制逻辑复杂，需要集成为IO拓展模块的硬件架构专门开发的驱动程序，开发难度大并且效率低，容易出现异常。
发明内容
为了解决上述技术问题，本申请提供了一种光模块控制系统、其实现方法和实现装置以及交换机。其能够减少所占用的控制模块的引脚的数量，并且无需专门开发的驱动程序，控制逻辑简单而且运行稳定。
为了达到上述目的，本申请实施例提供了一种控制系统，用于对执行装置进行控制，其特征在于，控制系统包括处理器、控制模块和地址解析模块；其中，
处理器通过外围组件互连高速PCIe总线与控制模块连接，控制模块通过地址总线与一个或多个地址解析模块连接，每个地址解析模块被设置为与一个执行装置连接；其中，
处理器上预先配置有每个执行装置上的待控制端口的地址信息，地址信息用于使处理器通过控制模块寻址相应的地址解析模块。
在一个可选的实施例中，处理器用于向控制模块发送控制指令；其中，控制指令包含执行装置的待控制端口的地址信息和控制动作信息；
控制模块用于根据控制指令中所包含的执行装置的待控制端口的地址信息寻址到对应的地址解析模块；
地址解析模块用于根据控制指令中的控制动作信息向对应的执行装置的待控制端口发送控制信号。
在一个可选的实施例中，地址解析模块包括地址解析器和具有锁存功能的触发器，地址解析器与触发器一一对应连接，该触发器被设置成与一个执行装置连接，其中，
地址解析器用于判断控制指令中的地址信息与所述触发器连接的执行装置的地址相匹配时，向对应的触发器发送控制动作信息；
触发器用于根据控制动作信息执行对于对应的执行装置的控制动作。
在一个可选的实施例中，控制模块是复杂可编程逻辑器件CPLD、微控制单元MCU或者现场可编程逻辑门阵列FPGA。
在一个可选的实施例中，地址解析模块与对应的执行装置封装在一起。
在一个可选的实施例中，控制系统包括多个地址解析模块，多个地址 解析模块与控制模块之间的地址总线采用菊花链拓扑结构。
在一个可选的实施例中，多个地址解析器被封装成为一个数据选择器，数据选择器用于对地址信息进行解析。
在一个可选的实施例中，地址解析器是数据选择器，地址解析器的输出端连接于多个触发器。
在一个可选的实施例中，执行装置是光模块或者硬盘。
为了达到上述目的，本申请实施例提供了一种交换机，该交换机包括权利要求上述任一个实施例中的控制系统以及执行装置；其中，执行装置是光模块。
为了达到上述目的，本申请实施例提供了一种对执行装置进行控制的方法，该方法由控制系统执行，控制系统包括处理器、控制模块以及地址解析模块，该方法包括：
由处理器向控制模块发送控制指令；其中，控制指令包含执行装置的待控制端口的地址信息和控制动作信息；
由控制模块根据控制指令中所包含的执行装置的待控制端口的地址信息寻址到对应的地址解析模块；
由地址解析模块根据控制指令中的控制动作信息向对应的执行装置的待控制端口发送控制信号。本申请实施例的有益效果在于：本申请实施例提供的控制系统采用地址总线将控制模块和地址解析模块连接，能够减少控制模块的引脚使用，从而可以选用引脚较少的控制模块，减小控制模块的尺寸，进而减少底板空间的占用，丰富了控制模块的选型范围，降低控制模块的成本；并且采用总线连接各个地址解析模块，可以使地址解析模块在交换机底板上的选位以及布线更加灵活，因此总体上减小了交换机底板的尺寸，乃至减小交换机底板的层数，进而降低制造成本；控制模块采用为执行装置的待控制的端口分配的索引地址来寻址到执行装置的端口，无需因为硬件架构专门开发适配的驱动程序，普遍适用于控制系统与执行装置的各种搭配，所以控制系统的驱动程序逻辑简单可靠，运行稳定，不易出现故障。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从 说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本申请实施例提供的光模块控制系统的框图；
图2为本申请实施例提供的光模块控制系统的实现方法的流程图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
为了解决上述技术问题，本申请实施例提供了一种控制系统，用于对执行装置进行控制，如图1所示，该控制系统包括处理器100、控制模块200和地址解析模块300，图1中还显示了与地址解析模块300连接的执行装置400。
其中，处理器100通过PCIe总线连接到控制模块200，控制模块200通过地址总线连接于一个或多个地址解析模块300，每个地址解析模块300通过引线连接执行装置400；
处理器100上预先配置有每个执行装置400上的待控制端口的地址信息，地址信息用于使处理器100通过控制模块寻址相应的地址解析模块300。
为了控制执行装置执行动作，现有的方案通常使用以下两种架构：分 别是基于FPGA(Field-Programmable Gate Array，现场可编程门阵列)的架构以及基于IO(Input/Output，输入/输出)拓展模块的架构。对于基于FPGA架构的设计，处理器通过PCIe(Peripheral Component Interconnect express)总线给FPGA发指令，FPGA通过解析该指令后直接控制光模块的各个端口。其优点在于通过FPGA直接控制执行装置，在驱动程序方面实现起来比较方便，另外，由于执行装置是直连的，架构上也比较简单清晰。缺点是所有的执行装置的引线都需要占用FPGA的一个引脚，因此引线占用了大量的板上空间，无论是对FPGA本身资源还是对板上空间来说都是一种极大的浪费。对于基于IO拓展模块的架构，执行装置的所有控制信号都是连接到了各自的IO拓展模块上，然后所有的IO拓展模块通过I2C总线上连至控制模块，当控制系统需要控制执行装置的时候，处理器会通过PCIe总线给控制模块下发指令，然后控制模块解析指令之后会转成I2C指令下发到对应的IO拓展模块上，从而实现对执行装置的控制。其优点在于通过增加IO拓展模块，降低了对控制模块的管脚数量的要求，并且IO拓展模块可以就近摆放，执行装置的控制信号不需要再跨很远才能引线，节省了大量的板上的空间。但是缺点在于控制逻辑复杂，需要集成为IO拓展模块的硬件架构专门开发的驱动程序，因此开发难度大并且效率低，容易出现异常。
与以上两种传统的方法相比，在上述申请实施例提供的技术方案中，控制模块200通过地址总线连接一个或多个地址解析模块300，控制模块200可以使用少量的引脚与地址总线连接，就能够控制数量较多的地址解析模块300，因此与基于FPGA的架构的方案相比，当需要控制数量较多的地址解析模块300的时候，可以占用较少数量的控制模块200的引脚；此外，在这个技术方案中使用预先配置的待控制端口的地址信息来寻址到地址解析模块300，从而控制与寻址到的地址解析模块300对应的执行装置400，因此，在本申请实施例提供的技术方案中，无需针对控制系统的硬件架构开发专门的驱动程序，因此在构建控制系统以及对执行装置进行控制的时候，用预先设置的端口地址信息来寻址地址解析模块300的方案普遍适用于控制系统与执行装置400的各种搭配，所以可以减小开发驱动 程序的工作量，创建控制系统以及运行控制系统以及执行装置的效率高；此外，因为该方案普遍适用于控制系统与执行装置400的各种搭配，所以控制系统的驱动程序稳定不易出现故障。
在一个可选的实施例中，处理器100用于向控制模块发送控制指令；其中，控制指令包含执行装置的待控制端口的地址信息和控制动作信息；
控制模块200用于根据控制指令中所包含的执行装置的待控制端口的地址信息寻址到对应的地址解析模块；
地址解析模块300用于根据控制指令中的控制动作信息向对应的执行装置的待控制端口发送控制信号。
在上述可选的实施例中，处理器100通过PCIe总线对控制模块200发出控制指令；处理器100用于在控制执行装置400的某个待控制端口的时候，查询到为执行装置的待控制端口预先分配的地址之后，向控制模块200发送控制指令，以便控制该控制系统之中的某个执行装置(410、420等等)。为执行装置的待控制端口预先分配的地址存储于该控制系统的内存中，该控制系统的内存保存了在初始化设置执行装置的待控制端口时为执行装置分配的索引地址。内存接受处理器100发送的访问，并且在查询到执行装置的待控制端口的索引地址之后，向处理器100返回查询到的执行装置的待控制端口的索引地址。
控制模块200通过PCIe总线接收到处理器100发送的控制指令之后，从控制指令之中解析出执行装置的待控制端口的地址信息和控制动作信息。其中，地址信息指的是控制系统的执行装置在内存中的索引地址，控制动作信息表示使执行装置400所连接的触发器触发或者解触发，以便控制执行装置400的工作与停止工作。
地址解析模块300用于根据通过地址总线从控制模块200获取到的地址信息，索引到地址信息对应的执行装置400的端口，并且根据通过地址总线从控制模块200获取到的控制动作信息，执行对于地址信息对应的执行装置400的控制动作。
在此，为了能够有效地减少执行装置控制所需要使用的走线以及控制模块(芯片)200占用的空间，在本申请实施例中，使用在内存查询到的 索引地址，将处理器100的控制动作信息索引到需要执行控制指令的执行装置400。为了实现上述目的，控制模块200用于从来自处理器100的控制指令之中解析出地址信息以及控制动作信息，然后所解析出的地址信息以及控制动作信息通过地址总线被传送到地址解析模块300，由地址解析模块300来根据地址信息，将控制动作信息索引到需要执行控制指令的执行装置400。本申请实施例提供的控制系统由于采用地址映射的方式，因此仅需要使用地址总线就能够索引到执行装置400，与现有的基于FPGA架构的设计相比，所使用的引线的数量更少，因此布置引线所占用的空间以及占用的引脚的数量就减少了；因此，当控制相同数量的执行装置400的时候，与基于FPGA架构的设计相比本申请实施例提供的控制系统中的控制模块200可以使用更少数量的引脚，控制模块200选型的范围变大，能够采用引脚较少的器件作为本申请实施例提供的控制系统中的控制模块200，因而控制模块200的成本可以相应地降低；另一方面，控制模块200不必是FPGA，而是可以采用其他类型的控制模块200，这些控制模块200可以比FPGA占用的空间更小，因此减少了控制模块200在底板上所占用的空间。对于采用基于IO拓展模块的设计来说，使用大量的支持I2C通信协议的设备会带来逻辑上的复杂度，因为所有的支持I2C通信协议的设备都是基于I2C总线协议的，控制器内必须针对不同的架构来集成不同的I2C总线协议(例如，在不同的架构下，支持I2C通信协议的设备的地址不一样，那么就需要重新修改代码，这样会带来开发上的成本)。与现有技术的基于IO拓展模块的设计相比，本申请实施例提供的方案中所使用的硬件与所加载的程序的逻辑是解耦的，因此程序的开发者不需要根据实际的硬件架构再去做开发，只需要根据一套硬件设备上的控制引脚的地址表即可开始软件的工作；而硬件同时也根据这个地址表来做硬件上的适配，大大提高了驱动程序的开发效率。本申请实施例提供的控制系统不需要使用IO拓展模块，因此在执行控制指令的时候，无需IO拓展模块占用底板上的空间，底板可以制作得尺寸更小，甚至使得作为底板的印刷电路板的层数可以更少，因此降低了在制造底板时的成本；并且由于控制系统采用地址映射的方式，而无需集成IO拓展模块的驱动以及采用拓展模块的驱动来找到 目标执行装置执行动作，因此控制逻辑上也更加的容易实现，执行控制动作时更加稳定。
与基于FPGA架构的设计相比，本申请实施例提供的控制系统采用控制模块200加上地址解析模块300两者来实现FPGA的功能；与基于IO拓展模块的设计相比，本申请实施例提供的控制系统采用控制模块200加上地址解析模块300两者来实现控制模块与IO拓展模块的功能。其中，控制模块200仅仅用于解析控制指令，因此，控制模块200的选材范围是非常大的。在一个可选的实施例中，控制模块200可以是CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)，可以是MCU(Microcontroller Unit，微控制单元)，也可以是FPGA，或者可以是其他尺寸更小的控制器件，只要能够解析处理器100发送的控制指令即可。在一个可选的实施例中，地址解析模块300为了能够索引到控制指令对应的执行装置，可以使用地址解析器和具有锁存功能的触发器，地址解析器与触发器一一对应连接，触发器设置为与一个执行装置连接；其中，地址解析器用于确定地址信息索引到的执行装置(410、420等等)：在判断控制指令中的地址信息与所述触发器连接的执行装置的地址相匹配时，向对应的触发器发送控制动作信息；触发器用于根据控制动作信息来执行对于该触发器对应的执行装置的控制动作。在一个可选的实施例中，触发器可以是JK触发器或者是RS触发器。触发器可以通过其输出端连接到的对应的执行装置。JK触发器的动作包括：保持状态、重置状态、设置状态以及状态翻转。JK触发器只有一个输出引脚，这个输出引脚连接到执行装置的输入端，通过JK触发器的输出引脚上的电平的变化来控制执行装置的输入信号。JK触发器的输出信号是脉冲形式的，每一次脉冲会改变一次输出的电平，从而起到高电平和低电平的切换。RS触发器的动作包括：保持状态、重置状态以及置位状态。与FPGA相比，地址解析模块300的尺寸非常小巧，甚至可以将地址解析模块300做到硅片级别的封装之中，因此尺寸远远小于FPGA等大规模的可编程控制器件。基于上述的地址解析模块300的尺寸小巧的特征，搭配着本申请实施例提供的控制系统采用地址总线来连接控制模块200以及地址解析模块300的方式，因此可以灵活地布置地 址解析模块300，将地址解析模块300布置成靠近执行装置400。在一个可选的实施例之中，可以将地址解析模块300与对应的执行装置400封装在一起，由此可以进一步减少地址解析模块300单独占用底板的空间。在一个可选的实施例中，地址解析模块300在执行装置400上面。在一个可选的实施例中，地址解析模块300在底板上。此外，由于在本申请实施例中，使用地址总线连接控制模块200以及地址解析模块300，因此可以不必像现有的技术方案一般，为了连接控制模块与执行装置(或者在基于IO拓展模块的设计中，是连接控制模块、IO拓展模块与执行装置)，首先在控制模块处汇总所有的引线，然后跨越大半个底板连接到执行装置(或者在基于IO拓展模块的设计中，在控制模块处汇总所有连接到IO拓展模块的引线，再从IO拓展模块分别引出引线连接至各个执行装置，在这样的布置中，同样需要大量的引线跨越大半个底板连接)。而在本申请实施例的实施方案中，仅仅需要采用地址总线连接各个地址解析模块，并且由于地址总线能够承载的信息量比较大，因此仅需要引线并不多的地址总线即可满足需要，所以，地址总线并不会占用大量的底板空间。例如，如果控制系统中具有56个执行装置400，每个执行装置400有3个控制信号，此时，总共有168个控制信号，如果采用基于FPGA架构的设计，则需要至少占用168个FPGA的引脚，因此对于FPGA的规格要求非常高，FPGA的尺寸大并且由于走线造成底板空间占用很大。而在本申请实施例的方案中，只需要8位位宽的总线(最大可提供28＝256个地址)即可访问到全部的控制信号，此时仅占用控制模块的8个引脚即可完成控制，因此控制模块200的筛选范围非常大，可以尽可能筛选出尺寸小巧并且满足使用需求的控制模块200。基于上述论述，本申请实施例提供的控制系统之中，与现有技术的技术方案相比，可以选择非常小巧的控制模块200，并且地址总线走线非常简洁，因此可以选用层数更少的印刷电路板作为底板，这将会减少印刷电路板的成本。例如，14层的印刷电路板与16层的印刷电路板相比，成本降低了40％。
为了实现采用地址映射的方式索引到控制指令的目标执行装置的目的，在一个可选的实施例中，控制系统中包括了多个地址解析模块(310、 320等等)，并且这多个地址解析模块与所述控制模块之间的地址总线采用菊花链拓扑结构，这多个地址解析模块也因此连接。然后，当通过地址总线接收到地址信息以及控制动作信息的时候，通过各个地址解析模块相互之间的连接所形成的菊花链，索引到地址信息对应的执行装置。具体来说，印刷电路板上的走线将所有的地址解析模块的输入接口串起来的，所有的地址解析模块实际上是一种并联的关系，当控制模块发送地址信息的时候，所有地址解析模块基本上是同时收到信息的，哪个地址解析模块能够解析出配对的地址，然后地址匹配的地址解析模块再发送触发信号，如果地址解析模块解析出的地址并非是配对的地址，那么该地址解析模块忽略所接收的地址信息以及控制动作信息。在采用地址解析器与JK触发器的方案中，地址匹配的地址解析器会触发后端的JK触发器，JK触发器电平翻转，从而完成被控信号的触发/解触发。在一个可选的实施例中，地址解析器可以是数据选择器，例如型号为日立74LS151的8选1数据选择器；地址解析器的输出端可以连接于多个触发器。或者，可以把以菊花链形式连接的多个地址解析器作为一个整体，设置成数据选择器的样式并且具有数据选择器的功能。
在一个可选的实施例中，将处理器100选型为Intel公司的Xeon D-1527型号的处理器，通过一组PCIe总线连接到控制模块；将控制模块200选型为lattice公司的LFE5U-12F-6MG285C型号的处理器，控制模块200通过一组地址总线连接到地址解析器，地址解析器可以是数据选择器，将数据选择器选型为日立74LS151型号的8选1数据选择器；针对48个执行装置的应用，一共需要18个8选1数据选择器，数据选择器的每一路下行端口接一个JK触发器，将JK触发器选型为日立74LS76型号，一共需要72个这种型号的JK触发器。数据选择器和JK触发器构成了地址解析模块300，靠近执行装置400摆放，可以选用小封装以达到节约空间的目的；从控制模块200输出的寻址总线通过菊花链来将地址解析模块连接起来。
本申请实施例提供的控制系统可以广泛地应用于各种领域。因此，在一个可选的实施例中，执行装置400是光模块。当执行装置400是光模块时，通过光模块的DIS、RS0、RS1引脚向该光模块发出指令，控制对应光 模块的动作。其中，触发器通过对应的光模块的DIS引脚向光模块发送的信号负责控制对应的光模块是否工作；RS0、RS1引脚引入的信号负责控制光模块的工作模式，用来切换光模块的速率。在另一个可选的实施例中，执行装置400是硬盘，控制系统连接的多个硬盘组成了硬盘阵列，控制系统用于控制硬盘阵列之中的硬盘是否运行。
本申请实施例提供了一种对执行装置进行控制的方法，该方法由控制系统执行，该控制系统包括处理器、控制模块以及地址解析模块，如图2所示，该方法包括步骤S101-步骤S105。
步骤S101，由处理器向控制模块发送控制指令。
其中，控制指令包含执行装置的待控制端口的地址信息和控制动作信息。
步骤S103，由控制模块根据控制指令中所包含的执行装置的待控制端口的地址信息寻址到对应的地址解析模块。
步骤S105，由地址解析模块根据控制指令中的控制动作信息向对应的执行装置的待控制端口发送控制信号。
虽然本申请所揭露的实施方式如上，但上述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

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  1. 一种控制系统，用于对执行装置进行控制，其特征在于，所述控制系统包括处理器、控制模块和地址解析模块；其中，
    所述处理器通过外围组件互连高速PCIe总线与所述控制模块连接，所述控制模块通过地址总线与一个或多个地址解析模块连接，每个地址解析模块被设置为与一个执行装置连接；其中，
    所述处理器上预先配置有每个执行装置上的待控制端口的地址信息，所述地址信息用于使所述处理器通过所述控制模块寻址相应的地址解析模块。
  2. 根据权利要求1所述的控制系统，其中，
    所述处理器用于向所述控制模块发送控制指令；其中，所述控制指令包含执行装置的待控制端口的地址信息和控制动作信息；
    所述控制模块用于根据所述控制指令中所包含的执行装置的待控制端口的地址信息寻址到对应的地址解析模块；
    所述地址解析模块用于根据所述控制指令中的控制动作信息向对应的执行装置的待控制端口发送控制信号。
  3. 根据权利要求1所述的控制系统，其特征在于，所述地址解析模块包括地址解析器和具有锁存功能的触发器，所述地址解析器与所述触发器一一对应连接，所述触发器被设置为与一个执行装置连接，其中，
    所述地址解析器用于判断控制指令中的地址信息与所述触发器连接的执行装置的地址相匹配时，向对应的触发器发送控制动作信息；
    所述触发器用于根据所述控制动作信息执行对于所述对应的执行装置的控制动作。
  4. 根据权利要求1所述的控制系统，其特征在于，所述控制模块是复杂可编程逻辑器件CPLD、微控制单元MCU或者现场可编程逻辑门阵列FPGA。
  5. 根据权利要求1所述的控制系统，其特征在于，所述地址解析模块与对应的执行装置封装在一起。
  6. 根据权利要求1所述的控制系统，其中，所述控制系统包括多个地 址解析模块，所述多个地址解析模块与所述控制模块之间的地址总线采用菊花链拓扑结构。
  7. 根据权利要求6所述的控制系统，其特征在于，所述多个地址解析器被封装成为一个数据选择器，所述数据选择器用于对所述地址信息进行解析。
  8. 根据权利要求3所述的系统，其特征在于，所述地址解析器是数据选择器，所述地址解析器的输出端连接于多个触发器。
  9. 根据权利要求1所述的控制系统，其中，所述执行装置是光模块或者硬盘。
  10. 一种交换机，其特征在于，所述交换机包括权利要求1-8中任一项所述的控制系统以及执行装置；其中，所述执行装置是光模块。
  11. 一种对执行装置进行控制的方法，所述方法由控制系统执行，所述控制系统包括处理器、控制模块以及地址解析模块，其特征在于，所述方法包括：
    由所述处理器向控制模块发送控制指令；其中，所述控制指令包含执行装置的待控制端口的地址信息和控制动作信息；
    由所述控制模块根据所述控制指令中所包含的执行装置的待控制端口的地址信息寻址到对应的地址解析模块；
    由所述地址解析模块根据所述控制指令中的控制动作信息向对应的执行装置的待控制端口发送控制信号。
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