WO2021056592A1 - 半导体装置、用于功率转换的设备和提供半导体装置的方法 - Google Patents

半导体装置、用于功率转换的设备和提供半导体装置的方法 Download PDF

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WO2021056592A1
WO2021056592A1 PCT/CN2019/109245 CN2019109245W WO2021056592A1 WO 2021056592 A1 WO2021056592 A1 WO 2021056592A1 CN 2019109245 W CN2019109245 W CN 2019109245W WO 2021056592 A1 WO2021056592 A1 WO 2021056592A1
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Prior art keywords
electrically coupled
conductive
semiconductor device
conductive region
capacitor
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PCT/CN2019/109245
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English (en)
French (fr)
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刘泽伟
姚吉隆
王会锦
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睿信科机器人股份有限公司
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Priority to PCT/CN2019/109245 priority Critical patent/WO2021056592A1/zh
Publication of WO2021056592A1 publication Critical patent/WO2021056592A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductors, and more specifically, to semiconductor devices, equipment for power conversion, and methods of providing semiconductor devices.
  • GaN-based power field effect transistors FETs
  • MOSFETs silicon-based power metal oxide field effect transistors
  • GaN-based semiconductor devices have very high switching performance. Compared with the current silicon technology, which usually switches at a rate lower than 50V/ns, the voltage slew rate of GaN-based semiconductor devices is approximately 150V/ns or higher. Compared with traditional silicon power FETs, this high switching speed results in a very significant increase in current commutation rate.
  • semiconductor devices such as GaN-based switching semiconductor devices have very high switching performance, high switching speeds also bring some negative problems. For example, in high parasitic inductance circuits, due to the high current rate of change (di/dt) The overvoltage problem. These problems increase the power loss of the semiconductor device and are detrimental to the performance of the semiconductor device.
  • the inventor of the present application realized that in order to maximize the efficiency advantage of fast switching, it is very important to optimize the layout and wiring of switching semiconductor devices and related components on a substrate (such as a circuit board) in order to reduce loop parasitic inductance. In order to obtain the best performance, it is essential to use proper component layout when designing power stages including semiconductor devices.
  • embodiments of the present disclosure provide a semiconductor device, an apparatus for power conversion, and a method of providing a semiconductor device.
  • the two switching semiconductor devices as the arms of the half-bridge circuit are arranged on the same side of the substrate, and the DC bus capacitors are arranged on the opposite side of the substrate. In this way, the distance between the two switching semiconductor devices can be reduced, and the number of DC bus capacitors can be flexibly set according to needs.
  • a semiconductor device in a first aspect of the present disclosure, includes: a substrate; a first switching semiconductor device disposed on a first surface of the substrate, a first end of the first switching semiconductor device is electrically coupled to a first conductive region of the first surface, and a second end is electrically coupled to the first surface A second conductive area on a surface; a second switching semiconductor device, arranged on the first surface, the first end of the second switching semiconductor device is electrically coupled to the second conductive area and the second end is electrically coupled to the third on the first surface A conductive area; and at least one capacitor disposed on a second surface of the substrate opposite to the first surface, a first end of the at least one capacitor is electrically coupled to the first conductive area and a second end is electrically coupled to the third conductive area.
  • the loop inductance can be reduced by reducing the distance between the two semiconductor devices.
  • the DC bus capacitors are arranged on the other surface of the substrate, the number of DC bus capacitors can be flexibly set, especially there is sufficient space to install more DC bus capacitors, thereby providing a more stable output. As a result, the overvoltage and power loss of the semiconductor device can be reduced, and stable voltage and ripple current can be provided.
  • the substrate includes: a first intermediate conductive layer disposed between the first surface and the second surface, the first end of the at least one capacitor is electrically coupled to the first conductive area via the first intermediate conductive layer; and Two intermediate conductive layers are arranged between the first surface and the second surface and are electrically isolated from the first intermediate conductive layer, and the second end of at least one capacitor is electrically coupled to the third conductive area via the second intermediate conductive layer.
  • the mutual inductance of the loop can be reduced by arranging the middle conductive layer with the opposite current direction.
  • the loop inductance can be further reduced, which is beneficial to the reduction of overvoltage and power loss.
  • the first intermediate conductive layer is electrically coupled to the fourth conductive region and the sixth conductive region of the second surface, and the first end of the at least one capacitor is electrically coupled to the fourth conductive region or the sixth conductive region, and
  • the second intermediate conductive layer is electrically coupled to the fifth conductive region of the second surface, and the second terminal of the at least one capacitor is electrically coupled to the fifth conductive region.
  • the at least one capacitor includes a first group of capacitors and a second group of capacitors, and wherein the first end of the first group of capacitors is electrically coupled to the fourth conductive region, and the first end of the second group of capacitors is electrically coupled to Sixth conductive area. In this way, a larger number of capacitors can be provided on the second surface, so that a stable DC power supply and sufficient ripple current can be provided.
  • the fifth conductive area is disposed between the fourth conductive area and the sixth conductive area, and wherein the first group of capacitors and the second group of capacitors are disposed side by side on the second surface. In this way, the DC link capacitors can be arranged in a simple manner.
  • the first terminal of at least one capacitor is electrically coupled to the seventh conductive region of the second surface
  • the seventh conductive region is electrically coupled to the first conductive region
  • the second terminal of at least one capacitor is electrically coupled to the first conductive region.
  • the eighth conductive area on the two surfaces is electrically coupled to the third conductive area.
  • the seventh conductive region is electrically coupled to the first conductive region via a via hole, and wherein the eighth conductive region is electrically coupled to the third conductive region via another via hole.
  • the DC bus capacitors located on both sides of the substrate and the switching semiconductor device are conveniently coupled together through via holes. Therefore, it is helpful to further reduce the structural complexity of the semiconductor device, which is beneficial to the manufacture of the device.
  • the second conductive region is disposed between the first conductive region and the third conductive region, and the first switching semiconductor device and the second switching semiconductor device are disposed side by side on the first surface. In this way, the current path between the switching semiconductor devices as the bridge arms can be further reduced, which is beneficial to the further reduction of loop inductance and the further reduction of overvoltage and loss.
  • At least one of the first switching semiconductor device and the second switching semiconductor device includes a gallium nitride-based semiconductor device. In such an embodiment, it is beneficial to solve the problem caused by the faster switching speed in the gallium nitride-based device.
  • the substrate includes a printed circuit board.
  • the semiconductor device of the present disclosure can be conveniently realized by a printed circuit board.
  • an apparatus for power conversion includes a semiconductor device according to the first aspect; a first direct current terminal electrically coupled to the first conductive area; a second direct current terminal electrically coupled to the third conductive area; and an output terminal electrically coupled to the second conductive area.
  • the device for power conversion provided in this way has the advantages as discussed above in relation to the first aspect.
  • a method of providing a semiconductor device includes providing a substrate; disposing a first switching semiconductor device on a first surface of the substrate, a first end of the first switching semiconductor device is electrically coupled to a first conductive area of the first surface, and a second end is electrically coupled to the first surface The second conductive region of the; a second switching semiconductor device is provided on the first surface, the first terminal of the second switching semiconductor device is electrically coupled to the second conductive region and the second terminal is electrically coupled to the third conductive region of the first surface; And at least one capacitor is provided on a second surface of the substrate opposite to the first surface, the first terminal of the at least one capacitor is electrically coupled to the first conductive region and the second terminal is electrically coupled to the third conductive region.
  • the semiconductor device provided in this way can have reduced overvoltage and power loss, and can provide stable voltage and ripple current.
  • providing the substrate includes: disposing a first intermediate conductive layer between the first surface and the second surface, and the first end of the at least one capacitor is electrically coupled to the first conductive area via the first intermediate conductive layer; and A second intermediate conductive layer electrically isolated from the first intermediate conductive layer is arranged between the first surface and the second surface, and the second end of at least one capacitor is electrically coupled to the third conductive area via the second intermediate conductive layer.
  • the mutual inductance of the loop can be reduced by arranging the middle conductive layer with the opposite current direction. As a result, the loop inductance can be further reduced, which is beneficial to the reduction of overvoltage and power loss.
  • the first intermediate conductive layer is electrically coupled to the fourth conductive region and the sixth conductive region of the second surface, and the first end of the at least one capacitor is electrically coupled to the fourth conductive region or the sixth conductive region, and
  • the second intermediate conductive layer is electrically coupled to the fifth conductive region of the second surface, and the second terminal of the at least one capacitor is electrically coupled to the fifth conductive region.
  • providing at least one capacitor includes providing a first group of capacitors and a second group of capacitors, and wherein the first end of the first group of capacitors is electrically coupled to the fourth conductive region, and the first end of the second group of capacitors is electrically coupled To the sixth conductive area. In this way, a larger number of capacitors can be provided on the second surface, so that a stable DC power supply and sufficient ripple current can be provided.
  • the method further includes: disposing the fifth conductive region between the fourth conductive region and the sixth conductive region, and disposing the first group of capacitors and the second group of capacitors includes combining the first group of capacitors and the second group of capacitors.
  • the group of capacitors are arranged side by side on the second surface. In this way, the DC link capacitors can be arranged in a simple manner.
  • Figure 1 shows a schematic circuit diagram of a semiconductor device including a half bridge
  • FIG. 2 shows a schematic diagram of an example of a semiconductor device according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of another example of a semiconductor device according to an embodiment of the present disclosure
  • FIG. 4 shows a top view of the semiconductor device of FIG. 3
  • FIG. 5 shows a bottom view of the semiconductor device of FIG. 3
  • FIG. 6 shows a schematic flowchart of a method for providing a semiconductor device according to an embodiment of the present disclosure.
  • an integrated GaN power module includes GaN-based upper and lower arm devices, bus capacitors, and substrates.
  • the upper bridge arm device, the lower bridge arm device and the bus capacitor are arranged on the same side surface of the substrate, and the bus capacitor is arranged between the upper bridge arm device and the lower bridge arm device.
  • This traditional scheme has some disadvantages. For example, because the bus capacitor is placed between the GaN semiconductor devices, the output parasitic inductance of the GaN half-bridge is still high.
  • the number of bus capacitors that can be set is limited, and usually only a few bus capacitors can be set. Therefore, it is difficult to set a bus capacitor sufficient to provide a stable DC voltage.
  • two switching semiconductor devices used as half-bridge arms are arranged on the same surface of the substrate, and the bus capacitor is arranged on the opposite surface of the substrate. In this way, the distance between the two switching semiconductor devices can be reduced, and the DC bus capacitor can be flexibly arranged according to needs.
  • FIG. 1 shows a schematic circuit diagram 100 of a semiconductor device including a half bridge.
  • the circuit shown in the schematic circuit diagram 100 includes an upper-side semiconductor device 101, a lower-side semiconductor device 102, and a DC bus capacitor 120.
  • the drain of the upper semiconductor device 101 and the upper electrode of the capacitor 120 are coupled to the first DC input terminal represented by DC+; the source of the lower semiconductor device 102 and the lower electrode of the capacitor 120 are coupled to the DC- represents the second direct current input terminal; the source of the upper-side semiconductor device 101 and the drain of the lower-side semiconductor device 102 are connected to the output terminal indicated by OUT.
  • the DC bus capacitor 120 may be used to provide a stable DC voltage and necessary ripple current.
  • the high loop inductance will cause significant overshoot at the switching node. Overshoot leads to an increase in switching loss, which in turn leads to a decrease in efficiency.
  • the length of the current path 110 can be reduced. For example, one or more of the following can be reduced: the distance between the drain of the upper semiconductor device 101 and the upper electrode of the capacitor 120, and the distance between the source of the lower semiconductor device 102 and the lower electrode of the capacitor 120 And the distance between the source of the upper semiconductor device 101 and the drain of the lower semiconductor device 102.
  • the layout of components and wires can be used to reduce or offset the mutual inductance between currents flowing to different conductors or conductive areas.
  • FIG. 2 shows a schematic diagram of an example of a semiconductor device 200 according to an embodiment of the present disclosure.
  • the semiconductor device 200 shown in FIG. 2 includes a substrate 210.
  • the substrate 210 may be, for example, a printed circuit board (PCB), or may be any form of carrier capable of realizing the layout and wiring described herein.
  • the substrate 210 has a first surface 211 and a second surface 212 opposite to the first surface 211.
  • the first switching semiconductor device 201 and the second switching semiconductor device 202 are disposed on the first surface 211.
  • the first switching semiconductor device and the second switching semiconductor device may be collectively referred to as a switching semiconductor device or a semiconductor device.
  • the first switching semiconductor device and the second switching semiconductor device may also be referred to as a first semiconductor device and a second semiconductor device, respectively.
  • the first switching semiconductor device 201 and the second switching semiconductor device 202 may be GaN-based semiconductor devices, such as GaN-based FETs.
  • the first switching semiconductor device 201 and the second switching semiconductor device 202 may also be other types of semiconductor devices, especially semiconductor devices with a relatively large switching speed.
  • One end (for example, the drain) of the first switching semiconductor device 201 is electrically coupled to the first conductive region 251 of the first surface 211, and the other end (for example, the source) is electrically coupled to the second conductive region 252 of the first surface 211 .
  • One end (for example, the source) of the second switching semiconductor device 202 is electrically coupled to the second conductive region 252, and the other end (for example, the source) is electrically coupled to the third conductive region 253 of the first surface 211.
  • the first conductive area 251 may be electrically coupled to the first input terminal, such as DC+ shown in FIG. 2, while the third conductive area 253 may be electrically coupled to the first input terminal.
  • the second conductive region 252 may be electrically coupled to the output terminal OUT.
  • the first switching semiconductor device 201 and the second switching semiconductor device 202 may be used as the upper arm device and the lower arm device of the half-bridge circuit, respectively.
  • the capacitor 220 is disposed on the second surface 212 of the substrate 210.
  • the term "capacitor” refers to any capacitive element that can achieve capacitance.
  • the capacitor 220 is electrically coupled to the first conductive area 251 and the third conductive area 253.
  • the first terminal (for example, the first electrode) of the capacitor 220 is electrically coupled to the first conductive region 251
  • the second terminal is electrically coupled to the third conductive region 253.
  • the capacitor 220 may be used as a DC bus capacitor, similar to the capacitor 120 shown in FIG. 1.
  • the capacitor 220 may be electrically coupled to the first conductive area 251 and the third conductive area 253 in various ways. In some embodiments, the corresponding ends of the capacitor 220 may be electrically connected to the first conductive area 251 and the third conductive area 253 through pins, leads, vias, etc., respectively. In other embodiments, the corresponding ends of the capacitor 220 may be electrically coupled to the first conductive region 251 and the third conductive region 253 via an intermediate conductive layer provided in the substrate, as described below with reference to FIGS. 3 to 5 .
  • capacitor 220 may be provided on the second surface 212.
  • These capacitors can be disposed on the second surface 212 in various relative positions and orientations, and the number of capacitors disposed can be determined as required.
  • the distance between the two switching semiconductor devices can be reduced as much as possible while meeting other requirements.
  • the current path between the source of the upper-side semiconductor device and the drain of the lower-side semiconductor device can be reduced, thereby reducing loop inductance.
  • the DC bus capacitance is arranged on the other surface instead of being arranged between two switching semiconductor devices, there is more space to arrange more capacitors according to demand. In this way, it is beneficial to provide a stable voltage output and necessary ripple current.
  • FIG. 3 shows a schematic diagram of a semiconductor device 300 according to an embodiment of the present disclosure
  • FIG. 4 shows a top view of the semiconductor device 300 of FIG. 3
  • FIG. 5 shows a bottom view of the semiconductor device 300 of FIG. 3.
  • the semiconductor device 300 includes a substrate 310 which is similar to the substrate 210 of FIG. 2.
  • the substrate 310 may be, for example, a PCB, or any form of carrier capable of realizing the layout and wiring described herein.
  • the substrate 310 has a first surface 311 and a second surface 312 opposite to the first surface 311.
  • the first switching semiconductor device 301 and the second switching semiconductor device 302 are disposed on the first surface 311.
  • One end (for example, the drain) of the first switching semiconductor device 301 is electrically coupled to the first conductive region 351 of the first surface 311, and the other end (for example, the source) is electrically coupled to the second conductive region 352 of the first surface 311 .
  • One end (for example, the drain) of the second switching semiconductor device 302 is electrically coupled to the second conductive region 352, and the other end (for example, the source) is electrically coupled to the third conductive region 353 of the first surface 311.
  • the first conductive area 351 may be electrically coupled to the first input terminal, such as DC+ shown in FIG.
  • the third conductive area 353 may be electrically coupled to the first input terminal.
  • the second conductive area 352 may be electrically coupled to the output terminal OUT. Similar to FIG. 2, the first switching semiconductor device 301 and the second switching semiconductor device 302 may be used as upper and lower arm devices of the half-bridge circuit, respectively.
  • the first group of capacitors 321 and the second group of capacitors 322 are disposed on the second surface 312 of the substrate 310.
  • the first surface 312 includes a fourth conductive region 354, a fifth conductive region 355, and a sixth conductive region 356.
  • One end (for example, the first electrode) of the first group of capacitors 321 is electrically coupled to the fourth conductive area 354, and the other end (for example, the second electrode) is electrically coupled to the fifth conductive area 355.
  • One end (for example, the first electrode) of the second group of capacitors 322 is electrically coupled to the sixth conductive region 356, and the other end (for example, the second electrode) is electrically coupled to the fifth conductive region 355.
  • the substrate 310 further includes a first intermediate conductive layer 331 and a second intermediate conductive layer 332 that are electrically isolated from each other.
  • the first intermediate conductive layer 331 is electrically coupled to the first conductive region 351 via the via 341, is electrically coupled to the fourth conductive region 354 via the via 344, and is electrically coupled to the sixth conductive region via the via 345 356.
  • the fourth conductive region 354 and the sixth conductive region 356 are electrically coupled to the first conductive region 351 via the first intermediate conductive layer 331.
  • the first conductive region 351 is electrically coupled to DC+
  • the first intermediate conductive layer 331, the fourth conductive region 354, and the sixth conductive region 356 are also electrically coupled to DC+.
  • the second intermediate conductive layer 332 is electrically coupled to the third conductive region 353 via the via hole 342, and is electrically coupled to the fifth conductive region 355 via the via hole 343.
  • the fifth conductive region 355 is electrically coupled to the third conductive region 353 via the second intermediate conductive layer 332.
  • the second intermediate conductive layer 332 and the fifth conductive region 355 are also electrically coupled to DC-.
  • the via holes shown in FIGS. 3 to 5 is only schematic and is not intended to be limiting.
  • the via holes may be arranged in various ways.
  • the via 341 and the via 344 are shown to be aligned in the vertical direction in FIG. 3, they may be spaced apart in the vertical direction.
  • the relative positions and sizes of the first intermediate conductive layer 311 and the second intermediate conductive layer 312 are also illustrative.
  • the first intermediate conductive layer may also be disposed above the second intermediate conductive layer.
  • the first intermediate conductive layer 311 is shown to include two parts on the left and right sides of the via 343, it should be understood that from the direction perpendicular to the normal line of the substrate 310 To observe, these two parts are a whole.
  • the first intermediate conductive layer 331 and the second intermediate conductive layer 332 will be electrically coupled to DC+ and DC-, respectively.
  • mutual inductance can be reduced, which is beneficial to further reduce loop inductance.
  • the second conductive region 352 is provided between the first conductive region 351 and the third conductive region 353, and the first switching semiconductor device 301 and the second switching semiconductor device 302 are arranged side by side in the On the first surface 311. In this way, the current path between the two switching semiconductor devices as bridge arms can be further reduced, thereby reducing loop inductance.
  • first, second, and third conductive regions shown in FIG. 4 are only schematic and not intended to be limiting.
  • the first, second, and third conductive regions may have other shapes, such as oval shapes.
  • the first, second, and third conductive regions can also be arranged in other relative orientations, such as an "L" shape, where the first and third conductive regions are located on the sides of the "L" shape, and the second conductive region is located in the "L" shape. L" shaped corners.
  • the fifth conductive area 355 is disposed between the fourth conductive area 354 and the sixth conductive area 356.
  • One end of the first group of capacitors 321 is electrically coupled to the fourth conductive area 354, and the other end is electrically coupled to the fifth conductive area 355.
  • One end of the second group of capacitors 322 is electrically coupled to the sixth conductive region 356 and the other end is also electrically coupled to the fifth conductive region 355. It should be understood that the number and arrangement of the first group of capacitors 321 and the second group of capacitors 322 shown in FIG. 5 are only illustrative and not intended to be limited. In the embodiments of the present disclosure, any suitable number of capacitors may be included, and the number of capacitors of the first group and the number of capacitors of the second group need not be the same.
  • the shapes and relative arrangements of the fourth, fifth, and sixth conductive regions shown in FIG. 5 are only schematic and are not intended to be limiting.
  • the fourth, fifth, and sixth conductive regions may also have other shapes and/or be arranged in other relative orientations, as discussed above with respect to the first, second, and third conductive regions.
  • the number of conductive regions included in the second surface 312 shown in FIGS. 3 and 5 is only illustrative, and the second surface 312 may include more or fewer conductive regions.
  • the second surface 212 on which the capacitor 220 is disposed may include two conductive regions, and two electrodes of the capacitor 220 are electrically coupled to the two conductive regions, respectively.
  • the two conductive regions may be electrically coupled to the first conductive region 251 and the third conductive region 253 via via holes (not shown) in the substrate 210, respectively.
  • the two conductive regions of the second surface 212 may be substantially aligned with the first conductive region 251 and the third conductive region 253, respectively.
  • the two conductive regions may be electrically coupled to the first conductive regions 251 and 312 via two intermediate conductive layers (similar to the intermediate conductive layers 311 and 312 shown in FIG. 3) provided in the substrate 210, respectively.
  • Various conductive materials can be used to realize the conductive regions and intermediate conductive layers described in FIGS. 2 to 5. Such conductive materials may include, but are not limited to, copper, platinum, and the like. In some embodiments, some or all of the conductive region and the intermediate conductive layer may be implemented with a copper layer. In this way, it can help to further reduce loop inductance.
  • Semiconductor devices can be used in various power electronic devices. For example, it can be used for power equipment, including but not limited to power converters, inverters, drives, etc.
  • the first conductive area 251, 351 may be electrically coupled to a first direct current terminal such as DC+
  • the third conductive area 253, 353 may be electrically coupled to a second direct current terminal such as DC-
  • the regions 252, 352 may be electrically coupled to the output terminal.
  • FIG. 6 shows a schematic flowchart of a method 600 for providing a semiconductor device according to an embodiment of the present disclosure.
  • substrates such as substrates 210, 310 are provided.
  • a first switching semiconductor device is disposed on the first surface of the substrate. The first terminal of the first switching semiconductor device is electrically coupled to the first conductive region of the first surface and the second terminal is electrically coupled to the second conductive region of the first surface.
  • the first switching semiconductor device 201 is provided on the first surface 211 of the substrate 210.
  • a second switching semiconductor device is provided on the first surface.
  • the first end of the second switching semiconductor device is electrically coupled to the second conductive area and the second end is electrically coupled to the third conductive area of the first surface.
  • the second switching semiconductor device 202 is provided on the first surface 211 of the substrate 210.
  • At 640, at least one capacitor is disposed on a second surface of the substrate opposite to the first surface.
  • the first end of the at least one capacitor is electrically coupled to the first conductive area and the second end is electrically coupled to the third conductive area.
  • a capacitor 220 is provided on the second surface 212 of the substrate 210.
  • providing the substrate may include: disposing a first intermediate conductive layer and a second intermediate conductive layer electrically isolated from the first intermediate conductive layer between the first surface and the second surface.
  • the first terminal of at least one capacitor is electrically coupled to the first conductive region via the first intermediate conductive layer
  • the second terminal is electrically coupled to the third conductive region via the second intermediate conductive layer.
  • a first intermediate conductive layer 331 and a second intermediate conductive layer 332 may be provided between the first surface 311 and the second surface 312 of the substrate 310.
  • the first intermediate conductive layer is electrically coupled to the fourth conductive region and the sixth conductive region of the second surface, and the first terminal of the at least one capacitor is electrically coupled to the fourth conductive region or the sixth conductive region.
  • the second intermediate conductive layer is electrically coupled to the fifth conductive region of the second surface, and the second end of the at least one capacitor is electrically coupled to the fifth conductive region.
  • providing at least one capacitor includes providing a first group of capacitors and a second group of capacitors. The first end of the first group of capacitors is electrically coupled to the fourth conductive area, and the first end of the second group of capacitors is electrically coupled to the sixth conductive area.
  • the method 600 may further include: disposing the fifth conductive region between the fourth conductive region and the sixth conductive region.
  • Providing the first group of capacitors and the second group of capacitors includes arranging the first group of capacitors and the second group of capacitors side by side on the second surface. For example, the first group of capacitors 321 and the second group of capacitors 322 are arranged side by side on the second surface 312.

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Abstract

提供了半导体装置（200）、用于功率转换的设备和提供半导体装置（200）的方法。一种半导体装置（200）包括基板（210）、设置在基板（210）的第一表面（211）上的第一和第二开关半导体器件（201、202）、以及设置在基板（210）的与第一表面（211）相对的第二表面（212）上的至少一个电容器（220）。第一开关半导体器件（201）的第一端电耦合至第一表面（211）的第一导电区域（251）并且第二端电耦合至第一表面（211）的第二导电区域（252）。第二开关半导体器件（202）的第一端电耦合至第二导电区域（252）并且第二端电耦合至第一表面（211）的第三导电区域（253）。至少一个电容器（220）的第一端电耦合至第一导电区域（251）并且第二端电耦合至第三导电区域（253）。可以降低半导体装置（200）的过电压和功率损耗，并提供稳定的电压和纹波电流。

Description

半导体装置、用于功率转换的设备和提供半导体装置的方法 技术领域
本公开的实施例涉及半导体领域，并且更具体地，涉及半导体装置、用于功率转换的设备和提供半导体装置的方法。
背景技术
半导体器件已经得到广泛的应用。例如，基于氮化镓(GaN)的功率场效应晶体管(FET)正在越来越多地被应用，诸如应用于高效的功率转换器中。基于GaN的开关器件与基于硅的功率金属氧化物场效应晶体管(MOSFET)相比具有明显的优势，例如，具有更低的栅极电荷、更快的开关速度和更小的反向恢复电荷。
这些性质使基于GaN的半导体器件具有非常高的开关性能。与目前通常以低于50V/ns的速率切换的硅技术相比，基于GaN的半导体器件的电压压摆率(slew rate)大约为150V/ns或更高。与传统的硅功率FET相比，这种高开关速度导致电流换向速率的非常显著的增加。
发明内容
尽管基于GaN的开关半导体器件之类的半导体器件具有非常高的开关性能，但是高开关速度也带来一些负面问题，例如在高寄生电感电路中，由于高的电流变化速率(di/dt)导致的过电压问题。这些问题增加了半导体器件的功率损耗，并且对半导体器件的性能是有损的。本申请的发明人意识到为了最大化快速切换的效率优势，优化开关半导体器件和相关元件在基板(诸如，电路板)上的布局和布线以便减小环路寄生电感是非常重要。为了获得最佳性能，在对包括半导体器件的功率级进行设计时，使用适当的元件布局至关重要。
为了至少部分地解决上述问题中的一个或多个以及其他潜在问题，本公开的实施例提供了半导体装置、用于功率转换的设备和提供半导体装置的方法。根据本公开的实施例，作为半桥电路桥臂的两个开关半导体器件布置在基板的同一侧，而直流母 线电容器布置在基板的相对的一侧。以此方式，可以减小两个开关半导体器件之间的距离，并且可以灵活地根据需要来设置直流母线电容器的数目。
在本公开的第一方面中，提供了一种半导体装置。该半导体装置包括：基板；第一开关半导体器件，设置在基板的第一表面上，第一开关半导体器件的第一端电耦合至第一表面的第一导电区域并且第二端电耦合至第一表面的第二导电区域；第二开关半导体器件，设置在第一表面上，第二开关半导体器件的第一端电耦合至第二导电区域并且第二端电耦合至第一表面的第三导电区域；以及至少一个电容器，设置在基板的与第一表面相对的第二表面上，至少一个电容器的第一端电耦合至第一导电区域并且第二端电耦合至第三导电区域。
以此方式，一方面，由于用作半桥桥臂的两个半导体器件布置在基板的相同表面上，可以通过减小两个半导体器件之间的距离来减小环路电感。另一方面，由于直流母线电容器布置在基板的另一表面上，可以灵活地设置直流母线电容器的数目，特别是有充足的空间来设置更多的直流母线电容器，从而提供更稳定的输出。由此，可以降低半导体装置的过电压和功率损耗，并提供稳定的电压和纹波电流。
在一些实施例中，基板包括：第一中间导电层，设置在第一表面与第二表面之间，至少一个电容器的第一端经由第一中间导电层电耦合至第一导电区域；以及第二中间导电层，设置在第一表面与第二表面之间并且与第一中间导电层电隔离，至少一个电容器的第二端经由第二中间导电层电耦合至第三导电区域。以此方式，通过设置电流方向相反的中间导电层，可以减小环路的互感。由此，可以进一步减小环路电感，有利于过电压和功率损耗的降低。
在一些实施例中，第一中间导电层电耦合至第二表面的第四导电区域和第六导电区域，并且至少一个电容器的第一端电耦合至第四导电区域或第六导电区域，并且其中第二中间导电层电耦合至第二表面的第五导电区域，并且至少一个电容器的第二端电耦合至第五导电区域。以此方式，可以通过第二表面的导电区域的分布来灵活地根据需求来设置直流母线电容器，从而可以提供所期望的直流电压和纹波电流。
在一些实施例中，至少一个电容器包括第一组电容器和第二组电容器，并且其中第一组电容器的第一端电耦合至第四导电区域，并且第二组电容器的第一端电耦合至第六导电区域。以此方式，可以在第二表面上设置较多数目的电容器，从而可以提供稳定的直流电源和足够的纹波电流。
在一些实施例中，第五导电区域被设置在第四导电区域与第六导电区域之间，并且其中第一组电容器和第二组电容器被并排地设置在第二表面上。以此方式，可以以简单的方式来布置直流母线电容器。
在一些实施例中，至少一个电容器的第一端电耦合至第二表面的第七导电区域，第七导电区域电耦合至第一导电区域，并且其中至少一个电容器的第二端电耦合至第二表面的第八导电区域，第八导电区域电耦合至第三导电区域。以此方式，可以在减小环路电感的情况下，降低半导体装置的结构复杂度，有利于装置的制造。
在一些实施例中，第七导电区域经由过孔而电耦合至第一导电区域，并且其中第八导电区域经由另外的过孔而电耦合至第三导电区域。以此方法，通过过孔来便捷地将位于基板两侧的直流母线电容器与开关半导体器件耦合在一起。由此，有助于进一步降低半导体装置的结构复杂度，有利于装置的制造。
在一些实施例中，第二导电区域设置在第一导电区域与第三导电区域之间，并且第一开关半导体器件和第二开关半导体器件被并排地设置在第一表面上。以此方式，可以进一步减小作为桥臂的开关半导体器件之间的电流路径，从而有利于环路电感的进一步降低以及过电压和损耗的进一步降低。
在一些实施例中，第一开关半导体器件和第二开关半导体器件中的至少一个包括基于氮化镓的半导体器件。在这样的实施例中，有利于解决基于氮化镓的器件中由较快的开关速度而引起的问题。
在一些实施例中，基板包括印刷电路板。在这样的实施例中，可以通过印刷电路板来便捷地实现本公开的半导体装置。
在本公开的第二方面中，提供了一种用于功率转换的设备。该设备包括根据第一方面的半导体装置；第一直流端子，电耦合至第一导电区域；第二直流端子，电耦合至第三导电区域；以及输出端子，电耦合至第二导电区域。以此方式提供的用于功率转换的设备具有如上文关于第一方面所讨论的优点。
在本公开的第三方面中，提供了一种提供半导体装置的方法。该方法包括提供基板；在基板的第一表面上设置第一开关半导体器件，第一开关半导体器件的第一端电耦合至第一表面的第一导电区域并且第二端电耦合至第一表面的第二导电区域；在第一表面上设置第二开关半导体器件，第二开关半导体器件的第一端电耦合至第二导电区域并且第二端电耦合至第一表面的第三导电区域；以及在基板的与第一表面相对 的第二表面上设置至少一个电容器，至少一个电容器的第一端电耦合至第一导电区域并且第二端电耦合至第三导电区域。以此方式提供的半导体装置可以具有降低的过电压和功率损耗，并且可以提供稳定的电压和纹波电流。
在一些实施例中，提供基板包括：在第一表面与第二表面之间设置第一中间导电层，至少一个电容器的第一端经由第一中间导电层电耦合至第一导电区域；以及在第一表面与第二表面之间设置与第一中间导电层电隔离的第二中间导电层，至少一个电容器的第二端经由第二中间导电层电耦合至第三导电区域。以此方式，通过设置电流方向相反的中间导电层，可以减小环路的互感。由此，可以进一步减小环路电感，有利于过电压和功率损耗的降低。
在一些实施例中，第一中间导电层电耦合至第二表面的第四导电区域和第六导电区域，并且至少一个电容器的第一端电耦合至第四导电区域或第六导电区域，并且其中第二中间导电层电耦合至第二表面的第五导电区域，并且至少一个电容器的第二端电耦合至第五导电区域。以此方式，可以通过第二表面的导电区域的分布来灵活地根据需求来设置直流母线电容器，从而可以提供所期望的直流电压和纹波电流。
在一些实施例中，设置至少一个电容器包括设置第一组电容器和第二组电容器，并且其中第一组电容器的第一端电耦合至第四导电区域，第二组电容器的第一端电耦合至第六导电区域。以此方式，可以在第二表面上设置较多数目的电容器，从而可以提供稳定的直流电源和足够的纹波电流。
在一些实施例中，该方法还包括：将第五导电区域设置在第四导电区域与第六导电区域之间，并且设置第一组电容器和第二组电容器包括将第一组电容器和第二组电容器并排地设置在第二表面上。以此方式，可以以简单的方式来布置直流母线电容器。
提供发明内容部分是为了简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开的关键特征或主要特征，也无意限制本公开的范围。
附图说明
下文将以明确易懂的方式通过对优选实施例的说明并结合附图来对本公开上述特性、技术特征、优点及其实现方式予以进一步说明，其中：
图1示出了包括半桥的半导体装置的示意电路图；
图2示出了根据本公开的一个实施例的半导体装置的一个示例的示意图；
图3示出了根据本公开的一个实施例的半导体装置的另一示例的示意图；
图4示出了图3的半导体装置的俯视图；
图5示出了图3的半导体装置的仰视图；以及
图6示出了根据本公开的一个实施例的用于提供半导体装置的方法的示意流程图。
附图标记列表：
100：示意电路图
101：上桥臂半导体器件；
102：下桥臂半导体器件；
120：电容器；
110：电流路径；
200：半导体装置；
201：第一开关半导体器件；
202：第二开关半导体器件；
210：基板；
211：第一表面；
212：第二表面；
220：电容器；
251：第一导电区域；
252：第二导电区域；
253：第三导电区域；
300：半导体装置；
301：第一开关半导体器件；
302：第二开关半导体器件；
310：基板；
311：第一表面；
312：第二表面；
321：第一组电容器；
322：第二组电容器；
351：第一导电区域；
352：第二导电区域；
353：第三导电区域；
354：第四导电区域；
355：第五导电区域；
356：第六导电区域；
331：第一中间导电层；
332：第二中间导电层；
341：过孔；
342：过孔；
343：过孔；
344：过孔；
345：过孔。
具体实施方式
下面将参考附图中示出的若干示例实施例来描述本公开的原理。虽然附图中显示了本公开的优选实施例，但应当理解，描述这些实施例仅是为了使本领域技术人员能够更好地理解进而实现本公开，而并非以任何方式限制本公开的范围。
在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。下文还可能包括其他明确的和隐含的定义。
如以上提及的，尽管基于诸如GaN的开关半导体器件具有非常高的开关性能，但是高开关速度也带来一些负面问题，例如过电压。这些问题增加了半导体器件的功率损耗，并且对半导体器件的性能是有损的。
存在一些减少寄生电感的方案。例如，一种集成GaN功率模块包括基于GaN的上桥臂器件和下桥臂器件、母线电容以及基板。上桥臂器件、下桥臂器件和母线电容设置在基板的同一侧表面上，并且母线电容安放在上桥臂器件与下桥臂器件中间。这种传统方案存在一些缺点。例如，由于母线电容放置在GaN半导体器件之间，GaN半桥的输出寄生电感仍然较高。另外，能够设置的母线电容的数目受限，通常仅能设置几个母线电容，因此难以设置足以提供稳定直流电压的母线电容。
可见，这样的传统方案并未解决环路寄生电感的问题。因此，可以通过优化开关半导体器件和相关元件在基板(诸如，电路板)上的布局和/或布线，进一步减小环路寄生电感并提供稳定的直流输出。
根据本公开的实施例，用作半桥桥臂的两个开关半导体器件布置在基板的同一表面上，而母线电容器布置在基板的相对的另一表面上。以此方式，可以减小两个开关半导体器件之间的距离，并且可以灵活地根据需要来设置直流母线电容器。
图1示出了包括半桥的半导体装置的示意电路图100。如示意电路图100所示的电路包括上桥臂半导体器件101、下桥臂半导体器件102和直流母线电容器120。应当理解，尽管仅示出了一个直流母线电容器120，但其可以表示多个直流母线电容器的等效。在使用中，上桥臂半导体器件101的漏极和电容器120的上电极耦合至由DC+表示的第一直流输入端；下桥臂半导体器件102的源极和电容器120的下电极耦合至由DC-表示的第二直流输入端；上桥臂半导体器件101的源极和下桥臂半导体器件102的漏极连接至由OUT表示的输出端子。
直流母线电容器120可以用于提供稳定的DC电压和必要的纹波电流。高的环路电感将在开关节点上引起显著的过冲。过冲导致开关损耗增加，开关损耗的增加又导致效率的降低。如上文所提及的，为了减小甚至最小化这种环路电感，使用布局技术有效消除环路的寄生电感至关重要。
为了减少这种环路电感，一方面可以减小电流路径110的长度。例如，可以减小以下中的一项或多项：上桥臂半导体器件101的漏极与电容器120的上电极之间的距离，下桥臂半导体器件102的源极与电容器120的下电极之间的距离，以及上桥臂半导体器件101的源极与下桥臂半导体器件102的漏极之间的距离。另一方面，可以通过元件和导线的布局来减小或抵消电流流向不同的导体或导电区域间的互感。
以下参考附图来描述本公开的一些示例实施例。图2示出了根据本公开的一个 实施例的半导体装置200的一个示例的示意图。图2所示的半导体装置200包括基板210。基板210可以是例如印刷电路板(PCB)，也可以是能够实现本文所描述的布局和布线的任何形式的载体。基板210具有第一表面211和与第一表面211相对的第二表面212。
第一开关半导体器件201和第二开关半导体器件202被设置在第一表面211上。在本文中，第一开关半导体器件和第二开关半导体器件可以被统称为开关半导体器件或半导体器件。第一开关半导体器件和第二开关半导体器件也可以分别被称为第一半导体器件和第二半导体器件。在一些实施例中，第一开关半导体器件201和第二开关半导体器件202可以是基于GaN的半导体器件，例如基于GaN的FET。在一些实施例中，第一开关半导体器件201和第二开关半导体器件202也可以是其他类型的半导体器件，特别是具有较大开关速度的半导体器件。
第一开关半导体器件201的一端(例如，漏极)电耦合至第一表面211的第一导电区域251，并且另一端(例如，源极)电耦合至第一表面211的第二导电区域252。第二开关半导体器件202的一端(例如，源极)电耦合至第二导电区域252，并且另一端(例如，源极)电耦合至第一表面211的第三导电区域253。在用于诸如转换器或逆变器之类的设备时，第一导电区域251可以电耦合至第一输入端子，例如图2中所示的DC+，同时第三导电区域253可以电耦合至第二输入端子，例如图2中所示的DC-。第二导电区域252可以电耦合至输出端子OUT。在这样的示例中，第一开关半导体器件201和第二开关半导体器件202可以分别用作半桥电路的上桥臂器件和下桥臂器件。
电容器220被设置在基板210的第二表面212上。如本文中所使用的，术语“电容器”指代可以实现电容的任何电容性元件。尽管未示出，但电容器220电耦合至第一导电区域251和第三导电区域253。例如，电容器220的第一端(例如，第一电极)电耦合至第一导电区域251，并且第二端(例如，第二电极)电耦合至第三导电区域253。电容器220可以用作直流母线电容，类似于图1中所示的电容器120。
电容器220可以以各种方式电耦合至第一导电区域251和第三导电区域253。在一些实施例中，电容器220的相应端可以通过管脚、引线、过孔等分别电连接至第一导电区域251和第三导电区域253。在另一些实施例中，电容器220的相应端可以经由设置在基板中的中间导电层而电耦合至第一导电区域251和第三导电区域253， 如下文将参考图3至图5所描述的。
此外，尽管图2中仅示出了一个电容器220，但是可以在第二表面212上设置多个电容器。这些电容器可以以各种相对位置和取向设置在第二表面212上，并且所设置的电容器的数目可以根据需要来确定。
在这样的实施例中，通过将直流母线电容器与开关半导体器件设置在基板的不同表面上，可以在满足其他要求的情况下尽可能的减小两个开关半导体器件之间的距离。以此方式，可以减小上桥臂半导体器件的源极与下桥臂半导体器件的漏极之间电流路径，从而降低环路电感。此外，由于直流母线电容设置在另一表面上，而不是被设置在两个开关半导体器件之间，因此存在更多的空间来根据需求设置更多的电容器。以此方式，有利于提供稳定的电压输出和必要的纹波电流。
下面参考图3至图5来描述根据本公开的一个实施例的半导体装置300。图3示出了根据本公开的一个实施例的半导体装置300的示意图；图4示出了图3的半导体装置300的俯视图；图5示出了图3的半导体装置300的仰视图。
半导体装置300包括基板310，其类似于图2的基板210。基板310例如可以是PCB，也可以是能够实现本文所描述的布局和布线的任何形式的载体。基板310具有第一表面311和与第一表面311相对的第二表面312。
第一开关半导体器件301和第二开关半导体器件302被设置在第一表面311上。第一开关半导体器件301的一端(例如，漏极)电耦合至第一表面311的第一导电区域351，并且另一端(例如，源极)电耦合至第一表面311的第二导电区域352。第二开关半导体器件302的一端(例如，漏极)电耦合至第二导电区域352，并且另一端(例如，源极)电耦合至第一表面311的第三导电区域353。在用于诸如转换器或逆变器之类的设备时，第一导电区域351可以电耦合至第一输入端子，例如图3中所示的DC+，同时第三导电区域353可以电耦合至第二输入端子，例如图3中所示的DC-。第二导电区域352可以电耦合至输出端子OUT。与图2类似，第一开关半导体器件301和第二开关半导体器件302可以分别用作半桥电路的上桥臂器件和下桥臂器件。
第一组电容器321和第二组电容器322被设置在基板310的第二表面312上。在该示例中，第一表面312包括第四导电区域354、第五导电区域355和第六导电区域356。第一组电容器321的一端(例如，第一电极)电耦合至第四导电区域354， 并且另一端(例如，第二电极)电耦合至第五导电区域355。第二组电容器322的一端(例如，第一电极)电耦合至第六导电区域356，并且另一端(例如，第二电极)电耦合至第五导电区域355。
基板310还包括彼此电隔离的第一中间导电层331和第二中间导电层332。如图3所示，第一中间导电层331经由过孔341电耦合至第一导电区域351，经由过孔344电耦合至第四导电区域354，并且经由过孔345电耦合至第六导电区域356。由此，第四导电区域354和第六导电区域356经由第一中间导电层331电耦合至第一导电区域351。在第一导电区域351电耦合至DC+的情况下，第一中间导电层331、第四导电区域354和第六导电区域356也电耦合至DC+。
第二中间导电层332经由过孔342电耦合至第三导电区域353，经由过孔343电耦合至第五导电区域355。由此，第五导电区域355经由第二中间导电层332电耦合至第三导电区域353。在第三导电区域353电耦合至DC-的情况下，第二中间导电层332和第五导电区域355也电耦合至DC-。
应当理解，图3至图5中所示的过孔的分布仅是示意性的，而无意限制。在本公开的实施例中，可以以各种方式来布置过孔。例如，尽管在图3中将过孔341和过孔344示出为在竖直方向上对齐，但它们在竖直方向也可以间隔开。另外，第一中间导电层311和第二中间导电层312的相对位置和大小也是示意性的。例如，第一中间导电层也可以被设置在第二中间导电层的上方。
另外，尽管在图3所示的截面中，第一中间导电层311被示出为包括分别在过孔343左侧和右侧的两部分，但应当理解，从垂直于基板310法线的方向来观察，这两部分是整体。
在使用中，第一中间导电层331和第二中间导电层332将分别电耦合至DC+与DC-。利用这种叠层布置，可以减少互感，从而有利于进一步减小环路电感。
在图4所示的俯视图中，第二导电区域352被设置在第一导电区域351与第三导电区域353之间，并且第一开关半导体器件301和第二开关半导体器件302被并排地设置在第一表面311上。以此方式，可以进一步减小作为桥臂的两个开关半导体器件之间的电流路径，从而降低环路电感。
图4中所示的第一、第二和第三导电区域的形状和相对布置仅是示意性的，而无意限制。第一、第二和第三导电区域可以呈其他形状，例如椭圆形。也可以将第一、 第二和第三导电区域设置成其他的相对取向，例如呈“L”形，其中第一和第三导电区域位于“L”形的边，而第二导电区域位于“L”形的拐角。
在图5所示的仰视图中，第五导电区域355被设置在第四导电区域354与第六导电区域356之间。第一组电容器321的一端电耦合至第四导电区域354，并且另一端电耦合至第五导电区域355。第二组电容器322的一端电耦合至第六导电区域356，并且另一端也电耦合至第五导电区域355。应当理解，图5中所示的第一组电容器321和第二组电容器322的数目和布置仅是示意性的，而无意限制。在本公开的实施例中，可以包括任何合适数目的电容器，并且第一组电容器和第二组电容器的数目不必相同。
图5中所示的第四、第五和第六导电区域的形状和相对布置仅是示意性的，而无意限制。第四、第五和第六导电区域也可以呈其他形状，和/或被设置成其他的相对取向，如上文关于第一、第二和第三导电区域所讨论的。另外，图3和图5中所示的第二表面312所包括的导电区域的数目仅是示意性的，第二表面312可以包括更多或更少数目的导电区域。
返回参考图2。在一些实施例中，电容器220所设置于的第二表面212可以包括两个导电区域，电容器220的两个电极分别电耦合至这两个导电区域。在一个示例中，这两个导电区域可以经由基板210中的过孔(未示出)分别电耦合至第一导电区域251和第三导电区域253。在这样的情况下，第二表面212的两个导电区域可以分别与第一导电区域251和第三导电区域253大体上对齐。在另一示例中，这两个导电区域可以分别经由设置在基板210中的两个中间导电层(类似于图3中所示的中间导电层311和312)电耦合至第一导电区域251和第三导电区域253。
可以用各种导电材料实现图2至图5中所描述的导电区域和中间导电层。这样的导电材料可以包括但不限于铜、铂等。在一些实施例中，导电区域和中间导电层中的一些或全部可以用铜层来实现。以此方式，可以有助于进一步减小环路电感。
根据本公开的半导体装置(诸如，半导体装置200、300)可以用于各种电力电子设备中。例如，可以用于功率设备，包括但不限于功率转换器、逆变器、驱动器等。在使用中，例如，第一导电区域251、351可以电耦合至诸如DC+的第一直流端子，第三导电区域253、353可以电耦合至诸如DC-的第二直流端子，并且第二导电区域252、352可以电耦合至输出端子。
图6示出了根据本公开的一个实施例的用于提供半导体装置的方法600的示意流程图。在610处，提供基板，诸如基板210、310。在620处，在基板的第一表面上设置第一开关半导体器件。该第一开关半导体器件的第一端电耦合至第一表面的第一导电区域并且第二端电耦合至第一表面的第二导电区域。例如，在基板210的第一表面211上设置第一开关半导体器件201。
在630处，在第一表面上设置第二开关半导体器件。该第二开关半导体器件的第一端电耦合至第二导电区域并且第二端电耦合至第一表面的第三导电区域。例如，在基板210的第一表面211上设置第二开关半导体器件202。
在640处，在基板的与第一表面相对的第二表面上设置至少一个电容器。该至少一个电容器的第一端电耦合至第一导电区域并且第二端电耦合至第三导电区域。例如，在基板210的第二表面212上设置电容器220。
可以理解，上面参考图2-图5所描述的特征可以被应用至图6的方法600。
在一些实施例中，提供基板可以包括：在第一表面与第二表面之间设置第一中间导电层以及与第一中间导电层电隔离的第二中间导电层。至少一个电容器的第一端经由该第一中间导电层电耦合至第一导电区域，并且第二端经由第二中间导电层电耦合至所述第三导电区域。例如，可以在基板310的第一表面311与第二表面312之间设置第一中间导电层331和第二中间导电层332。
在一些实施例中，第一中间导电层电耦合至第二表面的第四导电区域和第六导电区域，并且至少一个电容器的第一端电耦合至第四导电区域或第六导电区域。第二中间导电层电耦合至第二表面的第五导电区域，并且至少一个电容器的所述第二端电耦合至第五导电区域。
在一些实施例中，设置至少一个电容器包括设置第一组电容器和第二组电容器。第一组电容器的第一端电耦合至第四导电区域，第二组电容器的第一端电耦合至第六导电区域。
在一些实施例中，方法600还可以包括：将第五导电区域设置在第四导电区域与第六导电区域之间。设置第一组电容器和第二组电容器包括将第一组电容器和第二组电容器并排地设置在第二表面上。例如，将第一组电容器321和第二组电容器322并排地设备在第二表面312上。
应当理解，尽管在上文的详细描述中提及了设备的若干装置或子装置，但是这 种划分仅仅是示例性而非强制性的。实际上，根据本公开的实施例，上文描述的两个或更多装置的特征和功能可以在一个装置中具体化。反之，上文描述的一个装置的特征和功能可以进一步划分为由多个装置来具体化。
以上所述仅为本公开的可选实施例，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等效替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种半导体装置(200、300)，包括：
    基板(210、310)；
    第一开关半导体器件(201、301)，设置在所述基板(210、310)的第一表面(211、311)上，所述第一开关半导体器件(201、301)的第一端电耦合至所述第一表面(211、311)的第一导电区域(251、351)并且第二端电耦合至所述第一表面(211、311)的第二导电区域(252、352)；
    第二开关半导体器件(202、302)，设置在所述第一表面(211、311)上，所述第二开关半导体器件(202、302)的第一端电耦合至所述第二导电区域(252、352)并且第二端电耦合至所述第一表面(211、311)的第三导电区域(253、353)；以及
    至少一个电容器(220、321、322)，设置在所述基板(210、310)的与所述第一表面(211、311)相对的第二表面(212、312)上，所述至少一个电容器(220、321、322)的第一端电耦合至所述第一导电区域(251、351)并且第二端电耦合至所述第三导电区域(253、353)。
  2. 根据权利要求1所述的半导体装置(200、300)，其中所述基板(210、310)包括：
    第一中间导电层(331)，设置在所述第一表面(211、311)与所述第二表面(212、312)之间，所述至少一个电容器(220、321、322)的所述第一端经由所述第一中间导电层(331)电耦合至所述第一导电区域(251、351)；以及
    第二中间导电层(332)，设置在所述第一表面(211、311)与所述第二表面(212、312)之间并且与所述第一中间导电层(331)电隔离，所述至少一个电容器(220、321、322)的所述第二端经由所述第二中间导电层(332)电耦合至所述第三导电区域(253、353)。
  3. 根据权利要求2所述的半导体装置(200、300)，其中所述第一中间导电层(331)电耦合至所述第二表面(212、312)的第四导电区域(354)和第六导电区域(356)，并且所述至少一个电容器(220、321、322)的所述第一端电耦合至所述第四导电区域(354)或所述第六导电区域(356)，并且
    其中所述第二中间导电层(332)电耦合至所述第二表面(212、312)的第五导 电区域(355)，并且所述至少一个电容器(220、321、322)的所述第二端电耦合至所述第五导电区域(355)。
  4. 根据权利要求3所述的半导体装置(200、300)，其中所述至少一个电容器(220、321、322)包括第一组电容器(321)和第二组电容器(322)，并且
    其中所述第一组电容器(321)的所述第一端电耦合至所述第四导电区域(354)，并且所述第二组电容器(322)的所述第一端电耦合至所述第六导电区域(356)。
  5. 根据权利要求4所述的半导体装置(200、300)，其中所述第五导电区域(355)被设置在所述第四导电区域(354)与所述第六导电区域(356)之间，并且
    其中所述第一组电容器(321)和所述第二组电容器(322)被并排地设置在所述第二表面(212、312)上。
  6. 根据权利要求1所述的半导体装置(200、300)，其中所述至少一个电容器(220)的所述第一端电耦合至所述第二表面(212、312)的第七导电区域，所述第七导电区域电耦合至所述第一导电区域(251、351)，并且
    其中所述至少一个电容器(220)的所述第二端电耦合至所述第二表面(212、312)的第八导电区域，所述第八导电区域电耦合至所述第三导电区域(253、353)。
  7. 根据权利要求6所述的半导体装置(200、300)，其中所述第七导电区域经由过孔而电耦合至所述第一导电区域(251、351)，并且其中所述第八导电区域经由另外的过孔而电耦合至所述第三导电区域(253、353)。
  8. 根据权利要求1-7中的任一项所述的半导体装置(200、300)，其中所述第二导电区域(252、352)设置在所述第一导电区域(251、351)与所述第三导电区域(253、353)之间，并且所述第一开关半导体器件(201、301)和所述第二开关半导体器件(202、302)被并排地设置在所述第一表面(211、311)上。
  9. 根据权利要求1-7中的任一项所述的半导体装置(200、300)，其中所述第一开关半导体器件(201、301)和所述第二开关半导体器件(202、302)中的至少一个包括基于氮化镓的半导体器件。
  10. 根据权利要求1-7中的任一项所述的半导体装置(200、300)，其中所述基板(210、310)包括印刷电路板。
  11. 一种用于功率转换的设备，包括：
    根据权利要求1-10中的任一项所述的半导体装置(200、300)；
    第一直流端子，电耦合至所述第一导电区域(251、351)；
    第二直流端子，电耦合至所述第三导电区域(253、353)；以及
    输出端子，电耦合至所述第二导电区域(252、352)。
  12. 一种提供半导体装置(200、300)的方法(600)，包括：
    提供(610)基板(210、310)；
    在所述基板(210、310)的第一表面(211、311)上设置(620)第一开关半导体器件(201、301)，所述第一开关半导体器件(201、301)的第一端电耦合至所述第一表面(211、311)的第一导电区域(251、351)并且第二端电耦合至所述第一表面(211、311)的第二导电区域(252、352)；
    在所述第一表面(211、311)上设置(630)第二开关半导体器件(202、302)，所述第二开关半导体器件(202、302)的第一端电耦合至所述第二导电区域(252、352)并且第二端电耦合至所述第一表面(211、311)的第三导电区域(253、353)；以及
    在所述基板(210、310)的与所述第一表面(211、311)相对的第二表面(212、312)上设置(640)至少一个电容器(220、321、322)，所述至少一个电容器(220、321、322)的第一端电耦合至所述第一导电区域(251、351)并且第二端电耦合至所述第三导电区域(253、353)。
  13. 根据权利要求12所述的方法(600)，其中提供所述基板(210、310)包括：
    在所述第一表面(211、311)与所述第二表面(212、312)之间设置第一中间导电层(331)，所述至少一个电容器(220、321、322)的所述第一端经由所述第一中间导电层(331)电耦合至所述第一导电区域(251、351)；以及
    在所述第一表面(211、311)与所述第二表面(212、312)之间设置与所述第一中间导电层(331)电隔离的第二中间导电层(332)，所述至少一个电容器(220、321、322)的所述第二端经由所述第二中间导电层(332)电耦合至所述第三导电区域(253、353)。
  14. 根据权利要求13所述的方法(600)，其中所述第一中间导电层(331)电耦合至所述第二表面(212、312)的第四导电区域(354)和第六导电区域(356)，并且所述至少一个电容器(220、321、322)的所述第一端电耦合至所述第四导电区域(354)或所述第六导电区域(356)，并且
    其中所述第二中间导电层(332)电耦合至所述第二表面(212、312)的第五导电区域(355)，并且所述至少一个电容器(220、321、322)的所述第二端电耦合至所述第五导电区域(355)。
  15. 根据权利要求14所述的方法(600)，其中设置所述至少一个电容器(220、321、322)包括设置第一组电容器(321)和第二组电容器(322)，并且
    其中所述第一组电容器(321)的所述第一端电耦合至所述第四导电区域(354)，所述第二组电容器(322)的所述第一端电耦合至所述第六导电区域(356)。
  16. 根据权利要求15所述的方法(600)，还包括：将所述第五导电区域(355)设置在所述第四导电区域(354)与所述第六导电区域(356)之间，并且
    其中设置所述第一组电容器(321)和所述第二组电容器(322)包括将所述第一组电容器(321)和所述第二组电容器(322)并排地设置在所述第二表面(212、312)上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023039576A1 (en) * 2021-09-13 2023-03-16 Efficient Power Conversion Corporation Half-bridge switching circuits with parallel switches

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090002956A1 (en) * 2007-06-22 2009-01-01 Hitachi, Ltd. Power Converter
CN104112718A (zh) * 2014-07-25 2014-10-22 西安交通大学 一种双面布局的低寄生电感GaN功率集成模块
CN104143547A (zh) * 2014-07-25 2014-11-12 西安交通大学 一种并联电容中间布局的低寄生电感GaN功率集成模块
CN207303085U (zh) * 2016-06-23 2018-05-01 瑞萨电子株式会社 电子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090002956A1 (en) * 2007-06-22 2009-01-01 Hitachi, Ltd. Power Converter
CN104112718A (zh) * 2014-07-25 2014-10-22 西安交通大学 一种双面布局的低寄生电感GaN功率集成模块
CN104143547A (zh) * 2014-07-25 2014-11-12 西安交通大学 一种并联电容中间布局的低寄生电感GaN功率集成模块
CN207303085U (zh) * 2016-06-23 2018-05-01 瑞萨电子株式会社 电子装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023039576A1 (en) * 2021-09-13 2023-03-16 Efficient Power Conversion Corporation Half-bridge switching circuits with parallel switches
TWI825986B (zh) * 2021-09-13 2023-12-11 美商高效電源轉換公司 用於具並聯開關之半橋切換電路之電路板布局

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