WO2021051819A1 - 一种平板探测器及其制造方法 - Google Patents

一种平板探测器及其制造方法 Download PDF

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WO2021051819A1
WO2021051819A1 PCT/CN2020/087691 CN2020087691W WO2021051819A1 WO 2021051819 A1 WO2021051819 A1 WO 2021051819A1 CN 2020087691 W CN2020087691 W CN 2020087691W WO 2021051819 A1 WO2021051819 A1 WO 2021051819A1
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layer
insulating layer
barrier
tft device
interlayer insulating
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PCT/CN2020/087691
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English (en)
French (fr)
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陈钢
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南京迪钛飞光电科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/115—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the technical field of flat panel detectors, in particular to a flat panel detector and a manufacturing method thereof.
  • the X-ray of the flat-panel detector is first converted into visible light by the fluorescent medium material, and then the visible light signal is converted into an electric signal by the photosensitive element, and finally the analog electric signal is converted into a digital signal by A/D.
  • the flat panel detector includes a gate electrode 10, a gate insulating layer 20 covering the gate electrode 10, a semiconductor layer 30 on the gate insulating layer 20, an etching barrier layer 40 covering the semiconductor layer 30,
  • the etch stop layer 40 is in contact with the source 51 and the drain 52 of the semiconductor layer 30, the first insulating layer 60 covering the source 51 and the drain 52, the interlayer insulating layer 70 located on the first insulating layer 60, A cathode electrode 80 connected to the drain 52 on the interlayer insulating layer 70 and passing through the first insulating layer 60 and the interlayer insulating layer 70, a photoelectric conversion layer (PIN, Photo Diode) 90 on the cathode electrode 80, and a photoelectric conversion layer (PIN, Photo Diode) 90 located on the cathode electrode 80.
  • the semiconductor layer 30 needs to be insulated from hydrogen ions during the manufacturing process to prevent the characteristics of the semiconductor material from changing. In the process of manufacturing the photoelectric conversion layer 90, a large amount of hydrogen is needed. If hydrogen ions diffuse into the semiconductor layer 30, the TFT device may fail in severe cases.
  • the flat-panel detector needs to irradiate the detection panel under X-ray or visible light.
  • the ambient light is irradiated on the semiconductor layer 30, and the leakage current of the TFT increases due to the illumination, and the Vth drifts, which reduces the detection sensitivity of the photodetector and improves noise interference.
  • the object of the present invention is to provide a flat-panel detector that blocks the influence of various substances on the semiconductor layer and a manufacturing method thereof.
  • the invention provides a flat panel detector, which includes a TFT device with a semiconductor layer, a first insulating layer covering the TFT device, an interlayer insulating layer on the first insulating layer, and an interlayer insulating layer on the interlayer insulating layer and connected to the TFT device
  • the cathode electrode, the photoelectric conversion layer located on the cathode electrode further comprising a barrier layer located on the interlayer insulating layer; at least part of the barrier layer is in a floating state, and at least part of the barrier layer is located directly above the semiconductor layer.
  • the present invention also provides a flat panel detector, which includes a TFT device with a semiconductor layer, a first insulating layer covering the TFT device, an interlayer insulating layer on the first insulating layer, and a second insulating layer on the interlayer insulating layer.
  • Layer a cathode electrode located on the second insulating layer and connected to the TFT device, and a photoelectric conversion layer located on the cathode electrode; characterized in that it also includes a barrier layer located between the interlayer insulating layer and the second insulating layer; at least part of The barrier layer is located directly above the semiconductor layer, and at least part of the barrier layer is located below the photoelectric conversion layer.
  • barrier layer is linear.
  • the barrier layer includes a linear first barrier body and a second barrier body connected to one end of the first barrier body and close to the photoelectric conversion layer, and a sandwich between the first barrier body and the second barrier body The angle is obtuse.
  • the barrier layer includes a linear first barrier, a second barrier connected to one end of the first barrier, and a third barrier connected to the other end of the first barrier.
  • the first barrier is connected to the The angle between the second barrier and the third barrier is an obtuse angle.
  • the forming material of the barrier layer is the same as the material of the cathode electrode.
  • the present invention also provides a method for manufacturing a flat panel detector, which includes the following steps:
  • a photoelectric conversion layer is formed on the cathode electrode.
  • the present invention also provides a method for manufacturing a flat panel detector, which includes the following steps:
  • a cathode metal material is used in the interlayer insulating layer to form a barrier layer and a cathode electrode at the same time, the cathode electrode is connected to the TFT device through a contact hole, and the barrier layer is located on the surface of the interlayer insulating layer and in the barrier contact hole;
  • a photoelectric conversion layer is formed on the cathode electrode.
  • the present invention also provides a method for manufacturing a flat panel detector, which includes the following steps:
  • a photoelectric conversion layer is formed on the cathode electrode.
  • the present invention also provides a method for manufacturing a flat panel detector, which includes the following steps:
  • a photoelectric conversion layer is formed on the cathode electrode.
  • the flat panel detector of the present invention is provided with a barrier layer, at least part of the barrier layer is located directly above the semiconductor layer, the barrier layer can block the impact of hydrogen diffusion on the semiconductor layer when the photoelectric conversion layer is formed, and can also block the effect of X-rays or ambient light on the semiconductor layer. influences.
  • Figure 1 is a schematic diagram of the structure of an existing flat panel detector
  • FIG. 2 is a schematic structural diagram of the first embodiment of the flat panel detector of the present invention.
  • FIG. 3 is a schematic diagram of the structure of the second embodiment of the flat panel detector of the present invention.
  • FIG. 4 is a schematic structural diagram of a third embodiment of the flat panel detector of the present invention.
  • Fig. 5 is a schematic structural diagram of a fourth embodiment of a flat panel detector of the present invention.
  • Fig. 2 is a schematic structural diagram of the first embodiment of the flat panel detector of the present invention.
  • the flat panel detector includes a TFT device with a semiconductor layer 30, a first insulating layer 60 covering the TFT device 100, an interlayer insulating layer 70 on the first insulating layer 60, and an interlayer insulating layer 70.
  • the cathode electrode 80 connected to the TFT device 100 after passing through the first insulating layer 60 and the interlayer insulating layer 70, the photoelectric conversion layer (PIN, Photo Diode) 90 on the cathode electrode 80, and the photoelectric conversion layer 90 on the photoelectric conversion layer 90
  • the anode electrode 100 and the barrier layer 110 located between the semiconductor layer 30 and the photoelectric conversion layer 90, at least part of the barrier layer 110 is located directly above the semiconductor layer 30 of the TFT device.
  • the TFT device 100 includes a gate electrode 10, a gate insulating layer 20 covering the gate electrode 10, a semiconductor layer 30 on the gate insulating layer 20, an etching stopper layer 40 covering the semiconductor layer 30, and after passing through the etching stop layer 40
  • the source 51 and the drain 52 are both in contact with the semiconductor layer 30.
  • the first insulating layer 60 covers the source 51 and the drain 52, and the cathode electrode 80 is connected to the drain 52 of the TFT device 100.
  • the cathode electrode 80 is made of a cathode metal material with a low work function, such as silver, titanium, aluminum, molybdenum, or niobium.
  • the photoelectric conversion layer 90 includes an N-type amorphous silicon semiconductor layer 91 on the cathode electrode 80, an amorphous silicon intrinsic layer 91 on the N-type amorphous silicon semiconductor layer 91, and a P-type amorphous silicon semiconductor layer 91 on the amorphous silicon intrinsic layer 91.
  • Amorphous silicon semiconductor layer 93 is made of a cathode metal material with a low work function, such as silver, titanium, aluminum, molybdenum, or niobium.
  • the semiconductor layer 30 is a metal oxide semiconductor layer, and may also be a semiconductor layer of amorphous silicon or polysilicon, and is preferably a metal oxide semiconductor layer, such as IGZO.
  • the semiconductor layer 30 is a metal oxide, the flat panel detector has the advantages of low leakage current and high electron mobility.
  • the interlayer insulating layer 70 is an organic insulating layer, but may also be an inorganic insulating layer.
  • the barrier layer 120 is linear and is formed at the same time as the cathode electrode 80.
  • the barrier layer 120 does not contact the cathode electrode 80, and the barrier layer 120 is located on the interlayer insulating layer 70.
  • the invention also discloses a method for manufacturing a flat panel detector, which includes the following steps:
  • S5 forming a photoelectric conversion layer 90 on the cathode electrode 80 (the specific method is: first, an N-type amorphous silicon semiconductor layer 91, an amorphous silicon intrinsic layer 91, and a P-type amorphous silicon semiconductor layer are sequentially formed on the cathode electrode 80 93);
  • the anode electrode 100 is formed on the photoelectric conversion layer 90.
  • the barrier layer 120 Since the barrier layer 120 is not covered with other objects, the barrier layer 120 is in a floating state, which can directly block the influence of hydrogen diffusion on the semiconductor layer 30 when the photoelectric conversion layer 90 is formed, and can also block the influence of X-rays or ambient light on the semiconductor layer 30.
  • step S1 are: sequentially forming the gate electrode 10, forming a gate insulating layer 20 covering the gate electrode 10, forming a semiconductor layer 30 above the gate electrode 10 on the gate insulating layer 20, and forming a covering semiconductor layer 30, the stop layer 40 is etched and the source contact hole (not shown) and the drain contact hole (not shown) on the semiconductor layer 30 are formed, and the source 51 and the drain 52 are formed, and the source 51 passes through the source
  • the electrode contact hole is connected to the semiconductor layer 30, and the drain electrode 52 is connected to the semiconductor layer 30 through the drain contact hole.
  • the flat panel detector is formed by the above method.
  • At least part of the barrier layer 120 is located directly above the semiconductor layer 30.
  • the barrier layer 120 can block the influence of hydrogen diffusion on the semiconductor layer 30 when the photoelectric conversion layer 90 is formed, and can also block X-rays or ambient light from affecting the semiconductor layer 30. The influence of the semiconductor layer 30.
  • Fig. 3 is a schematic diagram of the structure of the second embodiment of the flat panel detector of the present invention.
  • the barrier layer 130 includes a linear first barrier 131 and a second barrier 132 connected to one end of the first barrier 131 and close to the photoelectric conversion layer 90.
  • the angle between the one blocking body 131 and the second blocking body 132 is an obtuse angle.
  • the second barrier 132 can block the influence of hydrogen diffusion on the semiconductor layer 30 during the manufacturing process of the photoelectric conversion layer 90, and the first barrier 131 can block the influence of X-rays or ambient light on the semiconductor layer 30.
  • the barrier layer 130 includes a linear first barrier 131, a second barrier 132 connected to one end of the first barrier 131, and a second barrier connected to the other end of the first barrier 131.
  • the angles between the first stopper 131 and the second stopper 132 and the third stopper 133 are obtuse angles.
  • the third stopper 133 can block X-rays or ambient light from the side. The impact of layer 30.
  • the first barrier 131 is located on the surface of the interlayer insulating layer 70, and the second barrier 132 and the third barrier 133 are located within the interlayer insulating layer 70.
  • the second barrier body 132 and the third barrier body 133 are formed on the interlayer insulating layer 70 by using a semi-transparent and semi-reverse mask to form the first barrier body 131 and the second barrier body 132 and the third barrier body 133 respectively.
  • the angle between is the effect of obtuse angle.
  • a barrier contact hole needs to be opened in the interlayer insulating layer 70, and the barrier contact hole may be formed at the same time as the contact hole.
  • the invention also discloses a method for manufacturing a flat panel detector, which includes the following steps:
  • the barrier layer 120 and the cathode electrode 80 are simultaneously formed by using a cathode metal material on the interlayer insulating layer 70, the cathode electrode 80 is connected to the drain 52 through a contact hole, and the barrier layer 120 is located on the surface of the interlayer insulating layer 70 and in the barrier contact hole;
  • S5 forming a photoelectric conversion layer 90 on the cathode electrode 80 (the specific method is: first, an N-type amorphous silicon semiconductor layer 91, an amorphous silicon intrinsic layer 91, and a P-type amorphous silicon semiconductor layer are sequentially formed on the cathode electrode 80 93);
  • the anode electrode 100 is formed on the photoelectric conversion layer 90.
  • Fig. 4 is a schematic structural diagram of a third embodiment of a flat-panel detector of the present invention.
  • a second insulating layer 61 is provided on the barrier layer 140 and a part of the barrier layer 140 is located below the photoelectric conversion layer 90, so that the barrier layer 140 is in a stable state; the cathode electrode 80 The cathode electrode is disposed on the second insulating layer 61 and connected to the drain 52 after passing through the second insulating layer 61, the interlayer insulating layer 70 and the first insulating layer 60.
  • At least part of the barrier layer 130 is located directly above the semiconductor layer 30.
  • the first insulating layer 60 and the second insulating layer 61 are both inorganic insulating layers.
  • the invention also discloses a method for manufacturing a flat panel detector, which includes the following steps:
  • S7 forming a photoelectric conversion layer 90 on the cathode electrode 80 (the specific method is: first, an N-type amorphous silicon semiconductor layer 91, an amorphous silicon intrinsic layer 91, and a P-type amorphous silicon semiconductor layer are sequentially formed on the cathode electrode 80 93);
  • the pixel electrode layer 100 is formed on the photoelectric conversion layer 90.
  • Part of the barrier layer 140 is located below the photoelectric conversion layer 90, so that the barrier layer 130 can better block the influence of hydrogen diffusion on the semiconductor layer 30 when the photoelectric conversion layer 90 is formed, and can also block the influence of X-rays or ambient light on the semiconductor layer 30
  • the second insulating layer 61 can also block the influence of hydrogen diffusion on the semiconductor 30.
  • Fig. 5 is a schematic structural diagram of a fourth embodiment of a flat panel detector of the present invention.
  • the shape of the barrier layer 150 is the same as the formation of the barrier layer of the second embodiment, that is, the barrier layer 150 is located on the interlayer insulating layer 70, and then the second insulating layer 61 is used.
  • the barrier layer 150 is covered, so that the barrier layer 150 can be in a stable state.
  • the barrier layer 150 is formed separately, and its material may be cathode metal or other metal materials.
  • the barrier layer 150 includes a linear first barrier 151, a second barrier 152 connected to one end of the first barrier 151 and close to the photoelectric conversion layer 90, and a sandwich between the first barrier 151 and the second barrier 152.
  • the angle is obtuse.
  • Part of the first barrier 151 is located below the photoelectric conversion layer 90.
  • the second barrier 152 can block the influence of hydrogen diffusion on the semiconductor layer 30 during the manufacturing process of the photoelectric conversion layer 90.
  • the first barrier 151 can block X-rays or ambient light. Impact on the semiconductor layer 30.
  • the barrier layer 150 includes a linear first barrier body 151, a second barrier body 152 connected to one end of the first barrier body 151, and a second barrier body 152 connected to the other end of the first barrier body 151.
  • the angles between the first stopper 131 and the second stopper 152 and the third stopper 153 are obtuse angles.
  • the third stopper 132 can block X-rays or ambient light from the side. The impact of layer 30.
  • the first barrier 151 is located on the surface of the interlayer insulating layer 70, and the second barrier 152 and the third barrier 153 are located within the interlayer insulating layer 70.
  • the invention also discloses a method for manufacturing a flat panel detector, which includes the following steps:
  • the barrier layer 150 is formed by using a cathode metal material or other metal materials on the interlayer insulating layer 70, and the barrier layer 150 is located on the surface of the interlayer insulating layer 70 and in the barrier contact hole;
  • S7 forming a photoelectric conversion layer 90 on the cathode electrode 80 (the specific method is: first, an N-type amorphous silicon semiconductor layer 91, an amorphous silicon intrinsic layer 91, and a P-type amorphous silicon semiconductor layer are sequentially formed on the cathode electrode 80 93);
  • the pixel electrode layer 100 is formed on the photoelectric conversion layer 90.
  • Part of the barrier layer 150 is located below the photoelectric conversion layer 90, so that the barrier layer 150 can better block the influence of hydrogen diffusion on the semiconductor layer 30 when the photoelectric conversion layer 90 is formed, and can also block the influence of X-rays or ambient light on the semiconductor layer 30
  • the second insulating layer 61 can also block the influence of hydrogen diffusion on the semiconductor 30.
  • first to fourth embodiments may not be provided with an etching stop layer, and the description will not be repeated here.
  • the gates 10 of the TFT devices in the first to fourth embodiments described above are all located at the bottom.
  • the gates of the TFT devices may also be located at the top, that is, the TFT devices include a semiconductor layer and a gate covering the semiconductor layer.
  • step S1 When the gate of the TFT device is on the top, the specific steps of step S1 are: sequentially forming a semiconductor layer, forming a gate insulating layer covering the semiconductor layer, forming a gate located above the semiconductor layer on the gate insulating layer, and forming uniform Source and drain in contact with the semiconductor layer.
  • the flat panel detector of the present invention is provided with a barrier layer, at least part of the barrier layer is located directly above the semiconductor layer, the barrier layer can block the impact of hydrogen diffusion on the semiconductor layer when the photoelectric conversion layer is formed, and can also block the effect of X-rays or ambient light on the semiconductor layer. influences.

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Abstract

一种平板探测器及其制造方法，一种平板探测器包括具有半导体层（30）的TFT器件、覆盖TFT器件的第一绝缘层（60）、位于第一绝缘层（60）上的层间绝缘层（70）、位于层间绝缘层（70）上且与TFT器件连接的阴极电极（80）、位于阴极电极（80）上的光电转换层（90）；还包括位于层间绝缘层（70）上的阻挡层（120）；至少部分所述阻挡层（120）呈浮动状态，至少部分所述阻挡层（120）位于所述半导体层（30）的正上方。平板探测器上设置阻挡层（120），至少部分阻挡层（120）位于半导体层（30）的正上方，阻挡层（120）可以阻挡光电转换层形成时氢气扩散对半导体层（30）的影响、也可以阻挡X射线或环境光对半导体层（30）的影响。

Description

一种平板探测器及其制造方法 技术领域
本发明涉及平板探测器的技术领域，尤其涉及一种平板探测器及其制造方法。
背景技术
平板探测器的X线先经荧光介质材料转换成可见光，再由光敏元件将可见光信号转换成电信号，最后将模拟电信号经A/D转换成数字信号。
如图1所示，平板探测器包括栅极10、覆盖栅极10的栅极绝缘层20、位于栅极绝缘层20上的半导体层30、覆盖半导体层30的刻蚀阻挡层40、穿过刻蚀阻挡层40均与半导体层30接触的源极51和漏极52、覆盖源极51和漏极52的第一绝缘层60、位于第一绝缘层60上的层间绝缘层70、位于层间绝缘层70上且穿过第一绝缘层60和层间绝缘层70后与漏极52连接的阴极电极80、位于阴极电极80上的光电转换层(PIN,Photo Diode)90以及位于光电转换层90上的阳极电极100。
半导体层30在制作过程中需要隔绝氢离子，以防止半导体材料的特性发生变化。在光电转换层90制作过程中，需要用到大量的氢气，如果氢离子扩散进半导体层30，严重的情况下会造成TFT器件失效。
平板探测器需要将检测面板置于X光或者可见光下进行照射，环境光照射到半导体层30上，因光照导致TFT漏电流增加，Vth漂移，降低光电探测器的检测灵敏度，提高噪声的干扰。
发明内容
本发明的目的在提供一种阻挡各种物质对半导体层影响的平板探测器及其制造方法。
本发明提供一种平板探测器，其包括具有半导体层的TFT器件、覆盖TFT器件的第一绝缘层、位于第一绝缘层上的层间绝缘层、位于层间绝缘层上且与TFT器件连接的阴极电极、位于阴极电极上的光电转换层；还包括位于层间绝缘层上的阻挡层；至少部分所述阻挡层呈浮动状态，至少部分所述阻挡层位于所述半导体层的正上方。
本发明还提供一种平板探测器，其包括具有半导体层的TFT器件、覆盖TFT器件的第一绝缘层、位于第一绝缘层上的层间绝缘层、位于层间绝缘层上的第二绝缘层、位于第二绝缘层上且与TFT器件连接的阴极电极、位于阴极电极上的光电转换层；其特征在于，还包括位于层间绝缘层和第二绝缘层之间的阻挡层；至少部分所述阻挡层位于所述半导体层的正上方，至少部分所述阻挡层位于所述光电转换层的下方。
进一步地，所述阻挡层呈直线状。
进一步地，所述阻挡层包括呈直线状的第一阻挡体以及与第一阻挡体一端连接且靠近光电转换层的第二阻挡体，所述第一阻挡体和第二阻挡体之间的夹角为钝角。
进一步地，所述阻挡层包括呈直线状的第一阻挡体、与第一阻挡体一端连接的第二阻挡体以及与第一阻挡体另一端连接的第三阻挡体，第一阻挡体分别与第二阻挡体和第三阻挡体之间的夹角为钝角。
进一步地，所述阻挡层的形成材料与所述阴极电极的材料相同。
本发明还提供一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件；
S2：形成覆盖TFT器件的第一绝缘层；
S3：第一绝缘层上铺设层间绝缘层并形成位于TFT器件上的接触孔；
S4：在层间绝缘层采用阴极金属材料同时形成阻挡层和阴极电极，且阴极电极通过接触孔与TFT器件连接；
S5：在阴极电极上形成光电转换层。
本发明还提供一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件；
S2：形成覆盖TFT器件的第一绝缘层；
S3：第一绝缘层上铺设层间绝缘层，然后形成位于TFT器件上的接触孔以及位于层间绝缘层内的阻挡接触孔；
S4：在层间绝缘层采用阴极金属材料同时形成阻挡层和阴极电极，阴极电极通过接触孔与TFT器件连接，阻挡层位于层间绝缘层表面和阻挡接触孔内；
S5：在阴极电极上形成光电转换层。
本发明还提供一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件；
S2：形成覆盖TFT器件的第一绝缘层；
S3：第一绝缘层上铺设层间绝缘层并形成位于TFT器件上的接触孔；
S4：在层间绝缘层采用阴极金属材料或其他金属材料形成阻挡层；
S5：形成覆盖阻挡层和层间绝缘层的第二绝缘层、并形成位于TFT器件的TFT器件上的接触孔；
S6：形成阴极电极，且阴极电极通过接触孔与TFT器件连接；
S7：在阴极电极上形成光电转换层。
本发明还提供一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件；
S2：形成覆盖TFT器件的第一绝缘层；
S3：第一绝缘层上铺设层间绝缘层并形成位于漏极上的接触孔和位于层间绝缘层内的阻挡接触孔；
S4：在层间绝缘层采用阴极金属材料或其他金属材料形成阻挡层，阻挡层位于层间绝缘层表面和阻挡接触孔内；
S5：形成覆盖阻挡层和层间绝缘层的第二绝缘层、并形成位于TFT器件上的接触孔；
S6：形成阴极电极，且阴极电极通过接触孔与TFT器件连接；
S7：在阴极电极上形成光电转换层。
本发明平板探测器上设置阻挡层，至少部分阻挡层位于半导体层的正上方，阻挡层可以阻挡光电转换层形成时氢气扩散对半导体层的影响、也可以阻挡X射线或环境光对半导体层的影响。
附图说明
下面将以明确易懂的方式，结合附图说明优选实施方式，对本发明予以进一步说明。
图1为现有平板探测器的结构示意图；
图2是本发明平板探测器的第一实施例的结构示意图；
图3是本发明平板探测器的第二实施例的结构示意图；
图4是本发明平板探测器的第三实施例的结构示意图；
图5是本发明平板探测器的第四实施例的结构示意图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本发明，应理解这些实施例仅用于说明本发明而不用于限制本发明的范围，在阅读了本发明 之后，本领域技术人员对本发明的各种等价形式的修改均落于本申请所附权利要求所限定的范围。
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
图2是本发明平板探测器的第一实施例的结构示意图。
如图2所示，平板探测器包括具有半导体层30的TFT器件1、覆盖TFT器件100的第一绝缘层60、位于第一绝缘层60上的层间绝缘层70、位于层间绝缘层70上且穿过第一绝缘层60和层间绝缘层70后与TFT器件100连接的阴极电极80、位于阴极电极80上的光电转换层(PIN,Photo Diode)90、位于光电转换层90上的阳极电极100以及位于半导体层30和光电转换层90之间的阻挡层110，至少部分阻挡层110位于TFT器件的半导体层30的正上方。
TFT器件100包括栅极10、覆盖栅极10的栅极绝缘层20、位于栅极绝缘层20上的半导体层30、覆盖半导体层30的刻蚀阻挡层40以及穿过刻蚀阻挡层40后均与半导体层30接触的源极51和漏极52。其中第一绝缘层60覆盖源极51和漏极52，阴极电极80与TFT器件100的漏极52连接。
其中阴极电极80采用功函数低的阴极金属材料制成，如银、钛、铝、钼或铌等。光电转换层90包括位于阴极电极80的N型非晶硅半导体层91、位于N型非晶硅半导体层91上的非晶硅本征层91以及位于非晶硅本征层91上的P型非晶硅半导体层93。
半导体层30为金属氧化物半导体层、也可以为非晶硅或多晶硅 的半导体层，最好为金属氧化物半导体层，如IGZO。当半导体层30为金属氧化物时，使得平板探测器具有漏电流低、电子迁移率高的优势。
层间绝缘层70为有机绝缘层，也可以为无机绝缘层。
阻挡层120呈直线状且与阴极电极80同时形成，阻挡层120与阴极电极80不接触，阻挡层120位于层间绝缘层70上。
本发明还揭示一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件1；
S2：形成覆盖TFT器件1的第一绝缘层60；
S3：第一绝缘层60上铺设层间绝缘层70并形成位于TFT器件1的漏极52上的接触孔(图未示)；
S4：在层间绝缘层70采用阴极金属材料同时形成阻挡层120和阴极电极80，且阴极电极80通过接触孔与漏极52连接；
S5：在阴极电极80上形成光电转换层90(具体方法为：首先在阴极电极80上依序形成N型非晶硅半导体层91、非晶硅本征层91以及P型非晶硅半导体层93)；
S6：在光电转换层90上形成阳极电极100。
由于阻挡层120上未覆盖其他物体，阻挡层120呈浮动状态，可以直接阻挡光电转换层90形成时氢气扩散对半导体层30的影响、也可以阻挡X射线或环境光对半导体层30的影响。
其中，步骤S1的具体步骤为：依序形成栅极10、形成覆盖栅极10的栅极绝缘层20、在栅极绝缘层20上形成位于栅极10上方的半导体层30、形成覆盖半导体层30的刻蚀阻挡层40并形成位于半导体层30上的源极接触孔(图未示)和漏极接触孔(图未示)以及形成源极51和漏极52，且源极51通过源极接触孔与半导体层30连接， 漏极52通过漏极接触孔与半导体层30连接。通过上述方法形成平板探测器，至少部分阻挡层120位于半导体层30的正上方，阻挡层120可以阻挡光电转换层90形成时氢气扩散对半导体层30的影响、也可以阻挡X射线或环境光对半导体层30的影响。
图3是本发明平板探测器的第二实施例的结构示意图。
第二实施例与上述第一实施例的区别是：阻挡层130包括呈直线状的第一阻挡体131以及与第一阻挡体131一端连接且靠近光电转换层90的第二阻挡体132，第一阻挡体131和第二阻挡体132之间的夹角为钝角。
通过第二阻挡体132可以阻挡光电转换层90的制程中氢气扩散对半导体层30的影响，第一阻挡体131可以阻挡X射线或环境光对半导体层30的影响。
在第二实施例的优选的实施例为：阻挡层130包括呈直线状的第一阻挡体131、与第一阻挡体131一端连接的第二阻挡体132以及与第一阻挡体131另一端连接的第三阻挡体133，第一阻挡体131分别与第二阻挡体132和第三阻挡体133之间的夹角为钝角，第三阻挡体133可以从侧边阻挡X射线或环境光对半导体层30的影响。
第一阻挡体131位于层间绝缘层70的表面上，第二阻挡体132和第三阻挡体133位于层间绝缘层70内。
第二阻挡体132和第三阻挡体133在层间绝缘层70，需要采用半透半反掩膜版来形成，才能形成第一阻挡体131分别与第二阻挡体132和第三阻挡体133之间的夹角为钝角的效果。
为了形成阻挡层130，需要在层间绝缘层70开设阻挡接触孔，阻挡接触孔可以与接触孔同时形成。
本发明还揭示一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件1；
S2：形成覆盖TFT器件1的第一绝缘层60；
S3：第一绝缘层60上铺设层间绝缘层70，然后形成位于TFT器件1的漏极52上的接触孔(图未示)以及位于层间绝缘层70内的阻挡接触孔；
S4：在层间绝缘层70采用阴极金属材料同时形成阻挡层120和阴极电极80，阴极电极80通过接触孔与漏极52连接，阻挡层120位于层间绝缘层70表面和阻挡接触孔内；
S5：在阴极电极80上形成光电转换层90(具体方法为：首先在阴极电极80上依序形成N型非晶硅半导体层91、非晶硅本征层91以及P型非晶硅半导体层93)；
S6：在光电转换层90上形成阳极电极100。
图4是本发明平板探测器的第三实施例的结构示意图。
第四实施例与上述第二实施例的区别是：在阻挡层140上设置第二绝缘层61且部分阻挡层140位于光电转换层90的下方，以使得阻挡层140呈稳定状态；阴极电极80设置在第二绝缘层61上且阴极电极穿过第二绝缘层61、层间绝缘层70和第一绝缘层60后与漏极52连接。
至少部分阻挡层130位于半导体层30的正上方。
其中，第一绝缘层60和第二绝缘层61都是无机绝缘层。
本发明还揭示一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件1；
S2：形成覆盖TFT器件的第一绝缘层60；
S3：第一绝缘层60上铺设层间绝缘层70并形成位于漏极53上的接触孔(图未示)；
S4：在层间绝缘层70采用阴极金属材料或其他金属材料形成阻挡层130；
S5：形成覆盖阻挡层130和层间绝缘层70的第二绝缘层61、并形成位于TFT器件的漏极52上的接触孔；
S6：形成阴极电极80，且阴极电极80通过接触孔与漏极52连接；
S7：在阴极电极80上形成光电转换层90(具体方法为：首先在阴极电极80上依序形成N型非晶硅半导体层91、非晶硅本征层91以及P型非晶硅半导体层93)；
S8：在光电转换层90上形成像素电极层100。
部分阻挡层140位于光电转换层90的下方，使得阻挡层130可以更好的阻挡光电转换层90形成时氢气扩散对半导体层30的影响、也可以阻挡X射线或环境光对半导体层30的影响，第二绝缘层61也可以阻挡氢气扩散对半导体30的影响。
图5是本发明平板探测器的第四实施例的结构示意图。
第四实施例与上述第三实施例的区别是：阻挡层150的形状与第二实施例阻挡层的形成相同，即：阻挡层150位于层间绝缘层70上，然后采用第二绝缘层61盖住阻挡层150，这样可以使得阻挡层150呈稳定状态。
阻挡层150是单独形成的，其材料可以是阴极金属，也可以是其他金属材料。
阻挡层150包括呈直线状的第一阻挡体151以及与第一阻挡体151一端连接且靠近光电转换层90的第二阻挡体152，第一阻挡体151和第二阻挡体152之间的夹角为钝角。
部分第一阻挡体151位于光电转换层90的下方，通过第二阻挡 体152可以阻挡光电转换层90的制程中氢气扩散对半导体层30的影响，第一阻挡体151可以阻挡X射线或环境光对半导体层30的影响。
在第四实施例的优选的实施例为：阻挡层150包括呈直线状的第一阻挡体151、与第一阻挡体151一端连接的第二阻挡体152以及与第一阻挡体151另一端连接的第三阻挡体153，第一阻挡体131分别与第二阻挡体152和第三阻挡体153之间的夹角为钝角，第三阻挡体132可以从侧边阻挡X射线或环境光对半导体层30的影响。
第一阻挡体151位于层间绝缘层70的表面上，第二阻挡体152和第三阻挡体153位于层间绝缘层70内。
本发明还揭示一种平板探测器的制造方法，包括如下步骤：
S1：形成TFT器件；
S2：形成覆盖TFT器件的第一绝缘层60；
S3：第一绝缘层60上铺设层间绝缘层70并形成位于漏极53上的接触孔(图未示)和位于层间绝缘层70内的阻挡接触孔(图未示)；
S4：在层间绝缘层70采用阴极金属材料或其他金属材料形成阻挡层150，阻挡层150位于层间绝缘层70表面和阻挡接触孔内；
S5：形成覆盖阻挡层150和层间绝缘层70的第二绝缘层61、并形成位于TFT器件的漏极52上的接触孔；
S6：形成阴极电极80，且阴极电极80通过接触孔与漏极52连接；
S7：在阴极电极80上形成光电转换层90(具体方法为：首先在阴极电极80上依序形成N型非晶硅半导体层91、非晶硅本征层91以及P型非晶硅半导体层93)；
S8：在光电转换层90上形成像素电极层100。
部分阻挡层150位于光电转换层90的下方，使得阻挡层150可 以更好的阻挡光电转换层90形成时氢气扩散对半导体层30的影响、也可以阻挡X射线或环境光对半导体层30的影响，第二绝缘层61也可以阻挡氢气扩散对半导体30的影响。
上述第一至第四实施例均可以不设置刻蚀阻挡层，在此就不重复叙述了。
上述第一至第四实施例的TFT器件的栅极10都是位于底部，在其他实施例中，TFT器件的栅极也可以位于顶部，即：TFT器件包括半导体层、覆盖半导体层的栅极绝缘层、在栅极绝缘层上形成栅极、与半导体层接触的源极和漏极。
当TFT器件的栅极是顶部时，步骤S1的具体步骤为：依序形成半导体层、形成覆盖半导体层的栅极绝缘层、在栅极绝缘层上形成位于半导体层上方的栅极以及形成均与半导体层接触的源极和漏极。
本发明平板探测器上设置阻挡层，至少部分阻挡层位于半导体层的正上方，阻挡层可以阻挡光电转换层形成时氢气扩散对半导体层的影响、也可以阻挡X射线或环境光对半导体层的影响。
以上详细描述了本发明的优选实施方式，但是本发明并不限于上述实施方式中的具体细节，在本发明的技术构思范围内，可以对本发明的技术方案进行多种等同变换(如数量、形状、位置等)，这些等同变换均属于本发明的保护范围。

Claims (10)

  1. 一种平板探测器，其包括具有半导体层的TFT器件、覆盖TFT器件的第一绝缘层、位于第一绝缘层上的层间绝缘层、位于层间绝缘层上且与TFT器件连接的阴极电极、位于阴极电极上的光电转换层；其特征在于，还包括位于层间绝缘层上的阻挡层；至少部分所述阻挡层呈浮动状态，至少部分所述阻挡层位于所述半导体层的正上方。
  2. 一种平板探测器，其包括具有半导体层的TFT器件、覆盖TFT器件的第一绝缘层、位于第一绝缘层上的层间绝缘层、位于层间绝缘层上的第二绝缘层、位于第二绝缘层上且与TFT器件连接的阴极电极、位于阴极电极上的光电转换层；其特征在于，还包括位于层间绝缘层和第二绝缘层之间的阻挡层；至少部分所述阻挡层位于所述半导体层的正上方，至少部分所述阻挡层位于所述光电转换层的下方。
  3. 根据权利要求1或2所述的平板探测器，其特征在于：所述阻挡层呈直线状。
  4. 根据权利要求1或2所述的平板探测器，其特征在于：所述阻挡层包括呈直线状的第一阻挡体以及与第一阻挡体一端连接且靠近光电转换层的第二阻挡体，所述第一阻挡体和第二阻挡体之间的夹角为钝角。
  5. 根据权利要求1或2所述的平板探测器，其特征在于：所述阻挡层包括呈直线状的第一阻挡体、与第一阻挡体一端连接的第二阻挡体以及与第一阻挡体另一端连接的第三阻挡体，第一阻挡体分别与第二阻挡体和第三阻挡体之间的夹角为钝角。
  6. 根据权利要求1或2所述的平板探测器，其特征在于：所述阻挡层的形成材料与所述阴极电极的材料相同。
  7. 一种平板探测器的制造方法，其特征在于，包括如下步骤：
    S1：形成TFT器件；
    S2：形成覆盖TFT器件的第一绝缘层；
    S3：第一绝缘层上铺设层间绝缘层并形成位于TFT器件上的接触孔；
    S4：在层间绝缘层采用阴极金属材料同时形成阻挡层和阴极电极，且阴极电极通过接触孔与TFT器件连接；
    S5：在阴极电极上形成光电转换层。
  8. 一种平板探测器的制造方法，其特征在于，包括如下步骤：
    S1：形成TFT器件；
    S2：形成覆盖TFT器件的第一绝缘层；
    S3：第一绝缘层上铺设层间绝缘层，然后形成位于TFT器件上的接触孔以及位于层间绝缘层内的阻挡接触孔；
    S4：在层间绝缘层采用阴极金属材料同时形成阻挡层和阴极电极，阴极电极通过接触孔与TFT器件连接，阻挡层位于层间绝缘层表面和阻挡接触孔内；
    S5：在阴极电极上形成光电转换层。
  9. 一种平板探测器的制造方法，其特征在于，包括如下步骤：
    S1：形成TFT器件；
    S2：形成覆盖TFT器件的第一绝缘层；
    S3：第一绝缘层上铺设层间绝缘层并形成位于TFT器件上的接触孔；
    S4：在层间绝缘层采用阴极金属材料或其他金属材料形成阻挡层；
    S5：形成覆盖阻挡层和层间绝缘层的第二绝缘层、并形成位于TFT器件的TFT器件上的接触孔；
    S6：形成阴极电极，且阴极电极通过接触孔与TFT器件连接；
    S7：在阴极电极上形成光电转换层。
  10. 一种平板探测器的制造方法，其特征在于，包括如下步骤：
    S1：形成TFT器件；
    S2：形成覆盖TFT器件的第一绝缘层；
    S3：第一绝缘层上铺设层间绝缘层并形成位于漏极上的接触孔和位于层间绝缘层内的阻挡接触孔；
    S4：在层间绝缘层采用阴极金属材料或其他金属材料形成阻挡层，阻挡层位于层间绝缘层表面和阻挡接触孔内；
    S5：形成覆盖阻挡层和层间绝缘层的第二绝缘层、并形成位于TFT器件上的接触孔；
    S6：形成阴极电极，且阴极电极通过接触孔与TFT器件连接；
    S7：在阴极电极上形成光电转换层。
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