WO2021042834A1

WO2021042834A1 - Electrode assembly preparation method

Info

Publication number: WO2021042834A1
Application number: PCT/CN2020/098496
Authority: WO
Inventors: 孙一慧; 孟凡涛
Original assignee: 浙江驰拓科技有限公司
Priority date: 2019-09-03
Filing date: 2020-06-28
Publication date: 2021-03-11
Also published as: CN112447900A

Abstract

The present invention provides an electrode assembly preparation method, comprising: providing a substrate having a through hole, a diffusion blocking layer being provided on the sidewall of the through hole; filling the through hole with a conductive material, and performing control to make the upper surface of the conductive material lower than the upper surface of the substrate; and depositing a bottom electrode material on the substrate and the conductive material to form a bottom electrode. According to the electrode assembly preparation method of the present invention, a closed space can be formed by the diffusion blocking layer and the bottom electrode, and the conductive material can be enclosed therein to avoid diffusion of the conductive material to the substrate.

Description

Electrode assembly preparation method

Technical field

The invention relates to the technical field of magnetic random access memory, in particular to a method for preparing an electrode assembly.

Background technique

In recent years, MRAM (Magnetic Random Access Memory) based on the magnetoresistance effect of MTJ (Magnetic Tunnel Junction) is due to its fast read and write speed, high rewritable times, and low power consumption. It has received widespread attention and is considered to be one of the most promising new types of memory in the future. The stack of magnetic/nonmagnetic films with a thickness of up to tens of layers or even around 1A makes it very sensitive to the surface roughness and flatness of the bottom electrode. Therefore, when preparing MRAM devices, it is a key to provide a flat MRAM bottom electrode. The steps can directly affect the performance of the subsequent MTJ unit.

In the current manufacturing technology of the bottom electrode of the magnetic tunnel junction, copper is usually used as the metal material for filling the conductive through holes, but the copper easily diffuses into the insulating medium around the through holes, resulting in degradation of device stability and other properties. The magnetic tunnel junction unit has higher requirements on the flatness/roughness of the substrate. Therefore, in the manufacturing process of the existing magnetic tunnel junction, materials such as Ta/TaN/Ti/TiN are usually covered on the through hole as the bottom electrode material, which prevents the diffusion of copper and improves the flatness of the magnetic tunnel junction substrate.

However, the current thickness of the bottom electrode is difficult to grasp during the manufacturing process. Due to the overall process fluctuation, in order to ensure that all the magnetic tunnel junctions are etched, there must be a certain amount of over-etching. When the bottom electrode is too thin, it is easy to expose the copper at the top of the conductive via and cause later copper diffusion. When the bottom electrode is too thick, it will be difficult to align the photolithography.

Summary of the invention

The preparation method of the electrode assembly provided by the present invention can avoid the diffusion of copper under the condition that the alignment accuracy is affected.

The present invention provides a method for preparing an electrode assembly, including:

Providing a substrate with a through hole, the side wall of the through hole has a diffusion barrier layer;

Filling the conductive material in the through hole, and controlling the upper surface of the conductive material to be lower than the upper surface of the substrate;

A bottom electrode material is deposited on the substrate and the conductive material to form a bottom electrode.

Optionally, after the conductive material is filled in the through hole, the substrate and the conductive material are planarized;

During the planarization process, the conductive material is excessively removed, so that the upper surface of the conductive material is lower than the upper surface of the substrate material.

Optionally, the planarization process is chemical mechanical polishing, in which chemical mechanical polishing is used to excessively remove the conductive material at different grinding rates of the conductive material and the substrate.

Optionally, after depositing the bottom electrode material, the method further includes:

The bottom electrode is planarized to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode coplanar with the substrate.

Optionally, after forming the bottom electrode, the method further includes:

The bottom electrode is etched to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode higher than the upper surface of the substrate.

Optionally, before etching the bottom electrode, the method further includes: performing a planarization treatment on the bottom electrode to eliminate the conformal topology structure at the through hole corresponding to the bottom electrode.

Optionally, the distance between the upper surface of the conductive material and the upper surface of the substrate is not less than 100 angstroms.

Optionally, the conductive material includes one or a combination of Cu, W, or Al.

Optionally, the diffusion barrier layer includes one or a combination of TaN, TiN, Ti, Co and Ru or Ta.

Optionally, the substrate at least includes a bottom diffusion barrier layer, a dielectric layer, and a top diffusion barrier layer stacked sequentially from bottom to top.

In the method for preparing the electrode assembly of the present invention, at least part of the bottom electrode is formed in the through hole. The side wall of the through hole has a diffusion barrier, and the top of the through hole is closed by the bottom electrode, so that the conductive material in the bottom through hole is completely closed, and the conductive material will not be exposed or even diffused due to the flattening of the bottom electrode . Therefore, when the bottom electrode is formed, the upper surface of the substrate can be formed as thin as possible according to requirements, and a thinner bottom electrode facilitates alignment during photolithography.

Description of the drawings

FIG. 1 is a schematic diagram after forming through holes in Embodiment 1 of the electrode assembly preparation method of the present invention;

2 is a schematic diagram of Embodiment 1 of the electrode assembly preparation method of the present invention after being filled with conductive material;

3 is a schematic diagram of a bottom electrode formed and planarized in Embodiment 1 of the method for manufacturing an electrode assembly of the present invention;

4 is a schematic diagram after the remaining layers are formed in Embodiment 1 of the electrode assembly preparation method of the present invention;

FIG. 5 is a schematic diagram of forming and etching the remaining layers and forming dielectric material protection in Embodiment 1 of the electrode assembly preparation method of the present invention; FIG.

FIG. 6 is a schematic diagram after forming through holes in Embodiment 2 of the electrode assembly manufacturing method of the present invention; FIG.

FIG. 7 is a schematic diagram of Embodiment 2 of the electrode assembly preparation method of the present invention after being filled with conductive material; FIG.

8 is a schematic diagram of the bottom electrode formed and etched in Embodiment 2 of the electrode assembly preparation method of the present invention;

9 is a schematic diagram after the remaining layers are formed in Embodiment 2 of the electrode assembly preparation method of the present invention;

FIG. 10 is a schematic diagram of the formation and etching of the remaining layers and the formation of dielectric material protection in Embodiment 2 of the preparation method of the electrode assembly of the present invention.

detailed description

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Example 1

The embodiment of the present invention provides a method for preparing an electrode assembly, as shown in FIGS. 1-5, the method includes:

S1: Provide a substrate 3 with a through hole, and a diffusion barrier layer 4 is provided on the sidewall of the through hole.

Step S1 specifically includes the following steps:

S11: Provide a substrate 3;

S12: forming a through hole on the substrate 3 by photolithography and etching, and the through hole penetrates the substrate 3;

S13: A diffusion barrier layer 4 is formed on the sidewall of the through hole.

As an optional implementation of this step: the diffusion barrier layer 4 includes one or a combination of TaN, TiN, Ti, or Ta.

S2: Fill the conductive material 5 in the through hole, and control the upper surface of the conductive material 5 to be lower than the upper surface of the substrate 3.

As an optional embodiment of this step: the conductive material 5 includes one or a combination of copper, W, or Al; as a preferred embodiment of this step: copper is used as the conductive material 5.

The above step S2 specifically includes the following steps:

The conductive material 5 is filled in the through hole of the substrate 3, and the substrate 3 and the conductive material 5 are planarized; in the planarization process, the conductive material 5 is excessively removed to make the The upper surface of the conductive material 5 is lower than the upper surface of the substrate 3 material.

As an optional implementation of this step, the Damascus process is used when filling the conductive material 5;

As an optional implementation of this step: the planarization process is chemical mechanical polishing, and the conductive material 5 is excessively removed by using the rate selection ratio of the polishing liquid. In the chemical mechanical polishing process, a polishing solution with a higher removal rate for the conductive material 5 and a lower removal rate for the substrate 3 is used.

As an optional implementation of this step: the distance between the upper surface of the conductive material 5 and the upper surface of the substrate 3 is not less than 100 angstroms.

S3: Depositing electrode material on the substrate 3 and the conductive material 5 to form a bottom electrode 6.

Optionally, in this step, when forming the bottom electrode 6, it is necessary to ensure that the upper surface of the bottom electrode 6 corresponding to the through hole is higher than the upper surface of the substrate 3 or flush with the upper surface of the substrate 3 to facilitate subsequent planarization. Craft.

Optionally, in this step, when the bottom electrode 6 is formed, the upper surface of the bottom electrode 6 corresponding to the through hole can be lower than the upper surface of the substrate 3. In the subsequent planarization process, the upper part of the substrate 3 is removed. , Until the substrate 3 is coplanar with the upper surface of the bottom electrode 6 in the through hole.

In the method for preparing the electrode assembly of this embodiment, at least part of the bottom electrode 6 is formed in the through hole. The sidewall of the through hole has a diffusion barrier layer 4, and the top of the through hole is closed by the bottom electrode 6, so that the conductive material 5 in the bottom through hole is completely closed, and the bottom electrode 6 will not be conductive due to the flattening of the bottom electrode 6. Material 5 is exposed or even diffused. Therefore, when the bottom electrode 6 is formed, the upper surface of the substrate 3 can be formed as thin as possible according to requirements, and a thinner bottom electrode 6 facilitates alignment during photolithography.

Optionally, this embodiment further includes the following steps:

S4: Plan the bottom electrode 6 to remove the material of the bottom electrode 6 formed on the upper surface of the substrate 3 and make the upper surface of the bottom electrode 6 coplanar with the substrate 3.

In this step, the excess bottom electrode material is removed by planarization, which can simplify the process flow. After the bottom electrode 6 is deposited, the original process includes the planarization process, and this step uses a flat method to remove the excess bottom electrode material, which can have a higher degree of fit with the original process, and no need to correct The original process and equipment carry out this advanced treatment. This can reduce implementation costs.

After the bottom electrode 6 is planarized, the functional layer 8, the top electrode 9 and the dielectric material 10 can be deposited sequentially, and then the above-mentioned layers are etched into patterns and the dielectric material 10 is deposited again for protection.

Optionally, before step S1, the method further includes: the bottom surface of the substrate 3 is in contact with the bottom medium 1; the bottom medium 1 and the through holes form seed through holes; and the seed layer 2 is formed in the seed through holes.

As an optional implementation of this embodiment, the substrate at least includes a bottom diffusion barrier layer 31, a dielectric layer 32, and a top diffusion barrier layer 33 that are sequentially stacked from bottom to top.

When the conductive material 5 and the substrate 6 are planarized, the top diffusion barrier layer 33 may be completely removed; or a part of the top diffusion barrier layer 33 may be removed, and the remaining top diffusion barrier layer 33 may be retained.

In the process of planarizing the bottom electrode and the substrate, if the substrate has a remaining top diffusion barrier layer 33, you can choose to planarize the bottom electrode 6 to the top diffusion barrier layer 33 to stop the planarization; you can also choose to continue the planarization To the dielectric layer 32, the top diffusion barrier layer 33 is completely removed. If the substrate 3 has no remaining top diffusion barrier layer 33, it can be planarized to the dielectric layer 32.

Example 2

The embodiment of the present invention provides a method for preparing an electrode assembly, as shown in FIGS. 6-10, the method includes:

Step S1 specifically includes the following steps:

S11: Provide a substrate 3;

S13: A diffusion barrier layer 4 is formed on the sidewall of the through hole.

The above step S2 specifically includes the following steps:

The conductive material 5 is filled in the through hole, and the substrate 3 and the conductive material 5 are planarized; during the planarization process, the conductive material 5 is excessively removed so that the conductive material 5 is The upper surface is lower than the upper surface of the substrate 3 material.

As an optional implementation of this step: the planarization process is chemical mechanical polishing, and the conductive material 5 is excessively removed by using the rate selection ratio of the polishing liquid.

Optionally, in this step, when the bottom electrode 6 is formed, it is necessary to ensure that the upper surface of the bottom electrode 6 corresponding to the through hole is higher than the upper surface of the substrate 3 to facilitate subsequent processes.

Optionally, this embodiment further includes the following steps:

S4: etching the bottom electrode 6 to remove the material of the bottom electrode 6 formed on the upper surface of the substrate 3 and make the upper surface of the bottom electrode 6 higher than the upper surface of the substrate 3.

In this step, the excess bottom electrode material is removed by etching, which can flexibly control the size of the bottom electrode and adjust it flexibly according to needs, thereby improving the quality of the final magnetic tunnel junction.

As an optional implementation of this step: after the bottom electrode 6 is etched, a dielectric material 10 is deposited around the bottom electrode 6 and the bottom electrode 6 and the dielectric material 10 are planarized. Here, a dielectric material 10 is deposited around the bottom electrode 6

As an alternative implementation of this step: a diffusion barrier layer 4 is also provided on the upper surface of the substrate 3. At this time, it is necessary to control the upper surface of the bottom electrode 6 in the via hole to be higher than the upper surface of the diffusion barrier layer 4, and After finishing the bottom electrode 6 layers, the bottom electrode 6 is first planarized. Subsequently, the bottom electrode 6 and the diffusion barrier layer 4 are removed by photolithography and etching processes. During the etching process, the diffusion barrier layer 4 on the upper surface of the substrate 3 is removed together until the upper surface of the substrate 3 is exposed Stop etching when.

After the bottom electrode 6 is etched, the insulating medium 7 is deposited around the bottom electrode 6 and planarized, and then the functional layer 8, the top electrode 9 and the dielectric material 10 can be deposited sequentially, and then the above layers are etched into patterns And the dielectric material 10 is deposited again for protection.

As an optional implementation of this embodiment, as an optional implementation of this embodiment, the substrate at least includes a bottom diffusion barrier layer 31, a dielectric layer 32, and a top diffusion barrier layer 33 that are sequentially stacked from bottom to top.

As an optional implementation of this embodiment, it also includes planarizing the conductive material 5 and the substrate 6, and you can choose to completely remove the top diffusion barrier layer 33; you can also choose to remove a part of the top diffusion barrier layer 33 and keep The remaining top diffusion barrier 33.

As an optional implementation of this embodiment, before the bottom electrode 6 is etched, the method further includes: planarizing the bottom electrode 6 so that the bottom electrode 6 forms a conformal topology structure at the position corresponding to the through hole eliminate.

In this embodiment, the bottom electrode 6 is etched before the functional layer 8 is deposited. However, it should be understood by those skilled in the art that the functional layer 8 can also be etched after the functional layer 8 is deposited in this embodiment. The etching is performed together; or, after the functional layer 8 and the top electrode 9 are deposited, the etching can be performed together with the functional layer 8 and the top electrode 9.

Example 3

The embodiment of the present invention provides a method for preparing an electrode assembly, the method including:

S1: Provide a substrate with a through hole, and a diffusion barrier layer is provided on the sidewall of the through hole.

Step S1 specifically includes the following steps:

S11: Provide a substrate;

S12: forming a through hole on the substrate by photolithography and etching, and the through hole penetrates the substrate;

S13: forming a diffusion barrier layer on the sidewall of the through hole.

As an optional implementation of this step: the diffusion barrier layer includes one or a combination of TaN, TiN, Ti, or Ta.

S2: Fill the through hole with a conductive material, and control the upper surface of the conductive material to be lower than the upper surface of the substrate.

As an optional embodiment of this step: the conductive material includes one or a combination of copper, W, or Al; as a preferred embodiment of this step: copper is used as the conductive material.

The above step S2 specifically includes the following steps:

A conductive material is filled in the through hole of the substrate, and the upper surface of the conductive material is controlled to be lower than the upper surface of the substrate. After the conductive material is formed, the upper surface of the conductive material is planarized, and the upper surface of the substrate is also planarized. The planarization process of the conductive material and the substrate are not related to each other, and the planarization process is performed separately, and the upper surface of the conductive material is ensured to be lower than the upper surface of the substrate. The difference between this step and the above two embodiments is that the height difference between the conductive material and the substrate is formed when the conductive material is deposited in this step. The height difference formed during the deposition process is easy to control the size. In theory, the height The larger the difference, the better the effect of this embodiment.

As an optional implementation of this step, the Damascus process is used when filling the conductive material;

As an optional implementation of this step: the distance between the upper surface of the conductive material and the upper surface of the substrate is not less than 100 angstroms.

S3: Depositing an electrode material on the substrate and the conductive material to form a bottom electrode.

Optionally, in this step, when forming the bottom electrode, it is necessary to ensure that the upper surface of the bottom electrode corresponding to the through hole is higher than or flush with the upper surface of the substrate to facilitate the subsequent planarization process.

Optionally, in this step, when the bottom electrode is formed, the upper surface of the bottom electrode corresponding to the through hole may be lower than the upper surface of the substrate. In the subsequent planarization process, the upper part of the substrate is removed until the substrate It is coplanar with the upper surface of the bottom electrode in the through hole.

Optionally, whether the upper surface of the bottom electrode in the through hole in S3 is higher than the upper surface of the substrate, lower than the upper surface of the substrate, or flat with the upper surface of the substrate, the following steps can be used to perform the bottom electrode Further processing:

In the method for preparing the electrode assembly of this embodiment, at least part of the bottom electrode is formed in the through hole. The side wall of the through hole has a diffusion barrier, and the top of the through hole is closed by the bottom electrode, so that the conductive material in the bottom through hole is completely closed, and the conductive material will not be exposed or even diffused due to the flattening of the bottom electrode . Therefore, when the bottom electrode is formed, the upper surface of the substrate can be formed as thin as possible according to requirements, and a thinner bottom electrode facilitates alignment during photolithography.

S4: The bottom electrode is planarized to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode coplanar with the substrate.

As an optional implementation of this step: a diffusion barrier layer is also provided on the upper surface of the substrate, and during the planarization process, the diffusion barrier layer on the upper surface of the substrate is removed together until the upper surface of the substrate Stop flattening when exposed.

Optionally, when the upper surface of the bottom electrode in the through hole is higher than the upper surface of the substrate, the following steps can also be used to process the bottom electrode:

S4: etching the bottom electrode to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode higher than the upper surface of the substrate.

As an optional implementation of this step: after the bottom electrode is etched, an insulating medium is deposited around the bottom electrode, and the bottom electrode and the dielectric material are planarized.

As an optional implementation of this step: a diffusion barrier layer is also provided on the upper surface of the substrate. At this time, it is necessary to control the upper surface of the bottom electrode in the via hole to be higher than the upper surface of the diffusion barrier layer. After that, the bottom electrode is first planarized. Subsequently, the bottom electrode and the diffusion barrier layer are removed by photolithography and etching processes. During the etching process, the diffusion barrier layer on the upper surface of the substrate is removed together, and the etching is stopped when the upper surface of the substrate is exposed.

After the bottom electrode is planarized or etched, the functional layer, the top electrode, and the dielectric material can be deposited sequentially, and then the above-mentioned layers are etched into patterns and the dielectric material is deposited again for protection.

Optionally, before step S1, the method further includes: the lower surface of the substrate is in contact with the bottom medium; the position of the bottom medium and the through hole is formed with a seed via; and the seed layer is formed in the seed via.

The above are only specific implementations of the present invention: but the protection scope of the present invention is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A method for preparing an electrode assembly, characterized in that it comprises:

Providing a substrate with a through hole, the side wall of the through hole has a diffusion barrier layer;

Filling the conductive material in the through hole, and controlling the upper surface of the conductive material to be lower than the upper surface of the substrate;

A bottom electrode material is deposited on the substrate and the conductive material to form a bottom electrode.
The method of manufacturing an electrode assembly according to claim 1, wherein:

After the conductive material is filled in the through hole, the substrate and the conductive material are planarized;

During the planarization process, the conductive material is excessively removed, so that the upper surface of the conductive material is lower than the upper surface of the substrate material.
2. The method for preparing an electrode assembly according to claim 2, wherein the planarization process is chemical mechanical polishing, and chemical mechanical polishing is used to over-process the conductive material at different grinding rates of the conductive material and the substrate. Remove.
8. The method of manufacturing an electrode assembly according to claim 1, wherein after depositing the bottom electrode material, the method further comprises:

The bottom electrode is planarized to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode coplanar with the substrate.
8. The method of manufacturing an electrode assembly according to claim 1, wherein after forming the bottom electrode, the method further comprises:

The bottom electrode is etched to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode higher than the upper surface of the substrate.
5. The method of manufacturing an electrode assembly according to claim 5, wherein before etching the bottom electrode, the method further comprises: planarizing the bottom electrode to eliminate conformal topology at the corresponding through hole of the bottom electrode structure.
The method for preparing an electrode assembly according to any one of claims 1 to 3, wherein the distance between the upper surface of the conductive material and the upper surface of the substrate is not less than 100 angstroms.
8. The method for preparing an electrode assembly according to claim 1, wherein the conductive material comprises one or a combination of Cu, W, and Al.
8. The method of manufacturing an electrode assembly according to claim 1, wherein the diffusion barrier layer comprises one or a combination of TaN, TiN, Ti, Co and Ru or Ta.
8. The method for preparing an electrode assembly according to claim 1, wherein the substrate at least comprises a bottom diffusion barrier layer, a dielectric layer, and a top diffusion barrier layer stacked sequentially from bottom to top.