WO2021042705A1

WO2021042705A1 - Pre-decoding system and method for instruction pipeline

Info

Publication number: WO2021042705A1
Application number: PCT/CN2020/082067
Authority: WO
Inventors: 吴汉明; 朱敏
Original assignee: 芯创智（北京）微电子有限公司
Priority date: 2019-09-02
Filing date: 2020-03-30
Publication date: 2021-03-11
Also published as: CN110780925A; CN110780925B

Abstract

Disclosed in the present invention are a pre-decoding system and method for an instruction pipeline. The pre-decoding system comprises an instruction pipeline, an instruction memory, pre-decoding logic, and a next-stage memory which are sequentially connected; the instruction memory is connected to the next-stage memory; the pre-decoding logic is used for obtaining, when determining that a current instruction taken out from the next-stage memory is a transfer instruction, second transfer instruction encoding information of the current instruction according to the address of the current instruction and first transfer instruction encoding information, and outputting the second transfer instruction encoding information to the instruction memory; the instruction pipeline is used for obtaining the address of a transfer target instruction of the current instruction according to the second transfer instruction encoding information of the current instruction obtained from the instruction memory and the address of the current instruction. The system and method provided by the present invention avoid repeated pre-decoding actions, and can effectively reduce dynamic power consumption of the front end of a processor pipeline.

Description

Pre-decoding system and method of instruction pipeline

Technical field

The present invention relates to the technical field of processors, in particular to a pre-decoding system and method of instruction pipeline.

Background technique

In modern processor design, the instruction pipeline obtains instructions from the first-level instruction buffer and submits them to the execution unit for execution. The binary code of the instruction stored in the first-level instruction cache, after the binary code of the instruction is read by the instruction pipeline, is converted into a control signal to instruct the operation of each component.

In order to maintain the correct instruction flow and support efficient instruction execution, pre-decoding components and branch prediction components are set up in the instruction pipeline to detect branch instructions in the instruction flow, calculate their branch direction as soon as possible, and perform timely Information update and instruction flow direction adjustment.

Since the instructions stored in the first-level instruction cache will be fetched multiple times and executed multiple times, for branch instructions, the pre-decoding action (judging the type of branch instruction and calculating the branch direction of the program) will be performed multiple times. Since most of the branch instructions have the same pre-decoding result each time, it can be considered that the repeated pre-decoding actions are redundant. Therefore, the repetition of these pre-decoding actions causes a waste of dynamic power consumption when the processor is running. .

Summary of the invention

In view of the defects in the prior art, the purpose of the present invention is to provide an instruction pipeline pre-decoding system and method, which avoids repeated pre-decoding actions and can effectively reduce the dynamic power consumption in the front stage of the processor pipeline.

In order to achieve the above objectives, the technical solutions adopted by the present invention are as follows:

An instruction pipeline pre-decoding system, the pre-decoding system comprising: an instruction pipeline, an instruction memory, a pre-decoding logic, and a next-level memory connected in sequence, the instruction memory being connected to the next-level memory;

The pre-decoding logic is used to obtain and output the second transfer instruction encoding information of the current instruction according to the address of the current instruction and the first transfer instruction encoding information when it is determined that the current instruction fetched from the next-level memory is a transfer instruction To the instruction memory;

The instruction pipeline is used to obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction obtained from the instruction memory and the address of the current instruction.

Further, in the pre-decoding system of an instruction pipeline as described above, the first transfer instruction encoding information includes an instruction type and a transfer offset, and the second transfer instruction encoding information includes a transfer instruction identifier and a simplified instruction type And transfer target information, where the simplified instruction type includes pre-decoded recognized information and transfer instruction subtypes;

The transfer instruction identifier is used to identify whether the current instruction is a transfer instruction;

The pre-decoded identification information is used to identify whether the transfer instruction has obtained the corresponding second transfer instruction encoding information through the pre-decode logic;

The transfer target information is used to record the address of the transfer target instruction of the transfer instruction;

The transfer instruction subtype is used to identify the specific type of the transfer instruction.

Further, in an instruction pipeline pre-decoding system as described above, the pre-decoding logic is used for:

When it is determined that the current instruction is a branch instruction, the address of the transfer target instruction of the current instruction is calculated according to the transfer offset in the encoding information of the first transfer instruction of the current instruction and the address of the current instruction, and the transfer target instruction of the current instruction is calculated according to the calculation And the first transfer instruction encoding information of the current instruction to obtain the second transfer instruction encoding information of the current instruction.

When it is determined that the current instruction is a branch instruction, the address of the branch target instruction of the current instruction is calculated according to the branch offset in the encoding information of the first branch instruction of the current instruction and the address of the current instruction, and the branch target instruction of the current instruction is calculated The address of is divided into a high section and a low section, and the low section is used as the transfer target information in the second transfer instruction encoding information of the current instruction;

According to the value of the high-segment part and the value of the high-segment address of the current instruction, the pre-decoded identification information in the second transfer instruction encoding information of the current instruction is identified.

When it is determined that the value of the high section of the address of the branch target instruction of the current instruction is equal to the value of the high section of the address of the current instruction, the pre-decode recognized information in the second branch instruction encoding information of the current instruction is identified as recognized.

Determine whether the current instruction is a transfer instruction according to the instruction type in the first transfer instruction encoding information of the current instruction, and identify the transfer instruction identifier and the transfer instruction subtype in the second transfer instruction encoding information of the current instruction according to the determination result.

Further, as described above, an instruction pipeline pre-decoding system, the instruction pipeline is used for:

Determine whether to obtain the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction and the address of the current instruction according to the pre-decoding identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory the address of.

When it is determined that the pre-decoding identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory is identified as recognized, the branch target information in the second branch instruction encoding information of the current instruction is combined with the current The high segment of the address of the instruction is spliced to get the address of the transfer target instruction of the current instruction.

A pre-decoding method for instruction pipeline, the pre-decoding method includes:

(1) When it is determined that the current instruction fetched from the next-level memory is a transfer instruction, the second transfer instruction encoding information of the current instruction is obtained according to the address of the current instruction and the first transfer instruction encoding information and output to the instruction memory ；

(2) Obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction obtained from the instruction memory and the address of the current instruction.

Further, in the pre-decoding method for an instruction pipeline as described above, the first transfer instruction encoding information includes an instruction type and a transfer offset, and the second transfer instruction encoding information includes a transfer instruction identifier and a simplified instruction type. And transfer target information, where the simplified instruction type includes pre-decoded recognized information and transfer instruction subtypes;

The beneficial effect of the present invention is that the system and method provided by the present invention analyze the transfer instructions in advance through the pre-decoding logic, and obtain the second transfer instruction encoding information and store it in the instruction memory. When the control logic of the pipeline is transferred from the instruction memory When fetching in the middle, you can directly obtain the address of the transfer target instruction of the current instruction by splicing the transfer target information in the second transfer instruction encoding information of the current instruction stored in the instruction store with the address of the current instruction, avoiding duplication The pre-decoding action can effectively reduce the dynamic power consumption at the front stage of the processor pipeline.

Description of the drawings

FIG. 1 is a schematic diagram of the relationship between the traditional pipeline and the pre-decoding logic provided in an embodiment of the present invention;

2 is a schematic structural diagram of an instruction pipeline pre-decoding system provided in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a transfer instruction encoding format stored in a next-level memory provided in an embodiment of the present invention;

4 is a schematic diagram of a transfer instruction encoding format stored in an instruction memory provided in an embodiment of the present invention;

FIG. 5 is a schematic diagram of the simplified instruction type in FIG. 4;

6 is a schematic diagram of the working mechanism of the pre-decoding logic provided in Embodiment 1 of the present invention;

Figure 7 is a schematic flow diagram of a pre-decoding method for an instruction pipeline provided in an embodiment of the present invention.

detailed description

The present invention will be further described in detail below in conjunction with the drawings and specific implementations of the specification.

The relationship between the traditional pipeline and the pre-decoding logic is shown in Figure 1. The cache of the processor is generally organized into a multi-level structure. The instruction pipeline obtains instructions from the first-level instruction cache, and the first-level instruction cache obtains instructions from the lower-level cache. After the instruction pipeline obtains the instruction, it is sent to the pre-decoding unit, which mainly includes the analysis of the instruction type and the calculation of the transfer type execution transfer direction. Since the instructions stored in the first-level instruction cache will be fetched multiple times and executed multiple times, for branch instructions, the pre-decoding action (judging the type of branch instruction and calculating the branch direction of the program) will be performed multiple times. Since most of the branch instructions have the same pre-decoding result each time, it can be considered that the repeated pre-decoding actions are redundant. Therefore, the repetition of these pre-decoding actions causes a waste of dynamic power consumption when the processor is running. .

In view of the above-mentioned defects, the present invention proposes an instruction pipeline pre-decoding system and method. As shown in Figure 2, the main structure includes three aspects: 1) Place the pre-decoding logic in the first-level instruction cache and the next-level cache Between; 2) The instruction storage structure design in the first-level instruction cache; 3) The transfer target address splicing in the instruction pipeline. The design of the present invention advances the pre-decoding component to the write path of the first-level instruction cache, analyzes the transfer instructions in advance, calculates the transfer direction in advance, avoids repeated pre-decoding actions, and can effectively reduce the dynamic functions in the front stage of the processor pipeline. Consumption.

As shown in Figure 2, the present invention provides an instruction pipeline pre-decoding system. The pre-decoding system includes: an instruction pipeline, an instruction memory, a pre-decoding logic, and a next-level memory that are connected in sequence, and the instruction memory and the next-level Memory connection

The pre-decoding logic is used to obtain the second transfer instruction encoding information of the current instruction according to the address of the current instruction and the first transfer instruction encoding information and output it to the instruction memory when it is determined that the current instruction fetched from the next-level memory is a transfer instruction;

The first transfer instruction encoding information includes the instruction type and the transfer offset, the second transfer instruction encoding information includes the transfer instruction identifier, the simplified instruction type, and the transfer target information, and the simplified instruction type includes the pre-decode identified information and the transfer instruction sub Types of;

The branch instruction subtype is used to identify the specific type of the branch instruction.

The pre-decoding logic is used to:

The instruction pipeline is used to:

Determine whether to obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction and the address of the current instruction according to the pre-decoding recognized information in the second branch instruction encoding information of the current instruction obtained from the instruction memory .

The instruction pipeline is used to:

When it is determined that the pre-decoding identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory is identified as recognized, the branch target information in the second branch instruction encoding information of the current instruction is combined with the current instruction The high segment of the address is spliced to obtain the address of the branch target instruction of the current instruction.

The present invention analyzes the first transfer instruction encoding information of the transfer instruction in advance through the pre-decoding logic, and obtains the second transfer instruction encoding information and stores it in the instruction memory. When the control logic of the pipeline fetches instructions from the instruction memory, it can directly By splicing the transfer target information in the second transfer instruction encoding information of the current instruction stored in the instruction store with the address high segment of the current instruction, the address of the transfer target instruction of the current instruction is obtained, avoiding repeated pre-decoding actions. Effectively reduce the dynamic power consumption in the front stage of the processor pipeline.

working principle:

In the present invention, the pre-decoding logic is placed between the first-level instruction cache and the next-level cache. All instructions obtained from the next-level cache need to be analyzed by the pre-decoding logic, the transfer instruction is identified, and the transfer is calculated. direction. For most branch instructions, the calculation of the branch target is unchanged each time it is executed. The calculation methods of the branch target of this type of instruction include:

Transfer target = address of this instruction + some fields in the code of this instruction, formula one

After the pre-decoding logic identifies the transfer type of the instruction and calculates the transfer direction, the information (including the transfer type and the transfer direction) is written into the first-level instruction cache. In traditional processor design, the instruction encoding information written in the first level instruction cache (instruction memory in Figure 1) is exactly the same as the instruction encoding information in the next level cache (the next level memory in Figure 1). The traditional The transfer instruction encoding information in the processor is shown in Figure 3. In the present invention, a new instruction encoding information format is provided, mainly to distinguish transfer instructions and non-transfer instructions with minimal overhead, and at the same time record the transfer instruction information recognized by the pre-decoding logic in the instruction encoding .

As shown in Figure 2, the information passed to the pre-decoding logic by the next level of memory contains several instructions, and the information of each instruction is shown in Figure 3, that is, the first transfer instruction encoding information, and the pre-decoding logic transmits it to the instruction. The information of the memory corresponds to the above-mentioned several instructions, and the information of each instruction is shown in Figure 4, that is, the second transfer instruction encoding information.

The transfer instruction encoding information of the present invention is shown in Fig. 4, and the main difference from the standard instruction encoding structure of Fig. 3 is:

(1) One bit is added to the instruction encoding width in Figure 3 to identify whether the current instruction is a transfer instruction, that is, the C bit in Figure 4.

(2) Shorten the "instruction type" field in Figure 3, the "instruction type" field in Figure 3 needs to encode all instruction types that the processor can recognize, and the "simplified instruction type" in Figure 4 only needs to distinguish different transfers The instruction is sufficient, that is, the "branch instruction subtype" in Figure 5, which is pertinent, in which the "pre-decoding recognized" is marked with 1 bit to mark whether the encoding of the branch instruction has been completely converted by the pre-decoding logic. There are two types of instructions that cannot be fully converted by the pre-decoding logic:

a) The transfer target calculation method does not belong to the transfer target calculation methods listed above;

For example: the transfer target address = the value of a certain register + the address of this instruction, where the value of a certain register needs to be obtained through a read register operation.

There are many types of branch instructions that the processor needs to process. One type is a). As shown in the case of a), the calculation of the branch target address needs to be dynamically changed each time it is executed (the root is that the target address calculation needs to obtain a dynamic The value of the register), so it cannot be calculated in advance. The present invention is suitable for another type of transfer instruction, whose transfer target calculation only relies on static information, so it can be calculated in advance.

b) The branch target calculated by the pre-decoding logic cannot be effectively stored in the "branch target" field in Figure 4 for branch instructions. When two situations a) and b) occur, the pre-decoding logic of the present invention will retain the "branch offset" field in the original branch instruction encoding information of the instruction, and will not convert it to the "branch target" field described below .

(3) Convert the "branch offset" field in Figure 3 to the "branch target" field in Figure 4, which is used to record the address of the branch target instruction of the branch instruction. Since the instruction address width of the processor usually exceeds the instruction encoding width, the "branch target" field in Figure 4 cannot completely store the complete branch target address. In the present invention, the address of the branch target instruction (branch target address) of the current instruction calculated by the pre-decoding logic is divided into two sections, the lower section is stored in the "branch target" field shown in Figure 4, and the pipeline executes the branch. When instructing, there are two addresses: the address of the branch instruction itself and the address of the branch target instruction. The pipeline itself has a special structure to store and maintain the address of the transfer instruction itself. In the present invention, the high-segment of the address of the transfer target instruction directly uses the high-segment of the address of the transfer instruction itself.

If the value of the high segment of the "current instruction address" is equal to the high segment of the "branch target address", the "predecoding recognized" flag is set, indicating that when this instruction is output from the instruction memory shown in Figure 2, the second The "transfer target" field in the transfer instruction encoding information is directly spliced with the high segment of the "address of the current instruction" to obtain the transfer target address, and the pre-decoding logic is responsible for the judgment and setting.

If the value of the high section of the "current instruction address" is not equal to the high section of the "branch target address", it corresponds to the case of type b) above. The branch target calculated by the pre-decoding logic cannot be in the "branch target" field in Figure 4 In the effective storage, the pre-decoding logic of the present invention will retain the "branch offset" field in the original transfer instruction encoding information of the instruction, and will not convert it into the "branch target" field. When the instruction is output from the instruction memory shown in Figure 2, it will re-use the above formula 1 to calculate the branch target address.

Example one

As shown in Figure 6, the pre-decoding logic fetches an instruction in the format of Figure 3 from the next level of memory, parses the instruction, recognizes that the instruction type of the instruction is a branch instruction, and based on the branch instruction address [50 :0] and transfer offset [20:0] to calculate the transfer target address [50:0] of the instruction, divide the transfer target address into high and low segments, of which the low segment [25:0] is stored in the instruction memory In the "transfer target" field in the format of Figure 4, the high segment [50:26] is used for subsequent judgment.

It can be seen from the figure that the value [50:26] of the high section of the "current instruction address" is equal to the calculated high section of the "branch target address" [50:26], which indicates that the encoding of the current instruction has been completely converted by the pre-decoding logic At this time, the pre-decoding logic sets the "pre-decoding recognized" flag. When the instruction "instruction memory" is output, the control logic directly obtains it from the "transfer target" field of the instruction storage location in the instruction memory For branch instructions that have set "pre-decoding recognized", you can directly use the "branch target" field as the lower segment of the branch target address.

The hardware logic of the pipeline itself concatenates the "branch target" field that the control logic fetched from the instruction memory with the high segment of the "current instruction address" stored by itself to obtain the branch target address of the current instruction, and then re-fetch the instruction from the branch target address , To avoid repeated pre-decoding actions at the front end of the pipeline.

The present invention analyzes transfer instructions in advance through the pre-decoding logic located between the instruction memory and the next-level memory, and calculates the transfer direction in advance. When the control logic of the pipeline fetches the instruction from the instruction memory, it can directly fetch the "transfer target" "Field, the transfer target address is obtained through hardware logic splicing, avoiding repeated pre-decoding actions, and effectively reducing the dynamic power consumption of the front stage of the processor pipeline.

As shown in Fig. 7, a pre-decoding method of instruction pipeline, the pre-decoding method includes:

S100. When it is determined that the current instruction fetched from the next-level memory is a transfer instruction, obtain the second transfer instruction encoding information of the current instruction according to the address of the current instruction and the first transfer instruction encoding information and output it to the instruction memory;

S200: Obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction obtained from the instruction memory and the address of the current instruction.

S100 includes:

S200 includes:

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. In this way, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

An instruction pipeline pre-decoding system, characterized in that the pre-decoding system includes: an instruction pipeline, an instruction memory, a pre-decoding logic, and a next-level memory connected in sequence, the instruction memory and the next Level memory connection;

The pre-decoding logic is used to obtain and output the second transfer instruction encoding information of the current instruction according to the address of the current instruction and the first transfer instruction encoding information when it is determined that the current instruction fetched from the next-level memory is a transfer instruction To the instruction memory;

The instruction pipeline is used to obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction obtained from the instruction memory and the address of the current instruction.
The pre-decoding system of an instruction pipeline according to claim 1, wherein the first transfer instruction encoding information includes an instruction type and a transfer offset, and the second transfer instruction encoding information includes a transfer instruction identifier 1. Simplified instruction type and transfer target information, where the simplified instruction type includes pre-decoded recognized information and transfer instruction subtypes;

The transfer instruction identifier is used to identify whether the current instruction is a transfer instruction;

The pre-decoded identification information is used to identify whether the transfer instruction has obtained the corresponding second transfer instruction encoding information through the pre-decode logic;

The transfer target information is used to record the address of the transfer target instruction of the transfer instruction;

The transfer instruction subtype is used to identify the specific type of the transfer instruction.
An instruction pipeline pre-decoding system according to claim 2, wherein the pre-decoding logic is used for:

When it is determined that the current instruction is a branch instruction, the address of the transfer target instruction of the current instruction is calculated according to the transfer offset in the encoding information of the first transfer instruction of the current instruction and the address of the current instruction, and the transfer target instruction of the current instruction is calculated according to the calculation And the first transfer instruction encoding information of the current instruction to obtain the second transfer instruction encoding information of the current instruction.
An instruction pipeline pre-decoding system according to claim 3, wherein the pre-decoding logic is used for:

When it is determined that the current instruction is a branch instruction, the address of the branch target instruction of the current instruction is calculated according to the branch offset in the encoding information of the first branch instruction of the current instruction and the address of the current instruction, and the branch target instruction of the current instruction is calculated The address of is divided into a high section and a low section, and the low section is used as the transfer target information in the second transfer instruction encoding information of the current instruction;

According to the value of the high-segment part and the value of the high-segment address of the current instruction, the pre-decoded identification information in the second transfer instruction encoding information of the current instruction is identified.
An instruction pipeline pre-decoding system according to claim 4, wherein the pre-decoding logic is used for:

When it is determined that the value of the high section of the address of the branch target instruction of the current instruction is equal to the value of the high section of the address of the current instruction, the pre-decode recognized information in the second branch instruction encoding information of the current instruction is identified as recognized.
An instruction pipeline pre-decoding system according to claim 2, wherein the pre-decoding logic is used for:

Determine whether the current instruction is a transfer instruction according to the instruction type in the first transfer instruction encoding information of the current instruction, and identify the transfer instruction identifier and the transfer instruction subtype in the second transfer instruction encoding information of the current instruction according to the determination result.
An instruction pipeline pre-decoding system according to claim 5, wherein the instruction pipeline is used for:

Determine whether to obtain the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction and the address of the current instruction according to the pre-decoding identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory the address of.
An instruction pipeline pre-decoding system according to claim 7, wherein the instruction pipeline is used for:

When it is determined that the pre-decoding identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory is identified as recognized, the branch target information in the second branch instruction encoding information of the current instruction is combined with the current The high segment of the address of the instruction is spliced to get the address of the transfer target instruction of the current instruction.
An instruction pipeline pre-decoding method, applied to an instruction pipeline pre-decoding system according to any one of claims 1-8, characterized in that the pre-decoding method comprises:

(1) When it is determined that the current instruction fetched from the next-level memory is a transfer instruction, the second transfer instruction encoding information of the current instruction is obtained according to the address of the current instruction and the first transfer instruction encoding information and output to the instruction memory ；

(2) Obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction obtained from the instruction memory and the address of the current instruction.
An instruction pipeline pre-decoding method according to claim 9, wherein the first transfer instruction encoding information includes an instruction type and a transfer offset, and the second transfer instruction encoding information includes a transfer instruction identifier 1. Simplified instruction type and transfer target information, where the simplified instruction type includes pre-decoded recognized information and transfer instruction subtypes;

The transfer instruction identifier is used to identify whether the current instruction is a transfer instruction;

The pre-decoded identification information is used to identify whether the transfer instruction has obtained the corresponding second transfer instruction encoding information through the pre-decode logic;

The transfer target information is used to record the address of the transfer target instruction of the transfer instruction;

The transfer instruction subtype is used to identify the specific type of the transfer instruction.