KR20080000944A - Processor with pipelined architecture and control method thereof - Google Patents

Abstract

A processor having a pipelined architecture and a control method thereof are provided to correct a branch command error owing to program cache miss even if an interruption tree is not found in a pipeline processor, secure a maximum operation frequency of the processor and reduce a chip area by deleting the interruption tree for managing the cache miss. A processor(160) fetches a command with a plurality of sequential processing stages(162-170). A program counter(140) outputs an address for the command fetched by the processor. A cache(130) receives a part of a program to be performed in the processor from a main memory(110), stores the received program, provides the command included in the program corresponding to the address to the processor by receiving the address from the program counter, and outputs a standby signal if the command corresponding to the received address is not found. A stall buffer stores a target address of the next branch command based on the standby signal and provides the target address to the program counter. The stall buffer has a space for storing the target address of the next branch command as much as the number of branch slots.

Description

PROCESSOR WITH PIPELINED ARCHITECTURE AND CONTROL METHOD THEREOF}

1 is a schematic block diagram of a conventional pipeline processor,

2 is a schematic block diagram of a pipeline processor according to the present invention;

3 is a flow chart of instructions of a processor when a cache hit occurs in a pipeline processor according to the present invention;

4 is a flow chart of instructions of a processor when a cache miss occurs in a pipeline processor according to the present invention;

5 is a flowchart showing a control method of a pipeline processor according to the present invention.

Explanation of symbols on the main parts of the drawings

210: external memory 220: processor

230: cache unit 240: program counter unit

250: stall buffer 260: processing unit

262: instruction fetch stage 264: instruction decoder stage

266: address generator stage 268: execution stage

270: Lightback Stage

The present invention relates to a processor and a control method thereof, and more particularly, to a processor and a control method thereof that can cope with the cache miss without stopping the operation of the pipeline.

Modern processors use many pipeline structures to improve performance. The pipeline structure divides the instruction processing process into a plurality of stages and maximizes the information processing per cycle by parallel processing a plurality of instructions in different stages during one cycle.

Such a pipeline is shown in FIG. 1 as a schematic block diagram of a conventional pipeline processor.

The processor 120 is connected to an external memory 110 that stores information to be processed by the processor 160, and includes a cache 130, a program counter 140, a stop signal generator 150, and a processor 160. Consists of

The cache unit 130 is a small memory area designed to have an operating frequency that is the same as or similar to that of the core of the processor 120. The cache unit 130 improves the performance of the processor 120, and the program counter 140 performs instruction fetch. Stores the address of the command to be executed.

When the address of the program counter unit 140 is requested to the cache unit 130, the cache unit 130 transmits the command of the corresponding address to the processing unit 160, and the processing unit 160 transmits the received command to the command decoder stage 164. ) And change it to the appropriate control signal.

However, since the cache unit 130 stores only a part of the entire program, there is a case where the processor 120 does not have an instruction of an address required. Such a case is called a cache miss, and the cache unit 130 obtains a corresponding instruction from the external memory 110, but since the external memory 110 is slow, the processing unit 160 of the processor 120 is a cache unit ( The operation must be paused while 130 is waiting for a command.

In other words, in a pipeline structure, when an instruction is executed before another instruction is completely finished, a mismatch occurs when a cache miss occurs. To prevent this, the stop signal generator 150 outputs a stop signal to the processor 160 to stop the progress of each stage of the processor 160.

Since the conventional stop signal must drive all pipeline registers (not shown) of the processor 120, the path for transmitting the stop signal has a great influence on the threshold delay that determines the operating frequency of the processor 120. It will occupy a large area of silicon.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a processor and a control method thereof that can cope with a cache miss without stopping the operation of the pipeline.

In order to achieve the above object, the present invention provides a processor comprising: a processor for performing an instruction fetch with a plurality of sequential processing stages, a program counter unit for outputting an address relating to an instruction for which the processor is to fetch, and Partially receive and store a program to be executed in the processing unit from the main memory of the controller, receive an address from the program counter and provide an instruction in the program corresponding to the address to the processing unit, and correspond to the received address A cache unit for outputting a wait signal when not having a command, and a stall buffer for storing a target address of a branch instruction to be executed next based on the wait signal and providing the program to the program counter unit.

Preferably, the stall buffer has a space that can be stored for the target address of the branch instruction to be executed next to the number of branch slots.

Meanwhile, the present invention provides a control method of a processor having a processor configured to perform instruction fetch with a plurality of sequential processing stages, and a cache configured to partially receive and store a program to be executed in the processor from a predetermined main memory. Requesting an instruction of an address of a program counter of a cache unit, and if there is no instruction requested of an address of the cache unit, advances a command of a processor consisting of a plurality of stages by one stage and inputs a specific value to the first stage of the processor; And the step of storing a target address in a stall buffer if a branch instruction exists in the one-stage advanced instruction of the processing unit.

After the target address is stored in the stall buffer, it is preferable to further include updating the target counter stored in the stall buffer to the program counter if there is an instruction requested for the cache address.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A schematic block diagram for a pipeline processor according to the present invention is shown in FIG. The processor 220 according to the present invention is connected to an external memory 210 that stores information to be processed by the processor 260, and includes a cache unit 230, a program counter unit 240, a stall buffer 250, and a processor unit ( 260).

The cache unit 230 stores instructions to be provided to the processing unit 260 of the processor 220, and the program counter unit 240 stores addresses of instructions to be fetched. When the address of the program counter 240 is requested to the cache 230, the cache 240 transmits an instruction of the corresponding address to the processor 260.

The processing unit 260 has five stages: an instruction fetch stage 262, an instruction decoder stage 264, an address generator stage 266, an execution stage 268, and a writeback stage 270.

The instruction fetch stage 262 is for fetching an instruction. If the instruction to be fetched exists in the cache unit 230, a cache hit is generated, and if the instruction does not exist, the cache miss is generated.

The instruction decoder stage 264 interprets the instructions to obtain data from a resource such as an internal register, and the address generator stage 266 calculates an address for accessing the data cache and determines a condition of a branch to determine the program counter unit 240. ).

The execution stage 268 actually calculates a resource to obtain a result. For example, the execution stage 268 executes a specified operation of adding or multiplying two numbers, and the writeback stage 270 internally stores the operation result or the value read from the cache unit. Write to register.

Although FIG. 2 shows a processor 260 having five stages, the present invention is not limited by the number of stages of the processor 260.

The cache unit 230 provides a signal corresponding to the cache miss generated by the instruction fetch stage 262 to the program counter unit 240 and the stall buffer 250. Here, the cache unit 230 includes not only a place for storing a program but also an area for generating and managing control signals related thereto.

The stall buffer 250 is for executing a normal branch instruction even if a cache miss occurs in a branch slot. The stall buffer has an entry corresponding to a branch slot, and each entry stores an address of a program to be obtained when a cache hit occurs. do.

3 shows a processing sequence of instructions that are processed in a pipeline when a cache hit occurs.

In (a), since the current program counter address of the program counter unit 240 is Ox80, the cache unit 230 obtains an instruction at the Ox80 address and inputs it to the IF stage 262, and each of the other instructions has an ID stage 264. ), AG stage 266, EX stage 268 and WB stage 270, respectively.

In (b), since the current program counter address of the program counter 240 is Ox81, the cache unit 230 obtains an instruction at the Ox81 address and inputs it to the IF stage 262. Since the branch instruction is input to the AG stage 266, the next program counter address of the program counter unit 240 becomes the Ox200 address indicated by the branch instruction. Therefore, in (c), the command at the current program counter Ox200 address of the program counter unit 240 is input to the IF stage 262. In this case, since the branch instruction in the AG stage 266 has updated the program counter unit 240, the two instructions following the branch instruction are unconditionally executed. The part that is performed by the pipeline even after the branch instruction is called a branch slot.

4 is a flowchart illustrating instructions of a processor when a cache miss occurs in a pipeline processor according to the present invention.

In (a), since the current program counter address of the program counter unit 240 is Ox79, the cache unit 230 obtains an instruction at the Ox79 address and inputs it to the IF stage 262, and each of the other instructions is an ID stage 264. , AG stage 266, EX stage 268 and WB stage 270, respectively.

In (b), a state in which a cash miss occurs in the current program counter address Ox80 of the program counter unit 240 is displayed. Since the cache misses, the program counter 240 is maintained as it is due to the wait signal of the cache 230. The processor 260 inserts a NOP into the IF stage 262 and stores the address of the Ox81 instruction to be performed after the Ox80 instruction in the first entry of the stall buffer 250.

In (c), the branch instruction is input to the AG stage 266. If it is not the cache miss, the program counter address of the program counter unit 240 is immediately updated to the branch target address Ox200 at the AG stage 266. However, the program counter unit 240 is caused by the wait signal of the cache unit 230 because it is a cache miss. Program counter address is not updated. In this case, the branch instruction writes the branch target address to the second entry of the stall buffer 250.

Thereafter, as shown in (e), when the cache hit occurs and the current program counter address Ox80 command of the program counter unit 240 is executed, the program counter unit 240 is changed by the program counter addresses stored in the stall buffer 250. Perform normal operation.

5 is a flowchart illustrating a control method of a pipeline processor according to the present invention.

When power is supplied to the processor, the program counting unit 240 and the stall buffer 250 of the processor are initialized (S502). The cache unit 230 requests an instruction of a program counter address of the program counter 240.

If there is no instruction requested by the cache unit 230 (S506), the instruction of the processing unit 260 is advanced one stage, and NOP is input to the IF stage 262 (S508). If a branch instruction exists in the AG stage 266 of the processing unit 260, the target address is stored in the stall buffer 250, and a signal indicating that the target address stored in the stall buffer 250 is valid is supplied to the program counter unit 240. (S510).

The cache unit 230 re-requests the command of the address held in the program counter unit 240 (S512). If a cache hit occurs (S506), the instruction in the processor 260 advances one stage, and the instruction is taken from the cache 230 (S520).

When the signal indicating that the target address stored in the stall buffer 250 is valid is supplied to the program counter unit 240 (S522), the program counter address of the program counter unit 240 is changed to the address stored in the stall buffer 250. In step S524, the address stored in the stall buffer 250 is cleared.

If an end instruction exists in the processing unit 260 (S526), the processing of the processing unit 260 ends. Otherwise, it is determined whether a branch exists in the processing unit 260 (S528), and if it is a branch, the program counter address of the program counter unit 240 is changed to a target address (S530), and if it is not a branch, the program counter unit 240 Increase the program counter address by the size of the instruction (S532).

As described above, according to the present invention, it is possible to correct an error of a branch instruction caused by a program cache miss even if there is no stop tree in the pipeline processor.

In addition, according to the present invention, the maximum operating frequency of the processor can be secured higher by deleting the stop tree corresponding to the cache miss, and the chip area is reduced.

Claims (4)

In the processor, A processor configured to perform instruction fetch with a plurality of sequential processing stages; A program counter unit for outputting an address relating to an instruction to be fetched by the processor; Partially receive and store a program to be executed in the processing unit from a predetermined main memory, receive an address from the program counting unit, and provide an instruction in the program corresponding to the address to the processing unit, and correspond to the received address. A cache unit for outputting a wait signal when the terminal does not have a command to perform the command; And a stall buffer storing a target address of a branch instruction to be executed next based on the wait signal and providing the target address to the program counter unit. The method of claim 1, The stall buffer has a space that can be stored for the target address of the branch instruction to be executed next to the number of branch slots. In the control method of the processor having a processing unit for performing instruction fetch with a plurality of sequential processing stages, and a cache unit for receiving and storing a program to be executed in the processing unit from a predetermined main memory, Requesting an instruction of an address of a program counter unit to the cache unit; If there is no instruction requested in the address of the cache unit, moving the instruction in the processing unit comprising a plurality of stages by one stage and inputting a specific value into the first stage of the processing unit; And storing a target address in a stall buffer when a branch instruction is present in the one-stage advanced instruction of the processing unit. The method of claim 3, And updating the target address stored in the stall buffer to the program counter if there is an instruction requested in the cache address after the target address is stored in the stall buffer.

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