JPH01296342A - Data processor - Google Patents

Abstract

PURPOSE:To directly verify the propriety of the function of a branching history memory mechanism by previously setting the bit of a mode register. CONSTITUTION:An AND circuit 103 produces a signal which cancels the fetching of a branched address from an address discordant output sent from an address comparator through a terminal 122 when the bit '2' of the mode register 65 is '1'. The bit '2' of the register 65 indicates the mode which inhibits the invalidation of fetching of a wrong branched address when the branched address is discordant. Accordingly, invalidation of previous fetching of improper branched address can be inhibited by the bit '2' of the register 65 when the address is discordant. Therefore, when already known branched addresses are previously registered in the branching history memory and the bit '2' of the register 65 is controlled thereafter, the operation of the branching history memory can be evaluated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a data processing device having a branch history memory.

In recent years, electronic computers have become faster and faster, especially in the area of large electronic computers, where instructions can be fetched and decoded.

Pipeline techniques are widely used to improve processing speed by dividing operand retrieval, computation, and storage of computation results into multiple pipeline stages and executing the processing in each stage in parallel. This pipeline technique achieves maximum performance when continuous processing continues at each pipeline stage.

However, in executing a branch instruction, it takes a great deal of time to retrieve the branch destination, which creates idle time in pipeline processing, resulting in a significant drop in performance. Therefore, the storage address of a branch instruction executed in the past and the branch destination address of the branch instruction are stored in memory as history information as a pair, and this memory is referred to when fetching an instruction to check the history of past branches at the instruction fetching address. If so, a branch history memory technology has emerged that uses the branch destination address obtained from this history as the predicted branch destination address to fetch subsequent instructions.

The effectiveness of this branch prediction technology based on the branch memory method is that it can be used not only for unconditional branch instructions in many programs.
This is supported by the fact that when coding a conditional branch instruction to form a loop, the probability of branching in the same direction as the previous one is extremely high. In order to realize this characteristic in a small-capacity branch memory, it is effective to replace old information with the execution result of a new branch instruction.
lyUsed).

A replacement algorithm such as HFO (First In First Out) is employed.

On the other hand, the branch destination may change due to a change in the state referenced by a conditional branch instruction in the program (eg, an operation result).

In this case, the branch destination address indicated by the branch history stored in the branch history memory and the branch destination address of the actual branch instruction do not match. In preparation for this, branch prediction verification technology compares both addresses when a branch instruction is executed, and if they do not match, invalidates the predicted branch destination prefetching operation, and then extracts the correct branch destination again based on the execution result of the branch instruction. There is.

In the conventional branch history memory described above, the old branch history in the branch history memory is updated every time a new branch instruction appears. For this reason, there is a drawback that it is not possible to implement a diagnostic method in which a branch history for a specific branch instruction is set in a branch history memory and a diagnosis of a branch prediction mechanism is executed.

In order to determine whether or not the branch destination should be retrieved again when the prediction is wrong, execution time is measured, which has the disadvantage that the diagnostic accuracy is extremely low. In other words, the validity verification of the branch prediction mechanism is replaced with an indirect parameter called time, and there is a drawback that the function cannot be directly verified.

Therefore, the present invention was made to solve the drawbacks of the conventional ones, and its purpose is to correctly and directly check the correctness of the function of the branch memory machine. The objective is to provide a data processing device that can be verified.

A data processing device according to the present invention includes a storage means for storing an instruction word, an address generation means for generating a branch destination address when the instruction word read from the storage means is a branch instruction, and a data processing device for storing an instruction word. branch history storage means for storing an address pair consisting of an instruction word fetching address of an instruction and the branch destination address as branch history information at a storage address corresponding to the instruction word fetching address; indexing means for reading branch history information in the branch history storage means based on the address and determining whether branch history information corresponding to the branch instruction is registered; and a branch destination address determined as a result of execution of the branch instruction; Disabling means for comparing the branch fetching address obtained as an output from the indexing means and disabling instruction fetching by the branch fetching address when the two do not match; and control for inhibiting the operation of the disabling means. It is characterized by including means.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data processing device to which the present invention is applied. In FIG. 1, an instruction control unit 1 has a built-in instruction cache memory (instruction cache) 30, and executes advance fetching of instruction words, decoding, fetching of operands, and creation of virtual addresses. The storage control unit 2 converts the virtual address created by the instruction control unit 1 into a real address, reads the operand by referring to the operand cache memory (operand cache > 53, 54) based on this address, and performs arithmetic control. Supply to unit 3.

The arithmetic control unit 3 executes arithmetic operations on the operands supplied from the storage control unit 2 based on control instructions sent from the instruction control unit 1, and stores the results in a general-purpose register and an operand cache. Note that the storage control unit 2 has an interface with the main memory, and also has a function to read data from the main memory when data not present in the operand cache or instruction cache is requested, but these interface sections are not shown in FIG. It is omitted.

The command control unit 1 is configured as follows.

An instruction word prefetching instruction counter (FIC) 13 and an instruction cache 3 referenced by the output of this instruction counter 13
0, and a save register (BICF) 14 for holding the output of the instruction counter 13 until the branch prediction result becomes clear.

The output of the instruction counter (NIC) 12 for branch prediction is supplied as an address to the address section (NA^) 10 and data section (NAB) 11 of the branch history memory, and the comparison circuit 17 compares the output of the address section 10 with the read address. When a match is detected, the output of the corresponding data section 11 is selected by one selection circuit and set in the save register (old C) 18. The save register 18 is stored in the predicted address buffer (NA8F) 20, and is also used in the selection circuits 15 and 16 for fetching instructions following branch prediction.
sent to.

The selection diagram FI@15 shows the predicted address buffer 20° and the save register 14. A six selection circuit 16 that selectively supplies four outputs of the +1 addition value of the instruction counter 12 and the branch destination real address of the branch instruction to the instruction counter 12 is a predicted address buffer 20. Save register 14. Instruction counter 13
+1 addition value and 4 of the branch destination execution address of the branch instruction
The output of the operator is alternatively supplied to the command counter 13.

The instruction word read from the instruction cache 30 is supplied to the instruction register 33, and the preceding decoder 34 detects that the instruction code is a branch instruction, and the result of this detection is supplied to the control circuit 21. A part of the instruction register 33 is used as a read address for the pace register (Gl?335), and the other part is used as a read address for the general purpose register (BR) 35.
>37 adds the address syllable part of the instruction register 33, the output of the pace register, and the output of the general-purpose register to create a virtual address and supplies it to the storage control unit 2.

On the other hand, the output of the instruction register 33 is used in a decoder 38 to generate a control signal within the instruction control unit, create control information for the arithmetic control unit, and create a save buffer (IS).
S) Supply to 40. The save buffer 40 outputs the stored control information to the arithmetic control unit 3 at the time when the storage control unit 2 supplies the operand to the arithmetic control unit 3. Also, the address save buffer (ABF)
41 stores the real address sent from the storage control unit 2.

The storage control unit 2 has a virtual address register (ν^R) that holds the virtual address sent from the address adder 37.
)50. An address translation buffer (TLB") 51 that converts this virtual address into a real address, a real address register (PAR) 52 that holds the real address output from this buffer 51, and an operand cache 53.
．． 54, and the output of the operand cache is supplied to the arithmetic and control unit 3 as an operand. Further, the output of the real address register 52 is supplied to the selection circuits 15 and 16 as the branch destination address of the branch instruction, as described above.

The arithmetic control unit 3 operates a working register 60 that holds the output of the general-purpose register 63, a working register 61 that holds the output from the operand cache 54, and the outputs of both working registers 60 and 61, and stores the results in the general-purpose register 6.
3 and AlB1 supplied to the operand cache 54
2, and the carry output and zero detection output of 8[062] are sent to the branch judgment circuit 66.
is Al when the instruction decoding information supplied from the save buffer 40 notifies the condition code of a conditional branch instruction.
Referring to the output of B62, branch Go/N.

GO is determined and the result is notified to the control circuit 21 of the instruction control unit 1.

The mode register 65 is a register that instructs the operation mode of the branch prediction mechanism, and the decoder 64 is a register that indicates the operation mode of the branch prediction mechanism.
The control information of the instruction supplied as the output of is decoded and the control signal within the arithmetic unit 3 is distributed. This decoder 64
A part of the control signal is connected to the mode register 65, so that the value held by the mode register 65 can be changed in accordance with this control signal.

FIG. 2 shows the mode register 65. A specific example of the control circuit 21 and its peripheral circuits is shown.

In the figure, AND gate 101 is mode register 6
5, the V bit indicating the validity of the branch history memory sent from the terminal 121 at the timing of the terminal 130 is referred to, and its output is branched via the OR gate 105 and sent to the branch history memory update circuit at the terminal 131. sent via.

Similarly, the AND gate 1G2 sends the address mismatch signal sent from the address comparator via the terminal 122 to the OR gate 105 only when bit 1 of the mode register 65 is "1°°" at the timing input from the terminal 130. If bit 1 is "0", transmission is inhibited.

When bit 3 of the mode register 65 is "1", the AND gate 104 refers to the address mismatch output of the address comparator input from the terminal 122 using the control timing sent from the terminal 124, and sets it in an indicator (not shown). When bit 2 of the mode register 65 is "1", the AND gate 103 refers to the address mismatch output of the address comparator input from the terminal 122 at the timing of input from the terminal 123, and cancels the extraction of the branch destination. generate a signal to

In the same figure, the mode register 65 has bits 0 to
3, a total of 4 bits. mode register 65
Bit 0 of the mode register 65 indicates a mode in which registration of new data is suppressed when the V bit, which is a valid indication bit of data output from the branch history memory, is invalid. Bit 1 of the mode register 65 is output from the branch history memory. If there is a mismatch between the branch destination address of the received data and the branch destination address obtained as a result of decoding and execution of the actual branch instruction, a mode is set that suppresses updating of the branch history memory using old data as a new address pair. Similarly to bit 1, bit 2 of mode register 65 indicates a mode for suppressing the operation of invalidating an incorrect branch destination when the branch destination addresses do not match.
Similarly to bit 1, bit 3 of 5 indicates a mode in which a specific indicator is set when the branch destination addresses do not match.

The functions suppressed in each of these modes, except for ``Tot 3'', are essential functions in a branch prediction mechanism that uses a branch history memory, and are particularly important in updating the branch history memory and in the event of a branch prediction error. This is a function related to correction.

Therefore, when the mode register 65 instructs inhibition, bit 0 branches and inhibits new registration of the storage memory, bit 1 inhibits updating in the event of a mismatch, bit 2 inhibits illegal pre-emption invalidation in the event of a mismatch, and furthermore. Bit 3 sets the indicator when there is a mismatch. Therefore, by registering a known branch destination in the branch history memory in advance and then controlling each bit of the mode register 65, it becomes possible to evaluate various branch history memory operations.

For example, by setting bit 1, updating of the branch history memory is suppressed, the branch prediction failure state is maintained, and prefetching of branch destination instructions based on branch prediction failures is frequently canceled, thereby preventing the advance control circuit from validating. Able to conduct gender evaluation.

Another example is to set bit 2 or bit 3 of the mode register 65 after setting the case where all the information in the branch history memory has a correct branch result, and setting an error indicating that a branch destination mismatch state has occurred as an indicator. Alternatively, by making it impossible to continue normal program logic by suppressing prefetch cancellation, it becomes possible to directly evaluate and verify the correctness of the branch prediction mechanism.

According to the present invention, by setting the bits of the mode register in advance, it is possible to directly verify the correctness of the function of the branch memory i structure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a partial block diagram of a control circuit and its peripheral circuits in FIG. 1. Explanation of symbols of main parts 1...Instruction control unit 1-2...Storage control unit 3...Arithmetic control unit 1-10.11...Branch History memory 12...
...Instruction counter for branch prediction 13 ...Instruction word preemption instruction counter 21 ...Control circuit 30 ...Instruction cache 65 ...Mode register 2nd figure

Claims (1)

[Claims] (1) storage means for storing an instruction word; address generation means for generating a branch destination address when the instruction word read from the storage means is a branch instruction; an instruction word fetch address of the branch instruction; A branch history storage means that stores an address pair consisting of a destination address as branch history information in a storage address corresponding to the instruction word fetch address, and a branch history in the branch history storage means based on the instruction word fetch address of the branch instruction. indexing means for reading information and determining whether or not branch history information corresponding to the branch instruction is registered; and a branch destination address determined as a result of execution of the branch instruction and a branch extraction obtained as an output from the indexing means. A data processing device characterized in that it includes a disabling means for disabling instruction fetching using the branch fetching address when the two address do not match, and a control means for inhibiting and controlling the operation of the disabling means. .